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-------------------------------------------------------------------------------
-- Copyright 2013-2014 Jonathon Pendlum
--
-- This is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
-- File: axi_lite_to_parallel_bus.vhd
-- Author: Jonathon Pendlum ([email protected])
-- Description: Converts a AXI-4 Lite slave interface to a simple parallel
-- address + data interface.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity axi_lite_to_parallel_bus is
generic (
-- 32K word address space
C_BASEADDR : std_logic_vector(31 downto 0) := x"40000000";
C_HIGHADDR : std_logic_vector(31 downto 0) := x"4001ffff");
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
read_addr : out std_logic_vector(14 downto 0);
read_data : in std_logic_vector(31 downto 0);
read_stb : out std_logic;
write_addr : out std_logic_vector(14 downto 0);
write_data : out std_logic_vector(31 downto 0);
write_stb : out std_logic);
end entity;
architecture RTL of axi_lite_to_parallel_bus is
-------------------------------------------------------------------------------
-- Signal Declaration
-------------------------------------------------------------------------------
type read_state_type is (READ_IDLE,WAIT_FOR_READ_DATA,SET_READ_DATA_VALID);
type write_state_type is (WRITE_IDLE,WAIT_FOR_WVALID,WAIT_TO_WRITE_DATA);
signal read_state : read_state_type;
signal write_state : write_state_type;
begin
-----------------------------------------------------------------------------
-- State machine for Read Interface
-----------------------------------------------------------------------------
proc_read_state_machine : process(S_AXI_ACLK,S_AXI_ARESETN)
begin
if (S_AXI_ARESETN = '0') then
S_AXI_ARREADY <= '0';
S_AXI_RVALID <= '0';
S_AXI_RDATA <= (others=>'0');
read_addr <= (others=>'0');
read_stb <= '0';
read_state <= READ_IDLE;
else
if rising_edge(S_AXI_ACLK) then
case read_state is
when READ_IDLE =>
read_stb <= '0';
S_AXI_RVALID <= '0';
S_AXI_ARREADY <= '0';
if (S_AXI_ARVALID = '1') then
-- ARREADY is held low until ARVALID is asserted.
-- This may seem a little backwards, but this is similar to Xilinx's
-- AXI4-Lite IPIF LogiCore documentation.
S_AXI_ARREADY <= '1';
-- Bus access is assumed to be by words so the lower 2 bits are not needed.
read_addr <= S_AXI_ARADDR(16 downto 2) - C_BASEADDR(16 downto 2);
read_stb <= '1';
read_state <= WAIT_FOR_READ_DATA;
end if;
-- Wait a single cycle for the strobe signal to propagate and
-- read_data to update
when WAIT_FOR_READ_DATA =>
S_AXI_ARREADY <= '0';
read_stb <= '0';
read_state <= SET_READ_DATA_VALID;
when SET_READ_DATA_VALID =>
if (S_AXI_RREADY = '1') then
S_AXI_RVALID <= '1';
S_AXI_RDATA <= read_data;
read_state <= READ_IDLE;
end if;
when others =>
read_state <= READ_IDLE;
end case;
end if;
end if;
end process;
S_AXI_RRESP <= "00";
-----------------------------------------------------------------------------
-- State machine for Write Interface
-----------------------------------------------------------------------------
proc_write_state_machine : process(S_AXI_ACLK,S_AXI_ARESETN)
begin
if (S_AXI_ARESETN = '0') then
S_AXI_AWREADY <= '0';
S_AXI_WREADY <= '0';
write_addr <= (others=>'0');
write_data <= (others=>'0');
write_stb <= '0';
write_state <= WRITE_IDLE;
else
if rising_edge(S_AXI_ACLK) then
case write_state is
when WRITE_IDLE =>
S_AXI_AWREADY <= '0';
S_AXI_WREADY <= '0';
write_stb <= '0';
if (S_AXI_AWVALID = '1') then
S_AXI_AWREADY <= '1';
write_addr <= S_AXI_AWADDR(16 downto 2) - C_BASEADDR(16 downto 2);
if (S_AXI_WVALID = '1') then
S_AXI_WREADY <= '1';
write_data <= S_AXI_WDATA;
write_stb <= '1';
write_state <= WAIT_TO_WRITE_DATA;
else
write_state <= WAIT_FOR_WVALID;
end if;
end if;
when WAIT_FOR_WVALID =>
S_AXI_AWREADY <= '0';
if (S_AXI_WVALID = '1') then
S_AXI_WREADY <= '1';
write_data <= S_AXI_WDATA;
write_stb <= '1';
write_state <= WAIT_TO_WRITE_DATA;
end if;
when WAIT_TO_WRITE_DATA =>
S_AXI_AWREADY <= '0';
S_AXI_WREADY <= '0';
write_stb <= '0';
write_state <= WRITE_IDLE;
when others =>
write_state <= WRITE_IDLE;
end case;
end if;
end if;
end process;
S_AXI_BRESP <= "00";
S_AXI_BVALID <= S_AXI_BREADY;
end architecture; |
-------------------------------------------------------------------------------
-- Copyright 2013-2014 Jonathon Pendlum
--
-- This is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
-- File: axi_lite_to_parallel_bus.vhd
-- Author: Jonathon Pendlum ([email protected])
-- Description: Converts a AXI-4 Lite slave interface to a simple parallel
-- address + data interface.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity axi_lite_to_parallel_bus is
generic (
-- 32K word address space
C_BASEADDR : std_logic_vector(31 downto 0) := x"40000000";
C_HIGHADDR : std_logic_vector(31 downto 0) := x"4001ffff");
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
read_addr : out std_logic_vector(14 downto 0);
read_data : in std_logic_vector(31 downto 0);
read_stb : out std_logic;
write_addr : out std_logic_vector(14 downto 0);
write_data : out std_logic_vector(31 downto 0);
write_stb : out std_logic);
end entity;
architecture RTL of axi_lite_to_parallel_bus is
-------------------------------------------------------------------------------
-- Signal Declaration
-------------------------------------------------------------------------------
type read_state_type is (READ_IDLE,WAIT_FOR_READ_DATA,SET_READ_DATA_VALID);
type write_state_type is (WRITE_IDLE,WAIT_FOR_WVALID,WAIT_TO_WRITE_DATA);
signal read_state : read_state_type;
signal write_state : write_state_type;
begin
-----------------------------------------------------------------------------
-- State machine for Read Interface
-----------------------------------------------------------------------------
proc_read_state_machine : process(S_AXI_ACLK,S_AXI_ARESETN)
begin
if (S_AXI_ARESETN = '0') then
S_AXI_ARREADY <= '0';
S_AXI_RVALID <= '0';
S_AXI_RDATA <= (others=>'0');
read_addr <= (others=>'0');
read_stb <= '0';
read_state <= READ_IDLE;
else
if rising_edge(S_AXI_ACLK) then
case read_state is
when READ_IDLE =>
read_stb <= '0';
S_AXI_RVALID <= '0';
S_AXI_ARREADY <= '0';
if (S_AXI_ARVALID = '1') then
-- ARREADY is held low until ARVALID is asserted.
-- This may seem a little backwards, but this is similar to Xilinx's
-- AXI4-Lite IPIF LogiCore documentation.
S_AXI_ARREADY <= '1';
-- Bus access is assumed to be by words so the lower 2 bits are not needed.
read_addr <= S_AXI_ARADDR(16 downto 2) - C_BASEADDR(16 downto 2);
read_stb <= '1';
read_state <= WAIT_FOR_READ_DATA;
end if;
-- Wait a single cycle for the strobe signal to propagate and
-- read_data to update
when WAIT_FOR_READ_DATA =>
S_AXI_ARREADY <= '0';
read_stb <= '0';
read_state <= SET_READ_DATA_VALID;
when SET_READ_DATA_VALID =>
if (S_AXI_RREADY = '1') then
S_AXI_RVALID <= '1';
S_AXI_RDATA <= read_data;
read_state <= READ_IDLE;
end if;
when others =>
read_state <= READ_IDLE;
end case;
end if;
end if;
end process;
S_AXI_RRESP <= "00";
-----------------------------------------------------------------------------
-- State machine for Write Interface
-----------------------------------------------------------------------------
proc_write_state_machine : process(S_AXI_ACLK,S_AXI_ARESETN)
begin
if (S_AXI_ARESETN = '0') then
S_AXI_AWREADY <= '0';
S_AXI_WREADY <= '0';
write_addr <= (others=>'0');
write_data <= (others=>'0');
write_stb <= '0';
write_state <= WRITE_IDLE;
else
if rising_edge(S_AXI_ACLK) then
case write_state is
when WRITE_IDLE =>
S_AXI_AWREADY <= '0';
S_AXI_WREADY <= '0';
write_stb <= '0';
if (S_AXI_AWVALID = '1') then
S_AXI_AWREADY <= '1';
write_addr <= S_AXI_AWADDR(16 downto 2) - C_BASEADDR(16 downto 2);
if (S_AXI_WVALID = '1') then
S_AXI_WREADY <= '1';
write_data <= S_AXI_WDATA;
write_stb <= '1';
write_state <= WAIT_TO_WRITE_DATA;
else
write_state <= WAIT_FOR_WVALID;
end if;
end if;
when WAIT_FOR_WVALID =>
S_AXI_AWREADY <= '0';
if (S_AXI_WVALID = '1') then
S_AXI_WREADY <= '1';
write_data <= S_AXI_WDATA;
write_stb <= '1';
write_state <= WAIT_TO_WRITE_DATA;
end if;
when WAIT_TO_WRITE_DATA =>
S_AXI_AWREADY <= '0';
S_AXI_WREADY <= '0';
write_stb <= '0';
write_state <= WRITE_IDLE;
when others =>
write_state <= WRITE_IDLE;
end case;
end if;
end if;
end process;
S_AXI_BRESP <= "00";
S_AXI_BVALID <= S_AXI_BREADY;
end architecture; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arch_defs.all;
use work.utils.all;
entity DataMem is
port (
Address : in addr_t;
WriteData : in word_t;
ReadData : out word_t;
MemRead, MemWrite : in ctrl_memwidth_t;
MemSex : in std_logic;
clk : in std_logic
);
end DataMem;
architecture behav of DataMem is
type code_t is array (natural range <>) of instruction_t;
constant code : code_t := (
-- start:
X"00_00_00_00", -- no-op
X"08_00_00_00" -- j start
);
begin process(Address, clk)
begin
if rising_edge(clk) then
ReadData <= code(vtou(Address));
end if;
end process;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity wl_code_table is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(3 downto 0)
);
end wl_code_table;
architecture augh of wl_code_table is
-- Embedded RAM
type ram_type is array (0 to 15) of std_logic_vector(31 downto 0);
signal ram : ram_type := ("11111111111111111111111111000100", "00000000000000000000101111100010", "00000000000000000000010010101110", "00000000000000000000001000011010", "00000000000000000000000101001110", "00000000000000000000000010101100", "00000000000000000000000000111010", "11111111111111111111111111100010", "00000000000000000000101111100010", "00000000000000000000010010101110", "00000000000000000000001000011010", "00000000000000000000000101001110", "00000000000000000000000010101100", "00000000000000000000000000111010", "11111111111111111111111111100010", "11111111111111111111111111000100");
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- The component is a ROM.
-- There is no Write side.
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity wl_code_table is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(3 downto 0)
);
end wl_code_table;
architecture augh of wl_code_table is
-- Embedded RAM
type ram_type is array (0 to 15) of std_logic_vector(31 downto 0);
signal ram : ram_type := ("11111111111111111111111111000100", "00000000000000000000101111100010", "00000000000000000000010010101110", "00000000000000000000001000011010", "00000000000000000000000101001110", "00000000000000000000000010101100", "00000000000000000000000000111010", "11111111111111111111111111100010", "00000000000000000000101111100010", "00000000000000000000010010101110", "00000000000000000000001000011010", "00000000000000000000000101001110", "00000000000000000000000010101100", "00000000000000000000000000111010", "11111111111111111111111111100010", "11111111111111111111111111000100");
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- The component is a ROM.
-- There is no Write side.
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity wl_code_table is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(3 downto 0)
);
end wl_code_table;
architecture augh of wl_code_table is
-- Embedded RAM
type ram_type is array (0 to 15) of std_logic_vector(31 downto 0);
signal ram : ram_type := ("11111111111111111111111111000100", "00000000000000000000101111100010", "00000000000000000000010010101110", "00000000000000000000001000011010", "00000000000000000000000101001110", "00000000000000000000000010101100", "00000000000000000000000000111010", "11111111111111111111111111100010", "00000000000000000000101111100010", "00000000000000000000010010101110", "00000000000000000000001000011010", "00000000000000000000000101001110", "00000000000000000000000010101100", "00000000000000000000000000111010", "11111111111111111111111111100010", "11111111111111111111111111000100");
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- The component is a ROM.
-- There is no Write side.
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_rx_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fifo_rx_pkg.ALL;
ENTITY fifo_rx_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fifo_rx_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 100 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fifo_rx_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:17:37 11/11/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/aaaaaaaaaaa/tbexecute.vhd
-- Project Name: aaaaaaaaaaa
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Execute
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tbexecute IS
END tbexecute;
ARCHITECTURE behavior OF tbexecute IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Execute
PORT(
callin : IN std_logic_vector(31 downto 0);
ifin : IN std_logic_vector(31 downto 0);
pcsourcein : IN std_logic_vector(1 downto 0);
aluopin : IN std_logic_vector(5 downto 0);
op1in : IN std_logic_vector(31 downto 0);
op2in : IN std_logic_vector(31 downto 0);
cwp : OUT std_logic;
ncwp : IN std_logic;
icc : OUT std_logic_vector(3 downto 0);
nextpc : OUT std_logic_vector(31 downto 0);
aluresult : OUT std_logic_vector(31 downto 0);
Clkinext : IN std_logic;
Resetext : IN std_logic
);
END COMPONENT;
--Inputs
signal callin : std_logic_vector(31 downto 0) := (others => '0');
signal ifin : std_logic_vector(31 downto 0) := (others => '0');
signal pcsourcein : std_logic_vector(1 downto 0) := (others => '0');
signal aluopin : std_logic_vector(5 downto 0) := (others => '0');
signal op1in : std_logic_vector(31 downto 0) := (others => '0');
signal op2in : std_logic_vector(31 downto 0) := (others => '0');
signal ncwp : std_logic := '0';
signal Clkinext : std_logic := '0';
signal Resetext : std_logic := '0';
--Outputs
signal cwp : std_logic;
signal icc : std_logic_vector(3 downto 0);
signal nextpc : std_logic_vector(31 downto 0);
signal aluresult : std_logic_vector(31 downto 0);
-- Clock period definitions
constant Clkinext_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Execute PORT MAP (
callin => callin,
ifin => ifin,
pcsourcein => pcsourcein,
aluopin => aluopin,
op1in => op1in,
op2in => op2in,
cwp => cwp,
ncwp => ncwp,
icc => icc,
nextpc => nextpc,
aluresult => aluresult,
Clkinext => Clkinext,
Resetext => Resetext
);
-- Clock process definitions
Clkinext_process :process
begin
Clkinext <= '0';
wait for Clkinext_period/2;
Clkinext <= '1';
wait for Clkinext_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
callin <= "00000000000000000000000000000101";
ifin <= "00000000000000000000000000000101";
pcsourcein <= "01";
aluopin <= "000010";
op1in <= "00000000000000000000000000000101";
op2in <= "00000000000000000000000000000101";
ncwp <= '0';
Resetext <= '1';
wait for 100 ns;
callin <= "00000000000000000000000000000101";
ifin <= "00000000000000000000000000000101";
pcsourcein <= "01";
aluopin <= "000010";
op1in <= "00000000000000000000000000000101";
op2in <= "00000000000000000000000000000101";
ncwp <= '0';
Resetext <= '0';
wait for 100 ns;
callin <= "00000000000000000000000000000101";
ifin <= "00000000000000000000000000000101";
pcsourcein <= "00";
aluopin <= "000000";
op1in <= "00000000000000000000000000000101";
op2in <= "00000000000000000000000000000101";
ncwp <= '0';
Resetext <= '0';
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
|
-------------------------------------------------------------------------------
--
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : gtx_drp_chanalign_fix_3752_v6.vhd
-- Description: Virtex6 Workaround for deadlock due lane-lane skew Bug
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity GTX_DRP_CHANALIGN_FIX_3752_V6 is
generic (
C_SIMULATION : integer := 0 -- Set to 1 for simulation
);
port (
dwe : out std_logic;
din : out std_logic_vector(15 downto 0); --THIS IS THE INPUT TO THE DRP
den : out std_logic;
daddr : out std_logic_vector(7 downto 0);
drpstate : out std_logic_vector(3 downto 0); --DEBUG
write_ts1 : in std_logic;
write_fts : in std_logic;
dout : in std_logic_vector(15 downto 0); --THIS IS THE OUTPUT OF THE DRP
drdy : in std_logic;
Reset_n : in std_logic;
drp_clk : in std_logic
);
end GTX_DRP_CHANALIGN_FIX_3752_V6;
architecture v6_pcie of GTX_DRP_CHANALIGN_FIX_3752_V6 is
constant TCQ : integer := 1;
constant DRP_IDLE_FTS : std_logic_vector(3 downto 0) := "0001";
constant DRP_IDLE_TS1 : std_logic_vector(3 downto 0) := "0010";
constant DRP_RESET : std_logic_vector(3 downto 0) := "0011";
constant DRP_WRITE_FTS : std_logic_vector(3 downto 0) := "0110";
constant DRP_WRITE_DONE_FTS : std_logic_vector(3 downto 0) := "0111";
constant DRP_WRITE_TS1 : std_logic_vector(3 downto 0) := "1000";
constant DRP_WRITE_DONE_TS1 : std_logic_vector(3 downto 0) := "1001";
constant DRP_COM : std_logic_vector(9 downto 0) := "0110111100";
constant DRP_FTS : std_logic_vector(9 downto 0) := "0100111100";
constant DRP_TS1 : std_logic_vector(9 downto 0) := "0001001010";
signal next_daddr : std_logic_vector(7 downto 0);
signal next_drpstate : std_logic_vector(3 downto 0);
signal write_ts1_gated : std_logic;
signal write_fts_gated : std_logic;
-- Declare intermediate signals for referenced outputs
signal daddr_v6pcie : std_logic_vector(7 downto 0);
signal drpstate_v6pcie : std_logic_vector(3 downto 0);
begin
-- Drive referenced outputs
daddr <= daddr_v6pcie;
drpstate <= drpstate_v6pcie;
process (drp_clk)
begin
if (drp_clk'event and drp_clk = '1') then
if ((not(Reset_n)) = '1') then
daddr_v6pcie <= X"08" after (TCQ)*1 ps;
drpstate_v6pcie <= DRP_RESET after (TCQ)*1 ps;
write_ts1_gated <= '0' after (TCQ)*1 ps;
write_fts_gated <= '0' after (TCQ)*1 ps;
else
daddr_v6pcie <= next_daddr after (TCQ)*1 ps;
drpstate_v6pcie <= next_drpstate after (TCQ)*1 ps;
write_ts1_gated <= write_ts1 after (TCQ)*1 ps;
write_fts_gated <= write_fts after (TCQ)*1 ps;
end if;
end if;
end process;
process (drpstate_v6pcie, daddr_v6pcie, drdy, write_ts1_gated, write_fts_gated)
begin
-- DEFAULT CONDITIONS
next_drpstate <= drpstate_v6pcie;
next_daddr <= daddr_v6pcie;
den <= '0';
din <= (others => '0');
dwe <= '0';
case drpstate_v6pcie is
-- RESET CONDITION, WE NEED TO READ THE TOP 6 BITS OF THE DRP REGISTER WHEN WE GET THE WRITE FTS TRIGGER
when DRP_RESET =>
next_drpstate <= DRP_WRITE_TS1;
next_daddr <= X"08";
-- WRITE FTS SEQUENCE
when DRP_WRITE_FTS =>
den <= '1';
dwe <= '1';
if (daddr_v6pcie = X"08") then
din <= X"FD3C";
elsif (daddr_v6pcie = X"09") then
din <= X"C53C";
elsif (daddr_v6pcie = X"0A") then
din <= X"FDBC";
elsif (daddr_v6pcie = X"0B") then
din <= X"853C";
end if;
next_drpstate <= DRP_WRITE_DONE_FTS;
-- WAIT FOR FTS SEQUENCE WRITE TO FINISH, ONCE WE FINISH ALL WRITES GO TO FTS IDLE
when DRP_WRITE_DONE_FTS =>
if (drdy = '1') then
if (daddr_v6pcie = X"0B") then
next_drpstate <= DRP_IDLE_FTS;
next_daddr <= X"08";
else
next_drpstate <= DRP_WRITE_FTS;
next_daddr <= daddr_v6pcie + X"01";
end if;
end if;
-- FTS IDLE: WAIT HERE UNTIL WE NEED TO WRITE TS1
when DRP_IDLE_FTS =>
if (write_ts1_gated = '1') then
next_drpstate <= DRP_WRITE_TS1;
next_daddr <= X"08";
end if;
-- WRITE TS1 SEQUENCE
when DRP_WRITE_TS1 =>
den <= '1';
dwe <= '1';
if (daddr_v6pcie = X"08") then
din <= X"FC4A";
elsif (daddr_v6pcie = X"09") then
din <= X"DC4A";
elsif (daddr_v6pcie = X"0A") then
din <= X"C04A";
elsif (daddr_v6pcie = X"0B") then
din <= X"85BC";
end if;
next_drpstate <= DRP_WRITE_DONE_TS1;
-- WAIT FOR TS1 SEQUENCE WRITE TO FINISH, ONCE WE FINISH ALL WRITES GO TO TS1 IDLE
when DRP_WRITE_DONE_TS1 =>
if (drdy = '1') then
if (daddr_v6pcie = X"0B") then
next_drpstate <= DRP_IDLE_TS1;
next_daddr <= X"08";
else
next_drpstate <= DRP_WRITE_TS1;
next_daddr <= daddr_v6pcie + X"01";
end if;
end if;
-- TS1 IDLE: WAIT HERE UNTIL WE NEED TO WRITE FTS
when DRP_IDLE_TS1 =>
if (write_fts_gated = '1') then
next_drpstate <= DRP_WRITE_FTS;
next_daddr <= X"08";
end if;
when others =>
next_drpstate <= DRP_RESET;
next_daddr <= X"00";
end case;
end process;
end v6_pcie;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2507.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b04x00p03n01i02507ent IS
END c07s03b04x00p03n01i02507ent;
ARCHITECTURE c07s03b04x00p03n01i02507arch OF c07s03b04x00p03n01i02507ent IS
BEGIN
TESTING: PROCESS
function F1 ( PARAM : bit ) return boolean is
begin
return boolean'(PARAM); -- Failure_here
-- SEMANTIC ERROR: type of expression does not match type mark.
end F1;
variable k : boolean;
BEGIN
k := F1('1');
assert FALSE
report "***FAILED TEST: c07s03b04x00p03n01i02507 - Expression type does not match type mark."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b04x00p03n01i02507arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2507.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b04x00p03n01i02507ent IS
END c07s03b04x00p03n01i02507ent;
ARCHITECTURE c07s03b04x00p03n01i02507arch OF c07s03b04x00p03n01i02507ent IS
BEGIN
TESTING: PROCESS
function F1 ( PARAM : bit ) return boolean is
begin
return boolean'(PARAM); -- Failure_here
-- SEMANTIC ERROR: type of expression does not match type mark.
end F1;
variable k : boolean;
BEGIN
k := F1('1');
assert FALSE
report "***FAILED TEST: c07s03b04x00p03n01i02507 - Expression type does not match type mark."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b04x00p03n01i02507arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2507.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b04x00p03n01i02507ent IS
END c07s03b04x00p03n01i02507ent;
ARCHITECTURE c07s03b04x00p03n01i02507arch OF c07s03b04x00p03n01i02507ent IS
BEGIN
TESTING: PROCESS
function F1 ( PARAM : bit ) return boolean is
begin
return boolean'(PARAM); -- Failure_here
-- SEMANTIC ERROR: type of expression does not match type mark.
end F1;
variable k : boolean;
BEGIN
k := F1('1');
assert FALSE
report "***FAILED TEST: c07s03b04x00p03n01i02507 - Expression type does not match type mark."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b04x00p03n01i02507arch;
|
-------------------------------------------------------------------------------
-- $Id: dynshreg_i_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- dynshreg_i_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: dynshreg_i_f.vhd
--
-- Description: This module implements a dynamic shift register with clock
-- enable. (Think, for example, of the function of the SRL16E.)
-- The width and depth of the shift register are selectable
-- via generics C_WIDTH and C_DEPTH, respectively. The C_FAMILY
-- allows the implementation to be tailored to the target
-- FPGA family. An inferred implementation is used if C_FAMILY
-- is "nofamily" (the default) or if synthesis will not produce
-- an optimal implementation. Otherwise, a structural
-- implementation will be generated.
--
-- There is no restriction on the values of C_WIDTH and
-- C_DEPTH and, in particular, the C_DEPTH does not have
-- to be a power of two.
--
-- This version allows the client to specify the initial value
-- of the contents of the shift register, as applied
-- during configuration.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: FLO
--
-- History:
-- FLO 01/03/07 First Version. Derived from dynshreg_f.
--
-- ~~~~~~
-- FLO 12/20/07
-- ^^^^^^
-- -Now using clog2 instead of log2.
-- ~~~~~~
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
---(
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.TO_INTEGER;
--
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.clog2;
--------------------------------------------------------------------------------
-- Explanations of generics and ports regarding aspects that may not be obvious.
--
-- C_DWIDTH
--------
-- Theoretically, C_DWIDTH may be set to zero and this could be a more
-- natural or preferrable way of excluding a dynamic shift register
-- in a client than using a VHDL Generate statement. However, this usage is not
-- tested, and the user should expect that some VHDL tools will be deficient
-- with respect to handling this properly.
--
-- C_INIT_VALUE
---------------
-- C_INIT_VALUE can be used to specify the initial values of the elements
-- in the dynamic shift register, i.e. the values to be present after config-
-- uration. C_INIT_VALUE need not be the same size as the dynamic shift
-- register, i.e. C_DWIDTH*C_DEPTH. When smaller, C_INIT_VALUE
-- is replicated as many times as needed (possibly fractionally the last time)
-- to form a full initial value that is the size of the shift register.
-- So, if C_INIT_VALUE is left at its default value--an array of size one
-- whose value is '0'--the shift register will initialize with all bits at
-- all addresses set to '0'. This will also be the case if C_INIT_VALUE is a
-- null (size zero) array.
-- When determined according to the rules outlined above, the full
-- initial value is a std_logic_vector value from (0 to C_DWIDTH*C_DEPTH-1). It
-- is allocated to the addresses of the dynamic shift register in this
-- manner: The first C_DWIDTH values (i.e. 0 to C_CWIDTH-1) assigned to
-- the corresponding indices at address 0, the second C_DWIDTH values
-- assigned to address 1, and so forth.
-- Please note that the shift register is not resettable after configuration.
--
-- Addr
----
-- Addr addresses the elements of the dynamic shift register. Addr=0 causes
-- the most recently shifted-in element to appear at Dout, Addr=1
-- the second most recently shifted in element, etc. If C_DEPTH is not
-- a power of two, then not all of the values of Addr correspond to an
-- element in the shift register. When such an address is applied, the value
-- of Dout is undefined until a valid address is established.
--------------------------------------------------------------------------------
entity dynshreg_i_f is
generic (
C_DEPTH : positive := 32;
C_DWIDTH : natural := 1;
C_INIT_VALUE : bit_vector := "0";
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Clken : in std_logic;
Addr : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Din : in std_logic_vector(0 to C_DWIDTH-1);
Dout : out std_logic_vector(0 to C_DWIDTH-1)
);
end dynshreg_i_f;
library proc_common_v3_00_a;
use proc_common_v3_00_a.family_support.all;
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
architecture behavioral of dynshreg_i_f is
type bv2sl_type is array(bit) of std_logic;
constant bv2sl : bv2sl_type := ('0' => '0', '1' => '1');
function min(a, b: natural) return natural is
begin
if a<b then return a; else return b; end if;
end min;
--
------------------------------------------------------------------------------
-- Function used to establish the full initial value. (See the comments for
-- C_INIT_VALUE, above.)
------------------------------------------------------------------------------
function full_initial_value(w : natural; d : positive; v : bit_vector
) return bit_vector is
variable r : bit_vector(0 to w*d-1);
variable i, j : natural;
-- i - the index where filling of r continues
-- j - the amount to fill on the cur. iteration of the while loop
begin
if w = 0 then null; -- Handle the case where the shift reg width is zero
elsif v'length = 0 then r := (others => '0');
else
i := 0;
while i /= r'length loop
j := min(v'length, r'length-i);
r(i to i+j-1) := v(0 to j-1);
i := i+j;
end loop;
end if;
return r;
end full_initial_value;
constant FULL_INIT_VAL : bit_vector(0 to C_DWIDTH*C_DEPTH -1)
:= full_initial_value(C_DWIDTH, C_DEPTH, C_INIT_VALUE);
--
constant K_FAMILY : families_type := str2fam(C_FAMILY);
--
constant W32 : boolean := supported(K_FAMILY, u_SRLC32E) and
(C_DEPTH > 16 or not supported(K_FAMILY, u_SRL16E));
constant W16 : boolean := supported(K_FAMILY, u_SRLC16E) and not W32;
-- XST faster if these two constants are declared here
-- instead of in STRUCTURAL_A_GEN. (I.25)
--
function power_of_2(n: positive) return boolean is
variable i: positive := 1;
begin
while n > i loop i := i*2; end loop;
return n = i;
end power_of_2;
--
constant USE_INFERRED : boolean := ( power_of_2(C_DEPTH)
and ( (W16 and C_DEPTH >= 16)
or (W32 and C_DEPTH >= 32)
)
)
or (not W32 and not W16);
-- As of I.32, XST is not infering optimal dynamic shift registers for
-- depths not a power of two (by not taking advantage of don't care
-- at output when address not within the range of the depth)
-- or a power of two less than the native SRL depth (by building shift
-- register out of discrete FFs and LUTs instead of SRLs).
constant USE_STRUCTURAL_A : boolean := not USE_INFERRED;
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
component SRLC16E
generic
(
INIT : bit_vector := X"0000"
);
port
(
Q : out STD_ULOGIC;
Q15 : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
component SRLC32E
generic
(
INIT : bit_vector := X"00000000"
);
port
(
Q : out STD_ULOGIC;
Q31 : out STD_ULOGIC;
A : in STD_LOGIC_VECTOR (4 downto 0);
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
begin
---(
STRUCTURAL_A_GEN : if USE_STRUCTURAL_A = true generate
type bo2na_type is array(boolean) of natural;
constant bo2na : bo2na_type := (false => 0, true => 1);
constant BPSRL : natural := bo2na(W16)*16 + bo2na(W32)*32; -- Bits per SRL
constant BTASRL : natural := clog2(BPSRL); -- Bits To Address SRL
constant NUM_SRLS_DEEP : natural := (C_DEPTH + BPSRL-1)/BPSRL;
constant ADDR_BITS : integer := Addr'length;
signal dynshreg_addr : std_logic_vector(ADDR_BITS-1 downto 0);
signal cascade_sigs : std_logic_vector(0 to C_DWIDTH*(NUM_SRLS_DEEP+1) - 1);
-- The data signals at the inputs and daisy-chain outputs of SRLs.
-- The last signal of each cascade is not used.
--
signal q_sigs : std_logic_vector(0 to C_DWIDTH*NUM_SRLS_DEEP - 1);
-- The data signals at the addressble outputs of SRLs.
function srl_init_string(i, j : natural;
w : natural;
d : positive;
bpsrl : positive;
v : bit_vector
) return bit_vector is
variable base : natural := j*bpsrl*w + i;
variable r : bit_vector(bpsrl-1 downto 0) := (others => '0');
begin
for k in 0 to min(bpsrl, d-j*bpsrl)-1 loop
r(k) := v(base+k*w);
end loop;
return r;
end srl_init_string;
---)(
begin
DIN_TO_CASCADE_GEN : for i in 0 to C_DWIDTH-1 generate
cascade_sigs(i*(NUM_SRLS_DEEP+1)) <= Din(i);
end generate;
dynshreg_addr(ADDR_BITS-1 downto 0) <= Addr(0 to ADDR_BITS-1);
BIT_OF_WIDTH_GEN : for i in 0 to C_DWIDTH-1 generate
CASCADES_GEN : for j in 0 to NUM_SRLS_DEEP-1 generate
signal srl_addr: std_logic_vector(4 downto 0);
begin
-- Here we form the address for the SRL elements. This is just
-- the corresponding low-order bits of dynshreg_addr but we
-- also handle the case where we have to zero-pad to the left
-- a dynshreg_addr that is smaller than the SRL address port.
SRL_ADDR_LO_GEN : for i in 0 to min(ADDR_BITS-1,4) generate
srl_addr(i) <= dynshreg_addr(i);
end generate;
SRL_ADDR_HI_GEN : for i in min(ADDR_BITS-1,4)+1 to 4 generate
srl_addr(i) <= '0';
end generate;
W16_GEN : if W16 generate
SRLC16E_I : component SRLC16E
generic map (
INIT => srl_init_string(i, j,
C_DWIDTH,
C_DEPTH,
BPSRL,
FULL_INIT_VAL)
)
port map
(
Q => q_sigs(j + i*NUM_SRLS_DEEP),
Q15 => cascade_sigs(j+1 + i*(NUM_SRLS_DEEP+1)),
A0 => srl_addr(0),
A1 => srl_addr(1),
A2 => srl_addr(2),
A3 => srl_addr(3),
CE => Clken,
Clk => Clk,
D => cascade_sigs(j + i*(NUM_SRLS_DEEP+1))
)
;
end generate;
W32_GEN : if W32 generate
begin
SRLC32E_I : component SRLC32E
generic map (
INIT => srl_init_string(i, j,
C_DWIDTH,
C_DEPTH,
BPSRL,
FULL_INIT_VAL)
)
port map
(
Q => q_sigs(j + i*NUM_SRLS_DEEP),
Q31 => cascade_sigs(j+1 + i*(NUM_SRLS_DEEP+1)),
A => srl_addr(4 downto 0),
CE => Clken,
Clk => Clk,
D => cascade_sigs(j + i*(NUM_SRLS_DEEP+1))
)
;
end generate;
end generate CASCADES_GEN;
end generate BIT_OF_WIDTH_GEN;
----------------------------------------------------------------------------
-- Generate a MUXFn structure to select the proper SRL
-- as the output of each shift register.
----------------------------------------------------------------------------
SINGLE_SRL_GEN : if NUM_SRLS_DEEP = 1 generate
Dout <= q_sigs;
end generate;
--
MULTI_SRL_GEN : if NUM_SRLS_DEEP > 1 generate
PER_BIT_GEN : for i in 0 to C_DWIDTH-1 generate
begin
MUXF_STRUCT_I0 : entity proc_common_v3_00_a.muxf_struct_f
generic map (
C_START_LEVEL => native_lut_size(fam => K_FAMILY,
no_lut_return_val => 10000),
-- Artificially high value for C_START_LEVEL when no LUT is
-- supported will cause muxf_struct_f to default to inferred
-- multiplexers.
C_NUM_INPUTS => NUM_SRLS_DEEP,
C_FAMILY => C_FAMILY
)
port map (
O => Dout(i),
Iv => q_sigs(i * (NUM_SRLS_DEEP) to
(i+1) * (NUM_SRLS_DEEP) - 1),
Sel => dynshreg_addr(ADDR_BITS-1 downto BTASRL)
--Bits To Addr SRL
)
;
end generate;
end generate;
end generate STRUCTURAL_A_GEN;
---)
---(
INFERRED_GEN : if USE_INFERRED = true generate
--
type dataType is array (0 to C_DEPTH-1) of std_logic_vector(0 to C_DWIDTH-1);
--
function fill_data(w: natural; d: positive; v: bit_vector
) return dataType is
variable r : dataType;
begin
for i in 0 to d-1 loop
for j in 0 to w-1 loop
r(i)(j) := bv2sl(v(i*w+j));
end loop;
end loop;
return r;
end fill_data;
signal data: dataType := fill_data(C_DWIDTH, C_DEPTH, FULL_INIT_VAL);
--
begin
process(Clk)
begin
if Clk'event and Clk = '1' then
if Clken = '1' then
data <= Din & data(0 to C_DEPTH-2);
end if;
end if;
end process;
Dout <= data(TO_INTEGER(UNSIGNED(Addr)))
when (TO_INTEGER(UNSIGNED(Addr)) < C_DEPTH)
else
(others => '-');
end generate INFERRED_GEN;
---)
end behavioral;
---)
|
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library cycloneiii;
use cycloneiii.all;
entity actrlout is
generic(
power_up : string := "high"
);
port(
clk : in std_logic;
i : in std_logic;
o : out std_logic
);
end;
architecture rtl of actrlout is
component cycloneiii_ddio_out
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_out"
);
port (
datainlo : in std_logic := '0';
datainhi : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
dataout : out std_logic;
dfflo : out std_logic;
dffhi : out std_logic-- ;
--devclrn : in std_logic := '1';
--devpor : in std_logic := '1'
);
end component;
signal vcc : std_logic;
signal gnd : std_logic_vector(13 downto 0);
signal clk_reg : std_logic;
signal clk_buf, clk_bufn : std_logic;
begin
vcc <= '1'; gnd <= (others => '0');
out_reg0 : cycloneiii_ddio_out
generic map(
power_up => power_up,--"high",
async_mode => "none",
sync_mode => "none",
lpm_type => "cycloneiii_ddio_out"
)
port map(
datainlo => i,
datainhi => i,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => o,
dfflo => open,
dffhi => open--,
--devclrn => vcc,
--devpor => vcc
);
end;
|
-------------------------------------------------------------------------------
-- system_xadc_wiz_0_0_family.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: system_xadc_wiz_0_0_family.vhd
--
-- Description:
-- This HDL file provides various functions for determining features (such
-- as BRAM types) in the various device families in Xilinx products.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- system_xadc_wiz_0_0_family.vhd
--
-------------------------------------------------------------------------------
-- Revision history
--
-- ??? ?????????? Initial version
-- jam 03/31/2003 added spartan3 to constants and derived function. Added
-- comments to try and explain how the function is used
-- jam 04/01/2003 removed VIRTEX from the derived list for BYZANTIUM,
-- VIRTEX2P, and SPARTAN3. This changes VIRTEX2 to be a
-- base family type, similar to X4K and VIRTEX
-- jam 04/02/2003 add VIRTEX back into the hierarchy of VIRTEX2P, BYZANTIUM
-- and SPARTAN3; add additional comments showing use in
-- VHDL
-- lss 03/24/2004 Added QVIRTEX2, QRVIRTEX2, VIRTEX4
-- flo 03/22/2005 Added SPARTAN3E
-- als 02/23/2006 Added VIRTEX5
-- flo 09/13/2006 Added SPARTAN3A and SPARTAN3A. This may allow
-- legacy designs to support spartan3a and spartan3an in
-- terms of BRAMs. For new work (and maintenence where
-- possible) this package, family, should be dropped in favor
-- of the package, family_support.
--
-- DET 1/17/2008 v3_30_a
-- ~~~~~~
-- - Changed proc_common library version to v3_30_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--------------------------------------------------------------------------------
-- @BEGIN_CHANGELOG EDK_H_SP1
-- Added spartan3e
-- @END_CHANGELOG
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
package system_xadc_wiz_0_0_family is
-- constant declarations
constant ANY : string := "any";
constant X4K : string := "x4k";
constant X4KE : string := "x4ke";
constant X4KL : string := "x4kl";
constant X4KEX : string := "x4kex";
constant X4KXL : string := "x4kxl";
constant X4KXV : string := "x4kxv";
constant X4KXLA : string := "x4kxla";
constant SPARTAN : string := "spartan";
constant SPARTANXL : string := "spartanxl";
constant SPARTAN2 : string := "spartan2";
constant SPARTAN2E : string := "spartan2e";
constant VIRTEX : string := "virtex";
constant VIRTEXE : string := "virtexe";
constant VIRTEX2 : string := "virtex2";
constant VIRTEX2P : string := "virtex2p";
constant BYZANTIUM : string := "byzantium";
constant SPARTAN3 : string := "spartan3";
constant QRVIRTEX2 : string := "qrvirtex2";
constant QVIRTEX2 : string := "qvirtex2";
constant VIRTEX4 : string := "virtex4";
constant VIRTEX5 : string := "virtex5";
constant SPARTAN3E : string := "spartan3e";
constant SPARTAN3A : string := "spartan3a";
constant SPARTAN3AN: string := "spartan3an";
-- function declarations
-- derived - provides a means to determine if a family specified in child is
-- the same as, or is a super set of, the family specified in
-- ancestor.
--
-- Typically, child is set to the generic specifying the family type
-- the user wishes to implement the design into (C_FAMILY), and the
-- designer hard codes ancestor to the family type supported by the
-- design. If the design supports multiple family types, then each
-- of those family types would need to be tested against C_FAMILY
-- using this function. An example for the VIRTEX2P hierarchy
-- is shown below:
--
-- VIRTEX2P_SPECIFIC_LOGIC_GEN:
-- if derived(C_FAMILY,VIRTEX2P)
-- generate
-- -- logic specific to Virtex2P family
-- end generate VIRTEX2P_SPECIFIC_LOGIC_GEN;
--
-- NON_VIRTEX2P_SPECIFIC_LOGIC_GEN:
-- if not derived(C_FAMILY,VIRTEX2P)
-- generate
--
-- VIRTEX2_SPECIFIC_LOGIC_GEN:
-- if derived(C_FAMILY,VIRTEX2)
-- generate
-- -- logic specific to Virtex2 family
-- end generate VIRTEX2_SPECIFIC_LOGIC_GEN;
--
-- NON_VIRTEX2_SPECIFIC_LOGIC_GEN
-- if not derived(C_FAMILY,VIRTEX2)
-- generate
--
-- VIRTEX_SPECIFIC_LOGIC_GEN:
-- if derived(C_FAMILY,VIRTEX)
-- generate
-- -- logic specific to Virtex family
-- end generate VIRTEX_SPECIFIC_LOGIC_GEN;
--
-- NON_VIRTEX_SPECIFIC_LOGIC_GEN;
-- if not derived(C_FAMILY,VIRTEX)
-- generate
--
-- ANY_FAMILY_TYPE_LOGIC_GEN:
-- if derived(C_FAMILY,ANY)
-- generate
-- -- logic not specific to any family
-- end generate ANY_FAMILY_TYPE_LOGIC_GEN;
--
-- end generate NON_VIRTEX_SPECIFIC_LOGIC_GEN;
--
-- end generate NON_VIRTEX2_SPECIFIC_LOGIC_GEN;
--
-- end generate NON_VIRTEX2P_SPECIFIC_LOGIC_GEN;
--
-- This function will return TRUE if the family type specified in
-- child is equal to, or a super set of, the family type specified in
-- ancestor, otherwise it returns FALSE.
--
-- The current super sets are defined by the following list, where
-- all family types listed to the right of an item are contained in
-- the super set of that item, for all lines containing that item.
--
-- ANY, X4K, SPARTAN, SPARTANXL
-- ANY, X4K, X4KE, X4KL
-- ANY, X4K, X4KEX, X4KXL, X4KXV, X4KXLA
-- ANY, VIRTEX, SPARTAN2, SPARTAN2E
-- ANY, VIRTEX, VIRTEXE
-- ANY, VIRTEX, VIRTEX2, BYZANTIUM
-- ANY, VIRTEX, VIRTEX2, VIRTEX2P
-- ANY, VIRTEX, VIRTEX2, SPARTAN3
--
-- For exampel, all other family types are contained in the super set
-- for ANY. Stated another way, if the designer specifies ANY
-- for the family type the design supports, then the function will
-- return TRUE for any family type the user wishes to implement the
-- design into.
--
-- if derived(C_FAMILY,ANY) generate ... end generate;
--
-- If the designer specifies VIRTEX2 as the family type supported by
-- the design, then the function will only return TRUE if the user
-- intends to implement the design in VIRTEX2, VIRTEX2P, BYZANTIUM,
-- or SPARTAN3.
--
-- if derived(C_FAMILY,VIRTEX2) generate
-- -- logic that uses VIRTEX2 BRAMs
-- end generate;
--
-- if not derived(C_FAMILY,VIRTEX2) generate
-- -- logic that uses non VIRTEX2 BRAMs
-- end generate;
--
-- Note:
-- The last three lines of the list above were modified from the
-- original to remove VIRTEX from those lines because, from our point
-- of view, VIRTEX2 is different enough from VIRTEX to conclude that
-- it should be its own base family type.
--
-- **************************************************************************
-- WARNING
-- **************************************************************************
-- DO NOT RELY ON THE DERIVED FUNCTION TO PROVIDE DIFFERENTIATION BETWEEN
-- FAMILY TYPES FOR ANYTHING OTHER THAN BRAMS
--
-- Use of the derived function assumes that the designer is not using
-- RLOCs (RLOC'd FIFO's from Coregen, etc.) and that the BRAMs in the
-- derived families are similar. If the designer is using specific
-- elements of a family type, they are responsible for ensuring that
-- those same elements are available in all family types supported by
-- their design, and that the elements function exactly the same in all
-- "similar" families.
--
-- **************************************************************************
--
function derived ( child, ancestor : string ) return boolean;
-- equalIgnoreCase - Returns TRUE if case insensitive string comparison
-- determines that str1 and str2 are equal, otherwise FALSE
function equalIgnoreCase( str1, str2 : string ) return boolean;
-- toLowerCaseChar - Returns the lower case form of char if char is an upper
-- case letter. Otherwise char is returned.
function toLowerCaseChar( char : character ) return character;
end system_xadc_wiz_0_0_family;
package body system_xadc_wiz_0_0_family is
-- True if architecture "child" is derived from, or equal to,
-- the architecture "ancestor".
-- ANY, X4K, SPARTAN, SPARTANXL
-- ANY, X4K, X4KE, X4KL
-- ANY, X4K, X4KEX, X4KXL, X4KXV, X4KXLA
-- ANY, VIRTEX, SPARTAN2, SPARTAN2E
-- ANY, VIRTEX, VIRTEXE
-- ANY, VIRTEX, VIRTEX2, BYZANTIUM
-- ANY, VIRTEX, VIRTEX2, VIRTEX2P
-- ANY, VIRTEX, VIRTEX2, SPARTAN3
function derived ( child, ancestor : string ) return boolean is
variable is_derived : boolean := FALSE;
begin
if equalIgnoreCase( child, VIRTEX ) then -- base family type
if ( equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX2 ) then
if ( equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, QRVIRTEX2 ) then
if ( equalIgnoreCase(ancestor,QRVIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, QVIRTEX2 ) then
if ( equalIgnoreCase(ancestor,QVIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX5 ) then
if ( equalIgnoreCase(ancestor,VIRTEX5) OR
equalIgnoreCase(ancestor,VIRTEX4) OR
equalIgnoreCase(ancestor,VIRTEX2P) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX4 ) then
if ( equalIgnoreCase(ancestor,VIRTEX4) OR
equalIgnoreCase(ancestor,VIRTEX2P) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX2P ) then
if ( equalIgnoreCase(ancestor,VIRTEX2P) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, BYZANTIUM ) then
if ( equalIgnoreCase(ancestor,BYZANTIUM) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEXE ) then
if ( equalIgnoreCase(ancestor,VIRTEXE) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN2 ) then
if ( equalIgnoreCase(ancestor,SPARTAN2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN2E ) then
if ( equalIgnoreCase(ancestor,SPARTAN2E) OR
equalIgnoreCase(ancestor,SPARTAN2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3 ) then
if ( equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3E ) then
if ( equalIgnoreCase(ancestor,SPARTAN3E) OR
equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3A ) then
if ( equalIgnoreCase(ancestor,SPARTAN3A) OR
equalIgnoreCase(ancestor,SPARTAN3E) OR
equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3AN ) then
if ( equalIgnoreCase(ancestor,SPARTAN3AN) OR
equalIgnoreCase(ancestor,SPARTAN3E) OR
equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4K ) then -- base family type
if ( equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KEX ) then
if ( equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KXL ) then
if ( equalIgnoreCase(ancestor,X4KXL) OR
equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KXV ) then
if ( equalIgnoreCase(ancestor,X4KXV) OR
equalIgnoreCase(ancestor,X4KXL) OR
equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KXLA ) then
if ( equalIgnoreCase(ancestor,X4KXLA) OR
equalIgnoreCase(ancestor,X4KXV) OR
equalIgnoreCase(ancestor,X4KXL) OR
equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KE ) then
if ( equalIgnoreCase(ancestor,X4KE) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KL ) then
if ( equalIgnoreCase(ancestor,X4KL) OR
equalIgnoreCase(ancestor,X4KE) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN ) then
if ( equalIgnoreCase(ancestor,SPARTAN) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTANXL ) then
if ( equalIgnoreCase(ancestor,SPARTANXL) OR
equalIgnoreCase(ancestor,SPARTAN) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, ANY ) then
if equalIgnoreCase( ancestor, any ) then is_derived := TRUE;
end if;
end if;
return is_derived;
end derived;
-- Returns the lower case form of char if char is an upper case letter.
-- Otherwise char is returned.
function toLowerCaseChar( char : character ) return character is
begin
-- If char is not an upper case letter then return char
if char < 'A' OR char > 'Z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'A' => return 'a';
when 'B' => return 'b';
when 'C' => return 'c';
when 'D' => return 'd';
when 'E' => return 'e';
when 'F' => return 'f';
when 'G' => return 'g';
when 'H' => return 'h';
when 'I' => return 'i';
when 'J' => return 'j';
when 'K' => return 'k';
when 'L' => return 'l';
when 'M' => return 'm';
when 'N' => return 'n';
when 'O' => return 'o';
when 'P' => return 'p';
when 'Q' => return 'q';
when 'R' => return 'r';
when 'S' => return 's';
when 'T' => return 't';
when 'U' => return 'u';
when 'V' => return 'v';
when 'W' => return 'w';
when 'X' => return 'x';
when 'Y' => return 'y';
when 'Z' => return 'z';
when others => return char;
end case;
end toLowerCaseChar;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
function equalIgnoreCase( str1, str2 : string ) return boolean is
constant LEN1 : integer := str1'length;
constant LEN2 : integer := str2'length;
variable equal : boolean := TRUE;
begin
if not (LEN1 = LEN2) then
equal := FALSE;
else
for i in str1'range loop
if not (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) then
equal := FALSE;
end if;
end loop;
end if;
return equal;
end equalIgnoreCase;
end system_xadc_wiz_0_0_family;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc623.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:45 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:08 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:24 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00623ent IS
END c03s04b01x00p01n01i00623ent;
ARCHITECTURE c03s04b01x00p01n01i00623arch OF c03s04b01x00p01n01i00623ent IS
constant C4 : positive := 3 ;
type positive_vector is array (natural range <>) of positive;
subtype positive_vector_st is positive_vector(0 to 15);
type positive_vector_st_file is file of positive_vector_st;
constant C27 : positive_vector_st := (others => C4);
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : positive_vector_st_file open read_mode is "iofile.30";
variable v : positive_vector_st;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C27) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00623"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00623 - File reading operation (positive_vector_st file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00623arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc623.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:45 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:08 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:24 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00623ent IS
END c03s04b01x00p01n01i00623ent;
ARCHITECTURE c03s04b01x00p01n01i00623arch OF c03s04b01x00p01n01i00623ent IS
constant C4 : positive := 3 ;
type positive_vector is array (natural range <>) of positive;
subtype positive_vector_st is positive_vector(0 to 15);
type positive_vector_st_file is file of positive_vector_st;
constant C27 : positive_vector_st := (others => C4);
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : positive_vector_st_file open read_mode is "iofile.30";
variable v : positive_vector_st;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C27) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00623"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00623 - File reading operation (positive_vector_st file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00623arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc623.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:45 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:08 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:24 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00623ent IS
END c03s04b01x00p01n01i00623ent;
ARCHITECTURE c03s04b01x00p01n01i00623arch OF c03s04b01x00p01n01i00623ent IS
constant C4 : positive := 3 ;
type positive_vector is array (natural range <>) of positive;
subtype positive_vector_st is positive_vector(0 to 15);
type positive_vector_st_file is file of positive_vector_st;
constant C27 : positive_vector_st := (others => C4);
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : positive_vector_st_file open read_mode is "iofile.30";
variable v : positive_vector_st;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C27) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00623"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00623 - File reading operation (positive_vector_st file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00623arch;
|
-------------------------------------------------------------------------------
--! @file dpRam-e.vhd
--
--! @brief Dual Port Ram Entity
--
--! @details This is the DPRAM entity
--
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity dpRam is
generic (
--! Data width [bit]
gWordWidth : natural := 32;
--! Number of words
gNumberOfWords : natural := 1024;
--! Initialization file
gInitFile : string := "UNUSED"
);
port (
-- PORT A
--! Clock of port A
iClk_A : in std_logic;
--! Enable of port A
iEnable_A : in std_logic;
--! Write enable of port A
iWriteEnable_A : in std_logic;
--! Address of port A
iAddress_A : in std_logic_vector(logDualis(gNumberOfWords)-1 downto 0);
--! Byteenable of port A
iByteenable_A : in std_logic_vector(gWordWidth/8-1 downto 0);
--! Writedata of port A
iWritedata_A : in std_logic_vector(gWordWidth-1 downto 0);
--! Readdata of port A
oReaddata_A : out std_logic_vector(gWordWidth-1 downto 0);
-- PORT B
--! Clock of port B
iClk_B : in std_logic;
--! Enable of port B
iEnable_B : in std_logic;
--! Write enable of port B
iWriteEnable_B : in std_logic;
--! Byteenable of port B
iByteenable_B : in std_logic_vector(gWordWidth/8-1 downto 0);
--! Address of port B
iAddress_B : in std_logic_vector(logDualis(gNumberOfWords)-1 downto 0);
--! Writedata of port B
iWritedata_B : in std_logic_vector(gWordWidth-1 downto 0);
--! Readdata of port B
oReaddata_B : out std_logic_vector(gWordWidth-1 downto 0)
);
end dpRam;
|
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12608)
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12608)
`protect data_block
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|
`protect begin_protected
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12608)
`protect data_block
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|
`protect begin_protected
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12608)
`protect data_block
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|
---------------------------------------------------------------------
-- TITLE: Controller / Opcode Decoder
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: control.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- NOTE: MIPS(tm) is a registered trademark of MIPS Technologies.
-- MIPS Technologies does not endorse and is not associated with
-- this project.
-- DESCRIPTION:
-- Controls the CPU by decoding the opcode and generating control
-- signals to the rest of the CPU.
-- This entity decodes the MIPS(tm) opcode into a
-- Very-Long-Word-Instruction.
-- The 32-bit opcode is converted to a
-- 6+6+6+16+4+2+4+3+2+2+3+2+4 = 60 bit VLWI opcode.
-- Based on information found in:
-- "MIPS RISC Architecture" by Gerry Kane and Joe Heinrich
-- and "The Designer's Guide to VHDL" by Peter J. Ashenden
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * EPC register have been changed! It used to be R0, now it is R26
-- * added the instruction type and signal for debuging the CPU behaviour!
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity control is
port(opcode : in std_logic_vector(31 downto 0); -- not opcode, but the whole instruction !!! (opcode is the first 6 most significant bits of the instruction.)
intr_signal : in std_logic;
--NI_read_flag : in std_logic;
--NI_write_flag : in std_logic;
rs_index : out std_logic_vector(5 downto 0);
rt_index : out std_logic_vector(5 downto 0);
rd_index : out std_logic_vector(5 downto 0);
imm_out : out std_logic_vector(15 downto 0);
alu_func : out alu_function_type;
shift_func : out shift_function_type;
mult_func : out mult_function_type;
branch_func : out branch_function_type;
a_source_out : out a_source_type;
b_source_out : out b_source_type;
c_source_out : out c_source_type;
pc_source_out: out pc_source_type;
mem_source_out:out mem_source_type;
exception_out: out std_logic);
end; --entity control
architecture logic of control is
-- this type and the signal after it has been added for debugging!
-- you can comment this if you dont want to debug!
type instruction_name is (i_None, i_SLL, i_SRL, i_SRA, i_SLLV, i_SRLV, i_SRAV,
i_JR, i_JALR, i_SYSCALL, i_BREAK, i_SYNC, i_MFHI,
i_MTHI, i_MFLO, i_MTLO, i_MULT, i_MULTU, i_DIV, i_DIVU, i_ADD,
i_ADDU, i_SUB, i_SUBU, i_AND, i_OR, i_XOR, i_NOR, i_SLT,
i_SLTU, i_DADDU, i_BLTZAL, i_BLTZ, i_BGEZAL, i_BGEZ,
i_JAL, i_J, i_BEQ, i_BNE, i_BLEZ, i_BGTZ, i_ADDI,
i_ADDIU, i_SLTI, i_SLTIU, i_ANDI, i_ORI, i_XORI, i_LUI,
i_MFC0, i_MTC0, i_SUBI, i_LB, i_LH, i_LWL, i_LW, i_LBU,
i_LHU, i_SB, i_SH, i_SWL, i_SW);
signal instruction : instruction_name;
-- end of debugging block
begin
control_proc: process(opcode, intr_signal)
variable op, func : std_logic_vector(5 downto 0);
variable rs, rt, rd : std_logic_vector(5 downto 0);
variable rtx : std_logic_vector(4 downto 0);
variable imm : std_logic_vector(15 downto 0);
variable alu_function : alu_function_type;
variable shift_function : shift_function_type;
variable mult_function : mult_function_type;
variable a_source : a_source_type;
variable b_source : b_source_type;
variable c_source : c_source_type;
variable pc_source : pc_source_type;
variable branch_function: branch_function_type;
variable mem_source : mem_source_type;
variable is_syscall : std_logic;
begin
alu_function := ALU_NOTHING;
shift_function := SHIFT_NOTHING;
mult_function := MULT_NOTHING;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_REG_TARGET;
c_source := C_FROM_NULL;
pc_source := FROM_INC4;
branch_function := BRANCH_EQ;
mem_source := MEM_FETCH;
op := opcode(31 downto 26);
rs := '0' & opcode(25 downto 21);
rt := '0' & opcode(20 downto 16);
rtx := opcode(20 downto 16);
rd := '0' & opcode(15 downto 11);
func := opcode(5 downto 0);
imm := opcode(15 downto 0);
is_syscall := '0';
instruction <= i_None;
case op is
when "000000" => --SPECIAL
case func is
when "000000" => --SLL r[rd]=r[rt]<<re;
-- This is overlapping with NOP instruction in which all bits are zero, so opcode is zero and the last 6 bits (funct) are also zero,
-- does this mean that NOP acts as SLL ???
a_source := A_FROM_IMM10_6;
c_source := C_FROM_SHIFT;
shift_function := SHIFT_LEFT_UNSIGNED;
--Comment the next line if you dont want to debug!
instruction <= i_SLL;
when "000010" => --SRL r[rd]=u[rt]>>re;
a_source := A_FROM_IMM10_6;
c_source := C_FROM_shift;
shift_function := SHIFT_RIGHT_UNSIGNED;
--Comment the next line if you dont want to debug!
instruction <= i_SRL;
when "000011" => --SRA r[rd]=r[rt]>>re;
a_source := A_FROM_IMM10_6;
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_SIGNED;
--Comment the next line if you dont want to debug!
instruction <= i_SRL;
when "000100" => --SLLV r[rd]=r[rt]<<r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_LEFT_UNSIGNED;
--Comment the next line if you dont want to debug!
instruction <= i_SLLV;
when "000110" => --SRLV r[rd]=u[rt]>>r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_UNSIGNED;
--Comment the next line if you dont want to debug!
instruction <= i_SRLV;
when "000111" => --SRAV r[rd]=r[rt]>>r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_SIGNED;
--Comment the next line if you dont want to debug!
instruction <= i_SRAV;
when "001000" => --JR s->pc_next=r[rs];
pc_source := FROM_BRANCH;
alu_function := ALU_ADD;
branch_function := BRANCH_YES;
--Comment the next line if you dont want to debug!
instruction <= i_JR;
when "001001" => --JALR r[rd]=s->pc_next; s->pc_next=r[rs];
c_source := C_FROM_PC_PLUS4;
pc_source := FROM_BRANCH;
alu_function := ALU_ADD;
branch_function := BRANCH_YES;
--Comment the next line if you dont want to debug!
instruction <= i_JALR;
--when "001010" => --MOVZ if(!r[rt]) r[rd]=r[rs]; /*IV*/
--when "001011" => --MOVN if(r[rt]) r[rd]=r[rs]; /*IV*/
when "001100" => --SYSCALL
is_syscall := '1';
--Comment the next line if you dont want to debug!
instruction <= i_SYSCALL;
when "001101" => --BREAK s->wakeup=1;
is_syscall := '1';
--Comment the next line if you dont want to debug!
instruction <= i_BREAK;
--when "001111" => --SYNC s->wakeup=1;
when "010000" => --MFHI r[rd]=s->hi;
c_source := C_FROM_MULT;
mult_function := MULT_READ_HI;
--Comment the next line if you dont want to debug!
instruction <= i_MFHI;
when "010001" => --MTHI s->hi=r[rs];
mult_function := MULT_WRITE_HI;
--Comment the next line if you dont want to debug!
instruction <= i_MTHI;
when "010010" => --MFLO r[rd]=s->lo;
c_source := C_FROM_MULT;
mult_function := MULT_READ_LO;
--Comment the next line if you dont want to debug!
instruction <= i_MFLO;
when "010011" => --MTLO s->lo=r[rs];
mult_function := MULT_WRITE_LO;
--Comment the next line if you dont want to debug!
instruction <= i_MTLO;
when "011000" => --MULT s->lo=r[rs]*r[rt]; s->hi=0;
mult_function := MULT_SIGNED_MULT;
--Comment the next line if you dont want to debug!
instruction <= i_MULT;
when "011001" => --MULTU s->lo=r[rs]*r[rt]; s->hi=0;
mult_function := MULT_MULT;
--Comment the next line if you dont want to debug!
instruction <= i_MULTU;
when "011010" => --DIV s->lo=r[rs]/r[rt]; s->hi=r[rs]%r[rt];
mult_function := MULT_SIGNED_DIVIDE;
--Comment the next line if you dont want to debug!
instruction <= i_DIV;
when "011011" => --DIVU s->lo=r[rs]/r[rt]; s->hi=r[rs]%r[rt];
mult_function := MULT_DIVIDE;
--Comment the next line if you dont want to debug!
instruction <= i_DIVU;
when "100000" => --ADD r[rd]=r[rs]+r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
--Comment the next line if you dont want to debug!
instruction <= i_ADD;
when "100001" => --ADDU r[rd]=r[rs]+r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
--Comment the next line if you dont want to debug!
instruction <= i_ADDU;
when "100010" => --SUB r[rd]=r[rs]-r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_SUBTRACT;
--Comment the next line if you dont want to debug!
instruction <= i_SUB;
when "100011" => --SUBU r[rd]=r[rs]-r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_SUBTRACT;
--Comment the next line if you dont want to debug!
instruction <= i_SUBU;
when "100100" => --AND r[rd]=r[rs]&r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_AND;
--Comment the next line if you dont want to debug!
instruction <= i_AND;
when "100101" => --OR r[rd]=r[rs]|r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_OR;
--Comment the next line if you dont want to debug!
instruction <= i_OR;
when "100110" => --XOR r[rd]=r[rs]^r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_XOR;
--Comment the next line if you dont want to debug!
instruction <= i_XOR;
when "100111" => --NOR r[rd]=~(r[rs]|r[rt]);
c_source := C_FROM_ALU;
alu_function := ALU_NOR;
--Comment the next line if you dont want to debug!
instruction <= i_NOR;
when "101010" => --SLT r[rd]=r[rs]<r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_LESS_THAN_SIGNED;
--Comment the next line if you dont want to debug!
instruction <= i_SLT;
when "101011" => --SLTU r[rd]=u[rs]<u[rt];
c_source := C_FROM_ALU;
alu_function := ALU_LESS_THAN;
--Comment the next line if you dont want to debug!
instruction <= i_SLTU;
when "101101" => --DADDU r[rd]=r[rs]+u[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
--Comment the next line if you dont want to debug!
instruction <= i_DADDU;
--when "110001" => --TGEU
--when "110010" => --TLT
--when "110011" => --TLTU
--when "110100" => --TEQ
--when "110110" => --TNE
when others =>
end case;
when "000001" => --REGIMM
rt := "000000";
rd := "011111";
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_GTZ;
--if(test) pc=pc+imm*4
case rtx is
when "10000" => --BLTZAL r[31]=s->pc_next; branch=r[rs]<0;
c_source := C_FROM_PC_PLUS4;
branch_function := BRANCH_LTZ;
--Comment the next line if you dont want to debug!
instruction <= i_BLTZAL;
when "00000" => --BLTZ branch=r[rs]<0;
branch_function := BRANCH_LTZ;
--Comment the next line if you dont want to debug!
instruction <= i_BLTZ;
when "10001" => --BGEZAL r[31]=s->pc_next; branch=r[rs]>=0;
c_source := C_FROM_PC_PLUS4;
branch_function := BRANCH_GEZ;
--Comment the next line if you dont want to debug!
instruction <= i_BGEZAL;
when "00001" => --BGEZ branch=r[rs]>=0;
branch_function := BRANCH_GEZ;
--Comment the next line if you dont want to debug!
instruction <= i_BGEZ;
--when "10010" => --BLTZALL r[31]=s->pc_next; lbranch=r[rs]<0;
--when "00010" => --BLTZL lbranch=r[rs]<0;
--when "10011" => --BGEZALL r[31]=s->pc_next; lbranch=r[rs]>=0;
--when "00011" => --BGEZL lbranch=r[rs]>=0;
when others =>
end case;
when "000011" => --JAL r[31]=s->pc_next; s->pc_next=(s->pc&0xf0000000)|target;
c_source := C_FROM_PC_PLUS4;
rd := "011111";
pc_source := FROM_OPCODE25_0;
--Comment the next line if you dont want to debug!
instruction <= i_JAL;
when "000010" => --J s->pc_next=(s->pc&0xf0000000)|target;
pc_source := FROM_OPCODE25_0;
--Comment the next line if you dont want to debug!
instruction <= i_J;
when "000100" => --BEQ branch=r[rs]==r[rt];
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_EQ;
--Comment the next line if you dont want to debug!
instruction <= i_BEQ;
when "000101" => --BNE branch=r[rs]!=r[rt];
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_NE;
--Comment the next line if you dont want to debug!
instruction <= i_BNE;
when "000110" => --BLEZ branch=r[rs]<=0;
a_source := A_FROM_PC;
b_source := b_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_LEZ;
--Comment the next line if you dont want to debug!
instruction <= i_BLEZ;
when "000111" => --BGTZ branch=r[rs]>0;
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_GTZ;
--Comment the next line if you dont want to debug!
instruction <= i_BGTZ;
when "001000" => --ADDI r[rt]=r[rs]+(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_ADD;
--Comment the next line if you dont want to debug!
instruction <= i_ADDI;
when "001001" => --ADDIU u[rt]=u[rs]+(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_ADD;
--Comment the next line if you dont want to debug!
instruction <= i_ADDIU;
when "001010" => --SLTI r[rt]=r[rs]<(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_LESS_THAN_SIGNED;
--Comment the next line if you dont want to debug!
instruction <= i_SLTI;
when "001011" => --SLTIU u[rt]=u[rs]<(unsigned long)(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_LESS_THAN;
--Comment the next line if you dont want to debug!
instruction <= i_SLTIU;
when "001100" => --ANDI r[rt]=r[rs]&imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_AND;
--Comment the next line if you dont want to debug!
instruction <= i_ANDI;
when "001101" => --ORI r[rt]=r[rs]|imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_OR;
--Comment the next line if you dont want to debug!
instruction <= i_ORI;
when "001110" => --XORI r[rt]=r[rs]^imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_XOR;
--Comment the next line if you dont want to debug!
instruction <= i_XORI;
when "001111" => --LUI r[rt]=(imm<<16);
c_source := C_FROM_IMM_SHIFT16;
rd := rt;
--Comment the next line if you dont want to debug!
instruction <= i_LUI;
when "010000" => --COP0
alu_function := ALU_OR;
c_source := C_FROM_ALU;
if opcode(23) = '0' then --move from CP0
rs := '1' & opcode(15 downto 11);
rt := "000000";
rd := '0' & opcode(20 downto 16);
--Comment the next line if you dont want to debug!
instruction <= i_MFC0;
else --move to CP0
rs := "000000";
rd(5) := '1';
pc_source := FROM_BRANCH; --delay possible interrupt
branch_function := BRANCH_NO;
--Comment the next line if you dont want to debug!
instruction <= i_MTC0;
end if;
--when "010001" => --COP1
--when "010010" => --COP2
--when "010011" => --COP3
--when "010100" => --BEQL lbranch=r[rs]==r[rt];
--when "010101" => --BNEL lbranch=r[rs]!=r[rt];
--when "010110" => --BLEZL lbranch=r[rs]<=0;
--when "010111" => --BGTZL lbranch=r[rs]>0;
when "011010" => -- SUBI r[rt]=r[rs]-(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_SUBTRACT;
--Comment the next line if you dont want to debug!
instruction <= i_SUBI;
when "100000" => --LB r[rt]=*(signed char*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ8S; --address=(short)imm+r[rs];
--Comment the next line if you dont want to debug!
instruction <= i_LB;
when "100001" => --LH r[rt]=*(signed short*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ16S; --address=(short)imm+r[rs];
--Comment the next line if you dont want to debug!
instruction <= i_LH;
when "100010" => --LWL //Not Implemented
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ32;
--Comment the next line if you dont want to debug!
instruction <= i_LWL;
when "100011" => --LW r[rt]=*(long*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ32;
--Comment the next line if you dont want to debug!
instruction <= i_LW;
when "100100" => --LBU r[rt]=*(unsigned char*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ8; --address=(short)imm+r[rs];
--Comment the next line if you dont want to debug!
instruction <= i_LBU;
when "100101" => --LHU r[rt]=*(unsigned short*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ16; --address=(short)imm+r[rs];
--Comment the next line if you dont want to debug!
instruction <= i_LHU;
--when "100110" => --LWR //Not Implemented
when "101000" => --SB *(char*)ptr=(char)r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE8; --address=(short)imm+r[rs];
--Comment the next line if you dont want to debug!
instruction <= i_SB;
when "101001" => --SH *(short*)ptr=(short)r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE16;
--Comment the next line if you dont want to debug!
instruction <= i_SH;
when "101010" => --SWL //Not Implemented
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE32; --address=(short)imm+r[rs];
--Comment the next line if you dont want to debug!
instruction <= i_SWL;
when "101011" => --SW *(long*)ptr=r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE32; --address=(short)imm+r[rs];
--Comment the next line if you dont want to debug!
instruction <= i_SW;
--when "101110" => --SWR //Not Implemented
--when "101111" => --CACHE
--when "110000" => --LL r[rt]=*(long*)ptr;
--when "110001" => --LWC1
--when "110010" => --LWC2
--when "110011" => --LWC3
--when "110101" => --LDC1
--when "110110" => --LDC2
--when "110111" => --LDC3
--when "111000" => --SC *(long*)ptr=r[rt]; r[rt]=1;
--when "111001" => --SWC1
--when "111010" => --SWC2
--when "111011" => --SWC3
--when "111101" => --SDC1
--when "111110" => --SDC2
--when "111111" => --SDC3
when others =>
end case;
if c_source = C_FROM_NULL then
rd := "000000";
end if;
if intr_signal = '1' or is_syscall = '1' then
rs := "111111"; --interrupt vector
rt := "000000";
rd := "101110"; --save PC in EPC
alu_function := ALU_OR;
shift_function := SHIFT_NOTHING;
mult_function := MULT_NOTHING;
branch_function := BRANCH_YES;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_REG_TARGET;
c_source := C_FROM_PC;
pc_source := FROM_LBRANCH; -- "11"
mem_source := MEM_FETCH;
exception_out <= '1';
else
exception_out <= '0';
end if;
rs_index <= rs;
rt_index <= rt;
rd_index <= rd;
imm_out <= imm;
alu_func <= alu_function;
shift_func <= shift_function;
mult_func <= mult_function;
branch_func <= branch_function;
a_source_out <= a_source;
b_source_out <= b_source;
c_source_out <= c_source;
pc_source_out <= pc_source;
mem_source_out <= mem_source;
end process;
end; --logic
|
---------------------------------------------------------------------
-- TITLE: Controller / Opcode Decoder
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: control.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- NOTE: MIPS(tm) is a registered trademark of MIPS Technologies.
-- MIPS Technologies does not endorse and is not associated with
-- this project.
-- DESCRIPTION:
-- Controls the CPU by decoding the opcode and generating control
-- signals to the rest of the CPU.
-- This entity decodes the MIPS(tm) opcode into a
-- Very-Long-Word-Instruction.
-- The 32-bit opcode is converted to a
-- 6+6+6+16+4+2+4+3+2+2+3+2+4 = 60 bit VLWI opcode.
-- Based on information found in:
-- "MIPS RISC Architecture" by Gerry Kane and Joe Heinrich
-- and "The Designer's Guide to VHDL" by Peter J. Ashenden
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * EPC register have been changed! It used to be R0, now it is R26
-- * added the instruction type and signal for debuging the CPU behaviour!
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity control is
port(opcode : in std_logic_vector(31 downto 0); -- not opcode, but the whole instruction !!! (opcode is the first 6 most significant bits of the instruction.)
intr_signal : in std_logic;
--NI_read_flag : in std_logic;
--NI_write_flag : in std_logic;
rs_index : out std_logic_vector(5 downto 0);
rt_index : out std_logic_vector(5 downto 0);
rd_index : out std_logic_vector(5 downto 0);
imm_out : out std_logic_vector(15 downto 0);
alu_func : out alu_function_type;
shift_func : out shift_function_type;
mult_func : out mult_function_type;
branch_func : out branch_function_type;
a_source_out : out a_source_type;
b_source_out : out b_source_type;
c_source_out : out c_source_type;
pc_source_out: out pc_source_type;
mem_source_out:out mem_source_type;
exception_out: out std_logic);
end; --entity control
architecture logic of control is
-- this type and the signal after it has been added for debugging!
-- you can comment this if you dont want to debug!
type instruction_name is (i_None, i_SLL, i_SRL, i_SRA, i_SLLV, i_SRLV, i_SRAV,
i_JR, i_JALR, i_SYSCALL, i_BREAK, i_SYNC, i_MFHI,
i_MTHI, i_MFLO, i_MTLO, i_MULT, i_MULTU, i_DIV, i_DIVU, i_ADD,
i_ADDU, i_SUB, i_SUBU, i_AND, i_OR, i_XOR, i_NOR, i_SLT,
i_SLTU, i_DADDU, i_BLTZAL, i_BLTZ, i_BGEZAL, i_BGEZ,
i_JAL, i_J, i_BEQ, i_BNE, i_BLEZ, i_BGTZ, i_ADDI,
i_ADDIU, i_SLTI, i_SLTIU, i_ANDI, i_ORI, i_XORI, i_LUI,
i_MFC0, i_MTC0, i_SUBI, i_LB, i_LH, i_LWL, i_LW, i_LBU,
i_LHU, i_SB, i_SH, i_SWL, i_SW);
signal instruction : instruction_name;
-- end of debugging block
begin
control_proc: process(opcode, intr_signal)
variable op, func : std_logic_vector(5 downto 0);
variable rs, rt, rd : std_logic_vector(5 downto 0);
variable rtx : std_logic_vector(4 downto 0);
variable imm : std_logic_vector(15 downto 0);
variable alu_function : alu_function_type;
variable shift_function : shift_function_type;
variable mult_function : mult_function_type;
variable a_source : a_source_type;
variable b_source : b_source_type;
variable c_source : c_source_type;
variable pc_source : pc_source_type;
variable branch_function: branch_function_type;
variable mem_source : mem_source_type;
variable is_syscall : std_logic;
begin
alu_function := ALU_NOTHING;
shift_function := SHIFT_NOTHING;
mult_function := MULT_NOTHING;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_REG_TARGET;
c_source := C_FROM_NULL;
pc_source := FROM_INC4;
branch_function := BRANCH_EQ;
mem_source := MEM_FETCH;
op := opcode(31 downto 26);
rs := '0' & opcode(25 downto 21);
rt := '0' & opcode(20 downto 16);
rtx := opcode(20 downto 16);
rd := '0' & opcode(15 downto 11);
func := opcode(5 downto 0);
imm := opcode(15 downto 0);
is_syscall := '0';
instruction <= i_None;
case op is
when "000000" => --SPECIAL
case func is
when "000000" => --SLL r[rd]=r[rt]<<re;
-- This is overlapping with NOP instruction in which all bits are zero, so opcode is zero and the last 6 bits (funct) are also zero,
-- does this mean that NOP acts as SLL ???
a_source := A_FROM_IMM10_6;
c_source := C_FROM_SHIFT;
shift_function := SHIFT_LEFT_UNSIGNED;
--Comment the next line if you dont want to debug!
instruction <= i_SLL;
when "000010" => --SRL r[rd]=u[rt]>>re;
a_source := A_FROM_IMM10_6;
c_source := C_FROM_shift;
shift_function := SHIFT_RIGHT_UNSIGNED;
--Comment the next line if you dont want to debug!
instruction <= i_SRL;
when "000011" => --SRA r[rd]=r[rt]>>re;
a_source := A_FROM_IMM10_6;
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_SIGNED;
--Comment the next line if you dont want to debug!
instruction <= i_SRL;
when "000100" => --SLLV r[rd]=r[rt]<<r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_LEFT_UNSIGNED;
--Comment the next line if you dont want to debug!
instruction <= i_SLLV;
when "000110" => --SRLV r[rd]=u[rt]>>r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_UNSIGNED;
--Comment the next line if you dont want to debug!
instruction <= i_SRLV;
when "000111" => --SRAV r[rd]=r[rt]>>r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_SIGNED;
--Comment the next line if you dont want to debug!
instruction <= i_SRAV;
when "001000" => --JR s->pc_next=r[rs];
pc_source := FROM_BRANCH;
alu_function := ALU_ADD;
branch_function := BRANCH_YES;
--Comment the next line if you dont want to debug!
instruction <= i_JR;
when "001001" => --JALR r[rd]=s->pc_next; s->pc_next=r[rs];
c_source := C_FROM_PC_PLUS4;
pc_source := FROM_BRANCH;
alu_function := ALU_ADD;
branch_function := BRANCH_YES;
--Comment the next line if you dont want to debug!
instruction <= i_JALR;
--when "001010" => --MOVZ if(!r[rt]) r[rd]=r[rs]; /*IV*/
--when "001011" => --MOVN if(r[rt]) r[rd]=r[rs]; /*IV*/
when "001100" => --SYSCALL
is_syscall := '1';
--Comment the next line if you dont want to debug!
instruction <= i_SYSCALL;
when "001101" => --BREAK s->wakeup=1;
is_syscall := '1';
--Comment the next line if you dont want to debug!
instruction <= i_BREAK;
--when "001111" => --SYNC s->wakeup=1;
when "010000" => --MFHI r[rd]=s->hi;
c_source := C_FROM_MULT;
mult_function := MULT_READ_HI;
--Comment the next line if you dont want to debug!
instruction <= i_MFHI;
when "010001" => --MTHI s->hi=r[rs];
mult_function := MULT_WRITE_HI;
--Comment the next line if you dont want to debug!
instruction <= i_MTHI;
when "010010" => --MFLO r[rd]=s->lo;
c_source := C_FROM_MULT;
mult_function := MULT_READ_LO;
--Comment the next line if you dont want to debug!
instruction <= i_MFLO;
when "010011" => --MTLO s->lo=r[rs];
mult_function := MULT_WRITE_LO;
--Comment the next line if you dont want to debug!
instruction <= i_MTLO;
when "011000" => --MULT s->lo=r[rs]*r[rt]; s->hi=0;
mult_function := MULT_SIGNED_MULT;
--Comment the next line if you dont want to debug!
instruction <= i_MULT;
when "011001" => --MULTU s->lo=r[rs]*r[rt]; s->hi=0;
mult_function := MULT_MULT;
--Comment the next line if you dont want to debug!
instruction <= i_MULTU;
when "011010" => --DIV s->lo=r[rs]/r[rt]; s->hi=r[rs]%r[rt];
mult_function := MULT_SIGNED_DIVIDE;
--Comment the next line if you dont want to debug!
instruction <= i_DIV;
when "011011" => --DIVU s->lo=r[rs]/r[rt]; s->hi=r[rs]%r[rt];
mult_function := MULT_DIVIDE;
--Comment the next line if you dont want to debug!
instruction <= i_DIVU;
when "100000" => --ADD r[rd]=r[rs]+r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
--Comment the next line if you dont want to debug!
instruction <= i_ADD;
when "100001" => --ADDU r[rd]=r[rs]+r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
--Comment the next line if you dont want to debug!
instruction <= i_ADDU;
when "100010" => --SUB r[rd]=r[rs]-r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_SUBTRACT;
--Comment the next line if you dont want to debug!
instruction <= i_SUB;
when "100011" => --SUBU r[rd]=r[rs]-r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_SUBTRACT;
--Comment the next line if you dont want to debug!
instruction <= i_SUBU;
when "100100" => --AND r[rd]=r[rs]&r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_AND;
--Comment the next line if you dont want to debug!
instruction <= i_AND;
when "100101" => --OR r[rd]=r[rs]|r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_OR;
--Comment the next line if you dont want to debug!
instruction <= i_OR;
when "100110" => --XOR r[rd]=r[rs]^r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_XOR;
--Comment the next line if you dont want to debug!
instruction <= i_XOR;
when "100111" => --NOR r[rd]=~(r[rs]|r[rt]);
c_source := C_FROM_ALU;
alu_function := ALU_NOR;
--Comment the next line if you dont want to debug!
instruction <= i_NOR;
when "101010" => --SLT r[rd]=r[rs]<r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_LESS_THAN_SIGNED;
--Comment the next line if you dont want to debug!
instruction <= i_SLT;
when "101011" => --SLTU r[rd]=u[rs]<u[rt];
c_source := C_FROM_ALU;
alu_function := ALU_LESS_THAN;
--Comment the next line if you dont want to debug!
instruction <= i_SLTU;
when "101101" => --DADDU r[rd]=r[rs]+u[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
--Comment the next line if you dont want to debug!
instruction <= i_DADDU;
--when "110001" => --TGEU
--when "110010" => --TLT
--when "110011" => --TLTU
--when "110100" => --TEQ
--when "110110" => --TNE
when others =>
end case;
when "000001" => --REGIMM
rt := "000000";
rd := "011111";
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_GTZ;
--if(test) pc=pc+imm*4
case rtx is
when "10000" => --BLTZAL r[31]=s->pc_next; branch=r[rs]<0;
c_source := C_FROM_PC_PLUS4;
branch_function := BRANCH_LTZ;
--Comment the next line if you dont want to debug!
instruction <= i_BLTZAL;
when "00000" => --BLTZ branch=r[rs]<0;
branch_function := BRANCH_LTZ;
--Comment the next line if you dont want to debug!
instruction <= i_BLTZ;
when "10001" => --BGEZAL r[31]=s->pc_next; branch=r[rs]>=0;
c_source := C_FROM_PC_PLUS4;
branch_function := BRANCH_GEZ;
--Comment the next line if you dont want to debug!
instruction <= i_BGEZAL;
when "00001" => --BGEZ branch=r[rs]>=0;
branch_function := BRANCH_GEZ;
--Comment the next line if you dont want to debug!
instruction <= i_BGEZ;
--when "10010" => --BLTZALL r[31]=s->pc_next; lbranch=r[rs]<0;
--when "00010" => --BLTZL lbranch=r[rs]<0;
--when "10011" => --BGEZALL r[31]=s->pc_next; lbranch=r[rs]>=0;
--when "00011" => --BGEZL lbranch=r[rs]>=0;
when others =>
end case;
when "000011" => --JAL r[31]=s->pc_next; s->pc_next=(s->pc&0xf0000000)|target;
c_source := C_FROM_PC_PLUS4;
rd := "011111";
pc_source := FROM_OPCODE25_0;
--Comment the next line if you dont want to debug!
instruction <= i_JAL;
when "000010" => --J s->pc_next=(s->pc&0xf0000000)|target;
pc_source := FROM_OPCODE25_0;
--Comment the next line if you dont want to debug!
instruction <= i_J;
when "000100" => --BEQ branch=r[rs]==r[rt];
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_EQ;
--Comment the next line if you dont want to debug!
instruction <= i_BEQ;
when "000101" => --BNE branch=r[rs]!=r[rt];
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_NE;
--Comment the next line if you dont want to debug!
instruction <= i_BNE;
when "000110" => --BLEZ branch=r[rs]<=0;
a_source := A_FROM_PC;
b_source := b_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_LEZ;
--Comment the next line if you dont want to debug!
instruction <= i_BLEZ;
when "000111" => --BGTZ branch=r[rs]>0;
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_GTZ;
--Comment the next line if you dont want to debug!
instruction <= i_BGTZ;
when "001000" => --ADDI r[rt]=r[rs]+(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_ADD;
--Comment the next line if you dont want to debug!
instruction <= i_ADDI;
when "001001" => --ADDIU u[rt]=u[rs]+(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_ADD;
--Comment the next line if you dont want to debug!
instruction <= i_ADDIU;
when "001010" => --SLTI r[rt]=r[rs]<(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_LESS_THAN_SIGNED;
--Comment the next line if you dont want to debug!
instruction <= i_SLTI;
when "001011" => --SLTIU u[rt]=u[rs]<(unsigned long)(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_LESS_THAN;
--Comment the next line if you dont want to debug!
instruction <= i_SLTIU;
when "001100" => --ANDI r[rt]=r[rs]&imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_AND;
--Comment the next line if you dont want to debug!
instruction <= i_ANDI;
when "001101" => --ORI r[rt]=r[rs]|imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_OR;
--Comment the next line if you dont want to debug!
instruction <= i_ORI;
when "001110" => --XORI r[rt]=r[rs]^imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_XOR;
--Comment the next line if you dont want to debug!
instruction <= i_XORI;
when "001111" => --LUI r[rt]=(imm<<16);
c_source := C_FROM_IMM_SHIFT16;
rd := rt;
--Comment the next line if you dont want to debug!
instruction <= i_LUI;
when "010000" => --COP0
alu_function := ALU_OR;
c_source := C_FROM_ALU;
if opcode(23) = '0' then --move from CP0
rs := '1' & opcode(15 downto 11);
rt := "000000";
rd := '0' & opcode(20 downto 16);
--Comment the next line if you dont want to debug!
instruction <= i_MFC0;
else --move to CP0
rs := "000000";
rd(5) := '1';
pc_source := FROM_BRANCH; --delay possible interrupt
branch_function := BRANCH_NO;
--Comment the next line if you dont want to debug!
instruction <= i_MTC0;
end if;
--when "010001" => --COP1
--when "010010" => --COP2
--when "010011" => --COP3
--when "010100" => --BEQL lbranch=r[rs]==r[rt];
--when "010101" => --BNEL lbranch=r[rs]!=r[rt];
--when "010110" => --BLEZL lbranch=r[rs]<=0;
--when "010111" => --BGTZL lbranch=r[rs]>0;
when "011010" => -- SUBI r[rt]=r[rs]-(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_SUBTRACT;
--Comment the next line if you dont want to debug!
instruction <= i_SUBI;
when "100000" => --LB r[rt]=*(signed char*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ8S; --address=(short)imm+r[rs];
--Comment the next line if you dont want to debug!
instruction <= i_LB;
when "100001" => --LH r[rt]=*(signed short*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ16S; --address=(short)imm+r[rs];
--Comment the next line if you dont want to debug!
instruction <= i_LH;
when "100010" => --LWL //Not Implemented
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ32;
--Comment the next line if you dont want to debug!
instruction <= i_LWL;
when "100011" => --LW r[rt]=*(long*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ32;
--Comment the next line if you dont want to debug!
instruction <= i_LW;
when "100100" => --LBU r[rt]=*(unsigned char*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ8; --address=(short)imm+r[rs];
--Comment the next line if you dont want to debug!
instruction <= i_LBU;
when "100101" => --LHU r[rt]=*(unsigned short*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ16; --address=(short)imm+r[rs];
--Comment the next line if you dont want to debug!
instruction <= i_LHU;
--when "100110" => --LWR //Not Implemented
when "101000" => --SB *(char*)ptr=(char)r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE8; --address=(short)imm+r[rs];
--Comment the next line if you dont want to debug!
instruction <= i_SB;
when "101001" => --SH *(short*)ptr=(short)r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE16;
--Comment the next line if you dont want to debug!
instruction <= i_SH;
when "101010" => --SWL //Not Implemented
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE32; --address=(short)imm+r[rs];
--Comment the next line if you dont want to debug!
instruction <= i_SWL;
when "101011" => --SW *(long*)ptr=r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE32; --address=(short)imm+r[rs];
--Comment the next line if you dont want to debug!
instruction <= i_SW;
--when "101110" => --SWR //Not Implemented
--when "101111" => --CACHE
--when "110000" => --LL r[rt]=*(long*)ptr;
--when "110001" => --LWC1
--when "110010" => --LWC2
--when "110011" => --LWC3
--when "110101" => --LDC1
--when "110110" => --LDC2
--when "110111" => --LDC3
--when "111000" => --SC *(long*)ptr=r[rt]; r[rt]=1;
--when "111001" => --SWC1
--when "111010" => --SWC2
--when "111011" => --SWC3
--when "111101" => --SDC1
--when "111110" => --SDC2
--when "111111" => --SDC3
when others =>
end case;
if c_source = C_FROM_NULL then
rd := "000000";
end if;
if intr_signal = '1' or is_syscall = '1' then
rs := "111111"; --interrupt vector
rt := "000000";
rd := "101110"; --save PC in EPC
alu_function := ALU_OR;
shift_function := SHIFT_NOTHING;
mult_function := MULT_NOTHING;
branch_function := BRANCH_YES;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_REG_TARGET;
c_source := C_FROM_PC;
pc_source := FROM_LBRANCH; -- "11"
mem_source := MEM_FETCH;
exception_out <= '1';
else
exception_out <= '0';
end if;
rs_index <= rs;
rt_index <= rt;
rd_index <= rd;
imm_out <= imm;
alu_func <= alu_function;
shift_func <= shift_function;
mult_func <= mult_function;
branch_func <= branch_function;
a_source_out <= a_source;
b_source_out <= b_source;
c_source_out <= c_source;
pc_source_out <= pc_source;
mem_source_out <= mem_source;
end process;
end; --logic
|
---------------------------------------------------------------------
-- TITLE: Controller / Opcode Decoder
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: control.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- NOTE: MIPS(tm) is a registered trademark of MIPS Technologies.
-- MIPS Technologies does not endorse and is not associated with
-- this project.
-- DESCRIPTION:
-- Controls the CPU by decoding the opcode and generating control
-- signals to the rest of the CPU.
-- This entity decodes the MIPS(tm) opcode into a
-- Very-Long-Word-Instruction.
-- The 32-bit opcode is converted to a
-- 6+6+6+16+4+2+4+3+2+2+3+2+4 = 60 bit VLWI opcode.
-- Based on information found in:
-- "MIPS RISC Architecture" by Gerry Kane and Joe Heinrich
-- and "The Designer's Guide to VHDL" by Peter J. Ashenden
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * EPC register have been changed! It used to be R0, now it is R26
-- * added the instruction type and signal for debuging the CPU behaviour!
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity control is
port(opcode : in std_logic_vector(31 downto 0); -- not opcode, but the whole instruction !!! (opcode is the first 6 most significant bits of the instruction.)
intr_signal : in std_logic;
--NI_read_flag : in std_logic;
--NI_write_flag : in std_logic;
rs_index : out std_logic_vector(5 downto 0);
rt_index : out std_logic_vector(5 downto 0);
rd_index : out std_logic_vector(5 downto 0);
imm_out : out std_logic_vector(15 downto 0);
alu_func : out alu_function_type;
shift_func : out shift_function_type;
mult_func : out mult_function_type;
branch_func : out branch_function_type;
a_source_out : out a_source_type;
b_source_out : out b_source_type;
c_source_out : out c_source_type;
pc_source_out: out pc_source_type;
mem_source_out:out mem_source_type;
exception_out: out std_logic);
end; --entity control
architecture logic of control is
-- this type and the signal after it has been added for debugging!
-- you can comment this if you dont want to debug!
type instruction_name is (i_None, i_SLL, i_SRL, i_SRA, i_SLLV, i_SRLV, i_SRAV,
i_JR, i_JALR, i_SYSCALL, i_BREAK, i_SYNC, i_MFHI,
i_MTHI, i_MFLO, i_MTLO, i_MULT, i_MULTU, i_DIV, i_DIVU, i_ADD,
i_ADDU, i_SUB, i_SUBU, i_AND, i_OR, i_XOR, i_NOR, i_SLT,
i_SLTU, i_DADDU, i_BLTZAL, i_BLTZ, i_BGEZAL, i_BGEZ,
i_JAL, i_J, i_BEQ, i_BNE, i_BLEZ, i_BGTZ, i_ADDI,
i_ADDIU, i_SLTI, i_SLTIU, i_ANDI, i_ORI, i_XORI, i_LUI,
i_MFC0, i_MTC0, i_SUBI, i_LB, i_LH, i_LWL, i_LW, i_LBU,
i_LHU, i_SB, i_SH, i_SWL, i_SW);
signal instruction : instruction_name;
-- end of debugging block
begin
control_proc: process(opcode, intr_signal)
variable op, func : std_logic_vector(5 downto 0);
variable rs, rt, rd : std_logic_vector(5 downto 0);
variable rtx : std_logic_vector(4 downto 0);
variable imm : std_logic_vector(15 downto 0);
variable alu_function : alu_function_type;
variable shift_function : shift_function_type;
variable mult_function : mult_function_type;
variable a_source : a_source_type;
variable b_source : b_source_type;
variable c_source : c_source_type;
variable pc_source : pc_source_type;
variable branch_function: branch_function_type;
variable mem_source : mem_source_type;
variable is_syscall : std_logic;
begin
alu_function := ALU_NOTHING;
shift_function := SHIFT_NOTHING;
mult_function := MULT_NOTHING;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_REG_TARGET;
c_source := C_FROM_NULL;
pc_source := FROM_INC4;
branch_function := BRANCH_EQ;
mem_source := MEM_FETCH;
op := opcode(31 downto 26);
rs := '0' & opcode(25 downto 21);
rt := '0' & opcode(20 downto 16);
rtx := opcode(20 downto 16);
rd := '0' & opcode(15 downto 11);
func := opcode(5 downto 0);
imm := opcode(15 downto 0);
is_syscall := '0';
instruction <= i_None;
case op is
when "000000" => --SPECIAL
case func is
when "000000" => --SLL r[rd]=r[rt]<<re;
-- This is overlapping with NOP instruction in which all bits are zero, so opcode is zero and the last 6 bits (funct) are also zero,
-- does this mean that NOP acts as SLL ???
a_source := A_FROM_IMM10_6;
c_source := C_FROM_SHIFT;
shift_function := SHIFT_LEFT_UNSIGNED;
--Comment the next line if you dont want to debug!
instruction <= i_SLL;
when "000010" => --SRL r[rd]=u[rt]>>re;
a_source := A_FROM_IMM10_6;
c_source := C_FROM_shift;
shift_function := SHIFT_RIGHT_UNSIGNED;
--Comment the next line if you dont want to debug!
instruction <= i_SRL;
when "000011" => --SRA r[rd]=r[rt]>>re;
a_source := A_FROM_IMM10_6;
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_SIGNED;
--Comment the next line if you dont want to debug!
instruction <= i_SRL;
when "000100" => --SLLV r[rd]=r[rt]<<r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_LEFT_UNSIGNED;
--Comment the next line if you dont want to debug!
instruction <= i_SLLV;
when "000110" => --SRLV r[rd]=u[rt]>>r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_UNSIGNED;
--Comment the next line if you dont want to debug!
instruction <= i_SRLV;
when "000111" => --SRAV r[rd]=r[rt]>>r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_SIGNED;
--Comment the next line if you dont want to debug!
instruction <= i_SRAV;
when "001000" => --JR s->pc_next=r[rs];
pc_source := FROM_BRANCH;
alu_function := ALU_ADD;
branch_function := BRANCH_YES;
--Comment the next line if you dont want to debug!
instruction <= i_JR;
when "001001" => --JALR r[rd]=s->pc_next; s->pc_next=r[rs];
c_source := C_FROM_PC_PLUS4;
pc_source := FROM_BRANCH;
alu_function := ALU_ADD;
branch_function := BRANCH_YES;
--Comment the next line if you dont want to debug!
instruction <= i_JALR;
--when "001010" => --MOVZ if(!r[rt]) r[rd]=r[rs]; /*IV*/
--when "001011" => --MOVN if(r[rt]) r[rd]=r[rs]; /*IV*/
when "001100" => --SYSCALL
is_syscall := '1';
--Comment the next line if you dont want to debug!
instruction <= i_SYSCALL;
when "001101" => --BREAK s->wakeup=1;
is_syscall := '1';
--Comment the next line if you dont want to debug!
instruction <= i_BREAK;
--when "001111" => --SYNC s->wakeup=1;
when "010000" => --MFHI r[rd]=s->hi;
c_source := C_FROM_MULT;
mult_function := MULT_READ_HI;
--Comment the next line if you dont want to debug!
instruction <= i_MFHI;
when "010001" => --MTHI s->hi=r[rs];
mult_function := MULT_WRITE_HI;
--Comment the next line if you dont want to debug!
instruction <= i_MTHI;
when "010010" => --MFLO r[rd]=s->lo;
c_source := C_FROM_MULT;
mult_function := MULT_READ_LO;
--Comment the next line if you dont want to debug!
instruction <= i_MFLO;
when "010011" => --MTLO s->lo=r[rs];
mult_function := MULT_WRITE_LO;
--Comment the next line if you dont want to debug!
instruction <= i_MTLO;
when "011000" => --MULT s->lo=r[rs]*r[rt]; s->hi=0;
mult_function := MULT_SIGNED_MULT;
--Comment the next line if you dont want to debug!
instruction <= i_MULT;
when "011001" => --MULTU s->lo=r[rs]*r[rt]; s->hi=0;
mult_function := MULT_MULT;
--Comment the next line if you dont want to debug!
instruction <= i_MULTU;
when "011010" => --DIV s->lo=r[rs]/r[rt]; s->hi=r[rs]%r[rt];
mult_function := MULT_SIGNED_DIVIDE;
--Comment the next line if you dont want to debug!
instruction <= i_DIV;
when "011011" => --DIVU s->lo=r[rs]/r[rt]; s->hi=r[rs]%r[rt];
mult_function := MULT_DIVIDE;
--Comment the next line if you dont want to debug!
instruction <= i_DIVU;
when "100000" => --ADD r[rd]=r[rs]+r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
--Comment the next line if you dont want to debug!
instruction <= i_ADD;
when "100001" => --ADDU r[rd]=r[rs]+r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
--Comment the next line if you dont want to debug!
instruction <= i_ADDU;
when "100010" => --SUB r[rd]=r[rs]-r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_SUBTRACT;
--Comment the next line if you dont want to debug!
instruction <= i_SUB;
when "100011" => --SUBU r[rd]=r[rs]-r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_SUBTRACT;
--Comment the next line if you dont want to debug!
instruction <= i_SUBU;
when "100100" => --AND r[rd]=r[rs]&r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_AND;
--Comment the next line if you dont want to debug!
instruction <= i_AND;
when "100101" => --OR r[rd]=r[rs]|r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_OR;
--Comment the next line if you dont want to debug!
instruction <= i_OR;
when "100110" => --XOR r[rd]=r[rs]^r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_XOR;
--Comment the next line if you dont want to debug!
instruction <= i_XOR;
when "100111" => --NOR r[rd]=~(r[rs]|r[rt]);
c_source := C_FROM_ALU;
alu_function := ALU_NOR;
--Comment the next line if you dont want to debug!
instruction <= i_NOR;
when "101010" => --SLT r[rd]=r[rs]<r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_LESS_THAN_SIGNED;
--Comment the next line if you dont want to debug!
instruction <= i_SLT;
when "101011" => --SLTU r[rd]=u[rs]<u[rt];
c_source := C_FROM_ALU;
alu_function := ALU_LESS_THAN;
--Comment the next line if you dont want to debug!
instruction <= i_SLTU;
when "101101" => --DADDU r[rd]=r[rs]+u[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
--Comment the next line if you dont want to debug!
instruction <= i_DADDU;
--when "110001" => --TGEU
--when "110010" => --TLT
--when "110011" => --TLTU
--when "110100" => --TEQ
--when "110110" => --TNE
when others =>
end case;
when "000001" => --REGIMM
rt := "000000";
rd := "011111";
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_GTZ;
--if(test) pc=pc+imm*4
case rtx is
when "10000" => --BLTZAL r[31]=s->pc_next; branch=r[rs]<0;
c_source := C_FROM_PC_PLUS4;
branch_function := BRANCH_LTZ;
--Comment the next line if you dont want to debug!
instruction <= i_BLTZAL;
when "00000" => --BLTZ branch=r[rs]<0;
branch_function := BRANCH_LTZ;
--Comment the next line if you dont want to debug!
instruction <= i_BLTZ;
when "10001" => --BGEZAL r[31]=s->pc_next; branch=r[rs]>=0;
c_source := C_FROM_PC_PLUS4;
branch_function := BRANCH_GEZ;
--Comment the next line if you dont want to debug!
instruction <= i_BGEZAL;
when "00001" => --BGEZ branch=r[rs]>=0;
branch_function := BRANCH_GEZ;
--Comment the next line if you dont want to debug!
instruction <= i_BGEZ;
--when "10010" => --BLTZALL r[31]=s->pc_next; lbranch=r[rs]<0;
--when "00010" => --BLTZL lbranch=r[rs]<0;
--when "10011" => --BGEZALL r[31]=s->pc_next; lbranch=r[rs]>=0;
--when "00011" => --BGEZL lbranch=r[rs]>=0;
when others =>
end case;
when "000011" => --JAL r[31]=s->pc_next; s->pc_next=(s->pc&0xf0000000)|target;
c_source := C_FROM_PC_PLUS4;
rd := "011111";
pc_source := FROM_OPCODE25_0;
--Comment the next line if you dont want to debug!
instruction <= i_JAL;
when "000010" => --J s->pc_next=(s->pc&0xf0000000)|target;
pc_source := FROM_OPCODE25_0;
--Comment the next line if you dont want to debug!
instruction <= i_J;
when "000100" => --BEQ branch=r[rs]==r[rt];
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_EQ;
--Comment the next line if you dont want to debug!
instruction <= i_BEQ;
when "000101" => --BNE branch=r[rs]!=r[rt];
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_NE;
--Comment the next line if you dont want to debug!
instruction <= i_BNE;
when "000110" => --BLEZ branch=r[rs]<=0;
a_source := A_FROM_PC;
b_source := b_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_LEZ;
--Comment the next line if you dont want to debug!
instruction <= i_BLEZ;
when "000111" => --BGTZ branch=r[rs]>0;
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_GTZ;
--Comment the next line if you dont want to debug!
instruction <= i_BGTZ;
when "001000" => --ADDI r[rt]=r[rs]+(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_ADD;
--Comment the next line if you dont want to debug!
instruction <= i_ADDI;
when "001001" => --ADDIU u[rt]=u[rs]+(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_ADD;
--Comment the next line if you dont want to debug!
instruction <= i_ADDIU;
when "001010" => --SLTI r[rt]=r[rs]<(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_LESS_THAN_SIGNED;
--Comment the next line if you dont want to debug!
instruction <= i_SLTI;
when "001011" => --SLTIU u[rt]=u[rs]<(unsigned long)(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_LESS_THAN;
--Comment the next line if you dont want to debug!
instruction <= i_SLTIU;
when "001100" => --ANDI r[rt]=r[rs]&imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_AND;
--Comment the next line if you dont want to debug!
instruction <= i_ANDI;
when "001101" => --ORI r[rt]=r[rs]|imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_OR;
--Comment the next line if you dont want to debug!
instruction <= i_ORI;
when "001110" => --XORI r[rt]=r[rs]^imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_XOR;
--Comment the next line if you dont want to debug!
instruction <= i_XORI;
when "001111" => --LUI r[rt]=(imm<<16);
c_source := C_FROM_IMM_SHIFT16;
rd := rt;
--Comment the next line if you dont want to debug!
instruction <= i_LUI;
when "010000" => --COP0
alu_function := ALU_OR;
c_source := C_FROM_ALU;
if opcode(23) = '0' then --move from CP0
rs := '1' & opcode(15 downto 11);
rt := "000000";
rd := '0' & opcode(20 downto 16);
--Comment the next line if you dont want to debug!
instruction <= i_MFC0;
else --move to CP0
rs := "000000";
rd(5) := '1';
pc_source := FROM_BRANCH; --delay possible interrupt
branch_function := BRANCH_NO;
--Comment the next line if you dont want to debug!
instruction <= i_MTC0;
end if;
--when "010001" => --COP1
--when "010010" => --COP2
--when "010011" => --COP3
--when "010100" => --BEQL lbranch=r[rs]==r[rt];
--when "010101" => --BNEL lbranch=r[rs]!=r[rt];
--when "010110" => --BLEZL lbranch=r[rs]<=0;
--when "010111" => --BGTZL lbranch=r[rs]>0;
when "011010" => -- SUBI r[rt]=r[rs]-(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_SUBTRACT;
--Comment the next line if you dont want to debug!
instruction <= i_SUBI;
when "100000" => --LB r[rt]=*(signed char*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ8S; --address=(short)imm+r[rs];
--Comment the next line if you dont want to debug!
instruction <= i_LB;
when "100001" => --LH r[rt]=*(signed short*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ16S; --address=(short)imm+r[rs];
--Comment the next line if you dont want to debug!
instruction <= i_LH;
when "100010" => --LWL //Not Implemented
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ32;
--Comment the next line if you dont want to debug!
instruction <= i_LWL;
when "100011" => --LW r[rt]=*(long*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ32;
--Comment the next line if you dont want to debug!
instruction <= i_LW;
when "100100" => --LBU r[rt]=*(unsigned char*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ8; --address=(short)imm+r[rs];
--Comment the next line if you dont want to debug!
instruction <= i_LBU;
when "100101" => --LHU r[rt]=*(unsigned short*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ16; --address=(short)imm+r[rs];
--Comment the next line if you dont want to debug!
instruction <= i_LHU;
--when "100110" => --LWR //Not Implemented
when "101000" => --SB *(char*)ptr=(char)r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE8; --address=(short)imm+r[rs];
--Comment the next line if you dont want to debug!
instruction <= i_SB;
when "101001" => --SH *(short*)ptr=(short)r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE16;
--Comment the next line if you dont want to debug!
instruction <= i_SH;
when "101010" => --SWL //Not Implemented
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE32; --address=(short)imm+r[rs];
--Comment the next line if you dont want to debug!
instruction <= i_SWL;
when "101011" => --SW *(long*)ptr=r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE32; --address=(short)imm+r[rs];
--Comment the next line if you dont want to debug!
instruction <= i_SW;
--when "101110" => --SWR //Not Implemented
--when "101111" => --CACHE
--when "110000" => --LL r[rt]=*(long*)ptr;
--when "110001" => --LWC1
--when "110010" => --LWC2
--when "110011" => --LWC3
--when "110101" => --LDC1
--when "110110" => --LDC2
--when "110111" => --LDC3
--when "111000" => --SC *(long*)ptr=r[rt]; r[rt]=1;
--when "111001" => --SWC1
--when "111010" => --SWC2
--when "111011" => --SWC3
--when "111101" => --SDC1
--when "111110" => --SDC2
--when "111111" => --SDC3
when others =>
end case;
if c_source = C_FROM_NULL then
rd := "000000";
end if;
if intr_signal = '1' or is_syscall = '1' then
rs := "111111"; --interrupt vector
rt := "000000";
rd := "101110"; --save PC in EPC
alu_function := ALU_OR;
shift_function := SHIFT_NOTHING;
mult_function := MULT_NOTHING;
branch_function := BRANCH_YES;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_REG_TARGET;
c_source := C_FROM_PC;
pc_source := FROM_LBRANCH; -- "11"
mem_source := MEM_FETCH;
exception_out <= '1';
else
exception_out <= '0';
end if;
rs_index <= rs;
rt_index <= rt;
rd_index <= rd;
imm_out <= imm;
alu_func <= alu_function;
shift_func <= shift_function;
mult_func <= mult_function;
branch_func <= branch_function;
a_source_out <= a_source;
b_source_out <= b_source;
c_source_out <= c_source;
pc_source_out <= pc_source;
mem_source_out <= mem_source;
end process;
end; --logic
|
------------------------------------------------------------------------------/
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------/
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: top_nto1_ddr_se_rx.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: June 1 2009
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: Example single ended input receiver for DDR clock and data using 2 x BUFIO2
-- Serdes factor and number of data lines are set by constants in the code
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
--
------------------------------------------------------------------------------/
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and signalulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity top_nto1_ddr_se_rx is port (
reset : in std_logic ; -- reset (active high)
datain : in std_logic_vector(7 downto 0) ; -- single ended data inputs
clkin1, clkin2 : in std_logic ; -- TWO single ended clock input
dummy_out : out std_logic_vector(63 downto 0) ) ; -- dummy outputs
end top_nto1_ddr_se_rx ;
architecture arch_top_nto1_ddr_se_rx of top_nto1_ddr_se_rx is
component serdes_1_to_n_clk_ddr_s8_se is generic (
S : integer := 8) ; -- Parameter to set the serdes factor 1..8
port (
clkin1 : in std_logic ; -- Input from se receiver pin
clkin2 : in std_logic ; -- Input from se receiver pin
rxioclkp : out std_logic ; -- IO Clock network
rxioclkn : out std_logic ; -- IO Clock network
rx_serdesstrobe : out std_logic ; -- Parallel data capture strobe
rx_bufg_x1 : out std_logic) ; -- Global clock
end component ;
component serdes_1_to_n_data_ddr_s8_se is generic (
USE_PD : boolean := FALSE ; -- Parameter to set generation of phase detector logic
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
D : integer := 16) ; -- Set the number of inputs and outputs
port (
use_phase_detector : in std_logic ; -- '1' enables the phase detector logic if USE_PD = TRUE
datain : in std_logic_vector(D-1 downto 0) ; -- Input from LVDS receiver pin
rxioclkp : in std_logic ; -- IO Clock network
rxioclkn : in std_logic ; -- IO Clock network
rxserdesstrobe : in std_logic ; -- Parallel data capture strobe
reset : in std_logic ; -- Reset line
gclk : in std_logic ; -- Global clock
bitslip : in std_logic ; -- Bitslip control line
data_out : out std_logic_vector((D*S)-1 downto 0) ; -- Output data
debug_in : in std_logic_vector(1 downto 0) ; -- Debug Inputs, set to '0' if not required
debug : out std_logic_vector((2*D)+6 downto 0)) ; -- Debug output bus, 2D+6 = 2 lines per input (from mux and ce) + 7, leave nc if debug not required
end component ;
-- constants for serdes factor and number of IO pins
constant S : integer := 8 ; -- Set the serdes factor to 8
constant D : integer := 8 ; -- Set the number of inputs and outputs
constant DS : integer := (D*S)-1 ; -- Used for bus widths = serdes factor * number of inputs - 1
signal rst : std_logic ;
signal rxd : std_logic_vector(DS downto 0) ; -- Data from serdeses
signal rxr : std_logic_vector(DS downto 0); -- signalistered Data from serdeses
signal state : std_logic ;
signal bslip : std_logic ;
signal count : std_logic_vector(3 downto 0);
signal rxioclkp : std_logic ;
signal rxioclkn : std_logic ;
signal rx_serdesstrobe : std_logic ;
signal rx_bufg_x1 : std_logic ;
begin
rst <= reset ; -- active high reset pin
dummy_out <= rxr ;
-- Clock Input. Generate ioclocks via BUFIO2
inst_clkin : serdes_1_to_n_clk_ddr_s8_se generic map(
S => S)
port map (
clkin1 => clkin1,
clkin2 => clkin2,
rxioclkp => rxioclkp,
rxioclkn => rxioclkn,
rx_serdesstrobe => rx_serdesstrobe,
rx_bufg_x1 => rx_bufg_x1);
-- Data Inputs
inst_datain : serdes_1_to_n_data_ddr_s8_se generic map(
S => S,
D => D,
USE_PD => TRUE) -- Enables use of the phase detector - will require 2 input serdes whatever the serdes ratio required
port map (
use_phase_detector => '1', -- '1' enables the phase detector logic
datain => datain,
rxioclkp => rxioclkp,
rxioclkn => rxioclkn,
rxserdesstrobe => rx_serdesstrobe,
gclk => rx_bufg_x1,
bitslip => bslip,
reset => rst,
data_out => rxd,
debug_in => "00",
debug => open);
process (rx_bufg_x1, rst) -- example bitslip logic, if required
begin
if rst = '1' then
state <= '0' ;
bslip <= '1' ;
count <= "0000" ;
elsif rx_bufg_x1'event and rx_bufg_x1 = '1' then
if state = '0' then
if rxd(63 downto 60) /= "0011" then
bslip <= '1' ; -- bitslip needed
state <= '1' ;
count <= "0000" ;
end if ;
elsif state = '1' then
bslip <= '0' ; -- bitslip low
count <= count + 1 ;
if count = "1111" then
state <= '0' ;
end if ;
end if ;
end if ;
end process ;
process (rx_bufg_x1) -- process received data
begin
if rx_bufg_x1'event and rx_bufg_x1 = '1' then
rxr <= rxd ;
end if ;
end process ;
end arch_top_nto1_ddr_se_rx ;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test is
port(
clk : in std_logic;
wr_addr : in std_logic_vector(0 downto 0);
wr_data : in std_logic_vector(7 downto 0)
);
end test;
architecture rtl of test is
type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
signal ram : ram_type := (others => (others => '0'));
begin
process(clk)
variable widx : integer range 0 to 1;
begin
if rising_edge(clk) then
widx := to_integer(unsigned(wr_addr));
ram(widx) <= wr_data;
end if;
end process;
end;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_p_src_data_stream_2_V_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_p_src_data_stream_2_V_shiftReg;
architecture rtl of FIFO_image_filter_p_src_data_stream_2_V_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_p_src_data_stream_2_V is
generic (
MEM_STYLE : string := "auto";
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_p_src_data_stream_2_V is
component FIFO_image_filter_p_src_data_stream_2_V_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_p_src_data_stream_2_V_shiftReg : FIFO_image_filter_p_src_data_stream_2_V_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_p_src_data_stream_2_V_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_p_src_data_stream_2_V_shiftReg;
architecture rtl of FIFO_image_filter_p_src_data_stream_2_V_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_p_src_data_stream_2_V is
generic (
MEM_STYLE : string := "auto";
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_p_src_data_stream_2_V is
component FIFO_image_filter_p_src_data_stream_2_V_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_p_src_data_stream_2_V_shiftReg : FIFO_image_filter_p_src_data_stream_2_V_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_208 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_208;
architecture augh of sub_208 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_208 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_208;
architecture augh of sub_208 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- testbench for classicalMIPS
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
library altera;
use altera.altera_syn_attributes.all;
entity tb_cMIPS is
port
(
-- {ALTERA_IO_BEGIN} DO NOT REMOVE THIS LINE!
clock_50mhz : in std_logic;
clock1_50mhz : in std_logic;
clock2_50mhz : in std_logic;
clock3_50mhz : in std_logic;
gpio0_clkin : in std_logic_vector(1 downto 0);
gpio0_clkout : in std_logic_vector(1 downto 0);
gpio0_d : in std_logic_vector(31 downto 0);
gpio1_clkin : in std_logic_vector(1 downto 0);
gpio1_clkout : in std_logic_vector(1 downto 0);
gpio1_d : in std_logic_vector(31 downto 0);
i2c_overtempn : in std_logic;
i2c_scl : in std_logic;
i2c_sda : in std_logic;
key : in std_logic_vector(11 downto 0);
lcd_backlight : out std_logic;
lcd_d : inout std_logic_vector(7 downto 0);
lcd_en : out std_logic;
lcd_rs : out std_logic;
lcd_rw : out std_logic;
ledm_c : in std_logic_vector(4 downto 0);
ledm_r : in std_logic_vector(7 downto 0);
led_r : out std_logic;
led_g : out std_logic;
led_b : out std_logic;
proto_a : in std_logic_vector(7 downto 0);
proto_b : in std_logic_vector(7 downto 0);
sw : in std_logic_vector(3 downto 0);
disp1 : out std_logic_vector (7 downto 0);
disp0 : out std_logic_vector (7 downto 0);
dac_sclk : in std_logic;
dac_din : in std_logic;
dac_clr : in std_logic;
dac_csn : in std_logic;
adc_ub : in std_logic;
adc_sel : in std_logic;
adc_sd : in std_logic;
adc_sclk : in std_logic;
adc_refsel : in std_logic;
adc_dout2 : in std_logic;
adc_dout1 : in std_logic;
adc_csn : in std_logic;
adc_cnvst : in std_logic;
vga_b : in std_logic_vector(3 downto 0);
vga_g : in std_logic_vector(3 downto 0);
vga_r : in std_logic_vector(3 downto 0);
vga_hs : in std_logic;
vga_vs : in std_logic;
uart_cts : in std_logic;
uart_rts : out std_logic;
uart_rxd : in std_logic;
uart_txd : out std_logic;
usb_d : in std_logic_vector(7 downto 0);
usb_powerenn : in std_logic;
usb_rd : in std_logic;
usb_rxfn : in std_logic;
usb_txen : in std_logic;
usb_wr : in std_logic;
sma_clkin : in std_logic;
sma_clkin1 : in std_logic;
sma_clkout : in std_logic;
sd_cdn : in std_logic; -- card plugged in (not connected)
sd_clk : out std_logic; -- serial clk
sd_cmd : in std_logic; -- mosi_i sd_d(3)=cs
sd_d : out std_logic_vector(3 downto 0); -- sd_d(0)=miso_o
eth_col : in std_logic;
eth_crs : in std_logic;
eth_mdc : in std_logic;
eth_mdio : in std_logic;
eth_rstn : in std_logic;
eth_rxc : in std_logic;
eth_rxd : in std_logic_vector(3 downto 0);
eth_rxdv : in std_logic;
eth_rxer : in std_logic;
eth_txc : in std_logic;
eth_txd : in std_logic_vector(3 downto 0);
eth_txen : in std_logic;
eth_txer : in std_logic;
sdram_a : in std_logic_vector(12 downto 0);
sdram_ba : in std_logic_vector(1 downto 0);
sdram_cke : in std_logic;
sdram_clk : in std_logic;
sdram_csn : in std_logic;
sdram_d : in std_logic_vector(15 downto 0);
sdram_ldqm : in std_logic;
sdram_rasn : in std_logic;
sdram_udqm : in std_logic;
sdram_wen : in std_logic;
sdram_casn : in std_logic
-- flash_data0 : in std_logic;
-- flash_dclk : in std_logic;
-- flash_cs0n : out std_logic;
-- flash_asdo : out std_logic
-- {ALTERA_IO_END} DO NOT REMOVE THIS LINE!
);
-- {ALTERA_ATTRIBUTE_BEGIN} DO NOT REMOVE THIS LINE!
-- {ALTERA_ATTRIBUTE_END} DO NOT REMOVE THIS LINE!
end tb_cMIPS;
architecture ppl_type of tb_cMIPS is
-- {ALTERA_COMPONENTS_BEGIN} DO NOT REMOVE THIS LINE!
-- {ALTERA_COMPONENTS_END} DO NOT REMOVE THIS LINE!
component FFD is
port(clk, rst, set, D : in std_logic; Q : out std_logic);
end component FFD;
component SDcard is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
rdy : out std_logic;
wr : in std_logic;
addr : in std_logic_vector; -- a03, a02
data_inp : in std_logic_vector;
data_out : out std_logic_vector;
sdc_cs : out std_logic; -- SDcard chip-select
sdc_clk : out std_logic; -- SDcard serial clock
sdc_mosi_o : out std_logic; -- SDcard serial data out (to card)
sdc_mosi_i : in std_logic; -- SDcard serial data inp (fro card)
irq : out std_logic); -- interrupt request (not yet used)
end component SDCard;
component LCD_display is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
rdy : out std_logic;
wr : in std_logic;
addr : in std_logic; -- 0=constrol, 1=data
data_inp : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
LCD_DATA : inout std_logic_vector(7 downto 0); -- bidirectional bus
LCD_RS : out std_logic; -- LCD register select 0=ctrl, 1=data
LCD_RW : out std_logic; -- LCD read=1, 0=write
LCD_EN : out std_logic; -- LCD enable=1
LCD_BLON : out std_logic);
end component LCD_display;
component to_7seg is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data : in std_logic_vector;
display0 : out std_logic_vector;
display1 : out std_logic_vector;
red : out std_logic;
green : out std_logic;
blue : out std_logic);
end component to_7seg;
component read_keys is
generic (DEB_CYCLES : natural);
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
data : out reg32;
kbd : in std_logic_vector (11 downto 0);
sw : in std_logic_vector (3 downto 0));
end component read_keys;
component to_stdout is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data : in std_logic_vector);
end component to_stdout;
component from_stdin is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data : out std_logic_vector);
end component from_stdin;
component print_data is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data : in std_logic_vector);
end component print_data;
component write_data_file is
generic (OUTPUT_FILE_NAME : string);
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
addr : in std_logic_vector;
data : in std_logic_vector;
byte_sel : in std_logic_vector;
dump_ram : out std_logic);
end component write_data_file;
component read_data_file is
generic (INPUT_FILE_NAME : string);
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
addr : in std_logic_vector;
data : out std_logic_vector;
byte_sel: in std_logic_vector);
end component read_data_file;
component do_interrupt is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data_inp : in std_logic_vector;
data_out : out std_logic_vector;
irq : out std_logic);
end component do_interrupt;
component simple_uart is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
addr : in std_logic;
data_inp : in std_logic_vector;
data_out : out std_logic_vector;
txdat : out std_logic;
rxdat : in std_logic;
rts : out std_logic;
cts : in std_logic;
irq : out std_logic;
bit_rt : out std_logic_vector);-- communication speed - TB only
end component simple_uart;
component FPU is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
rdy : out std_logic;
wr : in std_logic;
addr : in std_logic_vector;
data_inp : in std_logic_vector;
data_out : out std_logic_vector);
end component FPU;
component remota is
generic(OUTPUT_FILE_NAME : string; INPUT_FILE_NAME : string);
port(rst, clk : in std_logic;
start : in std_logic;
inpDat : in std_logic; -- serial input
outDat : out std_logic; -- serial output
bit_rt : in std_logic_vector);
end component remota;
component sys_stats is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
addr : in std_logic_vector;
data : out std_logic_vector;
cnt_dc_ref : in integer;
cnt_dc_rd_hit : in integer;
cnt_dc_wr_hit : in integer;
cnt_dc_flush : in integer;
cnt_ic_ref : in integer;
cnt_ic_hit : in integer);
end component sys_stats;
component ram_addr_decode is
port (rst : in std_logic;
cpu_d_aVal : in std_logic;
addr : in std_logic_vector;
aVal : out std_logic;
dev_select : out std_logic_vector);
end component ram_addr_decode;
component sdram_addr_decode is
port (rst : in std_logic;
cpu_d_aVal : in std_logic;
addr : in std_logic_vector;
aVal : out std_logic;
dev_select : out std_logic_vector);
end component sdram_addr_decode;
component io_addr_decode is
port (rst : in std_logic;
clk : in std_logic;
cpu_d_aVal : in std_logic;
addr : in std_logic_vector;
dev_select : out std_logic_vector;
print_sel : out std_logic;
stdout_sel : out std_logic;
stdin_sel : out std_logic;
read_sel : out std_logic;
write_sel : out std_logic;
counter_sel : out std_logic;
FPU_sel : out std_logic;
uart_sel : out std_logic;
sstats_sel : out std_logic;
dsp7seg_sel : out std_logic;
keybd_sel : out std_logic;
lcd_sel : out std_logic;
sdc_sel : out std_logic;
not_waiting : in std_logic);
end component io_addr_decode;
component busError_addr_decode is
port (rst : in std_logic;
cpu_d_aVal : in std_logic;
addr : in reg32;
d_busError : out std_logic); -- decoded address not in range (act=0)
end component busError_addr_decode;
component inst_addr_decode is
port (rst : in std_logic;
cpu_i_aVal : in std_logic;
addr : in std_logic_vector;
aVal : out std_logic;
i_busError : out std_logic);
end component inst_addr_decode;
component ROM is
generic (LOAD_FILE_NAME : string);
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
rdy : out std_logic;
strobe : in std_logic;
addr : in std_logic_vector;
data : out std_logic_vector);
end component ROM;
component RAM is
generic (LOAD_FILE_NAME : string; DUMP_FILE_NAME : string);
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
rdy : out std_logic;
wr : in std_logic;
strobe : in std_logic;
addr : in std_logic_vector;
data_inp : in std_logic_vector;
data_out : out std_logic_vector;
byte_sel : in std_logic_vector;
dump_ram : in std_logic);
end component RAM;
component SDRAM_controller is
port (rst : in std_logic; -- FPGA reset (=0)
clk : in std_logic; -- CPU clock
clk2x : in std_logic; -- 100MHz clock
sel : in std_logic; -- host side chip select (=0)
rdy : out std_logic; -- tell CPU to wait (=0)
wr : in std_logic; -- host side write enable (=0)
bsel : in reg4; -- byte select
haddr : in reg26; -- host side address
hDinp : in reg32; -- host side data input
hDout : out reg32; -- host side data output
cke : out std_logic; -- ram side clock enable
scs : out std_logic; -- ram side chip select
ras : out std_logic; -- ram side RAS
cas : out std_logic; -- ram side CAS
we : out std_logic; -- ram side write enable
dqm0 : out std_logic; -- ram side byte0 output enable
dqm1 : out std_logic; -- ram side byte0 output enable
ba0 : out std_logic; -- ram side bank select 0
ba1 : out std_logic; -- ram side bank select 1
saddr : out reg12; -- ram side address
sdata : inout reg16); -- ram side data
end component SDRAM_controller;
component I_CACHE is
port (rst : in std_logic;
clk4x : in std_logic;
ic_reset : out std_logic;
cpu_sel : in std_logic;
cpu_rdy : out std_logic;
cpu_addr : in std_logic_vector;
cpu_data : out std_logic_vector;
mem_sel : out std_logic;
mem_rdy : in std_logic;
mem_addr : out std_logic_vector;
mem_data : in std_logic_vector;
ref_cnt : out integer;
hit_cnt : out integer);
end component I_CACHE;
component I_CACHE_fpga is
port (rst : in std_logic;
clk4x : in std_logic;
ic_reset : out std_logic;
cpu_sel : in std_logic;
cpu_rdy : out std_logic;
cpu_addr : in std_logic_vector;
cpu_data : out std_logic_vector;
mem_sel : out std_logic;
mem_rdy : in std_logic;
mem_addr : out std_logic_vector;
mem_data : in std_logic_vector;
ref_cnt : out integer;
hit_cnt : out integer);
end component I_CACHE_fpga;
component D_CACHE is
port (rst : in std_logic;
clk4x : in std_logic;
cpu_sel : in std_logic;
cpu_rdy : out std_logic;
cpu_wr : in std_logic;
cpu_addr : in std_logic_vector;
cpu_data_inp : in std_logic_vector;
cpu_data_out : out std_logic_vector;
cpu_xfer : in std_logic_vector;
mem_sel : out std_logic;
mem_rdy : in std_logic;
mem_wr : out std_logic;
mem_addr : out std_logic_vector;
mem_data_inp : in std_logic_vector;
mem_data_out : out std_logic_vector;
mem_xfer : out std_logic_vector;
ref_cnt : out integer;
rd_hit_cnt : out integer;
wr_hit_cnt : out integer;
flush_cnt : out integer);
end component D_CACHE;
component core is
port (rst : in std_logic;
clk : in std_logic;
phi1 : in std_logic;
phi2 : in std_logic;
phi3 : in std_logic;
i_aVal : out std_logic;
i_wait : in std_logic;
i_addr : out std_logic_vector;
instr : in std_logic_vector;
d_aVal : out std_logic;
d_wait : in std_logic;
d_addr : out std_logic_vector;
data_inp : in std_logic_vector;
data_out : out std_logic_vector;
wr : out std_logic;
b_sel : out std_logic_vector;
nmi : in std_logic;
irq : in std_logic_vector;
i_busErr : in std_logic;
d_busErr : in std_logic);
end component core;
component mf_altpll port (
inclk0 : IN STD_LOGIC;
c0 : OUT STD_LOGIC;
c1 : OUT STD_LOGIC;
c2 : OUT STD_LOGIC;
c3 : OUT STD_LOGIC;
c4 : OUT STD_LOGIC;
locked : OUT STD_LOGIC);
end component mf_altpll;
component mf_altpll_io port (
areset : IN STD_LOGIC;
inclk0 : IN STD_LOGIC;
c0 : OUT STD_LOGIC;
c1 : OUT STD_LOGIC;
c2 : OUT STD_LOGIC);
end component mf_altpll_io;
component mf_altclkctrl port (
inclk : IN STD_LOGIC;
outclk : OUT STD_LOGIC);
end component mf_altclkctrl;
-- use fake / behavioral
for U_I_CACHE : I_cache use entity work.I_cache(fake);
-- use simulation / rtl
for U_ROM : ROM use entity work.ROM(rtl);
-- use simulation / rtl
for U_RAM : RAM use entity work.RAM(rtl);
-- use fake / behavioral
for U_D_CACHE : D_cache use entity work.D_cache(fake);
-- use fake / rtl
for U_FPU: FPU use entity work.FPU(fake);
-- use fake / simple
for U_SDRAMc : SDRAM_controller
use entity work.SDRAM_controller(fake);
signal clk,clkin,clk_locked,clk_50mhz : std_logic;
signal clk2x, clk4x,clk4x0,clk4x180 : std_logic;
signal phi0,phi1,phi2,phi3,phi0in,phi1in,phi2in,phi3in : std_logic;
signal cpu_i_aVal, cpu_i_wait, wr, cpu_d_aVal, cpu_d_wait : std_logic;
signal rst, ic_reset, cpu_reset : std_logic;
signal a_reset, a_rst0,a_rst1,a_rst2,a_rst3,a_rst4,a_rst5,a_rst6,a_rst7,a_rst8,a_rst9, a_rstA, a_rstB, a_rst :std_logic;
signal nmi, i_busError, d_busError : std_logic;
signal irq : reg6;
signal inst_aVal, inst_wait, rom_rdy : std_logic := '1';
signal data_aVal, data_wait, ram_rdy, mem_wr : std_logic;
signal sdram_aVal, sdram_wait, sdram_wr : std_logic;
signal cpu_xfer, mem_xfer : reg4;
signal dev_select, dev_select_ram, dev_select_io, dev_select_sdram : reg4;
signal io_print_sel : std_logic := '1';
signal io_stdout_sel : std_logic := '1';
signal io_stdin_sel : std_logic := '1';
signal io_write_sel : std_logic := '1';
signal io_read_sel : std_logic := '1';
signal io_counter_sel : std_logic := '1';
signal io_uart_sel : std_logic := '1';
signal io_sstats_sel : std_logic := '1';
signal io_7seg_sel : std_logic := '1';
signal io_keys_sel : std_logic := '1';
signal io_fpu_sel, io_fpu_wait : std_logic := '1';
signal io_lcd_sel, io_lcd_wait : std_logic := '1';
signal io_sdc_sel, io_sdc_wait : std_logic := '1';
signal d_cache_d_out, stdin_d_out, read_d_out, counter_d_out : reg32;
signal fpu_d_out, uart_d_out, sstats_d_out, keybd_d_out : reg32;
signal lcd_d_out, sdc_d_out, sdram_d_out : reg32;
signal hDinp, hDout: reg32;
signal sdcke,sdscs,sdras,sdcas,sdwe,sddqm0,sddqm1,sdba0,sdba1 : std_logic;
signal sdaddr : reg12;
signal sddata : reg16;
signal counter_irq : std_logic;
signal io_wait, not_waiting : std_logic;
signal i_addr,d_addr,p_addr : reg32;
signal datrom, datram_inp,datram_out, cpu_instr : reg32;
signal cpu_data_inp, cpu_data_out, cpu_data : reg32;
signal mem_i_sel, mem_d_sel: std_logic;
signal mem_i_addr, mem_addr, mem_d_addr: reg32;
signal cnt_i_ref,cnt_i_hit : integer;
signal cnt_d_ref,cnt_d_rd_hit,cnt_d_wr_hit,cnt_d_flush : integer;
signal dump_ram : std_logic;
signal uart_irq, start_remota, uart_inp, uart_out, u_rts, u_cts : std_logic;
signal bit_rt : reg3;
signal sdc_mosi_i, sdc_miso_o : std_logic;
begin -- TB
-- {ALTERA_INSTANTIATION_BEGIN} DO NOT REMOVE THIS LINE!
-- {ALTERA_INSTANTIATION_END} DO NOT REMOVE THIS LINE!
pll : mf_altpll port map (inclk0 => clock_50mhz, locked => clk_locked,
c0 => phi0in, c1 => phi1in, c2 => phi2in, c3 => phi3in, c4 => clkin);
-- pll_io : mf_altpll_io port map (areset => rst, inclk0 => clock_50mhz,
-- c0 => clk2x, c1 => clk4x0, c2 => clk4x180);
clk2x <= '0';
clk4x0 <= '0';
clk4x180 <= '0';
mf_altclkctrl_inst_clk : mf_altclkctrl port map (
inclk => clkin, outclk => clk);
mf_altclkctrl_inst_clk4x : mf_altclkctrl port map (
inclk => clk4x180, outclk => clk4x);
mf_altclkctrl_inst_phi0 : mf_altclkctrl port map (
inclk => phi0in, outclk => phi0);
mf_altclkctrl_inst_phi1 : mf_altclkctrl port map (
inclk => phi1in, outclk => phi1);
mf_altclkctrl_inst_phi2 : mf_altclkctrl port map (
inclk => phi2in, outclk => phi2);
mf_altclkctrl_inst_phi3 : mf_altclkctrl port map (
inclk => phi3in, outclk => phi3);
-- synchronize external asynchronous reset = sw(3) at lower left
a_reset <= not(sw(3));
U_SYNC_RESET0: FFD port map (clock_50mhz, a_reset, '1', '1', a_rst0);
U_SYNC_RESET1: FFD port map (clock_50mhz, '1', '1', a_rst0, a_rst1);
U_SYNC_RESET2: FFD port map (clock_50mhz, '1', '1', a_rst1, a_rst2);
-- pulse extender and debounce filter
U_SYNC_RESET3: FFD port map (clock_50mhz, '1','1', a_rst2, a_rst3);
U_SYNC_RESET4: FFD port map (clock_50mhz, '1','1', a_rst3, a_rst4);
U_SYNC_RESET5: FFD port map (clock_50mhz, '1','1', a_rst4, a_rst5);
U_SYNC_RESET6: FFD port map (clock_50mhz, '1','1', a_rst5, a_rst6);
U_SYNC_RESET7: FFD port map (clock_50mhz, '1','1', a_rst6, a_rst7);
a_rst8 <= (a_rst7 or a_rst2) and clk_locked;
-- synchronize reset
U_SYNC_RESET8: FFD port map (clk, '1','1', a_rst8, a_rst9);
U_SYNC_RESET9: FFD port map (clk, '1','1', a_rst9, rst);
-- synchronize cache-resets and external reset to reset the processor
a_rstA <= rst and ic_reset;
U_SYNC_RESETa: FFD port map (clk, rst, '1', a_rstA, a_rstB);
U_SYNC_RESETb: FFD port map (clk, rst, '1', a_rstB, cpu_reset);
cpu_i_wait <= inst_wait;
cpu_d_wait <= data_wait and io_wait; -- and sdram_wait;
io_wait <= io_lcd_wait; -- and io_fpu_wait;
not_waiting <= (inst_wait and data_wait); -- for I/O references
-- irq <= b"000000"; -- NO interrupt requests
-- Count=Compare at IRQ7, UART at IRQ6, extCounter at IRQ5
-- C=C U E 0 0 0 sw1 sw0
irq <= '0' & uart_irq & counter_irq & b"000"; -- uart+counter interrupts
-- irq <= b"00" & counter_irq & b"000"; -- counter interrupts
nmi <= '0'; -- input port to TB
U_CORE: core
port map (cpu_reset, clk, phi1,phi2,phi3,
cpu_i_aVal, cpu_i_wait, i_addr, cpu_instr,
cpu_d_aVal, cpu_d_wait, d_addr, cpu_data_inp, cpu_data,
wr, cpu_xfer, nmi, irq, i_busError, d_busError);
U_INST_ADDR_DEC: inst_addr_decode
port map (rst, cpu_i_aVal, i_addr, inst_aVal, i_busError);
-- U_I_CACHE: i_cache_fpga -- or FPGA implementation
U_I_CACHE: i_cache
port map (rst, clk4x, ic_reset,
inst_aVal, inst_wait, i_addr, cpu_instr,
mem_i_sel, rom_rdy, mem_i_addr, datrom, cnt_i_ref,cnt_i_hit);
U_ROM: ROM generic map ("prog.bin")
port map (rst, clk, mem_i_sel,rom_rdy, phi3, mem_i_addr,datrom);
U_DATA_BUS_ERROR_DEC: busError_addr_decode
port map (rst, cpu_d_aVal, d_addr, d_busError);
-- d_busError <= '1'; -- only while testing the SDRAM
U_IO_ADDR_DEC: io_addr_decode
port map (rst, phi0, cpu_d_aVal, d_addr, dev_select_io,
io_print_sel, io_stdout_sel, io_stdin_sel,io_read_sel,
io_write_sel, io_counter_sel, io_fpu_sel, io_uart_sel,
io_sstats_sel, io_7seg_sel, io_keys_sel, io_lcd_sel,
io_sdc_sel, not_waiting);
U_DATA_ADDR_DEC: ram_addr_decode
port map (rst, cpu_d_aVal, d_addr,data_aVal, dev_select_ram);
U_SDRAM_ADDR_DEC: sdram_addr_decode
port map (rst, cpu_d_aVal, d_addr,sdram_aVal, dev_select_sdram);
dev_select <= dev_select_io or dev_select_ram; -- or dev_select_sdram;
with dev_select select
cpu_data_inp <= d_cache_d_out when b"0001",
-- stdin_d_out when b"0100",
-- read_d_out when b"0101",
counter_d_out when b"0111",
fpu_d_out when b"1000",
uart_d_out when b"1001",
-- sstats_d_out when b"1010",
keybd_d_out when b"1100",
lcd_d_out when b"1101",
sdc_d_out when b"1110",
-- sdram_d_out when b"1110",
(others => 'X') when others;
U_D_CACHE: d_cache
port map (rst, clk4x,
data_aVal, data_wait, wr,
d_addr, cpu_data, d_cache_d_out, cpu_xfer,
mem_d_sel, ram_rdy, mem_wr,
mem_addr, datram_inp, datram_out, mem_xfer,
cnt_d_ref, cnt_d_rd_hit, cnt_d_wr_hit, cnt_d_flush);
U_RAM: RAM generic map ("data.bin", "dump.data")
port map (rst, clk, mem_d_sel, ram_rdy, mem_wr, phi2,
mem_addr, datram_out, datram_inp, mem_xfer, dump_ram);
dump_ram <= '0';
hDinp <= (others => 'X');
U_SDRAMc: SDRAM_controller port map
(rst, clk, clk2x, sdram_aVal, sdram_wait, wr,
cpu_xfer, d_addr(25 downto 0), hDinp,hDout,
sdcke,sdscs,sdras,sdcas,sdwe,sddqm0,sddqm1,sdba0,sdba1,sdaddr,sddata);
sdcke <= '1';
-- U_to_stdout: to_stdout
-- port map (rst,clk, io_stdout_sel, wr, cpu_data);
-- U_from_stdin: from_stdin
-- port map (rst,clk, io_stdin_sel, wr, stdin_d_out);
-- U_read_inp: read_data_file generic map ("input.data")
-- port map (rst,clk, io_read_sel, wr, d_addr, read_d_out, cpu_xfer);
-- U_write_out: write_data_file generic map ("output.data")
-- port map (rst,clk, io_write_sel, wr, d_addr,cpu_data,cpu_xfer,dump_ram);
-- U_print_data: print_data
-- port map (rst,clk, io_print_sel, wr, cpu_data);
U_interrupt_counter: do_interrupt -- external counter+interrupt
port map (rst,clk, io_counter_sel, wr, cpu_data,
counter_d_out, counter_irq);
U_to_7seg: to_7seg
port map (rst,clk,io_7seg_sel, wr, cpu_data, disp0, disp1,
led_r, led_g, led_b);
U_read_keys: read_keys
generic map (17500) -- debouncing interval, in clock cycles
port map (rst,clk, io_keys_sel, keybd_d_out, key, sw);
U_LCD_display: LCD_display
port map (rst, clk, io_lcd_sel, io_lcd_wait,
wr, d_addr(2), cpu_data, lcd_d_out,
lcd_d, lcd_rs, lcd_rw, lcd_en, lcd_backlight);
U_simple_uart: simple_uart
port map (rst,clk, io_uart_sel, wr, d_addr(2), cpu_data, uart_d_out,
uart_txd, uart_rxd, uart_rts, uart_cts, uart_irq, bit_rt);
-- to test in loopback mode, uncoment next line & replace 2nd line for above
-- uart_out, uart_inp, u_rts, u_cts, uart_irq, bit_rt);
-- uart_inp <= uart_out; -- looping back;
-- u_cts <= u_rts;
-- U_uart_remota: remota generic map ("serial.out","serial.inp")
-- port map (rst, clk, start_remota, txdat, rxdat, bit_rt);
U_sdcard: SDcard
port map (rst, clk, io_sdc_sel, io_sdc_wait,
wr, d_addr(3 downto 2), cpu_data, sdc_d_out,
sd_d(3), sd_clk, sdc_miso_o, sdc_mosi_i, open);
-- sd_clk <= sdc_clk; -- serial clock to SD card
-- sd_d(3) <= sdc_cs; -- chip-select (active low)
sd_d(0) <= sdc_miso_o; -- data outputo to SD card
sdc_mosi_i <= sd_cmd; -- data input form SD card
U_FPU: FPU
port map (rst,clk, io_FPU_sel, io_FPU_wait, wr, d_addr(5 downto 2),
cpu_data, fpu_d_out);
-- U_sys_stats: sys_stats -- CPU reads system counters
-- port map (cpu_reset,clk, io_sstats_sel, wr, d_addr, sstats_d_out,
-- cnt_d_ref,cnt_d_rd_hit,cnt_d_wr_hit,cnt_d_flush,
-- cnt_i_ref,cnt_i_hit);
-- U_clock: process -- simulate external clock
-- begin
-- clock_50mhz <= '1';
-- wait for CLOCK_PER / 2;
-- clock_50mhz <= '0';
-- wait for CLOCK_PER / 2;
-- end process; -- -------------------------------------------------------
-- simulate reset switch bounces
-- a_reset <= '1', '0' after 5 ns, '1' after 8 ns, '0' after 12 ns, '1' after 14 ns, '0' after 18 ns, '1' after 25 ns;
end architecture ppl_type;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- instruction address decoding
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity inst_addr_decode is -- CPU side triggers access
port (rst : in std_logic;
cpu_i_aVal : in std_logic; -- CPU instr addr valid (act=0)
addr : in reg32; -- CPU address
aVal : out std_logic; -- decoded address in range (act=0)
i_busError : out std_logic); -- decoded address not in range (act=0)
end entity inst_addr_decode;
architecture behavioral of inst_addr_decode is
signal in_range : boolean;
begin
in_range <= (addr(HI_SEL_BITS downto LO_SEL_BITS)
=
x_INST_BASE_ADDR(HI_SEL_BITS downto LO_SEL_BITS));
aVal <= '0' when ( cpu_i_aVal = '0' and in_range ) else
'1';
i_busError <= '0' when ( cpu_i_aVal = '0' and not(in_range) ) else
'1';
end architecture behavioral;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- RAM address decoding
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity ram_addr_decode is -- CPU side triggers access
port (rst : in std_logic;
cpu_d_aVal : in std_logic; -- CPU data addr valid (active=0)
addr : in reg32; -- CPU address
aVal : out std_logic; -- data address (act=0)
dev_select : out reg4); -- select input to CPU
constant LO_ADDR : integer := log2_ceil(DATA_BASE_ADDR);
constant HI_ADDR : integer := log2_ceil(DATA_BASE_ADDR + DATA_MEM_SZ - 1);
constant in_r : std_logic_vector(HI_ADDR downto LO_ADDR) := (others => '1');
constant ng_r : std_logic_vector(HI_ADDR downto LO_ADDR) := (others => '0');
constant oth : std_logic_vector(HI_SEL_BITS downto HI_ADDR+1):=(others=>'1');
constant ng_o : std_logic_vector(HI_SEL_BITS downto HI_ADDR+1):=(others=>'0');
end entity ram_addr_decode;
architecture behavioral of ram_addr_decode is
-- constant LO_ADDR : natural := log2_ceil(DATA_BASE_ADDR);
-- constant HI_ADDR : natural := log2_ceil(DATA_BASE_ADDR + DATA_MEM_SZ - 1);
constant all_0 : std_logic_vector(31 downto 0) := (others=>'0');
constant a_hi : std_logic_vector(31 downto HI_ADDR+1) := (others=>'0');
constant a_lo : std_logic_vector(LO_ADDR-1 downto 0) := (others=>'0');
constant a_bits : std_logic_vector(HI_ADDR downto LO_ADDR) := (others=>'1');
constant a_mask : std_logic_vector := a_hi & a_bits & a_lo;
constant LO_RAM : natural := 0;
constant HI_RAM : natural := log2_ceil(DATA_MEM_SZ-1);
constant r_hi : std_logic_vector(31 downto HI_RAM+1) := (others=>'1');
constant r_lo : std_logic_vector(HI_RAM downto LO_RAM) := (others=>'0');
constant r_mask : std_logic_vector := r_hi & r_lo;
signal in_range : boolean;
begin
-- in_range <= ( ((addr(HI_ADDR downto LO_ADDR) and in_r) /= ng_r) and
-- ((addr(HI_SEL_BITS downto HI_ADDR+1) and oth) = ng_o) );
in_range <= ( addr(HI_SEL_BITS downto LO_SEL_BITS)
=
x_DATA_BASE_ADDR(HI_SEL_BITS downto LO_SEL_BITS) );
aVal <= '0' when (cpu_d_aVal = '0' and in_range) else '1';
dev_select <= b"0001" when (cpu_d_aVal = '0' and in_range) else b"0000";
assert TRUE -- cpu_d_aVal = '1'
report LF & "e " & SLV32HEX(addr) &
" addr " & SLV2str(addr(15 downto 0)) & LF &
" LO_AD " & integer'image(LO_ADDR) &
" HI_AD " & integer'image(HI_ADDR) &
" a_hi " & SLV2STR(a_hi) &
" a_lo " & SLV2STR(a_lo) &
" a_bits " & SLV2STR(a_bits) &
" a_mask " & SLV32HEX(a_mask) & LF &
" LO_RAM " & integer'image(LO_RAM) &
" HI_RAM " & integer'image(HI_RAM) &
" r_hi " & SLV2STR(r_hi) &
" r_lo " & SLV2STR(r_lo) &
" r_mask " & SLV32HEX(r_mask)
severity NOTE;
end architecture behavioral;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- busError address decoding
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity busError_addr_decode is -- CPU side triggers access
port (rst : in std_logic;
cpu_d_aVal : in std_logic; -- CPU data addr valid (active=0)
addr : in reg32; -- CPU address
d_busError : out std_logic); -- decoded address not in range (act=0)
end entity busError_addr_decode;
architecture behavioral of busError_addr_decode is
constant all_0 : std_logic_vector(31 downto 0) := (others=>'0');
-- I/O constants
constant IO_RANGE : integer := IO_ADDR_RANGE * IO_MAX_NUM_DEVS;
constant LO_DEV : natural := 0;
constant HI_DEV : natural := log2_ceil(IO_RANGE);
constant IO_LO_ADDR : integer := log2_ceil(IO_BASE_ADDR);
constant IO_HI_ADDR : integer := log2_ceil(IO_BASE_ADDR + IO_RANGE - 1);
constant iin_r:std_logic_vector(IO_HI_ADDR downto IO_LO_ADDR) := (others=>'1');
constant ing_r:std_logic_vector(IO_HI_ADDR downto IO_LO_ADDR) := (others=>'0');
constant ioth:std_logic_vector(HI_SEL_BITS downto IO_HI_ADDR+1):=(others=>'1');
constant ing_o:std_logic_vector(HI_SEL_BITS downto IO_HI_ADDR+1):=(others=>'0');
constant x_hi : std_logic_vector(31 downto HI_DEV) := (others=>'1');
constant x_lo : std_logic_vector(HI_DEV-1 downto 0) := (others=>'0');
constant x_mask : std_logic_vector := x_hi & x_lo; -- 1..10..0
-- RAM constants
constant LO_ADDR : natural := log2_ceil(DATA_BASE_ADDR);
constant HI_ADDR : natural := log2_ceil(DATA_BASE_ADDR + DATA_MEM_SZ - 1);
constant a_hi : std_logic_vector(31 downto HI_ADDR+1) := (others=>'0');
constant a_lo : std_logic_vector(LO_ADDR-1 downto 0) := (others=>'0');
constant a_bits : std_logic_vector(HI_ADDR downto LO_ADDR) := (others=>'1');
constant a_mask : std_logic_vector := a_hi & a_bits & a_lo; -- 0..0110..0
constant LO_RAM : natural := 0;
constant HI_RAM : natural := log2_ceil(DATA_MEM_SZ-1);
constant r_hi : std_logic_vector(31 downto HI_RAM+1) := (others=>'1');
constant r_lo : std_logic_vector(HI_RAM downto LO_RAM) := (others=>'0');
constant r_mask : std_logic_vector := r_hi & r_lo; -- 1..10..0
constant in_r : std_logic_vector(HI_ADDR downto LO_ADDR) := (others => '1');
constant ng_r : std_logic_vector(HI_ADDR downto LO_ADDR) := (others => '0');
constant oth : std_logic_vector(HI_SEL_BITS downto HI_ADDR+1):=(others=>'1');
constant ng_o : std_logic_vector(HI_SEL_BITS downto HI_ADDR+1):=(others=>'0');
signal in_range, io_in_range : boolean;
begin
-- in_range <= ( ((addr and a_mask) = x_DATA_BASE_ADDR) and
-- ((addr and r_mask) = x_DATA_BASE_ADDR) );
-- io_in_range <= ( ((addr and x_mask) = x_IO_BASE_ADDR) );
in_range <= ( addr(HI_SEL_BITS downto LO_SEL_BITS)
=
x_DATA_BASE_ADDR(HI_SEL_BITS downto LO_SEL_BITS) );
io_in_range <= (addr(HI_SEL_BITS downto LO_SEL_BITS)
=
x_IO_BASE_ADDR(HI_SEL_BITS downto LO_SEL_BITS));
-- in_range <= ((addr(HI_ADDR downto LO_ADDR) and in_r) /= ng_r) and
-- ((addr(HI_SEL_BITS downto HI_ADDR+1) and oth) = ng_o);
-- io_in_range <= ((addr(IO_HI_ADDR downto IO_LO_ADDR) and iin_r)/=ing_r)and
-- ((addr(HI_SEL_BITS downto IO_HI_ADDR+1) and ioth) = ing_o);
-- d_busError <= '0' when ( (cpu_d_aVal = '0') and
-- (not(in_range) and not(io_in_range)) ) else '1';
d_busError <= '0' when ( (cpu_d_aVal = '0') and
(not(in_range) and not(io_in_range)) ) else '1';
assert TRUE -- cpu_d_aVal = '1'
report LF &
" e " & SLV32HEX(addr) &
" addr " & SLV2str(addr(15 downto 0)) & LF &
" LO_AD " & integer'image(LO_ADDR) &
" HI_AD " & integer'image(HI_ADDR) &
" a_hi " & SLV2STR(a_hi) &
" a_lo " & SLV2STR(a_lo) &
" a_bits " & SLV2STR(a_bits) &
" a_mask " & SLV32HEX(a_mask) & LF &
" LO_RAM " & integer'image(LO_RAM) &
" HI_RAM " & integer'image(HI_RAM) &
" r_hi " & SLV2STR(r_hi) &
" r_lo " & SLV2STR(r_lo) &
" r_mask " & SLV32HEX(r_mask)
severity NOTE;
assert TRUE -- cpu_d_aVal = '1' and io_busError
report LF &
" e " & SLV32HEX(addr) &
" addr " & SLV2str(addr(15 downto 0)) & LF &
" x_hi " & SLV2STR(x_hi) &
" x_lo " & SLV2STR(x_lo) &
" x_mask " & SLV32HEX(x_mask) & LF &
" LO_DEV " & integer'image(LO_DEV) &
" HI_DEV " & integer'image(HI_DEV)
severity NOTE;
end architecture behavioral;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- I/O address decoding
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity io_addr_decode is -- CPU side triggers access
port (rst : in std_logic;
clk : in std_logic; -- clk sparates back-to-back refs
cpu_d_aVal : in std_logic; -- CPU data addr valid (active=0)
addr : in reg32; -- CPU address
dev_select : out reg4; -- select input to CPU
print_sel : out std_logic; -- std_out (integer) (act=0)
stdout_sel : out std_logic; -- std_out (character) (act=0)
stdin_sel : out std_logic; -- std_inp (character) (act=0)
read_sel : out std_logic; -- file read (act=0)
write_sel : out std_logic; -- file write (act=0)
counter_sel : out std_logic; -- interrupt counter (act=0)
FPU_sel : out std_logic; -- floating point unit (act=0)
UART_sel : out std_logic; -- floating point unit (act=0)
SSTATS_sel : out std_logic; -- system statistics (act=0)
dsp7seg_sel : out std_logic; -- 7 segments display (act=0)
keybd_sel : out std_logic; -- telephone keyboard (act=0)
lcd_sel : out std_logic; -- LCD 2x16 char display (act=0)
sdc_sel : out std_logic; -- SDcard reader/writer (act=0)
not_waiting : in std_logic); -- no other device is waiting
end entity io_addr_decode;
architecture behavioral of io_addr_decode is
constant LO_SEL_ADDR : integer := log2_ceil(IO_ADDR_RANGE);
constant IO_RANGE : integer := IO_ADDR_RANGE * IO_MAX_NUM_DEVS;
constant LO_ADDR : integer := log2_ceil(IO_BASE_ADDR);
constant HI_ADDR : integer := log2_ceil(IO_BASE_ADDR + IO_RANGE - 1);
constant in_r : std_logic_vector(HI_ADDR downto LO_ADDR) := (others => '1');
constant ng_r : std_logic_vector(HI_ADDR downto LO_ADDR) := (others => '0');
constant oth : std_logic_vector(HI_SEL_BITS downto HI_ADDR+1):=(others=>'1');
constant ng_o : std_logic_vector(HI_SEL_BITS downto HI_ADDR+1):=(others=>'0');
constant all_0 : std_logic_vector(31 downto 0) := (others=>'0');
-- I/O constants
constant LO_DEV : natural := 0;
constant HI_DEV : natural := log2_ceil(IO_RANGE-1);
constant x_hi : std_logic_vector(31 downto HI_DEV) := (others=>'1');
constant x_lo : std_logic_vector(HI_DEV-1 downto 0) := (others=>'0');
constant x_mask : std_logic_vector := x_hi & x_lo; -- 1..10..0
signal in_range : boolean;
signal aVal : std_logic;
signal dev : integer; -- DEBUGGING only
begin
-- in_range <= ((addr and x_mask) = x_IO_BASE_ADDR);
-- in_range <= ((addr(HI_ADDR downto LO_ADDR) and in_r) /= ng_r) and
-- ((addr(HI_SEL_BITS downto HI_ADDR+1) and oth) = ng_o);
in_range <= (addr(HI_SEL_BITS downto LO_SEL_BITS)
=
x_IO_BASE_ADDR(HI_SEL_BITS downto LO_SEL_BITS));
-- in_range <= ( ((addr(HI_ADDR downto LO_ADDR) and in_r) /= ng_r) and
-- ((addr(HI_SEL_BITS downto HI_ADDR+1) and oth) = ng_o) );
-- dev <= to_integer(signed(addr(HI_SEL_ADDR downto LO_SEL_ADDR)));
dev <= to_integer(signed(addr(IO_ADDR_BITS downto LO_SEL_ADDR)));
aVal <= '0' when ( cpu_d_aVal = '0' and not_waiting = '1' and
in_range ) else '1';
U_decode: process(aVal, addr, dev)
variable dev_sel : reg4;
constant is_noise : integer := 0;
constant is_print : integer := 2;
constant is_stdout : integer := 3;
constant is_stdin : integer := 4;
constant is_read : integer := 5;
constant is_write : integer := 6;
constant is_count : integer := 7;
constant is_FPU : integer := 8;
constant is_UART : integer := 9;
constant is_SSTATS : integer := 10;
constant is_dsp7seg : integer := 11;
constant is_keybd : integer := 12;
constant is_lcd : integer := 13;
constant is_sdc : integer := 14;
begin
print_sel <= '1';
stdout_sel <= '1';
stdin_sel <= '1';
read_sel <= '1';
write_sel <= '1';
counter_sel <= '1';
FPU_sel <= '1';
UART_sel <= '1';
SSTATS_sel <= '1';
dsp7seg_sel <= '1';
keybd_sel <= '1';
lcd_sel <= '1';
sdc_sel <= '1';
case dev is -- to_integer(signed(addr(HI_ADDR downto LO_ADDR))) is
when 0 => dev_sel := std_logic_vector(to_signed(is_print, 4));
print_sel <= aVal;
when 1 => dev_sel := std_logic_vector(to_signed(is_stdout, 4));
stdout_sel <= aVal;
when 2 => dev_sel := std_logic_vector(to_signed(is_stdin, 4));
stdin_sel <= aVal;
when 3 => dev_sel := std_logic_vector(to_signed(is_read, 4));
read_sel <= aVal;
when 4 => dev_sel := std_logic_vector(to_signed(is_write, 4));
write_sel <= aVal;
when 5 => dev_sel := std_logic_vector(to_signed(is_count, 4));
counter_sel <= aVal;
when 6 => dev_sel := std_logic_vector(to_signed(is_FPU, 4));
FPU_sel <= aVal;
when 7 => dev_sel := std_logic_vector(to_signed(is_UART, 4));
UART_sel <= aVal;
when 8 => dev_sel := std_logic_vector(to_signed(is_SSTATS, 4));
SSTATS_sel <= aVal;
when 9 => dev_sel := std_logic_vector(to_signed(is_dsp7seg, 4));
dsp7seg_sel <= aVal;
when 10 => dev_sel := std_logic_vector(to_signed(is_keybd, 4));
keybd_sel <= aVal;
when 11 => dev_sel := std_logic_vector(to_signed(is_lcd, 4));
lcd_sel <= aVal;
when 12 => dev_sel := std_logic_vector(to_signed(is_sdc, 4));
sdc_sel <= aVal;
when others => dev_sel := std_logic_vector(to_signed(is_noise, 4));
end case;
assert TRUE report "IO_addr "& SLV32HEX(addr); -- DEBUG
if aVal = '0' then
dev_select <= dev_sel;
else
dev_select <= std_logic_vector(to_signed(is_noise, 4));
end if;
end process U_decode;
end architecture behavioral;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- SDRAM address decoding
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity sdram_addr_decode is -- CPU side triggers access
port (rst : in std_logic;
cpu_d_aVal : in std_logic; -- CPU data addr valid (active=0)
addr : in reg32; -- CPU address
aVal : out std_logic; -- data address (act=0)
dev_select : out reg4); -- select input to CPU
constant LO_ADDR : integer := log2_ceil(SDRAM_BASE_ADDR);
constant HI_ADDR : integer := log2_ceil(SDRAM_BASE_ADDR + SDRAM_MEM_SZ - 1);
constant in_r : std_logic_vector(HI_ADDR downto LO_ADDR) := (others => '1');
constant ng_r : std_logic_vector(HI_ADDR downto LO_ADDR) := (others => '0');
constant oth : std_logic_vector(HI_SEL_BITS downto HI_ADDR+1):=(others=>'1');
constant ng_o : std_logic_vector(HI_SEL_BITS downto HI_ADDR+1):=(others=>'0');
end entity sdram_addr_decode;
architecture behavioral of sdram_addr_decode is
constant all_0 : std_logic_vector(31 downto 0) := (others=>'0');
constant a_hi : std_logic_vector(31 downto HI_ADDR+1) := (others=>'0');
constant a_lo : std_logic_vector(LO_ADDR-1 downto 0) := (others=>'0');
constant a_bits : std_logic_vector(HI_ADDR downto LO_ADDR) := (others=>'1');
constant a_mask : std_logic_vector := a_hi & a_bits & a_lo;
constant LO_RAM : natural := 0;
constant HI_RAM : natural := log2_ceil(SDRAM_MEM_SZ-1);
constant r_hi : std_logic_vector(31 downto HI_RAM+1) := (others=>'1');
constant r_lo : std_logic_vector(HI_RAM downto LO_RAM) := (others=>'0');
constant r_mask : std_logic_vector := r_hi & r_lo;
signal in_range : boolean;
constant SDRAM_ADDR_BOTTOM : natural :=
to_integer(signed(x_SDRAM_BASE_ADDR(HI_SEL_BITS downto LO_SEL_BITS)));
constant SDRAM_ADDR_RANGE : natural :=
(to_integer(signed(x_SDRAM_BASE_ADDR(HI_SEL_BITS downto LO_SEL_BITS)))
+
to_integer(signed(x_SDRAM_MEM_SZ(HI_SEL_BITS downto LO_SEL_BITS))));
constant SDRAM_ADDR_TOP : natural := SDRAM_ADDR_BOTTOM + SDRAM_ADDR_RANGE;
begin
-- this is ONLY acceptable for simulations;
-- computing these differences is TOO expensive for synthesis
in_range <= ( (to_integer(signed(addr(HI_SEL_BITS downto LO_SEL_BITS)))
>=
SDRAM_ADDR_BOTTOM)
and
(to_integer(signed(addr(HI_SEL_BITS downto LO_SEL_BITS)))
<
SDRAM_ADDR_TOP)
);
aVal <= '0' when (cpu_d_aVal = '0' and in_range) else '1';
dev_select <= b"1110" when (cpu_d_aVal = '0' and in_range) else b"0000";
assert TRUE -- cpu_d_aVal = '1'
report "e " & SLV32HEX(addr) &
" addr " & SLV2str(addr(15 downto 0)) & LF &
" LO_AD " & integer'image(LO_ADDR) &
" HI_AD " & integer'image(HI_ADDR) &
" a_hi " & SLV2STR(a_hi) &
" a_lo " & SLV2STR(a_lo) &
" a_bits " & SLV2STR(a_bits) &
" a_mask " & SLV32HEX(a_mask) & LF &
" LO_RAM " & integer'image(LO_RAM) &
" HI_RAM " & integer'image(HI_RAM) &
" r_hi " & SLV2STR(r_hi) &
" r_lo " & SLV2STR(r_lo) &
" r_mask " & SLV32HEX(r_mask)
severity NOTE;
end architecture behavioral;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
use work.all;
configuration CFG_TB of TB_CMIPS is
for ppl_type
end for;
end configuration CFG_TB;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
-------------------------------------------------------------------------------
-- Company: RAT Technologies
-- Engineer: Various RAT rats
--
-- Create Date: 1/31/2012
-- Design Name:
-- Module Name: RAT_wrapper - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Wrapper for RAT MCU. This model provides a template to
-- interface the RAT MCU to the Nexys2 development board.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RAT_wrapper is
Port ( LEDS : out STD_LOGIC_VECTOR (7 downto 0);
SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0);
DISP_EN : out STD_LOGIC_VECTOR (3 downto 0);
SWITCHES : in STD_LOGIC_VECTOR (7 downto 0);
BUTTONS : in STD_LOGIC_VECTOR (3 downto 0);
RESET : in STD_LOGIC;
CLK : in STD_LOGIC);
end RAT_wrapper;
architecture Behavioral of RAT_wrapper is
-------------------------------------------------------------------------------
-- INPUT PORT IDS -------------------------------------------------------------
CONSTANT SWITCHES_ID : STD_LOGIC_VECTOR (7 downto 0) := X"20";
CONSTANT BUTTONS_ID : STD_LOGIC_VECTOR (7 downto 0) := X"24";
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- OUTPUT PORT IDS ------------------------------------------------------------
CONSTANT LEDS_ID : STD_LOGIC_VECTOR (7 downto 0) := X"40";
CONSTANT SEGMENTS_ID : STD_LOGIC_VECTOR (7 downto 0) := X"82";
CONSTANT DISP_EN_ID : STD_LOGIC_VECTOR (7 downto 0) := X"83";
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Declare RAT_MCU ------------------------------------------------------------
component RAT_MCU
Port ( IN_PORT : in STD_LOGIC_VECTOR (7 downto 0);
OUT_PORT : out STD_LOGIC_VECTOR (7 downto 0);
PORT_ID : out STD_LOGIC_VECTOR (7 downto 0);
IO_STRB : out STD_LOGIC;
RESET : in STD_LOGIC;
INT : in STD_LOGIC;
CLK : in STD_LOGIC);
end component RAT_MCU;
-------------------------------------------------------------------------------
-- Signals for connecting RAT_MCU to RAT_wrapper -------------------------------
signal s_input_port : std_logic_vector (7 downto 0);
signal s_output_port : std_logic_vector (7 downto 0);
signal s_port_id : std_logic_vector (7 downto 0);
signal s_load : std_logic;
--signal s_interrupt : std_logic; -- not yet used
-- Register definitions for output devices ------------------------------------
signal r_LEDS : std_logic_vector (7 downto 0) := (others => '0');
signal r_SEGMENTS : std_logic_vector (7 downto 0) := (others => '0');
signal r_DISP_EN : std_logic_vector (3 downto 0) := (others => '0');
-------------------------------------------------------------------------------
begin
-- Instantiate RAT_MCU --------------------------------------------------------
MCU: RAT_MCU
port map( IN_PORT => s_input_port,
OUT_PORT => s_output_port,
PORT_ID => s_port_id,
RESET => RESET,
IO_STRB => s_load,
INT => BUTTONS(3),
CLK => CLK);
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- MUX for selecting what input to read
-------------------------------------------------------------------------------
inputs: process(s_port_id, SWITCHES, BUTTONS)
begin
if (s_port_id = SWITCHES_ID) then
s_input_port <= SWITCHES;
elsif (s_port_id = BUTTONS_ID) then
s_input_port <= "00000" & BUTTONS(2 downto 0);
else
s_input_port <= x"00";
end if;
end process inputs;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Decoder for updating output registers
-- Register updates depend on rising clock edge and asserted load signal
-------------------------------------------------------------------------------
outputs: process(CLK, s_load, s_port_id)
begin
if (rising_edge(CLK)) then
if (s_load = '1') then
if (s_port_id = LEDS_ID) then
r_LEDS <= s_output_port;
elsif (s_port_id = SEGMENTS_ID) then
r_SEGMENTS <= s_output_port;
elsif (s_port_id = DISP_EN_ID) then
r_DISP_EN <= s_output_port(3 downto 0);
end if;
end if;
end if;
end process outputs;
-------------------------------------------------------------------------------
-- Register Interface Assignments ---------------------------------------------
LEDS <= r_LEDS;
SEGMENTS <= r_SEGMENTS;
DISP_EN <= r_DISP_EN;
-------------------------------------------------------------------------------
end Behavioral;
|
package gen1 is
generic (v : natural);
function get return natural;
end gen1;
package body gen1 is
function get return natural is
begin
return v;
end get;
end gen1;
package gen2 is
generic (package pkg is new work.gen1 generic map (<>));
function get2 return natural;
end gen2;
package body gen2 is
function get2 return natural is
begin
return pkg.get;
end get2;
end gen2;
|
package gen1 is
generic (v : natural);
function get return natural;
end gen1;
package body gen1 is
function get return natural is
begin
return v;
end get;
end gen1;
package gen2 is
generic (package pkg is new work.gen1 generic map (<>));
function get2 return natural;
end gen2;
package body gen2 is
function get2 return natural is
begin
return pkg.get;
end get2;
end gen2;
|
--===========================================================================--
-- --
-- bit_funcs.vhd - Power2 & Log2 Funtions Package --
-- --
--===========================================================================--
--
-- File name : bit_funcs.vhd
--
-- Purpose : Implements power2 and log2 functions.
--
-- Dependencies : ieee.std_logic_1164
-- ieee.std_logic_arith
-- ieee.std_logic_unsigned
--
-- Author : John E. Kent
--
-- Email : [email protected]
--
-- Web : http://opencores.org/project,system09
--
-- bit_func.vhd is a VHDL functions package for calulating power2 and log2.
--
-- Copyright (C) 2003 - 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
-- --
-- Revision History --
-- --
--===========================================================================--
--
-- Revision Name Date Description
-- 0.1 John E. Kent unknown Initial version
-- 1.0 John E. Kent 30th May 2010 Added GPL Header
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
package bit_funcs is
function log2(v: in natural) return natural;
function pow2(v: in natural) return natural;
end package bit_funcs;
package body bit_funcs is
function log2 (v : in natural) return natural is
variable temp, log: natural;
begin
temp := v / 2;
log := 0;
while (temp /= 0) loop
temp := temp/2;
log := log + 1;
end loop;
return log;
end function log2;
function pow2(v: in natural) return natural is
variable i: natural;
variable pown: natural;
begin
pown := 1;
for i in 0 to v loop
exit when (i=v);
pown := pown * 2;
end loop;
return pown;
end function pow2;
end package body bit_funcs;
|
-------------------------------------------------------------------------------
-- Title : IGMP processor
-- Project :
-------------------------------------------------------------------------------
--! @file : igmp_processor.vhd
-- Author : Colin W. Shea
-- Company
-- Last update : 2010-06-01
-- Platform : Virtex 4/5/6
-------------------------------------------------------------------------------
--
--* @brief parsing incoming data stream for igmp requests
--
--! @details: This module parses the incoming stream of igmp data and signals
--the igmp controller for the packet type ie which response needs to be generated.
--!
--!
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity igmp_processor is
generic (
gen_dataWidth : integer := 8
);
port (
dataClk : in std_logic;
reset : in std_logic;
in_destIP : in std_logic_vector(31 downto 0);
igmp_data : in std_logic_vector(gen_dataWidth - 1 downto 0);
igmp_vld : in std_logic;
igmp_sof : in std_logic;
igmp_eof : in std_logic;
respond : out std_logic;
rsptime : out std_logic_vector(gen_dataWidth - 1 downto 0)
);
end igmp_processor;
architecture rtl of igmp_processor is
signal igmp_data_r : std_logic_vector(gen_dataWidth - 1 downto 0) := (others => '0');
signal igmp_vld_r : std_logic := '0';
signal igmp_sof_r : std_logic := '0';
-- signal igmp_eof_r : std_logic;
signal igmp_data_r2 : std_logic_vector(gen_dataWidth - 1 downto 0) := (others => '0');
signal igmp_vld_r2 : std_logic := '0';
signal igmp_sof_r2 : std_logic := '0';
-- signal igmp_eof_r2 : std_logic;
signal destIP : std_logic_vector(31 downto 0) := (others => '0');
signal igmpState : std_logic_vector(2 downto 0) := (others => '0');
signal responseTime : std_logic_vector(7 downto 0) := (others => '0');
signal byteCount : integer range 0 to 2 := 0;
begin -- trl
register_in_coming_data : process(dataClk, reset)
begin
if(rising_edge(dataClk))then
if(reset = '1')then
igmp_data_r <= (others => '0');
igmp_vld_r <= '0';
igmp_sof_r <= '0';
-- igmp_eof_r <= '0';
igmp_data_r2 <= (others => '0');
igmp_vld_r2 <= '0';
igmp_sof_r2 <= '0';
-- igmp_eof_r2 <= '0';
else
igmp_data_r <= igmp_data;
igmp_vld_r <= igmp_vld;
igmp_sof_r <= igmp_sof;
-- igmp_eof_r <= igmp_eof;
igmp_data_r2 <= igmp_data_r;
igmp_vld_r2 <= igmp_vld_r;
igmp_sof_r2 <= igmp_sof_r;
-- igmp_eof_r2 <= igmp_eof_r;
end if;
end if;
end process;
process_imcoming_stream : process(dataClk, reset)
begin
if(rising_edge(dataClk))then
if(reset = '1')then
igmpState <= (others => '0');
byteCount <= 0;
respond <= '0';
rsptime <= (others => '0');
responseTime <= (others => '0');
destIP <= (others => '0');
else
if(igmp_vld_r2 = '1')then
case igmpState is
when "000" =>
respond <= '0';
if(igmp_sof_r2 = '1' and igmp_data_r2 = X"11")then
igmpState <= "001";
else
igmpState <= "000";
end if;
when "001" =>
responseTime <= igmp_data_r2;
igmpState <= "010";
byteCount <= 2;
when "010" =>
if(byteCount = 1)then
igmpState <= "011";
else
igmpState <= "010";
byteCount <= byteCount -1;
end if;
when "011" =>
destIP(31 downto 24) <= igmp_data_r2;
igmpState <= "100";
when "100" =>
destIP(23 downto 16) <= igmp_data_r2;
igmpState <= "101";
when "101" =>
destIP(15 downto 8) <= igmp_data_r2;
igmpState <= "110";
when "110" =>
destIP(7 downto 0) <= igmp_data_r2;
igmpState <= "111";
when "111" =>
if((destIP = in_destIP) or (destIP = X"00000000"))then
respond <= '1';
rsptime <= responseTime;
else
respond <= '0';
end if;
igmpState <= "000";
when others =>
igmpState <= "000";
end case;
else
respond <= '0';
end if;
end if;
end if;
end process;
end rtl;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
-- synthesis translate_off
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;
use std.textio.all;
--library work;
--use work.AESL_components.all;
package AESL_sim_components is
-- simulation routines
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING;
token_len: out INTEGER);
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING);
procedure esl_assign_lv (signal LHS : out STD_LOGIC_VECTOR;
variable RHS : in STRING);
procedure esl_assign_l (signal LHS : out STD_LOGIC;
variable RHS : in STRING);
procedure esl_compare_l (signal LHS: in STD_LOGIC;
variable RHS: in STRING;
variable dontcare: in BOOLEAN;
variable isok: out BOOLEAN);
procedure esl_compare_lv (signal LHS: in STD_LOGIC_VECTOR;
variable RHS: in STRING;
variable dontcare: in BOOLEAN;
variable isok: out BOOLEAN);
function esl_conv_string (lv : STD_LOGIC_VECTOR) return STRING;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING;
function esl_conv_lv (str : string; base : integer; len : integer) return STD_LOGIC_VECTOR;
end package;
package body AESL_sim_components is
--simulation routines
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING;
token_len: out INTEGER) is
variable whitespace : CHARACTER;
variable i : INTEGER;
variable ok: BOOLEAN;
variable buff: STRING(1 to token'length);
begin
ok := false;
i := 1;
loop_main: while not endfile(textfile) loop
if textline = null or textline'length = 0 then
readline(textfile, textline);
end if;
loop_remove_whitespace: while textline'length > 0 loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
read(textline, whitespace);
else
exit loop_remove_whitespace;
end if;
end loop;
loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
exit loop_aesl_read_token;
else
read(textline, buff(i));
i := i + 1;
end if;
ok := true;
end loop;
if ok = true then
exit loop_main;
end if;
end loop;
buff(i) := ' ';
token := buff;
token_len:= i-1;
end procedure esl_read_token;
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING) is
variable i : INTEGER;
begin
esl_read_token (textfile, textline, token, i);
end procedure esl_read_token;
procedure esl_assign_lv (signal LHS : out STD_LOGIC_VECTOR;
variable RHS : in STRING) is
variable i : INTEGER;
variable bitwidth : INTEGER;
begin
bitwidth := LHS'length;
for i in 1 to bitwidth loop
if RHS(i) = '1' then
LHS(bitwidth - i) <= '1';
elsif RHS(i) = '0' then
LHS(bitwidth - i) <= '0';
else
LHS(bitwidth - i) <= 'X';
end if;
end loop;
end procedure;
procedure esl_assign_l (signal LHS : out STD_LOGIC;
variable RHS : in STRING) is
begin
if RHS(1) = '1' then
LHS <= '1';
elsif RHS(1) = '0' then
LHS <= '0';
else
LHS <= 'X';
end if;
end procedure;
procedure esl_compare_l (signal LHS: in STD_LOGIC;
variable RHS: in STRING;
variable dontcare: in BOOLEAN;
variable isok: out BOOLEAN) is
begin
if dontcare then
isok := true;
elsif RHS(1) = '1' then
if LHS = '1' then
isok := true;
else
isok := false;
end if;
elsif RHS(1) = '0' then
if LHS = '0' then
isok := true;
else
isok := false;
end if;
else
isok := true;
end if;
end procedure;
procedure esl_compare_lv (signal LHS: in STD_LOGIC_VECTOR;
variable RHS: in STRING;
variable dontcare: in BOOLEAN;
variable isok: out BOOLEAN) is
variable i : INTEGER;
variable bitwidth : INTEGER;
begin
bitwidth := LHS'length;
if dontcare then
isok := true;
else
isok := true;
loop_compare: for i in 1 to bitwidth loop
if RHS(i) = '1' then
if LHS(bitwidth - i) /= '1' then
isok := false;
exit loop_compare;
end if;
elsif RHS(i) = '0' then
if LHS(bitwidth - i) /= '0' then
isok := false;
exit loop_compare;
end if;
end if;
end loop;
end if;
end procedure;
function esl_conv_string (lv : STD_LOGIC_VECTOR) return STRING is
variable ret : STRING (1 to lv'length);
variable i: INTEGER;
begin
for i in 1 to lv'length loop
if lv(lv'length - i) = '1' then
ret(i) := '1';
elsif lv(lv'length - i) = '0' then
ret(i) := '0';
else
ret(i) := 'X';
end if;
end loop;
return ret;
end function;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is
constant LEN : integer := (lv'length + 3)/4;
variable ret : STRING (1 to LEN);
variable i, tmp: INTEGER;
variable normal_lv : STD_LOGIC_VECTOR(LEN * 4 - 1 downto 0);
variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0);
begin
normal_lv := (others => '0');
normal_lv(lv'length - 1 downto 0) := lv;
for i in 0 to LEN - 1 loop
tmp_lv := normal_lv(LEN * 4 - 1 - i * 4 downto LEN * 4 - 4 - i * 4);
case tmp_lv is
when "0000" => ret(i + 1) := '0';
when "0001" => ret(i + 1) := '1';
when "0010" => ret(i + 1) := '2';
when "0011" => ret(i + 1) := '3';
when "0100" => ret(i + 1) := '4';
when "0101" => ret(i + 1) := '5';
when "0110" => ret(i + 1) := '6';
when "0111" => ret(i + 1) := '7';
when "1000" => ret(i + 1) := '8';
when "1001" => ret(i + 1) := '9';
when "1010" => ret(i + 1) := 'a';
when "1011" => ret(i + 1) := 'b';
when "1100" => ret(i + 1) := 'c';
when "1101" => ret(i + 1) := 'd';
when "1110" => ret(i + 1) := 'e';
when "1111" => ret(i + 1) := 'f';
when others => ret(i + 1) := '0';
end case;
end loop;
return ret;
end function;
function esl_conv_lv (str : STRING; base : integer; len : integer) return STD_LOGIC_VECTOR is
variable ret : STD_LOGIC_VECTOR(len - 1 downto 0);
variable val : integer := 0;
variable pos : boolean := true;
variable i : integer;
begin
loop_main: for i in 1 to str'length loop
if str(i) = ' ' or str(i) = HT or str(i) = CR or str(i) = LF then
exit loop_main;
elsif str(i) = '-' then
pos := false;
else
case base is
when 10 =>
if '0' <= str(i) and str(i) <= '9' then
val := val*10 + character'pos(str(i)) - character'pos('0');
else
val := val*10;
end if;
when others =>
val := 0;
end case;
end if;
end loop;
if pos = false then
val := val * (-1);
end if;
ret := conv_std_logic_vector(val, len);
return ret;
end function;
end package body;
-- synthesis translate_on
-- XSIP watermark, do not delete 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
-- synthesis translate_off
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;
use std.textio.all;
--library work;
--use work.AESL_components.all;
package AESL_sim_components is
-- simulation routines
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING;
token_len: out INTEGER);
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING);
procedure esl_assign_lv (signal LHS : out STD_LOGIC_VECTOR;
variable RHS : in STRING);
procedure esl_assign_l (signal LHS : out STD_LOGIC;
variable RHS : in STRING);
procedure esl_compare_l (signal LHS: in STD_LOGIC;
variable RHS: in STRING;
variable dontcare: in BOOLEAN;
variable isok: out BOOLEAN);
procedure esl_compare_lv (signal LHS: in STD_LOGIC_VECTOR;
variable RHS: in STRING;
variable dontcare: in BOOLEAN;
variable isok: out BOOLEAN);
function esl_conv_string (lv : STD_LOGIC_VECTOR) return STRING;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING;
function esl_conv_lv (str : string; base : integer; len : integer) return STD_LOGIC_VECTOR;
end package;
package body AESL_sim_components is
--simulation routines
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING;
token_len: out INTEGER) is
variable whitespace : CHARACTER;
variable i : INTEGER;
variable ok: BOOLEAN;
variable buff: STRING(1 to token'length);
begin
ok := false;
i := 1;
loop_main: while not endfile(textfile) loop
if textline = null or textline'length = 0 then
readline(textfile, textline);
end if;
loop_remove_whitespace: while textline'length > 0 loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
read(textline, whitespace);
else
exit loop_remove_whitespace;
end if;
end loop;
loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
exit loop_aesl_read_token;
else
read(textline, buff(i));
i := i + 1;
end if;
ok := true;
end loop;
if ok = true then
exit loop_main;
end if;
end loop;
buff(i) := ' ';
token := buff;
token_len:= i-1;
end procedure esl_read_token;
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING) is
variable i : INTEGER;
begin
esl_read_token (textfile, textline, token, i);
end procedure esl_read_token;
procedure esl_assign_lv (signal LHS : out STD_LOGIC_VECTOR;
variable RHS : in STRING) is
variable i : INTEGER;
variable bitwidth : INTEGER;
begin
bitwidth := LHS'length;
for i in 1 to bitwidth loop
if RHS(i) = '1' then
LHS(bitwidth - i) <= '1';
elsif RHS(i) = '0' then
LHS(bitwidth - i) <= '0';
else
LHS(bitwidth - i) <= 'X';
end if;
end loop;
end procedure;
procedure esl_assign_l (signal LHS : out STD_LOGIC;
variable RHS : in STRING) is
begin
if RHS(1) = '1' then
LHS <= '1';
elsif RHS(1) = '0' then
LHS <= '0';
else
LHS <= 'X';
end if;
end procedure;
procedure esl_compare_l (signal LHS: in STD_LOGIC;
variable RHS: in STRING;
variable dontcare: in BOOLEAN;
variable isok: out BOOLEAN) is
begin
if dontcare then
isok := true;
elsif RHS(1) = '1' then
if LHS = '1' then
isok := true;
else
isok := false;
end if;
elsif RHS(1) = '0' then
if LHS = '0' then
isok := true;
else
isok := false;
end if;
else
isok := true;
end if;
end procedure;
procedure esl_compare_lv (signal LHS: in STD_LOGIC_VECTOR;
variable RHS: in STRING;
variable dontcare: in BOOLEAN;
variable isok: out BOOLEAN) is
variable i : INTEGER;
variable bitwidth : INTEGER;
begin
bitwidth := LHS'length;
if dontcare then
isok := true;
else
isok := true;
loop_compare: for i in 1 to bitwidth loop
if RHS(i) = '1' then
if LHS(bitwidth - i) /= '1' then
isok := false;
exit loop_compare;
end if;
elsif RHS(i) = '0' then
if LHS(bitwidth - i) /= '0' then
isok := false;
exit loop_compare;
end if;
end if;
end loop;
end if;
end procedure;
function esl_conv_string (lv : STD_LOGIC_VECTOR) return STRING is
variable ret : STRING (1 to lv'length);
variable i: INTEGER;
begin
for i in 1 to lv'length loop
if lv(lv'length - i) = '1' then
ret(i) := '1';
elsif lv(lv'length - i) = '0' then
ret(i) := '0';
else
ret(i) := 'X';
end if;
end loop;
return ret;
end function;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is
constant LEN : integer := (lv'length + 3)/4;
variable ret : STRING (1 to LEN);
variable i, tmp: INTEGER;
variable normal_lv : STD_LOGIC_VECTOR(LEN * 4 - 1 downto 0);
variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0);
begin
normal_lv := (others => '0');
normal_lv(lv'length - 1 downto 0) := lv;
for i in 0 to LEN - 1 loop
tmp_lv := normal_lv(LEN * 4 - 1 - i * 4 downto LEN * 4 - 4 - i * 4);
case tmp_lv is
when "0000" => ret(i + 1) := '0';
when "0001" => ret(i + 1) := '1';
when "0010" => ret(i + 1) := '2';
when "0011" => ret(i + 1) := '3';
when "0100" => ret(i + 1) := '4';
when "0101" => ret(i + 1) := '5';
when "0110" => ret(i + 1) := '6';
when "0111" => ret(i + 1) := '7';
when "1000" => ret(i + 1) := '8';
when "1001" => ret(i + 1) := '9';
when "1010" => ret(i + 1) := 'a';
when "1011" => ret(i + 1) := 'b';
when "1100" => ret(i + 1) := 'c';
when "1101" => ret(i + 1) := 'd';
when "1110" => ret(i + 1) := 'e';
when "1111" => ret(i + 1) := 'f';
when others => ret(i + 1) := '0';
end case;
end loop;
return ret;
end function;
function esl_conv_lv (str : STRING; base : integer; len : integer) return STD_LOGIC_VECTOR is
variable ret : STD_LOGIC_VECTOR(len - 1 downto 0);
variable val : integer := 0;
variable pos : boolean := true;
variable i : integer;
begin
loop_main: for i in 1 to str'length loop
if str(i) = ' ' or str(i) = HT or str(i) = CR or str(i) = LF then
exit loop_main;
elsif str(i) = '-' then
pos := false;
else
case base is
when 10 =>
if '0' <= str(i) and str(i) <= '9' then
val := val*10 + character'pos(str(i)) - character'pos('0');
else
val := val*10;
end if;
when others =>
val := 0;
end case;
end if;
end loop;
if pos = false then
val := val * (-1);
end if;
ret := conv_std_logic_vector(val, len);
return ret;
end function;
end package body;
-- synthesis translate_on
-- XSIP watermark, do not delete 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_sincos_s5
-- VHDL created on Wed Mar 27 09:55:14 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_sincos_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
s : out std_logic_vector(31 downto 0);
c : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_sincos_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid8_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid22_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid23_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShift_uid24_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid25_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid26_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstZwShiftP1_uid27_fpSinCosXTest_q : std_logic_vector (13 downto 0);
signal cstNaNwF_uid32_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal cstZmwFRRPwSM1_uid52_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal cPi_uid71_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal p_uid73_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal p_uid73_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal expPSin_uid76_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal expPSin_uid76_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal multSinOp2_uid91_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal multSinOp2_uid91_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_a : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_s1 : std_logic_vector (51 downto 0);
signal mulSin_uid92_fpSinCosXTest_pr : UNSIGNED (51 downto 0);
signal mulSin_uid92_fpSinCosXTest_q : std_logic_vector (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_a : std_logic_vector (25 downto 0);
signal mulCos_uid105_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal mulCos_uid105_fpSinCosXTest_s1 : std_logic_vector (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_pr : UNSIGNED (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_q : std_logic_vector (51 downto 0);
signal excSelSin_uid119_fpSinCosXTest_q : std_logic_vector(1 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expSelectorCos_uid145_fpSinCosXTest_q : std_logic_vector(1 downto 0);
signal signRCond2_uid152_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_d : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_d : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q : std_logic_vector (29 downto 0);
signal leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal zs_uid236_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal mO_uid239_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (62 downto 0);
signal zs_uid244_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal zs_uid250_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (5 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(63 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(63 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (47 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a : std_logic_vector (12 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr : SIGNED (26 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q : std_logic_vector (25 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a : std_logic_vector (14 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b : std_logic_vector (22 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr : SIGNED (38 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q : std_logic_vector (37 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a : std_logic_vector (12 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr : SIGNED (26 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q : std_logic_vector (25 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a : std_logic_vector (14 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b : std_logic_vector (22 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr : SIGNED (38 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q : std_logic_vector (37 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0 : std_logic;
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0 : std_logic;
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q : std_logic_vector (39 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a : std_logic_vector(81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b : std_logic_vector(81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o : std_logic_vector (81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q : std_logic_vector (81 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC0_uid394_tableGensinPiZ_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC1_uid396_tableGensinPiZ_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC2_uid398_tableGensinPiZ_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_q : std_logic_vector (12 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC0_uid400_tableGencosPiZ_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC1_uid402_tableGencosPiZ_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC2_uid404_tableGencosPiZ_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_q : std_logic_vector (12 downto 0);
signal reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q : std_logic_vector (2 downto 0);
signal reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q : std_logic_vector (39 downto 0);
signal reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (39 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q : std_logic_vector (26 downto 0);
signal reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (77 downto 0);
signal reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q : std_logic_vector (67 downto 0);
signal reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q : std_logic_vector (66 downto 0);
signal reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q : std_logic_vector (65 downto 0);
signal reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q : std_logic_vector (67 downto 0);
signal reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q : std_logic_vector (25 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q : std_logic_vector (12 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q : std_logic_vector (20 downto 0);
signal reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q : std_logic_vector (22 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q : std_logic_vector (29 downto 0);
signal reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q : std_logic_vector (6 downto 0);
signal reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q : std_logic_vector (22 downto 0);
signal reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q : std_logic_vector (0 downto 0);
signal reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q : std_logic_vector (12 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q : std_logic_vector (20 downto 0);
signal reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q : std_logic_vector (22 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q : std_logic_vector (29 downto 0);
signal reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q : std_logic_vector (25 downto 0);
signal reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q : std_logic_vector (25 downto 0);
signal reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q : std_logic_vector (6 downto 0);
signal reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q : std_logic_vector (22 downto 0);
signal reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q : std_logic_vector (3 downto 0);
signal reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q : std_logic_vector (52 downto 0);
signal ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q : std_logic_vector (65 downto 0);
signal ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q : std_logic_vector (67 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (7 downto 0);
signal ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (66 downto 0);
signal ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (65 downto 0);
signal ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (64 downto 0);
signal ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q : std_logic_vector (63 downto 0);
signal ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q : std_logic_vector (31 downto 0);
signal ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (58 downto 0);
signal ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q : std_logic_vector (63 downto 0);
signal ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q : std_logic_vector (31 downto 0);
signal ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (58 downto 0);
signal ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (76 downto 0);
signal ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (75 downto 0);
signal ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (74 downto 0);
signal ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q : std_logic_vector (12 downto 0);
signal ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q : std_logic_vector (53 downto 0);
signal ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q : std_logic_vector (12 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0 : std_logic;
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q : signal is true;
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q : std_logic_vector (6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0 : std_logic;
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q : signal is true;
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q : signal is true;
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0 : std_logic;
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0 : std_logic;
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0 : std_logic;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq : std_logic;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q : signal is true;
signal sinXIsXRR_uid41_fpSinCosXTest_a : std_logic_vector(11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_b : std_logic_vector(11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_o : std_logic_vector (11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_a : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_b : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_o : std_logic_vector (11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal yIsZero_uid51_fpSinCosXTest_a : std_logic_vector(65 downto 0);
signal yIsZero_uid51_fpSinCosXTest_b : std_logic_vector(65 downto 0);
signal yIsZero_uid51_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal pad_one_uid55_fpSinCosXTest_q : std_logic_vector (66 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_a : std_logic_vector(70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_b : std_logic_vector(70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_o : std_logic_vector (70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_c : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal InvCmpYToOneMinusY_uid61_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCmpYToOneMinusY_uid61_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid127_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid127_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvSinXIsXRR_uid128_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsXRR_uid128_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid131_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid131_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid132_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid132_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid136_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid136_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvCosXONe_uid149_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCosXONe_uid149_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid151_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid151_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvIntXParity_uid155_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvIntXParity_uid155_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal oFracXRR_uid43_uid43_fpSinCosXTest_q : std_logic_vector (53 downto 0);
signal half_uid53_fpSinCosXTest_q : std_logic_vector (65 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal exp_uid9_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal exp_uid9_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal frac_uid13_fpSinCosXTest_in : std_logic_vector (22 downto 0);
signal frac_uid13_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal signX_uid37_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal signX_uid37_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal expFracX_uid166_px_uid33_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal expFracX_uid166_px_uid33_fpSinCosXTest_b : std_logic_vector (30 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_q : std_logic_vector (9 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_a : std_logic_vector(65 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_b : std_logic_vector(65 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_a : std_logic_vector(67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_b : std_logic_vector(67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_o : std_logic_vector (67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal zSin_uid60_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal zSin_uid60_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal zCos_uid64_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal zCos_uid64_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal expSinHC_uid74_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal excRNaN_uid117_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid117_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid117_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracRPostExcSin_uid122_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExcSin_uid122_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal expRPostExcSin_uid126_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExcSin_uid126_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracRPostExcCos_uid142_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExcCos_uid142_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal expRPostExcCos_uid147_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExcCos_uid147_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cosXONe_uid148_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal cosXONe_uid148_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal cosXONe_uid148_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal finalExp_uid209_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal finalExp_uid209_rrx_uid34_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal extendedFracX_uid47_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal normBitSin_uid93_fpSinCosXTest_in : std_logic_vector (51 downto 0);
signal normBitSin_uid93_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal fracRSinPreRndHigh_uid95_fpSinCosXTest_in : std_logic_vector (50 downto 0);
signal fracRSinPreRndHigh_uid95_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracRSinPreRndLow_uid96_fpSinCosXTest_in : std_logic_vector (49 downto 0);
signal fracRSinPreRndLow_uid96_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal normBitCos_uid106_fpSinCosXTest_in : std_logic_vector (51 downto 0);
signal normBitCos_uid106_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal fracRCosPreRndHigh_uid108_fpSinCosXTest_in : std_logic_vector (50 downto 0);
signal fracRCosPreRndHigh_uid108_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracRCosPreRndLow_uid109_fpSinCosXTest_in : std_logic_vector (49 downto 0);
signal fracRCosPreRndLow_uid109_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q : std_logic_vector (52 downto 0);
signal leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b : std_logic_vector (23 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int : std_logic_vector (80 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q : std_logic_vector (80 downto 0);
signal os_uid196_rrx_uid34_fpSinCosXTest_q : std_logic_vector (79 downto 0);
signal leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal join_uid99_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal join_uid141_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal zSinYBottom_uid59_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal zSinYBottom_uid59_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal zSinOMyBottom_uid58_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal zSinOMyBottom_uid58_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal excSelBitsSin_uid118_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal fpSin_uid134_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal join_uid143_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal fpCos_uid162_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int : std_logic_vector (107 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q : std_logic_vector (107 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal fracX_uid187_rrx_uid34_fpSinCosXTest_in : std_logic_vector (22 downto 0);
signal fracX_uid187_rrx_uid34_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal oFracXRRSmallXRR_uid90_fpSinCosXTest_in : std_logic_vector (53 downto 0);
signal oFracXRRSmallXRR_uid90_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal R_uid167_px_uid33_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal InvFracXIsZero_uid16_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid16_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fxpXShiftVal_uid46_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal fxpXShiftVal_uid46_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal addr_uid81_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal addr_uid81_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal zPsinPiZ_uid84_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal zPsinPiZ_uid84_fpSinCosXTest_b : std_logic_vector (14 downto 0);
signal rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (32 downto 0);
signal addr_uid83_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal addr_uid83_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal zPcosPiZ_uid87_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal zPcosPiZ_uid87_fpSinCosXTest_b : std_logic_vector (14 downto 0);
signal rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (32 downto 0);
signal expSinHCR_uid75_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expSinHCR_uid75_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal expPCos_uid79_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expPCos_uid79_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (66 downto 0);
signal LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (66 downto 0);
signal LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (65 downto 0);
signal LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (58 downto 0);
signal rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (58 downto 0);
signal rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (76 downto 0);
signal LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (76 downto 0);
signal LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (75 downto 0);
signal LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (75 downto 0);
signal LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (74 downto 0);
signal LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (74 downto 0);
signal X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (59 downto 0);
signal X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (59 downto 0);
signal X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (55 downto 0);
signal X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (55 downto 0);
signal fracRSinPreRnd_uid97_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal fracRSinPreRnd_uid97_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal fracRCosPreRnd_uid110_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal fracRCosPreRnd_uid110_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal cosRndOp_uid112_uid113_fpSinCosXTest_q : std_logic_vector (24 downto 0);
signal rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal lowRangeB_uid408_polyEvalsinPiZ_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid408_polyEvalsinPiZ_b : std_logic_vector (0 downto 0);
signal highBBits_uid409_polyEvalsinPiZ_in : std_logic_vector (13 downto 0);
signal highBBits_uid409_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid414_polyEvalsinPiZ_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid414_polyEvalsinPiZ_b : std_logic_vector (1 downto 0);
signal highBBits_uid415_polyEvalsinPiZ_in : std_logic_vector (23 downto 0);
signal highBBits_uid415_polyEvalsinPiZ_b : std_logic_vector (21 downto 0);
signal lowRangeB_uid421_polyEvalcosPiZ_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid421_polyEvalcosPiZ_b : std_logic_vector (0 downto 0);
signal highBBits_uid422_polyEvalcosPiZ_in : std_logic_vector (13 downto 0);
signal highBBits_uid422_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid427_polyEvalcosPiZ_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid427_polyEvalcosPiZ_b : std_logic_vector (1 downto 0);
signal highBBits_uid428_polyEvalcosPiZ_in : std_logic_vector (23 downto 0);
signal highBBits_uid428_polyEvalcosPiZ_b : std_logic_vector (21 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in : std_logic_vector (80 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b : std_logic_vector (26 downto 0);
signal fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in : std_logic_vector (76 downto 0);
signal fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b : std_logic_vector (52 downto 0);
signal intXParity_uid49_fpSinCosXTest_in : std_logic_vector (67 downto 0);
signal intXParity_uid49_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal y_uid50_fpSinCosXTest_in : std_logic_vector (66 downto 0);
signal y_uid50_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal sinRndOp_uid100_uid101_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal expSelBitsCos_uid144_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a : std_logic_vector(108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b : std_logic_vector(108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o : std_logic_vector (108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q : std_logic_vector (108 downto 0);
signal oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal expX_uid186_rrx_uid34_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal expX_uid186_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal exc_N_uid17_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal yT1_uid406_polyEvalsinPiZ_in : std_logic_vector (14 downto 0);
signal yT1_uid406_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal yT1_uid419_polyEvalcosPiZ_in : std_logic_vector (14 downto 0);
signal yT1_uid419_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_a : std_logic_vector(32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_b : std_logic_vector(32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_o : std_logic_vector (32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_q : std_logic_vector (30 downto 0);
signal finalFrac_uid208_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal finalFrac_uid208_rrx_uid34_fpSinCosXTest_q : std_logic_vector (52 downto 0);
signal signComp_uid129_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_a : std_logic_vector(32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_b : std_logic_vector(32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_o : std_logic_vector (32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_q : std_logic_vector (32 downto 0);
signal leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal multFracBits_uid199_rrx_uid34_fpSinCosXTest_in : std_logic_vector (77 downto 0);
signal multFracBits_uid199_rrx_uid34_fpSinCosXTest_b : std_logic_vector (77 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b : std_logic_vector (26 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (5 downto 0);
signal fracRCompCos_uid115_fpSinCosXTest_in : std_logic_vector (23 downto 0);
signal fracRCompCos_uid115_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal expRCompSin_uid116_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal expRCompSin_uid116_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal s1_uid408_uid411_polyEvalsinPiZ_q : std_logic_vector (22 downto 0);
signal s2_uid414_uid417_polyEvalsinPiZ_q : std_logic_vector (32 downto 0);
signal s1_uid421_uid424_polyEvalcosPiZ_q : std_logic_vector (22 downto 0);
signal s2_uid427_uid430_polyEvalcosPiZ_q : std_logic_vector (32 downto 0);
signal RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q : std_logic_vector (61 downto 0);
signal signR_uid130_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signR_uid130_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signR_uid130_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal fracRCompSin_uid103_fpSinCosXTest_in : std_logic_vector (23 downto 0);
signal fracRCompSin_uid103_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal expRCompSin_uid104_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal expRCompSin_uid104_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in : std_logic_vector (77 downto 0);
signal multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (61 downto 0);
signal X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (61 downto 0);
signal X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (45 downto 0);
signal X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (45 downto 0);
signal X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (29 downto 0);
signal X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (29 downto 0);
signal expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal polyEvalSigsinPiZ_uid86_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal polyEvalSigsinPiZ_uid86_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal polyEvalSigcosPiZ_uid89_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal polyEvalSigcosPiZ_uid89_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal expXRR_uid38_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal expXRR_uid38_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal fracXRR_uid39_fpSinCosXTest_in : std_logic_vector (52 downto 0);
signal fracXRR_uid39_fpSinCosXTest_b : std_logic_vector (52 downto 0);
signal pHigh_uid72_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal pHigh_uid72_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal pCos_uid77_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal pCos_uid77_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal r_uid277_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (6 downto 0);
signal r_uid356_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (6 downto 0);
signal expCompOut_uid205_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expCompOut_uid205_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (73 downto 0);
signal LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (73 downto 0);
signal LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (69 downto 0);
signal LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (69 downto 0);
signal LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (65 downto 0);
signal LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (56 downto 0);
signal LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (48 downto 0);
signal LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (48 downto 0);
signal LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (40 downto 0);
signal LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (40 downto 0);
signal LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (56 downto 0);
signal LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (48 downto 0);
signal LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (48 downto 0);
signal LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (40 downto 0);
signal LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (40 downto 0);
signal leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
begin
--xIn(GPIN,3)@0
--GND(CONSTANT,0)
GND_q <= "0";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable(LOGICAL,1282)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q <= not ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor(LOGICAL,1422)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q <= not (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a or ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b);
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top(CONSTANT,1418)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q <= "01011";
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp(LOGICAL,1419)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q <= "1" when ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a = ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b else "0";
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg(REG,1420)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena(REG,1423)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd(LOGICAL,1424)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b <= en;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a and ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b;
--expFracX_uid166_px_uid33_fpSinCosXTest(BITSELECT,165)@0
expFracX_uid166_px_uid33_fpSinCosXTest_in <= a(30 downto 0);
expFracX_uid166_px_uid33_fpSinCosXTest_b <= expFracX_uid166_px_uid33_fpSinCosXTest_in(30 downto 0);
--R_uid167_px_uid33_fpSinCosXTest(BITJOIN,166)@0
R_uid167_px_uid33_fpSinCosXTest_q <= GND_q & expFracX_uid166_px_uid33_fpSinCosXTest_b;
--expX_uid186_rrx_uid34_fpSinCosXTest(BITSELECT,185)@0
expX_uid186_rrx_uid34_fpSinCosXTest_in <= R_uid167_px_uid33_fpSinCosXTest_q(30 downto 0);
expX_uid186_rrx_uid34_fpSinCosXTest_b <= expX_uid186_rrx_uid34_fpSinCosXTest_in(30 downto 23);
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg(DELAY,1412)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid186_rrx_uid34_fpSinCosXTest_b, xout => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt(COUNTER,1414)
-- every=1, low=0, high=11, step=1, init=1
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i = 10 THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i - 11;
ELSE
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg(REG,1415)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux(MUX,1416)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem(DUALMEM,1413)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 12,
width_b => 8,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia
);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--zs_uid244_lzcZSin_uid66_fpSinCosXTest(CONSTANT,243)
zs_uid244_lzcZSin_uid66_fpSinCosXTest_q <= "00000000000000000000000000000000";
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor(LOGICAL,1396)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q <= not (ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a or ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b);
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg(REG,1318)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena(REG,1397)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q = "1") THEN
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd(LOGICAL,1398)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b <= en;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a and ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg(DELAY,1388)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid167_px_uid33_fpSinCosXTest_q, xout => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt(COUNTER,1314)
-- every=1, low=0, high=1, step=1, init=1
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i,1));
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg(REG,1315)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux(MUX,1316)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s <= en;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux: PROCESS (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s, ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q, ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q)
BEGIN
CASE ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s IS
WHEN "0" => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
WHEN "1" => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem(DUALMEM,1389)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 1,
numwords_a => 2,
width_b => 32,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq,
address_a => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa,
data_a => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia
);
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0 <= areset;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq(31 downto 0);
--fracX_uid187_rrx_uid34_fpSinCosXTest(BITSELECT,186)@4
fracX_uid187_rrx_uid34_fpSinCosXTest_in <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q(22 downto 0);
fracX_uid187_rrx_uid34_fpSinCosXTest_b <= fracX_uid187_rrx_uid34_fpSinCosXTest_in(22 downto 0);
--oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest(BITJOIN,196)@4
oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q <= VCC_q & fracX_uid187_rrx_uid34_fpSinCosXTest_b;
--prod_uid198_rrx_uid34_fpSinCosXTest_b_0(BITSELECT,518)@4
prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in <= STD_LOGIC_VECTOR("000" & oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q);
prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b <= prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in(26 downto 0);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1(REG,539)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q <= prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShift_uid24_fpSinCosXTest(CONSTANT,23)
cstBiasMwShift_uid24_fpSinCosXTest_q <= "01110011";
--expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest(SUB,191)@0
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expX_uid186_rrx_uid34_fpSinCosXTest_b);
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0" & cstBiasMwShift_uid24_fpSinCosXTest_q);
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b));
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q <= expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o(8 downto 0);
--expXTableAddr_uid193_rrx_uid34_fpSinCosXTest(BITSELECT,192)@0
expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in <= expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q(7 downto 0);
expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b <= expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0(REG,534)@0
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q <= expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem(DUALMEM,514)@1
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia <= (others => '0');
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa <= (others => '0');
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab <= reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q;
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq,
address_a => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa,
data_a => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia
);
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0 <= areset;
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q <= rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1(REG,537)@3
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q <= rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem(DUALMEM,513)@1
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia <= (others => '0');
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa <= (others => '0');
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab <= reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q;
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq,
address_a => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa,
data_a => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia
);
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0 <= areset;
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q <= rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0(REG,536)@3
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q <= rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid196_rrx_uid34_fpSinCosXTest(BITJOIN,195)@4
os_uid196_rrx_uid34_fpSinCosXTest_q <= reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q & reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q;
--prod_uid198_rrx_uid34_fpSinCosXTest_a_2(BITSELECT,517)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in <= STD_LOGIC_VECTOR("0" & os_uid196_rrx_uid34_fpSinCosXTest_q);
prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in(80 downto 54);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0(REG,542)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0(MULT,521)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1;
END IF;
END IF;
END PROCESS;
--ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a(DELAY,1145)@8
ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a : dspba_delay
GENERIC MAP ( width => 54, depth => 1 )
PORT MAP ( xin => prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q, xout => ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--prod_uid198_rrx_uid34_fpSinCosXTest_align_2(BITSHIFT,524)@9
prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int <= ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int(107 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_a_1(BITSELECT,516)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in <= os_uid196_rrx_uid34_fpSinCosXTest_q(53 downto 0);
prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in(53 downto 27);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0(REG,540)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0(MULT,520)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_align_1(BITSHIFT,523)@8
prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int <= prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q & "000000000000000000000000000";
prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int(80 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_a_0(BITSELECT,515)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in <= os_uid196_rrx_uid34_fpSinCosXTest_q(26 downto 0);
prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in(26 downto 0);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0(REG,538)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0(MULT,519)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_align_0(BITSHIFT,522)@8
prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int <= prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int(53 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0(ADD,525)@8
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a <= STD_LOGIC_VECTOR("0000000000000000000000000000" & prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b <= STD_LOGIC_VECTOR("0" & prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a) + UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b));
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o(81 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0(ADD,526)@9
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a <= STD_LOGIC_VECTOR("000000000000000000000000000" & prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b <= STD_LOGIC_VECTOR("0" & prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a) + UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b));
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o(108 downto 0);
--multFracBits_uid199_rrx_uid34_fpSinCosXTest(BITSELECT,198)@9
multFracBits_uid199_rrx_uid34_fpSinCosXTest_in <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q(77 downto 0);
multFracBits_uid199_rrx_uid34_fpSinCosXTest_b <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_in(77 downto 0);
--multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest(BITSELECT,199)@9
multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b;
multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b <= multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in(77 downto 46);
--reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1(REG,544)@9
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,433)@10
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a(DELAY,1178)@10
ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xout => ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5(REG,555)@12
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q <= ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q;
END IF;
END IF;
END PROCESS;
--zs_uid250_lzcZSin_uid66_fpSinCosXTest(CONSTANT,249)
zs_uid250_lzcZSin_uid66_fpSinCosXTest_q <= "0000000000000000";
--mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest(CONSTANT,434)
mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "11111111111111111111111111111111";
--vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,436)@10
vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q, mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,438)@10
rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in(31 downto 16);
--reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1(REG,546)@10
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,439)@11
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4(REG,554)@11
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q <= vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e(DELAY,1081)@12
ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWE_uid8_fpSinCosXTest(CONSTANT,7)
cstAllZWE_uid8_fpSinCosXTest_q <= "00000000";
--vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,440)@10
vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q(15 downto 0);
vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in(15 downto 0);
--reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,548)@10
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,442)@11
vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q, reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,444)@11
rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in(15 downto 8);
--vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,445)@11
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i <= "1" when vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xin => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d(DELAY,1080)@12
ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xout => ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest(CONSTANT,212)
leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q <= "0000";
--vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,446)@11
vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q(7 downto 0);
vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,550)@11
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,549)@11
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,448)@12
vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q, reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,450)@12
rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in(7 downto 4);
--vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,451)@12
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,553)@12
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest(CONSTANT,226)
leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q <= "00";
--vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,452)@12
vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q(3 downto 0);
vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in(3 downto 0);
--vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,454)@12
vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b, vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
WHEN "1" => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,456)@12
rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in(3 downto 2);
--vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,457)@12
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i <= "1" when vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xin => vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,458)@12
vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q(1 downto 0);
vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in(1 downto 0);
--reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,552)@12
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,551)@12
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,460)@13
vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q, reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,462)@13
rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in(1 downto 1);
--vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,463)@13
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= GND_q;
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest(BITJOIN,464)@13
r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q & ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q & ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q & reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q & vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q & vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
--cstBiasM1_uid23_fpSinCosXTest(CONSTANT,22)
cstBiasM1_uid23_fpSinCosXTest_q <= "01111110";
--expCompOutExt_uid204_rrx_uid34_fpSinCosXTest(SUB,203)@13
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("000" & r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q);
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b));
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q <= expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o(8 downto 0);
--expCompOut_uid205_rrx_uid34_fpSinCosXTest(BITSELECT,204)@13
expCompOut_uid205_rrx_uid34_fpSinCosXTest_in <= expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q(7 downto 0);
expCompOut_uid205_rrx_uid34_fpSinCosXTest_b <= expCompOut_uid205_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2(REG,564)@13
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q <= expCompOut_uid205_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--xBranch_uid191_rrx_uid34_fpSinCosXTest(COMPARE,190)@0
xBranch_uid191_rrx_uid34_fpSinCosXTest_cin <= GND_q;
xBranch_uid191_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid24_fpSinCosXTest_q) & '0';
xBranch_uid191_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & expX_uid186_rrx_uid34_fpSinCosXTest_b) & xBranch_uid191_rrx_uid34_fpSinCosXTest_cin(0);
xBranch_uid191_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xBranch_uid191_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(xBranch_uid191_rrx_uid34_fpSinCosXTest_b));
xBranch_uid191_rrx_uid34_fpSinCosXTest_n(0) <= not xBranch_uid191_rrx_uid34_fpSinCosXTest_o(10);
--reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1(REG,563)@0
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q <= xBranch_uid191_rrx_uid34_fpSinCosXTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b(DELAY,829)@1
ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q, xout => ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalExp_uid209_rrx_uid34_fpSinCosXTest(MUX,208)@14
finalExp_uid209_rrx_uid34_fpSinCosXTest_s <= ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q;
finalExp_uid209_rrx_uid34_fpSinCosXTest: PROCESS (finalExp_uid209_rrx_uid34_fpSinCosXTest_s, en, reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q)
BEGIN
CASE finalExp_uid209_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b(DELAY,833)@14
ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => finalExp_uid209_rrx_uid34_fpSinCosXTest_q, xout => ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1409)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a or ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top(CONSTANT,1279)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q <= "01000";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp(LOGICAL,1280)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q <= "1" when ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a = ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b else "0";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg(REG,1281)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1410)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1411)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1399)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid187_rrx_uid34_fpSinCosXTest_b, xout => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt(COUNTER,1275)
-- every=1, low=0, high=8, step=1, init=1
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i = 7 THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i - 8;
ELSE
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg(REG,1276)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux(MUX,1277)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s, ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q, ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1400)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 4,
numwords_a => 9,
width_b => 23,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(22 downto 0);
--ZerosGB_uid206_rrx_uid34_fpSinCosXTest(CONSTANT,205)
ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q <= "000000000000000000000000000000";
--fracXRExt_uid207_rrx_uid34_fpSinCosXTest(BITJOIN,206)@15
fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q & ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q;
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1499)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1500)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1501)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,474)@9
X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(29 downto 0);
X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in(29 downto 0);
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1491)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 30, depth => 1 )
PORT MAP ( xin => X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1492)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 1,
numwords_a => 2,
width_b => 30,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(29 downto 0);
--leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest(CONSTANT,473)
leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,475)@13
leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1488)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1489)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1490)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,471)@9
X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(45 downto 0);
X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in(45 downto 0);
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1480)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1481)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 1,
numwords_a => 2,
width_b => 46,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(45 downto 0);
--leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,472)@13
leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1477)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1478)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1479)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,468)@9
X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(61 downto 0);
X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in(61 downto 0);
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1469)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1470)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 62,
widthad_a => 1,
numwords_a => 2,
width_b => 62,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(61 downto 0);
--leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,469)@13
leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor(LOGICAL,1510)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q <= not (ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a or ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b);
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena(REG,1511)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q = "1") THEN
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd(LOGICAL,1512)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b <= en;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a and ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg(DELAY,1502)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 78, depth => 1 )
PORT MAP ( xin => multFracBits_uid199_rrx_uid34_fpSinCosXTest_b, xout => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem(DUALMEM,1503)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 78,
widthad_a => 1,
numwords_a => 2,
width_b => 78,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia
);
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq(77 downto 0);
--leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,476)@13
leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in(5 downto 4);
--leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,477)@13
leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b;
leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,485)@13
LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(65 downto 0);
LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in(65 downto 0);
--leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest(CONSTANT,218)
leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q <= "000000000000";
--leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,486)@13
leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b & leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5(REG,560)@13
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,482)@13
LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(69 downto 0);
LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in(69 downto 0);
--leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,483)@13
leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4(REG,559)@13
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,479)@13
LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(73 downto 0);
LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in(73 downto 0);
--leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,480)@13
leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3(REG,558)@13
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2(REG,557)@13
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,487)@13
leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1(REG,556)@13
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,488)@14
leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q;
leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,496)@14
LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(74 downto 0);
LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in(74 downto 0);
--ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1112)@14
ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 75, depth => 1 )
PORT MAP ( xin => LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest(CONSTANT,229)
leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q <= "000";
--leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,497)@15
leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,493)@14
LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(75 downto 0);
LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in(75 downto 0);
--ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1110)@14
ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 76, depth => 1 )
PORT MAP ( xin => LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,494)@15
leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,490)@14
LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(76 downto 0);
LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in(76 downto 0);
--ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1108)@14
ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 77, depth => 1 )
PORT MAP ( xin => LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,491)@15
leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & GND_q;
--reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2(REG,562)@14
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,498)@13
leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a(DELAY,1184)@13
ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1(REG,561)@14
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,499)@15
leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q;
leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracCompOut_uid203_rrx_uid34_fpSinCosXTest(BITSELECT,202)@15
fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in <= leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q(76 downto 0);
fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b <= fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in(76 downto 24);
--ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b(DELAY,826)@0
ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => xBranch_uid191_rrx_uid34_fpSinCosXTest_n, xout => ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalFrac_uid208_rrx_uid34_fpSinCosXTest(MUX,207)@15
finalFrac_uid208_rrx_uid34_fpSinCosXTest_s <= ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q;
finalFrac_uid208_rrx_uid34_fpSinCosXTest: PROCESS (finalFrac_uid208_rrx_uid34_fpSinCosXTest_s, en, fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b, fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE finalFrac_uid208_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b;
WHEN "1" => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RRangeRed_uid210_rrx_uid34_fpSinCosXTest(BITJOIN,209)@15
RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q <= GND_q & ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q & finalFrac_uid208_rrx_uid34_fpSinCosXTest_q;
--expXRR_uid38_fpSinCosXTest(BITSELECT,37)@15
expXRR_uid38_fpSinCosXTest_in <= RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q(60 downto 0);
expXRR_uid38_fpSinCosXTest_b <= expXRR_uid38_fpSinCosXTest_in(60 downto 53);
--reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1(REG,565)@15
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q <= expXRR_uid38_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShiftM2_uid26_fpSinCosXTest(CONSTANT,25)
cstBiasMwShiftM2_uid26_fpSinCosXTest_q <= "01110000";
--cosXIsOneXRR_uid42_fpSinCosXTest(COMPARE,41)@16
cosXIsOneXRR_uid42_fpSinCosXTest_cin <= GND_q;
cosXIsOneXRR_uid42_fpSinCosXTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid26_fpSinCosXTest_q) & '0';
cosXIsOneXRR_uid42_fpSinCosXTest_b <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q) & cosXIsOneXRR_uid42_fpSinCosXTest_cin(0);
cosXIsOneXRR_uid42_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(cosXIsOneXRR_uid42_fpSinCosXTest_a) - SIGNED(cosXIsOneXRR_uid42_fpSinCosXTest_b));
cosXIsOneXRR_uid42_fpSinCosXTest_n(0) <= not cosXIsOneXRR_uid42_fpSinCosXTest_o(11);
--exp_uid9_fpSinCosXTest(BITSELECT,8)@0
exp_uid9_fpSinCosXTest_in <= a(30 downto 0);
exp_uid9_fpSinCosXTest_b <= exp_uid9_fpSinCosXTest_in(30 downto 23);
--sinXIsX_uid40_fpSinCosXTest(COMPARE,39)@0
sinXIsX_uid40_fpSinCosXTest_cin <= GND_q;
sinXIsX_uid40_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid24_fpSinCosXTest_q) & '0';
sinXIsX_uid40_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & exp_uid9_fpSinCosXTest_b) & sinXIsX_uid40_fpSinCosXTest_cin(0);
sinXIsX_uid40_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid40_fpSinCosXTest_a) - UNSIGNED(sinXIsX_uid40_fpSinCosXTest_b));
sinXIsX_uid40_fpSinCosXTest_n(0) <= not sinXIsX_uid40_fpSinCosXTest_o(10);
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a(DELAY,789)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--cosXONe_uid148_fpSinCosXTest(LOGICAL,147)@16
cosXONe_uid148_fpSinCosXTest_a <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q;
cosXONe_uid148_fpSinCosXTest_b <= cosXIsOneXRR_uid42_fpSinCosXTest_n;
cosXONe_uid148_fpSinCosXTest_q <= cosXONe_uid148_fpSinCosXTest_a or cosXONe_uid148_fpSinCosXTest_b;
--ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a(DELAY,791)@16
ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => cosXONe_uid148_fpSinCosXTest_q, xout => ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvCosXONe_uid149_fpSinCosXTest(LOGICAL,148)@20
InvCosXONe_uid149_fpSinCosXTest_a <= ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q;
InvCosXONe_uid149_fpSinCosXTest_q <= not InvCosXONe_uid149_fpSinCosXTest_a;
--cstZwShiftP1_uid27_fpSinCosXTest(CONSTANT,26)
cstZwShiftP1_uid27_fpSinCosXTest_q <= "00000000000000";
--fracXRR_uid39_fpSinCosXTest(BITSELECT,38)@15
fracXRR_uid39_fpSinCosXTest_in <= RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q(52 downto 0);
fracXRR_uid39_fpSinCosXTest_b <= fracXRR_uid39_fpSinCosXTest_in(52 downto 0);
--ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a(DELAY,668)@15
ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => fracXRR_uid39_fpSinCosXTest_b, xout => ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracXRR_uid43_uid43_fpSinCosXTest(BITJOIN,42)@16
oFracXRR_uid43_uid43_fpSinCosXTest_q <= VCC_q & ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q;
--extendedFracX_uid47_fpSinCosXTest(BITJOIN,46)@16
extendedFracX_uid47_fpSinCosXTest_q <= cstZwShiftP1_uid27_fpSinCosXTest_q & oFracXRR_uid43_uid43_fpSinCosXTest_q;
--X55dto0_uid220_fxpX_uid48_fpSinCosXTest(BITSELECT,219)@16
X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(55 downto 0);
X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b <= X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in(55 downto 0);
--leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest(BITJOIN,220)@16
leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q <= X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b & leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5(REG,571)@16
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q <= leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--X59dto0_uid217_fxpX_uid48_fpSinCosXTest(BITSELECT,216)@16
X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(59 downto 0);
X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b <= X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in(59 downto 0);
--leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest(BITJOIN,217)@16
leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q <= X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4(REG,570)@16
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q <= leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--X63dto0_uid214_fxpX_uid48_fpSinCosXTest(BITSELECT,213)@16
X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(63 downto 0);
X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b <= X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in(63 downto 0);
--leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest(BITJOIN,214)@16
leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q <= X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3(REG,569)@16
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q <= leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2(REG,568)@16
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q <= extendedFracX_uid47_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--fxpXShiftValExt_uid45_fpSinCosXTest(SUB,44)@16
fxpXShiftValExt_uid45_fpSinCosXTest_a <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q);
fxpXShiftValExt_uid45_fpSinCosXTest_b <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid26_fpSinCosXTest_q);
fxpXShiftValExt_uid45_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(fxpXShiftValExt_uid45_fpSinCosXTest_a) - SIGNED(fxpXShiftValExt_uid45_fpSinCosXTest_b));
fxpXShiftValExt_uid45_fpSinCosXTest_q <= fxpXShiftValExt_uid45_fpSinCosXTest_o(9 downto 0);
--fxpXShiftVal_uid46_fpSinCosXTest(BITSELECT,45)@16
fxpXShiftVal_uid46_fpSinCosXTest_in <= fxpXShiftValExt_uid45_fpSinCosXTest_q(3 downto 0);
fxpXShiftVal_uid46_fpSinCosXTest_b <= fxpXShiftVal_uid46_fpSinCosXTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest(BITSELECT,221)@16
leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in <= fxpXShiftVal_uid46_fpSinCosXTest_b;
leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b <= leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1(REG,567)@16
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q <= leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest(MUX,222)@17
leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s <= reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q;
leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest: PROCESS (leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s, en, reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q, reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q, reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q, reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest(BITSELECT,230)@17
LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(64 downto 0);
LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in(64 downto 0);
--ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b(DELAY,851)@17
ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest(BITJOIN,231)@18
leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q & leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest(BITSELECT,227)@17
LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(65 downto 0);
LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in(65 downto 0);
--ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b(DELAY,849)@17
ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 66, depth => 1 )
PORT MAP ( xin => LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest(BITJOIN,228)@18
leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest(BITSELECT,224)@17
LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(66 downto 0);
LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in(66 downto 0);
--ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b(DELAY,847)@17
ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 67, depth => 1 )
PORT MAP ( xin => LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest(BITJOIN,225)@18
leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q & GND_q;
--reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2(REG,573)@17
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest(BITSELECT,232)@16
leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in <= fxpXShiftVal_uid46_fpSinCosXTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b <= leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a(DELAY,1195)@16
ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b, xout => ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1(REG,572)@17
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q <= ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest(MUX,233)@18
leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s <= reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q;
leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest: PROCESS (leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s, en, reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q, leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q, leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q, leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q;
WHEN "10" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q;
WHEN "11" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid50_fpSinCosXTest(BITSELECT,49)@18
y_uid50_fpSinCosXTest_in <= leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q(66 downto 0);
y_uid50_fpSinCosXTest_b <= y_uid50_fpSinCosXTest_in(66 downto 1);
--ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b(DELAY,680)@18
ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 66, depth => 2 )
PORT MAP ( xin => y_uid50_fpSinCosXTest_b, xout => ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1(REG,575)@18
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q <= y_uid50_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--pad_one_uid55_fpSinCosXTest(BITJOIN,54)@18
pad_one_uid55_fpSinCosXTest_q <= VCC_q & STD_LOGIC_VECTOR((65 downto 1 => GND_q(0)) & GND_q);
--reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0(REG,574)@18
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q <= pad_one_uid55_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--oneMinusY_uid55_fpSinCosXTest(SUB,55)@19
oneMinusY_uid55_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q);
oneMinusY_uid55_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q);
oneMinusY_uid55_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid55_fpSinCosXTest_a) - UNSIGNED(oneMinusY_uid55_fpSinCosXTest_b));
oneMinusY_uid55_fpSinCosXTest_q <= oneMinusY_uid55_fpSinCosXTest_o(67 downto 0);
--reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0(REG,576)@19
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q <= oneMinusY_uid55_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid57_fpSinCosXTest(COMPARE,56)@20
cmpYToOneMinusY_uid57_fpSinCosXTest_cin <= GND_q;
cmpYToOneMinusY_uid57_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q) & '0';
cmpYToOneMinusY_uid57_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q) & cmpYToOneMinusY_uid57_fpSinCosXTest_cin(0);
cmpYToOneMinusY_uid57_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid57_fpSinCosXTest_a) - UNSIGNED(cmpYToOneMinusY_uid57_fpSinCosXTest_b));
cmpYToOneMinusY_uid57_fpSinCosXTest_c(0) <= cmpYToOneMinusY_uid57_fpSinCosXTest_o(70);
--InvCmpYToOneMinusY_uid61_fpSinCosXTest(LOGICAL,60)@20
InvCmpYToOneMinusY_uid61_fpSinCosXTest_a <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
InvCmpYToOneMinusY_uid61_fpSinCosXTest_q <= not InvCmpYToOneMinusY_uid61_fpSinCosXTest_a;
--intXParity_uid49_fpSinCosXTest(BITSELECT,48)@18
intXParity_uid49_fpSinCosXTest_in <= leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q;
intXParity_uid49_fpSinCosXTest_b <= intXParity_uid49_fpSinCosXTest_in(67 downto 67);
--ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b(DELAY,794)@18
ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => intXParity_uid49_fpSinCosXTest_b, xout => ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--yIsZero_uid51_fpSinCosXTest(LOGICAL,50)@19
yIsZero_uid51_fpSinCosXTest_a <= reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q;
yIsZero_uid51_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000000000000000000000000000000000" & GND_q);
yIsZero_uid51_fpSinCosXTest_q <= "1" when yIsZero_uid51_fpSinCosXTest_a = yIsZero_uid51_fpSinCosXTest_b else "0";
--ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a(DELAY,792)@19
ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => yIsZero_uid51_fpSinCosXTest_q, xout => ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvYIsZero_uid151_fpSinCosXTest(LOGICAL,150)@20
InvYIsZero_uid151_fpSinCosXTest_a <= ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q;
InvYIsZero_uid151_fpSinCosXTest_q <= not InvYIsZero_uid151_fpSinCosXTest_a;
--signRCond2_uid152_fpSinCosXTest(LOGICAL,151)@20
signRCond2_uid152_fpSinCosXTest_a <= InvYIsZero_uid151_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_b <= ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q;
signRCond2_uid152_fpSinCosXTest_c <= InvCmpYToOneMinusY_uid61_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_d <= InvCosXONe_uid149_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_q_i <= signRCond2_uid152_fpSinCosXTest_a and signRCond2_uid152_fpSinCosXTest_b and signRCond2_uid152_fpSinCosXTest_c and signRCond2_uid152_fpSinCosXTest_d;
signRCond2_uid152_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRCond2_uid152_fpSinCosXTest_q, xin => signRCond2_uid152_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--InvIntXParity_uid155_fpSinCosXTest(LOGICAL,154)@20
InvIntXParity_uid155_fpSinCosXTest_a <= ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q;
InvIntXParity_uid155_fpSinCosXTest_q <= not InvIntXParity_uid155_fpSinCosXTest_a;
--signRCond1_uid157_fpSinCosXTest(LOGICAL,156)@20
signRCond1_uid157_fpSinCosXTest_a <= InvYIsZero_uid151_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_b <= InvIntXParity_uid155_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_c <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
signRCond1_uid157_fpSinCosXTest_d <= InvCosXONe_uid149_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_q_i <= signRCond1_uid157_fpSinCosXTest_a and signRCond1_uid157_fpSinCosXTest_b and signRCond1_uid157_fpSinCosXTest_c and signRCond1_uid157_fpSinCosXTest_d;
signRCond1_uid157_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRCond1_uid157_fpSinCosXTest_q, xin => signRCond1_uid157_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--signRCos_uid158_fpSinCosXTest(LOGICAL,157)@21
signRCos_uid158_fpSinCosXTest_a <= signRCond1_uid157_fpSinCosXTest_q;
signRCos_uid158_fpSinCosXTest_b <= signRCond2_uid152_fpSinCosXTest_q;
signRCos_uid158_fpSinCosXTest_q <= signRCos_uid158_fpSinCosXTest_a or signRCos_uid158_fpSinCosXTest_b;
--cstAllZWF_uid7_fpSinCosXTest(CONSTANT,6)
cstAllZWF_uid7_fpSinCosXTest_q <= "00000000000000000000000";
--frac_uid13_fpSinCosXTest(BITSELECT,12)@0
frac_uid13_fpSinCosXTest_in <= a(22 downto 0);
frac_uid13_fpSinCosXTest_b <= frac_uid13_fpSinCosXTest_in(22 downto 0);
--fracXIsZero_uid14_fpSinCosXTest(LOGICAL,13)@0
fracXIsZero_uid14_fpSinCosXTest_a <= frac_uid13_fpSinCosXTest_b;
fracXIsZero_uid14_fpSinCosXTest_b <= cstAllZWF_uid7_fpSinCosXTest_q;
fracXIsZero_uid14_fpSinCosXTest_q <= "1" when fracXIsZero_uid14_fpSinCosXTest_a = fracXIsZero_uid14_fpSinCosXTest_b else "0";
--cstAllOWE_uid6_fpSinCosXTest(CONSTANT,5)
cstAllOWE_uid6_fpSinCosXTest_q <= "11111111";
--expXIsMax_uid12_fpSinCosXTest(LOGICAL,11)@0
expXIsMax_uid12_fpSinCosXTest_a <= exp_uid9_fpSinCosXTest_b;
expXIsMax_uid12_fpSinCosXTest_b <= cstAllOWE_uid6_fpSinCosXTest_q;
expXIsMax_uid12_fpSinCosXTest_q <= "1" when expXIsMax_uid12_fpSinCosXTest_a = expXIsMax_uid12_fpSinCosXTest_b else "0";
--exc_I_uid15_fpSinCosXTest(LOGICAL,14)@0
exc_I_uid15_fpSinCosXTest_a <= expXIsMax_uid12_fpSinCosXTest_q;
exc_I_uid15_fpSinCosXTest_b <= fracXIsZero_uid14_fpSinCosXTest_q;
exc_I_uid15_fpSinCosXTest_q <= exc_I_uid15_fpSinCosXTest_a and exc_I_uid15_fpSinCosXTest_b;
--ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a(DELAY,762)@0
ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 20 )
PORT MAP ( xin => exc_I_uid15_fpSinCosXTest_q, xout => ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_I_uid131_fpSinCosXTest(LOGICAL,130)@20
InvExc_I_uid131_fpSinCosXTest_a <= ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q;
InvExc_I_uid131_fpSinCosXTest_q <= not InvExc_I_uid131_fpSinCosXTest_a;
--reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2(REG,649)@20
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q <= InvExc_I_uid131_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--InvFracXIsZero_uid16_fpSinCosXTest(LOGICAL,15)@0
InvFracXIsZero_uid16_fpSinCosXTest_a <= fracXIsZero_uid14_fpSinCosXTest_q;
InvFracXIsZero_uid16_fpSinCosXTest_q <= not InvFracXIsZero_uid16_fpSinCosXTest_a;
--exc_N_uid17_fpSinCosXTest(LOGICAL,16)@0
exc_N_uid17_fpSinCosXTest_a <= expXIsMax_uid12_fpSinCosXTest_q;
exc_N_uid17_fpSinCosXTest_b <= InvFracXIsZero_uid16_fpSinCosXTest_q;
exc_N_uid17_fpSinCosXTest_q <= exc_N_uid17_fpSinCosXTest_a and exc_N_uid17_fpSinCosXTest_b;
--ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a(DELAY,763)@0
ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 20 )
PORT MAP ( xin => exc_N_uid17_fpSinCosXTest_q, xout => ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid132_fpSinCosXTest(LOGICAL,131)@20
InvExc_N_uid132_fpSinCosXTest_a <= ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q;
InvExc_N_uid132_fpSinCosXTest_q <= not InvExc_N_uid132_fpSinCosXTest_a;
--reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1(REG,648)@20
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q <= InvExc_N_uid132_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--signRCosFull_uid161_fpSinCosXTest(LOGICAL,160)@21
signRCosFull_uid161_fpSinCosXTest_a <= reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q;
signRCosFull_uid161_fpSinCosXTest_b <= reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q;
signRCosFull_uid161_fpSinCosXTest_c <= signRCos_uid158_fpSinCosXTest_q;
signRCosFull_uid161_fpSinCosXTest_q <= signRCosFull_uid161_fpSinCosXTest_a and signRCosFull_uid161_fpSinCosXTest_b and signRCosFull_uid161_fpSinCosXTest_c;
--ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c(DELAY,809)@21
ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signRCosFull_uid161_fpSinCosXTest_q, xout => ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid22_fpSinCosXTest(CONSTANT,21)
cstBias_uid22_fpSinCosXTest_q <= "01111111";
--ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a(DELAY,681)@19
ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 68, depth => 1 )
PORT MAP ( xin => oneMinusY_uid55_fpSinCosXTest_q, xout => ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--zSinOMyBottom_uid58_fpSinCosXTest(BITSELECT,57)@20
zSinOMyBottom_uid58_fpSinCosXTest_in <= ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q(64 downto 0);
zSinOMyBottom_uid58_fpSinCosXTest_b <= zSinOMyBottom_uid58_fpSinCosXTest_in(64 downto 0);
--reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3(REG,579)@20
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q <= zSinOMyBottom_uid58_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--zSinYBottom_uid59_fpSinCosXTest(BITSELECT,58)@20
zSinYBottom_uid59_fpSinCosXTest_in <= ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q(64 downto 0);
zSinYBottom_uid59_fpSinCosXTest_b <= zSinYBottom_uid59_fpSinCosXTest_in(64 downto 0);
--reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2(REG,578)@20
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q <= zSinYBottom_uid59_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1(REG,614)@20
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q <= InvCmpYToOneMinusY_uid61_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--zCos_uid64_fpSinCosXTest(MUX,63)@21
zCos_uid64_fpSinCosXTest_s <= reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q;
zCos_uid64_fpSinCosXTest: PROCESS (zCos_uid64_fpSinCosXTest_s, en, reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q, reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q)
BEGIN
CASE zCos_uid64_fpSinCosXTest_s IS
WHEN "0" => zCos_uid64_fpSinCosXTest_q <= reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q;
WHEN "1" => zCos_uid64_fpSinCosXTest_q <= reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q;
WHEN OTHERS => zCos_uid64_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--addr_uid83_fpSinCosXTest(BITSELECT,82)@21
addr_uid83_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q;
addr_uid83_fpSinCosXTest_b <= addr_uid83_fpSinCosXTest_in(64 downto 57);
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0(REG,630)@21
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q <= addr_uid83_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid404_tableGencosPiZ_lutmem(DUALMEM,532)@22
memoryC2_uid404_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC2_uid404_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC2_uid404_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q;
memoryC2_uid404_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC2_uid404_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid404_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid404_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid404_tableGencosPiZ_lutmem_iq,
address_a => memoryC2_uid404_tableGencosPiZ_lutmem_aa,
data_a => memoryC2_uid404_tableGencosPiZ_lutmem_ia
);
memoryC2_uid404_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC2_uid404_tableGencosPiZ_lutmem_q <= memoryC2_uid404_tableGencosPiZ_lutmem_iq(12 downto 0);
--reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1(REG,632)@24
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q <= memoryC2_uid404_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPcosPiZ_uid87_fpSinCosXTest(BITSELECT,86)@21
zPcosPiZ_uid87_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(56 downto 0);
zPcosPiZ_uid87_fpSinCosXTest_b <= zPcosPiZ_uid87_fpSinCosXTest_in(56 downto 42);
--yT1_uid419_polyEvalcosPiZ(BITSELECT,418)@21
yT1_uid419_polyEvalcosPiZ_in <= zPcosPiZ_uid87_fpSinCosXTest_b;
yT1_uid419_polyEvalcosPiZ_b <= yT1_uid419_polyEvalcosPiZ_in(14 downto 2);
--reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0(REG,631)@21
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q <= yT1_uid419_polyEvalcosPiZ_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg(DELAY,1513)
ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q, xout => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a(DELAY,1125)@22
ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q, xout => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid508_pT1_uid420_polyEvalcosPiZ(MULT,507)@25
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a),14)) * SIGNED(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b);
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a <= (others => '0');
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b <= (others => '0');
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a <= ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b <= reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q <= prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ(BITSELECT,508)@28
prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in <= prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q;
prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in(25 downto 12);
--highBBits_uid422_polyEvalcosPiZ(BITSELECT,421)@28
highBBits_uid422_polyEvalcosPiZ_in <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b;
highBBits_uid422_polyEvalcosPiZ_b <= highBBits_uid422_polyEvalcosPiZ_in(13 downto 1);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a(DELAY,1256)@21
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => addr_uid83_fpSinCosXTest_b, xout => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0(REG,633)@24
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid402_tableGencosPiZ_lutmem(DUALMEM,531)@25
memoryC1_uid402_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC1_uid402_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC1_uid402_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q;
memoryC1_uid402_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC1_uid402_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid402_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid402_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid402_tableGencosPiZ_lutmem_iq,
address_a => memoryC1_uid402_tableGencosPiZ_lutmem_aa,
data_a => memoryC1_uid402_tableGencosPiZ_lutmem_ia
);
memoryC1_uid402_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC1_uid402_tableGencosPiZ_lutmem_q <= memoryC1_uid402_tableGencosPiZ_lutmem_iq(20 downto 0);
--reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0(REG,634)@27
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q <= memoryC1_uid402_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid423_polyEvalcosPiZ(ADD,422)@28
sumAHighB_uid423_polyEvalcosPiZ_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q(20)) & reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q);
sumAHighB_uid423_polyEvalcosPiZ_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid422_polyEvalcosPiZ_b(12)) & highBBits_uid422_polyEvalcosPiZ_b);
sumAHighB_uid423_polyEvalcosPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid423_polyEvalcosPiZ_a) + SIGNED(sumAHighB_uid423_polyEvalcosPiZ_b));
sumAHighB_uid423_polyEvalcosPiZ_q <= sumAHighB_uid423_polyEvalcosPiZ_o(21 downto 0);
--lowRangeB_uid421_polyEvalcosPiZ(BITSELECT,420)@28
lowRangeB_uid421_polyEvalcosPiZ_in <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b(0 downto 0);
lowRangeB_uid421_polyEvalcosPiZ_b <= lowRangeB_uid421_polyEvalcosPiZ_in(0 downto 0);
--s1_uid421_uid424_polyEvalcosPiZ(BITJOIN,423)@28
s1_uid421_uid424_polyEvalcosPiZ_q <= sumAHighB_uid423_polyEvalcosPiZ_q & lowRangeB_uid421_polyEvalcosPiZ_b;
--reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1(REG,636)@28
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q <= s1_uid421_uid424_polyEvalcosPiZ_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor(LOGICAL,1524)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q <= not (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a or ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b);
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top(CONSTANT,1520)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q <= "0100";
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp(LOGICAL,1521)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q <= "1" when ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a = ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b else "0";
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg(REG,1522)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena(REG,1525)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd(LOGICAL,1526)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b <= en;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a and ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b;
--reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0(REG,635)@21
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q <= zPcosPiZ_uid87_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg(DELAY,1514)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q, xout => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt(COUNTER,1516)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i = 3 THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i,3));
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg(REG,1517)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux(MUX,1518)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s <= en;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux: PROCESS (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s, ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q, ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem(DUALMEM,1515)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq,
address_a => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa,
data_a => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia
);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0 <= areset;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq(14 downto 0);
--prodXY_uid511_pT2_uid426_polyEvalcosPiZ(MULT,510)@29
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a),16)) * SIGNED(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b);
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a <= (others => '0');
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b <= (others => '0');
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b <= reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q <= prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ(BITSELECT,511)@32
prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in <= prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q;
prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in(37 downto 14);
--highBBits_uid428_polyEvalcosPiZ(BITSELECT,427)@32
highBBits_uid428_polyEvalcosPiZ_in <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b;
highBBits_uid428_polyEvalcosPiZ_b <= highBBits_uid428_polyEvalcosPiZ_in(23 downto 2);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor(LOGICAL,1577)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q <= not (ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a or ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena(REG,1578)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q = "1") THEN
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd(LOGICAL,1579)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b <= en;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a and ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b;
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg(DELAY,1567)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addr_uid83_fpSinCosXTest_b, xout => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem(DUALMEM,1568)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq,
address_a => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa,
data_a => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia
);
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0(REG,637)@28
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid400_tableGencosPiZ_lutmem(DUALMEM,530)@29
memoryC0_uid400_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC0_uid400_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC0_uid400_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q;
memoryC0_uid400_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC0_uid400_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid400_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid400_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid400_tableGencosPiZ_lutmem_iq,
address_a => memoryC0_uid400_tableGencosPiZ_lutmem_aa,
data_a => memoryC0_uid400_tableGencosPiZ_lutmem_ia
);
memoryC0_uid400_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC0_uid400_tableGencosPiZ_lutmem_q <= memoryC0_uid400_tableGencosPiZ_lutmem_iq(29 downto 0);
--reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0(REG,638)@31
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q <= memoryC0_uid400_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid429_polyEvalcosPiZ(ADD,428)@32
sumAHighB_uid429_polyEvalcosPiZ_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q(29)) & reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q);
sumAHighB_uid429_polyEvalcosPiZ_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid428_polyEvalcosPiZ_b(21)) & highBBits_uid428_polyEvalcosPiZ_b);
sumAHighB_uid429_polyEvalcosPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid429_polyEvalcosPiZ_a) + SIGNED(sumAHighB_uid429_polyEvalcosPiZ_b));
sumAHighB_uid429_polyEvalcosPiZ_q <= sumAHighB_uid429_polyEvalcosPiZ_o(30 downto 0);
--lowRangeB_uid427_polyEvalcosPiZ(BITSELECT,426)@32
lowRangeB_uid427_polyEvalcosPiZ_in <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b(1 downto 0);
lowRangeB_uid427_polyEvalcosPiZ_b <= lowRangeB_uid427_polyEvalcosPiZ_in(1 downto 0);
--s2_uid427_uid430_polyEvalcosPiZ(BITJOIN,429)@32
s2_uid427_uid430_polyEvalcosPiZ_q <= sumAHighB_uid429_polyEvalcosPiZ_q & lowRangeB_uid427_polyEvalcosPiZ_b;
--polyEvalSigcosPiZ_uid89_fpSinCosXTest(BITSELECT,88)@32
polyEvalSigcosPiZ_uid89_fpSinCosXTest_in <= s2_uid427_uid430_polyEvalcosPiZ_q(30 downto 0);
polyEvalSigcosPiZ_uid89_fpSinCosXTest_b <= polyEvalSigcosPiZ_uid89_fpSinCosXTest_in(30 downto 5);
--reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1(REG,640)@32
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q <= polyEvalSigcosPiZ_uid89_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor(LOGICAL,1590)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q <= not (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a or ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b);
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top(CONSTANT,1586)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q <= "010";
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp(LOGICAL,1587)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q <= "1" when ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a = ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b else "0";
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg(REG,1588)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena(REG,1591)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd(LOGICAL,1592)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b <= en;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a and ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b;
--LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest(BITSELECT,388)@27
LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q(63 downto 0);
LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in(63 downto 0);
--leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest(BITJOIN,389)@27
leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b & GND_q;
--cstZmwFRRPwSM1_uid52_fpSinCosXTest(CONSTANT,51)
cstZmwFRRPwSM1_uid52_fpSinCosXTest_q <= "00000000000000000000000000000000000000000000000000000000000000000";
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor(LOGICAL,1455)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q <= not (ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a or ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b);
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena(REG,1456)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q = "1") THEN
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd(LOGICAL,1457)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b <= en;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a and ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b;
--X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest(BITSELECT,359)@21
X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(32 downto 0);
X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b <= X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in(32 downto 0);
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg(DELAY,1447)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem(DUALMEM,1448)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 33,
widthad_a => 1,
numwords_a => 2,
width_b => 33,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia
);
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq(32 downto 0);
--leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest(BITJOIN,360)@25
leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor(LOGICAL,1466)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q <= not (ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a or ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b);
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena(REG,1467)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q = "1") THEN
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd(LOGICAL,1468)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b <= en;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a and ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg(DELAY,1458)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => zCos_uid64_fpSinCosXTest_q, xout => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem(DUALMEM,1459)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 65,
widthad_a => 1,
numwords_a => 2,
width_b => 65,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia
);
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq(64 downto 0);
--zs_uid236_lzcZSin_uid66_fpSinCosXTest(CONSTANT,235)
zs_uid236_lzcZSin_uid66_fpSinCosXTest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--rVStage_uid316_lzcZCos_uid69_fpSinCosXTest(BITSELECT,315)@21
rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q;
rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in(64 downto 1);
--vCount_uid317_lzcZCos_uid69_fpSinCosXTest(LOGICAL,316)@21
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid236_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g(DELAY,985)@22
ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid319_lzcZCos_uid69_fpSinCosXTest(BITSELECT,318)@21
vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(0 downto 0);
vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in(0 downto 0);
--ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b(DELAY,943)@21
ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid239_lzcZSin_uid66_fpSinCosXTest(CONSTANT,238)
mO_uid239_lzcZSin_uid66_fpSinCosXTest_q <= "111111111111111111111111111111111111111111111111111111111111111";
--cStage_uid320_lzcZCos_uid69_fpSinCosXTest(BITJOIN,319)@22
cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q <= ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q & mO_uid239_lzcZSin_uid66_fpSinCosXTest_q;
--ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c(DELAY,945)@21
ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid322_lzcZCos_uid69_fpSinCosXTest(MUX,321)@22
vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid322_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s, en, ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q, cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid324_lzcZCos_uid69_fpSinCosXTest(BITSELECT,323)@22
rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in(63 downto 32);
--vCount_uid325_lzcZCos_uid69_fpSinCosXTest(LOGICAL,324)@22
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f(DELAY,984)@23
ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid326_lzcZCos_uid69_fpSinCosXTest(BITSELECT,325)@22
vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q(31 downto 0);
vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in(31 downto 0);
--ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d(DELAY,952)@22
ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c(DELAY,951)@22
ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid328_lzcZCos_uid69_fpSinCosXTest(MUX,327)@23
vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid328_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s, en, ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q, ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q)
BEGIN
CASE vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q;
WHEN OTHERS => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid330_lzcZCos_uid69_fpSinCosXTest(BITSELECT,329)@23
rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in(31 downto 16);
--vCount_uid331_lzcZCos_uid69_fpSinCosXTest(LOGICAL,330)@23
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b else "0";
--reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4(REG,622)@23
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q <= vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e(DELAY,983)@24
ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid332_lzcZCos_uid69_fpSinCosXTest(BITSELECT,331)@23
vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q(15 downto 0);
vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in(15 downto 0);
--vStagei_uid334_lzcZCos_uid69_fpSinCosXTest(MUX,333)@23
vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid334_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s, en, rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b, vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b;
WHEN "1" => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid336_lzcZCos_uid69_fpSinCosXTest(BITSELECT,335)@23
rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in(15 downto 8);
--reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1(REG,617)@23
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q <= rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid337_lzcZCos_uid69_fpSinCosXTest(LOGICAL,336)@24
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a <= reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q;
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b else "0";
--ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d(DELAY,982)@24
ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid338_lzcZCos_uid69_fpSinCosXTest(BITSELECT,337)@23
vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q(7 downto 0);
vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3(REG,619)@23
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q <= vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid340_lzcZCos_uid69_fpSinCosXTest(MUX,339)@24
vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid340_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s, en, reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q, reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid342_lzcZCos_uid69_fpSinCosXTest(BITSELECT,341)@24
rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in(7 downto 4);
--vCount_uid343_lzcZCos_uid69_fpSinCosXTest(LOGICAL,342)@24
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid344_lzcZCos_uid69_fpSinCosXTest(BITSELECT,343)@24
vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q(3 downto 0);
vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in(3 downto 0);
--reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3(REG,621)@24
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q <= vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2(REG,620)@24
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid346_lzcZCos_uid69_fpSinCosXTest(MUX,345)@25
vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid346_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s, en, reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q, reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid348_lzcZCos_uid69_fpSinCosXTest(BITSELECT,347)@25
rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in(3 downto 2);
--vCount_uid349_lzcZCos_uid69_fpSinCosXTest(LOGICAL,348)@25
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b else "0";
--vStage_uid350_lzcZCos_uid69_fpSinCosXTest(BITSELECT,349)@25
vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q(1 downto 0);
vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in(1 downto 0);
--vStagei_uid352_lzcZCos_uid69_fpSinCosXTest(MUX,351)@25
vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid352_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s, en, rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b, vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b;
WHEN "1" => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid354_lzcZCos_uid69_fpSinCosXTest(BITSELECT,353)@25
rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in(1 downto 1);
--vCount_uid355_lzcZCos_uid69_fpSinCosXTest(LOGICAL,354)@25
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b <= GND_q;
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b else "0";
--r_uid356_lzcZCos_uid69_fpSinCosXTest(BITJOIN,355)@25
r_uid356_lzcZCos_uid69_fpSinCosXTest_q <= ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q & ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q & ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q & ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q & vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q & vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q & vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q;
--leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest(BITSELECT,363)@25
leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q;
leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in(6 downto 5);
--leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest(MUX,364)@25
leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s <= leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b;
leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s, en, ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest(BITSELECT,372)@25
LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(40 downto 0);
LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in(40 downto 0);
--leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest(CONSTANT,292)
leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q <= "000000000000000000000000";
--leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest(BITJOIN,373)@25
leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b & leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5(REG,627)@25
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest(BITSELECT,369)@25
LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(48 downto 0);
LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in(48 downto 0);
--leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest(BITJOIN,370)@25
leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4(REG,626)@25
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest(BITSELECT,366)@25
LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(56 downto 0);
LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in(56 downto 0);
--leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest(BITJOIN,367)@25
leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3(REG,625)@25
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2(REG,624)@25
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest(BITSELECT,374)@25
leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1(REG,623)@25
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q <= leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest(MUX,375)@26
leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s <= reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q;
leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s, en, reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest(BITSELECT,383)@26
LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(58 downto 0);
LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1009)@26
ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest(CONSTANT,303)
leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q <= "000000";
--leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest(BITJOIN,384)@27
leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q;
--LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest(BITSELECT,380)@26
LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(60 downto 0);
LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1007)@26
ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest(BITJOIN,381)@27
leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest(BITSELECT,377)@26
LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(62 downto 0);
LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in(62 downto 0);
--ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1005)@26
ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest(BITJOIN,378)@27
leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2(REG,629)@26
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest(BITSELECT,385)@25
leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1(REG,628)@25
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q <= leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1011)@26
ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest(MUX,386)@27
leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s <= ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q;
leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s, en, reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest(BITSELECT,390)@25
leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1019)@25
ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest(MUX,391)@27
leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s <= ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q;
leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s, en, leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "0" => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "1" => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--pCos_uid77_fpSinCosXTest(BITSELECT,76)@27
pCos_uid77_fpSinCosXTest_in <= leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q;
pCos_uid77_fpSinCosXTest_b <= pCos_uid77_fpSinCosXTest_in(64 downto 39);
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg(DELAY,1580)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => pCos_uid77_fpSinCosXTest_b, xout => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt(COUNTER,1582)
-- every=1, low=0, high=2, step=1, init=1
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i = 1 THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i - 2;
ELSE
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i,2));
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg(REG,1583)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux(MUX,1584)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s <= en;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux: PROCESS (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s, ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q, ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q)
BEGIN
CASE ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s IS
WHEN "0" => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q;
WHEN "1" => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem(DUALMEM,1581)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 2,
numwords_a => 3,
width_b => 26,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq,
address_a => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa,
data_a => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia
);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0 <= areset;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq(25 downto 0);
--reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0(REG,639)@32
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--mulCos_uid105_fpSinCosXTest(MULT,104)@33
mulCos_uid105_fpSinCosXTest_pr <= UNSIGNED(mulCos_uid105_fpSinCosXTest_a) * UNSIGNED(mulCos_uid105_fpSinCosXTest_b);
mulCos_uid105_fpSinCosXTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulCos_uid105_fpSinCosXTest_a <= (others => '0');
mulCos_uid105_fpSinCosXTest_b <= (others => '0');
mulCos_uid105_fpSinCosXTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulCos_uid105_fpSinCosXTest_a <= reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q;
mulCos_uid105_fpSinCosXTest_b <= reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q;
mulCos_uid105_fpSinCosXTest_s1 <= STD_LOGIC_VECTOR(mulCos_uid105_fpSinCosXTest_pr);
END IF;
END IF;
END PROCESS;
mulCos_uid105_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulCos_uid105_fpSinCosXTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulCos_uid105_fpSinCosXTest_q <= mulCos_uid105_fpSinCosXTest_s1;
END IF;
END IF;
END PROCESS;
--normBitCos_uid106_fpSinCosXTest(BITSELECT,105)@36
normBitCos_uid106_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q;
normBitCos_uid106_fpSinCosXTest_b <= normBitCos_uid106_fpSinCosXTest_in(51 downto 51);
--cosRndOp_uid112_uid113_fpSinCosXTest(BITJOIN,112)@36
cosRndOp_uid112_uid113_fpSinCosXTest_q <= normBitCos_uid106_fpSinCosXTest_b & cstAllZWF_uid7_fpSinCosXTest_q & VCC_q;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor(LOGICAL,1296)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q <= not (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a or ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b);
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top(CONSTANT,1292)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q <= "0110";
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp(LOGICAL,1293)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q <= "1" when ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a = ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b else "0";
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg(REG,1294)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena(REG,1297)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd(LOGICAL,1298)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b <= en;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a and ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b;
--reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1(REG,641)@25
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg(DELAY,1286)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q, xout => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt(COUNTER,1288)
-- every=1, low=0, high=6, step=1, init=1
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i = 5 THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i - 6;
ELSE
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i,3));
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg(REG,1289)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux(MUX,1290)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s <= en;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux: PROCESS (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s, ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q, ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem(DUALMEM,1287)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 7,
width_b => 7,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia
);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq(6 downto 0);
--expHardCase_uid78_fpSinCosXTest(SUB,77)@35
expHardCase_uid78_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expHardCase_uid78_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q);
expHardCase_uid78_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid78_fpSinCosXTest_a) - UNSIGNED(expHardCase_uid78_fpSinCosXTest_b));
expHardCase_uid78_fpSinCosXTest_q <= expHardCase_uid78_fpSinCosXTest_o(8 downto 0);
--expPCos_uid79_fpSinCosXTest(BITSELECT,78)@35
expPCos_uid79_fpSinCosXTest_in <= expHardCase_uid78_fpSinCosXTest_q(7 downto 0);
expPCos_uid79_fpSinCosXTest_b <= expPCos_uid79_fpSinCosXTest_in(7 downto 0);
--reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1(REG,642)@35
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q <= expPCos_uid79_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--fracRCosPreRndHigh_uid108_fpSinCosXTest(BITSELECT,107)@36
fracRCosPreRndHigh_uid108_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q(50 downto 0);
fracRCosPreRndHigh_uid108_fpSinCosXTest_b <= fracRCosPreRndHigh_uid108_fpSinCosXTest_in(50 downto 27);
--fracRCosPreRndLow_uid109_fpSinCosXTest(BITSELECT,108)@36
fracRCosPreRndLow_uid109_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q(49 downto 0);
fracRCosPreRndLow_uid109_fpSinCosXTest_b <= fracRCosPreRndLow_uid109_fpSinCosXTest_in(49 downto 26);
--fracRCosPreRnd_uid110_fpSinCosXTest(MUX,109)@36
fracRCosPreRnd_uid110_fpSinCosXTest_s <= normBitCos_uid106_fpSinCosXTest_b;
fracRCosPreRnd_uid110_fpSinCosXTest: PROCESS (fracRCosPreRnd_uid110_fpSinCosXTest_s, en, fracRCosPreRndLow_uid109_fpSinCosXTest_b, fracRCosPreRndHigh_uid108_fpSinCosXTest_b)
BEGIN
CASE fracRCosPreRnd_uid110_fpSinCosXTest_s IS
WHEN "0" => fracRCosPreRnd_uid110_fpSinCosXTest_q <= fracRCosPreRndLow_uid109_fpSinCosXTest_b;
WHEN "1" => fracRCosPreRnd_uid110_fpSinCosXTest_q <= fracRCosPreRndHigh_uid108_fpSinCosXTest_b;
WHEN OTHERS => fracRCosPreRnd_uid110_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracRCosPreRnd_uid111_uid111_fpSinCosXTest(BITJOIN,110)@36
expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q <= reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q & fracRCosPreRnd_uid110_fpSinCosXTest_q;
--expFracRCos_uid114_fpSinCosXTest(ADD,113)@36
expFracRCos_uid114_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q);
expFracRCos_uid114_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00000000" & cosRndOp_uid112_uid113_fpSinCosXTest_q);
expFracRCos_uid114_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRCos_uid114_fpSinCosXTest_a) + UNSIGNED(expFracRCos_uid114_fpSinCosXTest_b));
expFracRCos_uid114_fpSinCosXTest_q <= expFracRCos_uid114_fpSinCosXTest_o(32 downto 0);
--expRCompSin_uid116_fpSinCosXTest(BITSELECT,115)@36
expRCompSin_uid116_fpSinCosXTest_in <= expFracRCos_uid114_fpSinCosXTest_q(31 downto 0);
expRCompSin_uid116_fpSinCosXTest_b <= expRCompSin_uid116_fpSinCosXTest_in(31 downto 24);
--reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2(REG,646)@36
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q <= expRCompSin_uid116_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor(LOGICAL,1385)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q <= not (ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a or ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top(CONSTANT,1305)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q <= "01101";
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp(LOGICAL,1306)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q <= "1" when ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a = ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b else "0";
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg(REG,1307)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena(REG,1386)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q = "1") THEN
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd(LOGICAL,1387)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b <= en;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a and ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b;
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a(DELAY,745)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c(DELAY,783)@16
ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => cosXIsOneXRR_uid42_fpSinCosXTest_n, xout => ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--InvCosXIsOneXRR_uid136_fpSinCosXTest(LOGICAL,135)@16
InvCosXIsOneXRR_uid136_fpSinCosXTest_a <= cosXIsOneXRR_uid42_fpSinCosXTest_n;
InvCosXIsOneXRR_uid136_fpSinCosXTest_q <= not InvCosXIsOneXRR_uid136_fpSinCosXTest_a;
--ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c(DELAY,773)@16
ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => InvCosXIsOneXRR_uid136_fpSinCosXTest_q, xout => ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a(DELAY,755)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsX_uid127_fpSinCosXTest(LOGICAL,126)@18
InvSinXIsX_uid127_fpSinCosXTest_a <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q;
InvSinXIsX_uid127_fpSinCosXTest_q <= not InvSinXIsX_uid127_fpSinCosXTest_a;
--ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b(DELAY,772)@18
ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => InvSinXIsX_uid127_fpSinCosXTest_q, xout => ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--half_uid53_fpSinCosXTest(BITJOIN,52)@19
half_uid53_fpSinCosXTest_q <= VCC_q & cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
--yIsHalf_uid54_fpSinCosXTest(LOGICAL,53)@19
yIsHalf_uid54_fpSinCosXTest_a <= reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q;
yIsHalf_uid54_fpSinCosXTest_b <= half_uid53_fpSinCosXTest_q;
yIsHalf_uid54_fpSinCosXTest_q <= "1" when yIsHalf_uid54_fpSinCosXTest_a = yIsHalf_uid54_fpSinCosXTest_b else "0";
--yHalfCosXNotOne_uid138_fpSinCosXTest(LOGICAL,137)@19
yHalfCosXNotOne_uid138_fpSinCosXTest_a <= yIsHalf_uid54_fpSinCosXTest_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_b <= ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_c <= ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_q <= yHalfCosXNotOne_uid138_fpSinCosXTest_a and yHalfCosXNotOne_uid138_fpSinCosXTest_b and yHalfCosXNotOne_uid138_fpSinCosXTest_c;
--ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b(DELAY,744)@0
ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => exc_I_uid15_fpSinCosXTest_q, xout => ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a(DELAY,743)@0
ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => exc_N_uid17_fpSinCosXTest_q, xout => ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRNaN_uid117_fpSinCosXTest(LOGICAL,116)@19
excRNaN_uid117_fpSinCosXTest_a <= ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q;
excRNaN_uid117_fpSinCosXTest_b <= ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q;
excRNaN_uid117_fpSinCosXTest_q <= excRNaN_uid117_fpSinCosXTest_a or excRNaN_uid117_fpSinCosXTest_b;
--join_uid143_fpSinCosXTest(BITJOIN,142)@19
join_uid143_fpSinCosXTest_q <= ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q & yHalfCosXNotOne_uid138_fpSinCosXTest_q & excRNaN_uid117_fpSinCosXTest_q;
--expSelBitsCos_uid144_fpSinCosXTest(BITJOIN,143)@19
expSelBitsCos_uid144_fpSinCosXTest_q <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q & join_uid143_fpSinCosXTest_q;
--reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0(REG,645)@19
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q <= expSelBitsCos_uid144_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--expSelectorCos_uid145_fpSinCosXTest(LOOKUP,144)@20
expSelectorCos_uid145_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSelectorCos_uid145_fpSinCosXTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q) IS
WHEN "0000" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "0001" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "0010" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "0011" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "0100" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "0101" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "0110" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "0111" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "1000" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "1001" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "1010" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "1011" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "1100" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "1101" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "1110" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "1111" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN OTHERS =>
expSelectorCos_uid145_fpSinCosXTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg(DELAY,1375)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => expSelectorCos_uid145_fpSinCosXTest_q, xout => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt(COUNTER,1301)
-- every=1, low=0, high=13, step=1, init=1
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i = 12 THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i - 13;
ELSE
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg(REG,1302)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux(MUX,1303)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s, ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q, ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem(DUALMEM,1376)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia
);
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq(1 downto 0);
--expRPostExcCos_uid147_fpSinCosXTest(MUX,146)@37
expRPostExcCos_uid147_fpSinCosXTest_s <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q;
expRPostExcCos_uid147_fpSinCosXTest: PROCESS (expRPostExcCos_uid147_fpSinCosXTest_s, en, reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q, cstBias_uid22_fpSinCosXTest_q, cstAllZWE_uid8_fpSinCosXTest_q, cstAllOWE_uid6_fpSinCosXTest_q)
BEGIN
CASE expRPostExcCos_uid147_fpSinCosXTest_s IS
WHEN "00" => expRPostExcCos_uid147_fpSinCosXTest_q <= reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q;
WHEN "01" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstBias_uid22_fpSinCosXTest_q;
WHEN "10" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstAllZWE_uid8_fpSinCosXTest_q;
WHEN "11" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstAllOWE_uid6_fpSinCosXTest_q;
WHEN OTHERS => expRPostExcCos_uid147_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstNaNwF_uid32_fpSinCosXTest(CONSTANT,31)
cstNaNwF_uid32_fpSinCosXTest_q <= "00000000000000000000001";
--fracRCompCos_uid115_fpSinCosXTest(BITSELECT,114)@36
fracRCompCos_uid115_fpSinCosXTest_in <= expFracRCos_uid114_fpSinCosXTest_q(23 downto 0);
fracRCompCos_uid115_fpSinCosXTest_b <= fracRCompCos_uid115_fpSinCosXTest_in(23 downto 1);
--reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2(REG,644)@36
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q <= fracRCompCos_uid115_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor(LOGICAL,1372)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q <= not (ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a or ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b);
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena(REG,1373)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q = "1") THEN
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd(LOGICAL,1374)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b <= en;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a and ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b;
--reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1(REG,613)@19
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q <= excRNaN_uid117_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3(REG,612)@19
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q <= ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q;
END IF;
END IF;
END PROCESS;
--reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2(REG,611)@19
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q;
END IF;
END IF;
END PROCESS;
--reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1(REG,610)@19
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q <= yHalfCosXNotOne_uid138_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--rZOrOne_uid140_fpSinCosXTest(LOGICAL,139)@20
rZOrOne_uid140_fpSinCosXTest_a <= reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q;
rZOrOne_uid140_fpSinCosXTest_b <= reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q;
rZOrOne_uid140_fpSinCosXTest_c <= reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q;
rZOrOne_uid140_fpSinCosXTest_q <= rZOrOne_uid140_fpSinCosXTest_a or rZOrOne_uid140_fpSinCosXTest_b or rZOrOne_uid140_fpSinCosXTest_c;
--join_uid141_fpSinCosXTest(BITJOIN,140)@20
join_uid141_fpSinCosXTest_q <= reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q & rZOrOne_uid140_fpSinCosXTest_q;
--reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1(REG,643)@20
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q <= join_uid141_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg(DELAY,1362)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q, xout => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem(DUALMEM,1363)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia
);
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq(1 downto 0);
--fracRPostExcCos_uid142_fpSinCosXTest(MUX,141)@37
fracRPostExcCos_uid142_fpSinCosXTest_s <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q;
fracRPostExcCos_uid142_fpSinCosXTest: PROCESS (fracRPostExcCos_uid142_fpSinCosXTest_s, en, reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q, cstAllZWF_uid7_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q)
BEGIN
CASE fracRPostExcCos_uid142_fpSinCosXTest_s IS
WHEN "00" => fracRPostExcCos_uid142_fpSinCosXTest_q <= reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q;
WHEN "01" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstAllZWF_uid7_fpSinCosXTest_q;
WHEN "10" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN "11" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN OTHERS => fracRPostExcCos_uid142_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpCos_uid162_fpSinCosXTest(BITJOIN,161)@37
fpCos_uid162_fpSinCosXTest_q <= ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q & expRPostExcCos_uid147_fpSinCosXTest_q & fracRPostExcCos_uid142_fpSinCosXTest_q;
--cstBiasMwShiftM2_uid25_fpSinCosXTest(CONSTANT,24)
cstBiasMwShiftM2_uid25_fpSinCosXTest_q <= "01110001";
--sinXIsXRR_uid41_fpSinCosXTest(COMPARE,40)@16
sinXIsXRR_uid41_fpSinCosXTest_cin <= GND_q;
sinXIsXRR_uid41_fpSinCosXTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid25_fpSinCosXTest_q) & '0';
sinXIsXRR_uid41_fpSinCosXTest_b <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q) & sinXIsXRR_uid41_fpSinCosXTest_cin(0);
sinXIsXRR_uid41_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(sinXIsXRR_uid41_fpSinCosXTest_a) - SIGNED(sinXIsXRR_uid41_fpSinCosXTest_b));
sinXIsXRR_uid41_fpSinCosXTest_n(0) <= not sinXIsXRR_uid41_fpSinCosXTest_o(11);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a(DELAY,756)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsXRR_uid128_fpSinCosXTest(LOGICAL,127)@18
InvSinXIsXRR_uid128_fpSinCosXTest_a <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q;
InvSinXIsXRR_uid128_fpSinCosXTest_q <= not InvSinXIsXRR_uid128_fpSinCosXTest_a;
--signComp_uid129_fpSinCosXTest(LOGICAL,128)@18
signComp_uid129_fpSinCosXTest_a <= InvSinXIsXRR_uid128_fpSinCosXTest_q;
signComp_uid129_fpSinCosXTest_b <= InvSinXIsX_uid127_fpSinCosXTest_q;
signComp_uid129_fpSinCosXTest_c <= intXParity_uid49_fpSinCosXTest_b;
signComp_uid129_fpSinCosXTest_q <= signComp_uid129_fpSinCosXTest_a and signComp_uid129_fpSinCosXTest_b and signComp_uid129_fpSinCosXTest_c;
--signX_uid37_fpSinCosXTest(BITSELECT,36)@0
signX_uid37_fpSinCosXTest_in <= a;
signX_uid37_fpSinCosXTest_b <= signX_uid37_fpSinCosXTest_in(31 downto 31);
--ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a(DELAY,760)@0
ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => signX_uid37_fpSinCosXTest_b, xout => ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid130_fpSinCosXTest(LOGICAL,129)@18
signR_uid130_fpSinCosXTest_a <= ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q;
signR_uid130_fpSinCosXTest_b <= signComp_uid129_fpSinCosXTest_q;
signR_uid130_fpSinCosXTest_q <= signR_uid130_fpSinCosXTest_a xor signR_uid130_fpSinCosXTest_b;
--ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c(DELAY,766)@18
ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => signR_uid130_fpSinCosXTest_q, xout => ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--signRSinFull_uid133_fpSinCosXTest(LOGICAL,132)@20
signRSinFull_uid133_fpSinCosXTest_a <= InvExc_N_uid132_fpSinCosXTest_q;
signRSinFull_uid133_fpSinCosXTest_b <= InvExc_I_uid131_fpSinCosXTest_q;
signRSinFull_uid133_fpSinCosXTest_c <= ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q;
signRSinFull_uid133_fpSinCosXTest_q_i <= signRSinFull_uid133_fpSinCosXTest_a and signRSinFull_uid133_fpSinCosXTest_b and signRSinFull_uid133_fpSinCosXTest_c;
signRSinFull_uid133_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRSinFull_uid133_fpSinCosXTest_q, xin => signRSinFull_uid133_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c(DELAY,769)@21
ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signRSinFull_uid133_fpSinCosXTest_q, xout => ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor(LOGICAL,1359)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q <= not (ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a or ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b);
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top(CONSTANT,1342)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q <= "0100010";
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp(LOGICAL,1343)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q <= "1" when ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a = ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b else "0";
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg(REG,1344)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena(REG,1360)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q = "1") THEN
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd(LOGICAL,1361)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b <= en;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a and ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg(DELAY,1349)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => exp_uid9_fpSinCosXTest_b, xout => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt(COUNTER,1338)
-- every=1, low=0, high=34, step=1, init=1
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i = 33 THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i - 34;
ELSE
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i,6));
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg(REG,1339)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux(MUX,1340)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem(DUALMEM,1350)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 6,
numwords_a => 35,
width_b => 8,
widthad_b => 6,
numwords_b => 35,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia
);
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a(DELAY,1228)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1(REG,605)@35
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor(LOGICAL,1309)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q <= not (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a or ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena(REG,1310)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd(LOGICAL,1311)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b <= en;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a and ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b;
--oFracXRRSmallXRR_uid90_fpSinCosXTest(BITSELECT,89)@16
oFracXRRSmallXRR_uid90_fpSinCosXTest_in <= oFracXRR_uid43_uid43_fpSinCosXTest_q;
oFracXRRSmallXRR_uid90_fpSinCosXTest_b <= oFracXRRSmallXRR_uid90_fpSinCosXTest_in(53 downto 28);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg(DELAY,1299)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => oFracXRRSmallXRR_uid90_fpSinCosXTest_b, xout => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem(DUALMEM,1300)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 4,
numwords_a => 14,
width_b => 26,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia
);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq(25 downto 0);
--reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1(REG,577)@20
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
END IF;
END IF;
END PROCESS;
--zSin_uid60_fpSinCosXTest(MUX,59)@21
zSin_uid60_fpSinCosXTest_s <= reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q;
zSin_uid60_fpSinCosXTest: PROCESS (zSin_uid60_fpSinCosXTest_s, en, reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q, reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q)
BEGIN
CASE zSin_uid60_fpSinCosXTest_s IS
WHEN "0" => zSin_uid60_fpSinCosXTest_q <= reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q;
WHEN "1" => zSin_uid60_fpSinCosXTest_q <= reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q;
WHEN OTHERS => zSin_uid60_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--addr_uid81_fpSinCosXTest(BITSELECT,80)@21
addr_uid81_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q;
addr_uid81_fpSinCosXTest_b <= addr_uid81_fpSinCosXTest_in(64 downto 57);
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0(REG,595)@21
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q <= addr_uid81_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid398_tableGensinPiZ_lutmem(DUALMEM,529)@22
memoryC2_uid398_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC2_uid398_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC2_uid398_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q;
memoryC2_uid398_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC2_uid398_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid398_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid398_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid398_tableGensinPiZ_lutmem_iq,
address_a => memoryC2_uid398_tableGensinPiZ_lutmem_aa,
data_a => memoryC2_uid398_tableGensinPiZ_lutmem_ia
);
memoryC2_uid398_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC2_uid398_tableGensinPiZ_lutmem_q <= memoryC2_uid398_tableGensinPiZ_lutmem_iq(12 downto 0);
--reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1(REG,597)@24
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q <= memoryC2_uid398_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPsinPiZ_uid84_fpSinCosXTest(BITSELECT,83)@21
zPsinPiZ_uid84_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(56 downto 0);
zPsinPiZ_uid84_fpSinCosXTest_b <= zPsinPiZ_uid84_fpSinCosXTest_in(56 downto 42);
--yT1_uid406_polyEvalsinPiZ(BITSELECT,405)@21
yT1_uid406_polyEvalsinPiZ_in <= zPsinPiZ_uid84_fpSinCosXTest_b;
yT1_uid406_polyEvalsinPiZ_b <= yT1_uid406_polyEvalsinPiZ_in(14 downto 2);
--ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg(DELAY,1540)
ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => yT1_uid406_polyEvalsinPiZ_b, xout => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a(DELAY,1219)@21
ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q, xout => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0(REG,596)@24
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q <= ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid502_pT1_uid407_polyEvalsinPiZ(MULT,501)@25
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a),14)) * SIGNED(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b);
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a <= (others => '0');
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b <= (others => '0');
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a <= reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b <= reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q <= prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ(BITSELECT,502)@28
prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in <= prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q;
prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in(25 downto 12);
--highBBits_uid409_polyEvalsinPiZ(BITSELECT,408)@28
highBBits_uid409_polyEvalsinPiZ_in <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b;
highBBits_uid409_polyEvalsinPiZ_b <= highBBits_uid409_polyEvalsinPiZ_in(13 downto 1);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a(DELAY,1221)@21
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => addr_uid81_fpSinCosXTest_b, xout => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0(REG,598)@24
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid396_tableGensinPiZ_lutmem(DUALMEM,528)@25
memoryC1_uid396_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC1_uid396_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC1_uid396_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q;
memoryC1_uid396_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC1_uid396_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid396_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid396_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid396_tableGensinPiZ_lutmem_iq,
address_a => memoryC1_uid396_tableGensinPiZ_lutmem_aa,
data_a => memoryC1_uid396_tableGensinPiZ_lutmem_ia
);
memoryC1_uid396_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC1_uid396_tableGensinPiZ_lutmem_q <= memoryC1_uid396_tableGensinPiZ_lutmem_iq(20 downto 0);
--reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0(REG,599)@27
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q <= memoryC1_uid396_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid410_polyEvalsinPiZ(ADD,409)@28
sumAHighB_uid410_polyEvalsinPiZ_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q(20)) & reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q);
sumAHighB_uid410_polyEvalsinPiZ_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid409_polyEvalsinPiZ_b(12)) & highBBits_uid409_polyEvalsinPiZ_b);
sumAHighB_uid410_polyEvalsinPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid410_polyEvalsinPiZ_a) + SIGNED(sumAHighB_uid410_polyEvalsinPiZ_b));
sumAHighB_uid410_polyEvalsinPiZ_q <= sumAHighB_uid410_polyEvalsinPiZ_o(21 downto 0);
--lowRangeB_uid408_polyEvalsinPiZ(BITSELECT,407)@28
lowRangeB_uid408_polyEvalsinPiZ_in <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b(0 downto 0);
lowRangeB_uid408_polyEvalsinPiZ_b <= lowRangeB_uid408_polyEvalsinPiZ_in(0 downto 0);
--s1_uid408_uid411_polyEvalsinPiZ(BITJOIN,410)@28
s1_uid408_uid411_polyEvalsinPiZ_q <= sumAHighB_uid410_polyEvalsinPiZ_q & lowRangeB_uid408_polyEvalsinPiZ_b;
--reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1(REG,601)@28
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q <= s1_uid408_uid411_polyEvalsinPiZ_q;
END IF;
END IF;
END PROCESS;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor(LOGICAL,1551)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q <= not (ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a or ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b);
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena(REG,1552)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q = "1") THEN
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd(LOGICAL,1553)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b <= en;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a and ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg(DELAY,1541)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => zPsinPiZ_uid84_fpSinCosXTest_b, xout => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem(DUALMEM,1542)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq,
address_a => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa,
data_a => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia
);
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0 <= areset;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq(14 downto 0);
--reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0(REG,600)@28
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid505_pT2_uid413_polyEvalsinPiZ(MULT,504)@29
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a),16)) * SIGNED(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b);
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a <= (others => '0');
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b <= (others => '0');
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a <= reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b <= reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q <= prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ(BITSELECT,505)@32
prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in <= prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q;
prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in(37 downto 14);
--highBBits_uid415_polyEvalsinPiZ(BITSELECT,414)@32
highBBits_uid415_polyEvalsinPiZ_in <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b;
highBBits_uid415_polyEvalsinPiZ_b <= highBBits_uid415_polyEvalsinPiZ_in(23 downto 2);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor(LOGICAL,1564)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q <= not (ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a or ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena(REG,1565)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q = "1") THEN
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd(LOGICAL,1566)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b <= en;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a and ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b;
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg(DELAY,1554)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addr_uid81_fpSinCosXTest_b, xout => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem(DUALMEM,1555)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq,
address_a => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa,
data_a => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia
);
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0(REG,602)@28
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid394_tableGensinPiZ_lutmem(DUALMEM,527)@29
memoryC0_uid394_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC0_uid394_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC0_uid394_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q;
memoryC0_uid394_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC0_uid394_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid394_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid394_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid394_tableGensinPiZ_lutmem_iq,
address_a => memoryC0_uid394_tableGensinPiZ_lutmem_aa,
data_a => memoryC0_uid394_tableGensinPiZ_lutmem_ia
);
memoryC0_uid394_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC0_uid394_tableGensinPiZ_lutmem_q <= memoryC0_uid394_tableGensinPiZ_lutmem_iq(29 downto 0);
--reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0(REG,603)@31
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q <= memoryC0_uid394_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid416_polyEvalsinPiZ(ADD,415)@32
sumAHighB_uid416_polyEvalsinPiZ_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q(29)) & reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q);
sumAHighB_uid416_polyEvalsinPiZ_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid415_polyEvalsinPiZ_b(21)) & highBBits_uid415_polyEvalsinPiZ_b);
sumAHighB_uid416_polyEvalsinPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid416_polyEvalsinPiZ_a) + SIGNED(sumAHighB_uid416_polyEvalsinPiZ_b));
sumAHighB_uid416_polyEvalsinPiZ_q <= sumAHighB_uid416_polyEvalsinPiZ_o(30 downto 0);
--lowRangeB_uid414_polyEvalsinPiZ(BITSELECT,413)@32
lowRangeB_uid414_polyEvalsinPiZ_in <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b(1 downto 0);
lowRangeB_uid414_polyEvalsinPiZ_b <= lowRangeB_uid414_polyEvalsinPiZ_in(1 downto 0);
--s2_uid414_uid417_polyEvalsinPiZ(BITJOIN,416)@32
s2_uid414_uid417_polyEvalsinPiZ_q <= sumAHighB_uid416_polyEvalsinPiZ_q & lowRangeB_uid414_polyEvalsinPiZ_b;
--polyEvalSigsinPiZ_uid86_fpSinCosXTest(BITSELECT,85)@32
polyEvalSigsinPiZ_uid86_fpSinCosXTest_in <= s2_uid414_uid417_polyEvalsinPiZ_q(30 downto 0);
polyEvalSigsinPiZ_uid86_fpSinCosXTest_b <= polyEvalSigsinPiZ_uid86_fpSinCosXTest_in(30 downto 5);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b(DELAY,708)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--multSinOp2_uid91_fpSinCosXTest(MUX,90)@32
multSinOp2_uid91_fpSinCosXTest_s <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q;
multSinOp2_uid91_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSinOp2_uid91_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE multSinOp2_uid91_fpSinCosXTest_s IS
WHEN "0" => multSinOp2_uid91_fpSinCosXTest_q <= polyEvalSigsinPiZ_uid86_fpSinCosXTest_b;
WHEN "1" => multSinOp2_uid91_fpSinCosXTest_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => multSinOp2_uid91_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor(LOGICAL,1320)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q <= not (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a or ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b);
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena(REG,1321)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd(LOGICAL,1322)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b <= en;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a and ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b;
--cPi_uid71_fpSinCosXTest(CONSTANT,70)
cPi_uid71_fpSinCosXTest_q <= "11001001000011111101101011";
--LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest(BITSELECT,309)@27
LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q(63 downto 0);
LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in(63 downto 0);
--leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest(BITJOIN,310)@27
leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b & GND_q;
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor(LOGICAL,1433)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q <= not (ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a or ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b);
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena(REG,1434)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q = "1") THEN
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd(LOGICAL,1435)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b <= en;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a and ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b;
--X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest(BITSELECT,280)@21
X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(32 downto 0);
X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b <= X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in(32 downto 0);
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg(DELAY,1425)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem(DUALMEM,1426)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 33,
widthad_a => 1,
numwords_a => 2,
width_b => 33,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia
);
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq(32 downto 0);
--leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest(BITJOIN,281)@25
leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor(LOGICAL,1444)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q <= not (ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a or ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b);
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena(REG,1445)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q = "1") THEN
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd(LOGICAL,1446)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b <= en;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a and ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg(DELAY,1436)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => zSin_uid60_fpSinCosXTest_q, xout => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem(DUALMEM,1437)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 65,
widthad_a => 1,
numwords_a => 2,
width_b => 65,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia
);
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq(64 downto 0);
--rVStage_uid237_lzcZSin_uid66_fpSinCosXTest(BITSELECT,236)@21
rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q;
rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in(64 downto 1);
--vCount_uid238_lzcZSin_uid66_fpSinCosXTest(LOGICAL,237)@21
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid236_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g(DELAY,903)@22
ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid240_lzcZSin_uid66_fpSinCosXTest(BITSELECT,239)@21
vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(0 downto 0);
vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in(0 downto 0);
--ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b(DELAY,861)@21
ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cStage_uid241_lzcZSin_uid66_fpSinCosXTest(BITJOIN,240)@22
cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q <= ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q & mO_uid239_lzcZSin_uid66_fpSinCosXTest_q;
--ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c(DELAY,863)@21
ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid243_lzcZSin_uid66_fpSinCosXTest(MUX,242)@22
vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid243_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s, en, ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q, cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid245_lzcZSin_uid66_fpSinCosXTest(BITSELECT,244)@22
rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in(63 downto 32);
--vCount_uid246_lzcZSin_uid66_fpSinCosXTest(LOGICAL,245)@22
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f(DELAY,902)@23
ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid247_lzcZSin_uid66_fpSinCosXTest(BITSELECT,246)@22
vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q(31 downto 0);
vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in(31 downto 0);
--ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d(DELAY,870)@22
ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c(DELAY,869)@22
ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid249_lzcZSin_uid66_fpSinCosXTest(MUX,248)@23
vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid249_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s, en, ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q, ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q)
BEGIN
CASE vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q;
WHEN OTHERS => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid251_lzcZSin_uid66_fpSinCosXTest(BITSELECT,250)@23
rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in(31 downto 16);
--vCount_uid252_lzcZSin_uid66_fpSinCosXTest(LOGICAL,251)@23
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b else "0";
--reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4(REG,585)@23
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q <= vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e(DELAY,901)@24
ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid253_lzcZSin_uid66_fpSinCosXTest(BITSELECT,252)@23
vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q(15 downto 0);
vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in(15 downto 0);
--vStagei_uid255_lzcZSin_uid66_fpSinCosXTest(MUX,254)@23
vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid255_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s, en, rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b, vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b;
WHEN "1" => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid257_lzcZSin_uid66_fpSinCosXTest(BITSELECT,256)@23
rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in(15 downto 8);
--reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1(REG,580)@23
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q <= rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid258_lzcZSin_uid66_fpSinCosXTest(LOGICAL,257)@24
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a <= reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q;
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b else "0";
--ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d(DELAY,900)@24
ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid259_lzcZSin_uid66_fpSinCosXTest(BITSELECT,258)@23
vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q(7 downto 0);
vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3(REG,582)@23
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q <= vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid261_lzcZSin_uid66_fpSinCosXTest(MUX,260)@24
vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid261_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s, en, reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q, reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid263_lzcZSin_uid66_fpSinCosXTest(BITSELECT,262)@24
rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in(7 downto 4);
--vCount_uid264_lzcZSin_uid66_fpSinCosXTest(LOGICAL,263)@24
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid265_lzcZSin_uid66_fpSinCosXTest(BITSELECT,264)@24
vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q(3 downto 0);
vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in(3 downto 0);
--reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3(REG,584)@24
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q <= vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2(REG,583)@24
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid267_lzcZSin_uid66_fpSinCosXTest(MUX,266)@25
vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid267_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s, en, reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q, reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid269_lzcZSin_uid66_fpSinCosXTest(BITSELECT,268)@25
rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in(3 downto 2);
--vCount_uid270_lzcZSin_uid66_fpSinCosXTest(LOGICAL,269)@25
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b else "0";
--vStage_uid271_lzcZSin_uid66_fpSinCosXTest(BITSELECT,270)@25
vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q(1 downto 0);
vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in(1 downto 0);
--vStagei_uid273_lzcZSin_uid66_fpSinCosXTest(MUX,272)@25
vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid273_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s, en, rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b, vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b;
WHEN "1" => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid275_lzcZSin_uid66_fpSinCosXTest(BITSELECT,274)@25
rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in(1 downto 1);
--vCount_uid276_lzcZSin_uid66_fpSinCosXTest(LOGICAL,275)@25
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b <= GND_q;
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b else "0";
--r_uid277_lzcZSin_uid66_fpSinCosXTest(BITJOIN,276)@25
r_uid277_lzcZSin_uid66_fpSinCosXTest_q <= ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q & ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q & ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q & ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q & vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q & vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q & vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q;
--leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest(BITSELECT,284)@25
leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q;
leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in(6 downto 5);
--leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest(MUX,285)@25
leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s <= leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b;
leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s, en, ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest(BITSELECT,293)@25
LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(40 downto 0);
LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in(40 downto 0);
--leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest(BITJOIN,294)@25
leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b & leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5(REG,590)@25
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest(BITSELECT,290)@25
LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(48 downto 0);
LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in(48 downto 0);
--leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest(BITJOIN,291)@25
leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4(REG,589)@25
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest(BITSELECT,287)@25
LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(56 downto 0);
LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in(56 downto 0);
--leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest(BITJOIN,288)@25
leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3(REG,588)@25
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2(REG,587)@25
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest(BITSELECT,295)@25
leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1(REG,586)@25
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q <= leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest(MUX,296)@26
leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s <= reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q;
leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s, en, reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest(BITSELECT,304)@26
LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(58 downto 0);
LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b(DELAY,927)@26
ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest(BITJOIN,305)@27
leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q;
--LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest(BITSELECT,301)@26
LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(60 downto 0);
LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b(DELAY,925)@26
ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest(BITJOIN,302)@27
leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest(BITSELECT,298)@26
LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(62 downto 0);
LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in(62 downto 0);
--ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b(DELAY,923)@26
ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest(BITJOIN,299)@27
leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2(REG,592)@26
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest(BITSELECT,306)@25
leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in(2 downto 1);
--ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a(DELAY,1214)@25
ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1(REG,591)@26
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q <= ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest(MUX,307)@27
leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s <= reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q;
leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s, en, reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest(BITSELECT,311)@25
leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b(DELAY,937)@25
ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest(MUX,312)@27
leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s <= ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q;
leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s, en, leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "0" => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "1" => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--pHigh_uid72_fpSinCosXTest(BITSELECT,71)@27
pHigh_uid72_fpSinCosXTest_in <= leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q;
pHigh_uid72_fpSinCosXTest_b <= pHigh_uid72_fpSinCosXTest_in(64 downto 39);
--reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2(REG,594)@27
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q <= pHigh_uid72_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a(DELAY,1216)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1(REG,593)@27
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--p_uid73_fpSinCosXTest(MUX,72)@28
p_uid73_fpSinCosXTest_s <= reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q;
p_uid73_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p_uid73_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE p_uid73_fpSinCosXTest_s IS
WHEN "0" => p_uid73_fpSinCosXTest_q <= reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q;
WHEN "1" => p_uid73_fpSinCosXTest_q <= cPi_uid71_fpSinCosXTest_q;
WHEN OTHERS => p_uid73_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg(DELAY,1312)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => p_uid73_fpSinCosXTest_q, xout => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem(DUALMEM,1313)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 1,
numwords_a => 2,
width_b => 26,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq,
address_a => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa,
data_a => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia
);
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0 <= areset;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq(25 downto 0);
--mulSin_uid92_fpSinCosXTest(MULT,91)@33
mulSin_uid92_fpSinCosXTest_pr <= UNSIGNED(mulSin_uid92_fpSinCosXTest_a) * UNSIGNED(mulSin_uid92_fpSinCosXTest_b);
mulSin_uid92_fpSinCosXTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulSin_uid92_fpSinCosXTest_a <= (others => '0');
mulSin_uid92_fpSinCosXTest_b <= (others => '0');
mulSin_uid92_fpSinCosXTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulSin_uid92_fpSinCosXTest_a <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q;
mulSin_uid92_fpSinCosXTest_b <= multSinOp2_uid91_fpSinCosXTest_q;
mulSin_uid92_fpSinCosXTest_s1 <= STD_LOGIC_VECTOR(mulSin_uid92_fpSinCosXTest_pr);
END IF;
END IF;
END PROCESS;
mulSin_uid92_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulSin_uid92_fpSinCosXTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulSin_uid92_fpSinCosXTest_q <= mulSin_uid92_fpSinCosXTest_s1;
END IF;
END IF;
END PROCESS;
--normBitSin_uid93_fpSinCosXTest(BITSELECT,92)@36
normBitSin_uid93_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q;
normBitSin_uid93_fpSinCosXTest_b <= normBitSin_uid93_fpSinCosXTest_in(51 downto 51);
--join_uid99_fpSinCosXTest(BITJOIN,98)@36
join_uid99_fpSinCosXTest_q <= reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q & normBitSin_uid93_fpSinCosXTest_b;
--sinRndOp_uid100_uid101_fpSinCosXTest(BITJOIN,100)@36
sinRndOp_uid100_uid101_fpSinCosXTest_q <= join_uid99_fpSinCosXTest_q & cstAllZWF_uid7_fpSinCosXTest_q & VCC_q;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor(LOGICAL,1333)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q <= not (ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a or ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b);
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena(REG,1334)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q = "1") THEN
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd(LOGICAL,1335)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b <= en;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a and ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor(LOGICAL,1283)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q <= not (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a or ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b);
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena(REG,1284)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd(LOGICAL,1285)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a and ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg(DELAY,1273)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expXRR_uid38_fpSinCosXTest_b, xout => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem(DUALMEM,1274)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 9,
width_b => 8,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia
);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1(REG,604)@25
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--expSinHC_uid74_fpSinCosXTest(SUB,73)@26
expSinHC_uid74_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expSinHC_uid74_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q);
expSinHC_uid74_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSinHC_uid74_fpSinCosXTest_a) - UNSIGNED(expSinHC_uid74_fpSinCosXTest_b));
expSinHC_uid74_fpSinCosXTest_q <= expSinHC_uid74_fpSinCosXTest_o(8 downto 0);
--expSinHCR_uid75_fpSinCosXTest(BITSELECT,74)@26
expSinHCR_uid75_fpSinCosXTest_in <= expSinHC_uid74_fpSinCosXTest_q(7 downto 0);
expSinHCR_uid75_fpSinCosXTest_b <= expSinHCR_uid75_fpSinCosXTest_in(7 downto 0);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b(DELAY,695)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expPSin_uid76_fpSinCosXTest(MUX,75)@26
expPSin_uid76_fpSinCosXTest_s <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q;
expPSin_uid76_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expPSin_uid76_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expPSin_uid76_fpSinCosXTest_s IS
WHEN "0" => expPSin_uid76_fpSinCosXTest_q <= expSinHCR_uid75_fpSinCosXTest_b;
WHEN "1" => expPSin_uid76_fpSinCosXTest_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => expPSin_uid76_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg(DELAY,1323)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expPSin_uid76_fpSinCosXTest_q, xout => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem(DUALMEM,1324)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 7,
width_b => 8,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia
);
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq(7 downto 0);
--fracRSinPreRndHigh_uid95_fpSinCosXTest(BITSELECT,94)@36
fracRSinPreRndHigh_uid95_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q(50 downto 0);
fracRSinPreRndHigh_uid95_fpSinCosXTest_b <= fracRSinPreRndHigh_uid95_fpSinCosXTest_in(50 downto 27);
--fracRSinPreRndLow_uid96_fpSinCosXTest(BITSELECT,95)@36
fracRSinPreRndLow_uid96_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q(49 downto 0);
fracRSinPreRndLow_uid96_fpSinCosXTest_b <= fracRSinPreRndLow_uid96_fpSinCosXTest_in(49 downto 26);
--fracRSinPreRnd_uid97_fpSinCosXTest(MUX,96)@36
fracRSinPreRnd_uid97_fpSinCosXTest_s <= normBitSin_uid93_fpSinCosXTest_b;
fracRSinPreRnd_uid97_fpSinCosXTest: PROCESS (fracRSinPreRnd_uid97_fpSinCosXTest_s, en, fracRSinPreRndLow_uid96_fpSinCosXTest_b, fracRSinPreRndHigh_uid95_fpSinCosXTest_b)
BEGIN
CASE fracRSinPreRnd_uid97_fpSinCosXTest_s IS
WHEN "0" => fracRSinPreRnd_uid97_fpSinCosXTest_q <= fracRSinPreRndLow_uid96_fpSinCosXTest_b;
WHEN "1" => fracRSinPreRnd_uid97_fpSinCosXTest_q <= fracRSinPreRndHigh_uid95_fpSinCosXTest_b;
WHEN OTHERS => fracRSinPreRnd_uid97_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracRSinPreRnd_uid98_uid98_fpSinCosXTest(BITJOIN,97)@36
expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q & fracRSinPreRnd_uid97_fpSinCosXTest_q;
--expFracRSin_uid102_fpSinCosXTest(ADD,101)@36
expFracRSin_uid102_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q);
expFracRSin_uid102_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0000000" & sinRndOp_uid100_uid101_fpSinCosXTest_q);
expFracRSin_uid102_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRSin_uid102_fpSinCosXTest_a) + UNSIGNED(expFracRSin_uid102_fpSinCosXTest_b));
expFracRSin_uid102_fpSinCosXTest_q <= expFracRSin_uid102_fpSinCosXTest_o(32 downto 0);
--expRCompSin_uid104_fpSinCosXTest(BITSELECT,103)@36
expRCompSin_uid104_fpSinCosXTest_in <= expFracRSin_uid102_fpSinCosXTest_q(31 downto 0);
expRCompSin_uid104_fpSinCosXTest_b <= expRCompSin_uid104_fpSinCosXTest_in(31 downto 24);
--reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2(REG,607)@36
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q <= expRCompSin_uid104_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor(LOGICAL,1537)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q <= not (ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a or ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b);
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena(REG,1538)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q = "1") THEN
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd(LOGICAL,1539)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b <= en;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a and ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b;
--expXIsZero_uid10_fpSinCosXTest(LOGICAL,9)@0
expXIsZero_uid10_fpSinCosXTest_a <= exp_uid9_fpSinCosXTest_b;
expXIsZero_uid10_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
expXIsZero_uid10_fpSinCosXTest_q <= "1" when expXIsZero_uid10_fpSinCosXTest_a = expXIsZero_uid10_fpSinCosXTest_b else "0";
--ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b(DELAY,746)@0
ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => expXIsZero_uid10_fpSinCosXTest_q, xout => ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excSelBitsSin_uid118_fpSinCosXTest(BITJOIN,117)@19
excSelBitsSin_uid118_fpSinCosXTest_q <= excRNaN_uid117_fpSinCosXTest_q & ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q & ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg(DELAY,1527)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => excSelBitsSin_uid118_fpSinCosXTest_q, xout => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem(DUALMEM,1528)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 4,
numwords_a => 14,
width_b => 3,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq,
address_a => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa,
data_a => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia
);
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0 <= areset;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq(2 downto 0);
--reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0(REG,533)@35
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--excSelSin_uid119_fpSinCosXTest(LOOKUP,118)@36
excSelSin_uid119_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excSelSin_uid119_fpSinCosXTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q) IS
WHEN "000" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN "001" => excSelSin_uid119_fpSinCosXTest_q <= "01";
WHEN "010" => excSelSin_uid119_fpSinCosXTest_q <= "10";
WHEN "011" => excSelSin_uid119_fpSinCosXTest_q <= "10";
WHEN "100" => excSelSin_uid119_fpSinCosXTest_q <= "11";
WHEN "101" => excSelSin_uid119_fpSinCosXTest_q <= "11";
WHEN "110" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN "111" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN OTHERS =>
excSelSin_uid119_fpSinCosXTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRPostExcSin_uid126_fpSinCosXTest(MUX,125)@37
expRPostExcSin_uid126_fpSinCosXTest_s <= excSelSin_uid119_fpSinCosXTest_q;
expRPostExcSin_uid126_fpSinCosXTest: PROCESS (expRPostExcSin_uid126_fpSinCosXTest_s, en, reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q, ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q, cstAllZWE_uid8_fpSinCosXTest_q, cstAllOWE_uid6_fpSinCosXTest_q)
BEGIN
CASE expRPostExcSin_uid126_fpSinCosXTest_s IS
WHEN "00" => expRPostExcSin_uid126_fpSinCosXTest_q <= reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q;
WHEN "01" => expRPostExcSin_uid126_fpSinCosXTest_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q;
WHEN "10" => expRPostExcSin_uid126_fpSinCosXTest_q <= cstAllZWE_uid8_fpSinCosXTest_q;
WHEN "11" => expRPostExcSin_uid126_fpSinCosXTest_q <= cstAllOWE_uid6_fpSinCosXTest_q;
WHEN OTHERS => expRPostExcSin_uid126_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor(LOGICAL,1346)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q <= not (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a or ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b);
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena(REG,1347)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd(LOGICAL,1348)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b <= en;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a and ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg(DELAY,1336)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => frac_uid13_fpSinCosXTest_b, xout => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem(DUALMEM,1337)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 6,
numwords_a => 35,
width_b => 23,
widthad_b => 6,
numwords_b => 35,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia
);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq(22 downto 0);
--fracRCompSin_uid103_fpSinCosXTest(BITSELECT,102)@36
fracRCompSin_uid103_fpSinCosXTest_in <= expFracRSin_uid102_fpSinCosXTest_q(23 downto 0);
fracRCompSin_uid103_fpSinCosXTest_b <= fracRCompSin_uid103_fpSinCosXTest_in(23 downto 1);
--reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2(REG,606)@36
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q <= fracRCompSin_uid103_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--fracRPostExcSin_uid122_fpSinCosXTest(MUX,121)@37
fracRPostExcSin_uid122_fpSinCosXTest_s <= excSelSin_uid119_fpSinCosXTest_q;
fracRPostExcSin_uid122_fpSinCosXTest: PROCESS (fracRPostExcSin_uid122_fpSinCosXTest_s, en, reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q, cstAllZWF_uid7_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q)
BEGIN
CASE fracRPostExcSin_uid122_fpSinCosXTest_s IS
WHEN "00" => fracRPostExcSin_uid122_fpSinCosXTest_q <= reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q;
WHEN "01" => fracRPostExcSin_uid122_fpSinCosXTest_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q;
WHEN "10" => fracRPostExcSin_uid122_fpSinCosXTest_q <= cstAllZWF_uid7_fpSinCosXTest_q;
WHEN "11" => fracRPostExcSin_uid122_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN OTHERS => fracRPostExcSin_uid122_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpSin_uid134_fpSinCosXTest(BITJOIN,133)@37
fpSin_uid134_fpSinCosXTest_q <= ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q & expRPostExcSin_uid126_fpSinCosXTest_q & fracRPostExcSin_uid122_fpSinCosXTest_q;
--xOut(GPOUT,4)@37
s <= fpSin_uid134_fpSinCosXTest_q;
c <= fpCos_uid162_fpSinCosXTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_sincos_s5
-- VHDL created on Wed Mar 27 09:55:14 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_sincos_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
s : out std_logic_vector(31 downto 0);
c : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_sincos_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid8_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid22_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid23_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShift_uid24_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid25_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid26_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstZwShiftP1_uid27_fpSinCosXTest_q : std_logic_vector (13 downto 0);
signal cstNaNwF_uid32_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal cstZmwFRRPwSM1_uid52_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal cPi_uid71_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal p_uid73_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal p_uid73_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal expPSin_uid76_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal expPSin_uid76_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal multSinOp2_uid91_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal multSinOp2_uid91_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_a : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_s1 : std_logic_vector (51 downto 0);
signal mulSin_uid92_fpSinCosXTest_pr : UNSIGNED (51 downto 0);
signal mulSin_uid92_fpSinCosXTest_q : std_logic_vector (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_a : std_logic_vector (25 downto 0);
signal mulCos_uid105_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal mulCos_uid105_fpSinCosXTest_s1 : std_logic_vector (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_pr : UNSIGNED (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_q : std_logic_vector (51 downto 0);
signal excSelSin_uid119_fpSinCosXTest_q : std_logic_vector(1 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expSelectorCos_uid145_fpSinCosXTest_q : std_logic_vector(1 downto 0);
signal signRCond2_uid152_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_d : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_d : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q : std_logic_vector (29 downto 0);
signal leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal zs_uid236_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal mO_uid239_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (62 downto 0);
signal zs_uid244_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal zs_uid250_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (5 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(63 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(63 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (47 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a : std_logic_vector (12 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr : SIGNED (26 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q : std_logic_vector (25 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a : std_logic_vector (14 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b : std_logic_vector (22 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr : SIGNED (38 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q : std_logic_vector (37 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a : std_logic_vector (12 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr : SIGNED (26 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q : std_logic_vector (25 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a : std_logic_vector (14 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b : std_logic_vector (22 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr : SIGNED (38 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q : std_logic_vector (37 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0 : std_logic;
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0 : std_logic;
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q : std_logic_vector (39 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a : std_logic_vector(81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b : std_logic_vector(81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o : std_logic_vector (81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q : std_logic_vector (81 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC0_uid394_tableGensinPiZ_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC1_uid396_tableGensinPiZ_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC2_uid398_tableGensinPiZ_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_q : std_logic_vector (12 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC0_uid400_tableGencosPiZ_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC1_uid402_tableGencosPiZ_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC2_uid404_tableGencosPiZ_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_q : std_logic_vector (12 downto 0);
signal reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q : std_logic_vector (2 downto 0);
signal reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q : std_logic_vector (39 downto 0);
signal reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (39 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q : std_logic_vector (26 downto 0);
signal reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (77 downto 0);
signal reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q : std_logic_vector (67 downto 0);
signal reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q : std_logic_vector (66 downto 0);
signal reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q : std_logic_vector (65 downto 0);
signal reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q : std_logic_vector (67 downto 0);
signal reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q : std_logic_vector (25 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q : std_logic_vector (12 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q : std_logic_vector (20 downto 0);
signal reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q : std_logic_vector (22 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q : std_logic_vector (29 downto 0);
signal reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q : std_logic_vector (6 downto 0);
signal reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q : std_logic_vector (22 downto 0);
signal reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q : std_logic_vector (0 downto 0);
signal reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q : std_logic_vector (12 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q : std_logic_vector (20 downto 0);
signal reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q : std_logic_vector (22 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q : std_logic_vector (29 downto 0);
signal reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q : std_logic_vector (25 downto 0);
signal reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q : std_logic_vector (25 downto 0);
signal reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q : std_logic_vector (6 downto 0);
signal reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q : std_logic_vector (22 downto 0);
signal reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q : std_logic_vector (3 downto 0);
signal reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q : std_logic_vector (52 downto 0);
signal ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q : std_logic_vector (65 downto 0);
signal ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q : std_logic_vector (67 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (7 downto 0);
signal ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (66 downto 0);
signal ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (65 downto 0);
signal ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (64 downto 0);
signal ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q : std_logic_vector (63 downto 0);
signal ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q : std_logic_vector (31 downto 0);
signal ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (58 downto 0);
signal ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q : std_logic_vector (63 downto 0);
signal ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q : std_logic_vector (31 downto 0);
signal ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (58 downto 0);
signal ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (76 downto 0);
signal ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (75 downto 0);
signal ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (74 downto 0);
signal ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q : std_logic_vector (12 downto 0);
signal ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q : std_logic_vector (53 downto 0);
signal ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q : std_logic_vector (12 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0 : std_logic;
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q : signal is true;
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q : std_logic_vector (6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0 : std_logic;
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q : signal is true;
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q : signal is true;
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0 : std_logic;
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0 : std_logic;
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0 : std_logic;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq : std_logic;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q : signal is true;
signal sinXIsXRR_uid41_fpSinCosXTest_a : std_logic_vector(11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_b : std_logic_vector(11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_o : std_logic_vector (11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_a : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_b : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_o : std_logic_vector (11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal yIsZero_uid51_fpSinCosXTest_a : std_logic_vector(65 downto 0);
signal yIsZero_uid51_fpSinCosXTest_b : std_logic_vector(65 downto 0);
signal yIsZero_uid51_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal pad_one_uid55_fpSinCosXTest_q : std_logic_vector (66 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_a : std_logic_vector(70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_b : std_logic_vector(70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_o : std_logic_vector (70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_c : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal InvCmpYToOneMinusY_uid61_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCmpYToOneMinusY_uid61_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid127_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid127_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvSinXIsXRR_uid128_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsXRR_uid128_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid131_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid131_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid132_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid132_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid136_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid136_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvCosXONe_uid149_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCosXONe_uid149_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid151_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid151_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvIntXParity_uid155_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvIntXParity_uid155_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal oFracXRR_uid43_uid43_fpSinCosXTest_q : std_logic_vector (53 downto 0);
signal half_uid53_fpSinCosXTest_q : std_logic_vector (65 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal exp_uid9_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal exp_uid9_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal frac_uid13_fpSinCosXTest_in : std_logic_vector (22 downto 0);
signal frac_uid13_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal signX_uid37_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal signX_uid37_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal expFracX_uid166_px_uid33_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal expFracX_uid166_px_uid33_fpSinCosXTest_b : std_logic_vector (30 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_q : std_logic_vector (9 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_a : std_logic_vector(65 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_b : std_logic_vector(65 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_a : std_logic_vector(67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_b : std_logic_vector(67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_o : std_logic_vector (67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal zSin_uid60_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal zSin_uid60_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal zCos_uid64_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal zCos_uid64_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal expSinHC_uid74_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal excRNaN_uid117_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid117_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid117_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracRPostExcSin_uid122_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExcSin_uid122_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal expRPostExcSin_uid126_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExcSin_uid126_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracRPostExcCos_uid142_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExcCos_uid142_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal expRPostExcCos_uid147_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExcCos_uid147_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cosXONe_uid148_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal cosXONe_uid148_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal cosXONe_uid148_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal finalExp_uid209_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal finalExp_uid209_rrx_uid34_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal extendedFracX_uid47_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal normBitSin_uid93_fpSinCosXTest_in : std_logic_vector (51 downto 0);
signal normBitSin_uid93_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal fracRSinPreRndHigh_uid95_fpSinCosXTest_in : std_logic_vector (50 downto 0);
signal fracRSinPreRndHigh_uid95_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracRSinPreRndLow_uid96_fpSinCosXTest_in : std_logic_vector (49 downto 0);
signal fracRSinPreRndLow_uid96_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal normBitCos_uid106_fpSinCosXTest_in : std_logic_vector (51 downto 0);
signal normBitCos_uid106_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal fracRCosPreRndHigh_uid108_fpSinCosXTest_in : std_logic_vector (50 downto 0);
signal fracRCosPreRndHigh_uid108_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracRCosPreRndLow_uid109_fpSinCosXTest_in : std_logic_vector (49 downto 0);
signal fracRCosPreRndLow_uid109_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q : std_logic_vector (52 downto 0);
signal leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b : std_logic_vector (23 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int : std_logic_vector (80 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q : std_logic_vector (80 downto 0);
signal os_uid196_rrx_uid34_fpSinCosXTest_q : std_logic_vector (79 downto 0);
signal leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal join_uid99_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal join_uid141_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal zSinYBottom_uid59_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal zSinYBottom_uid59_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal zSinOMyBottom_uid58_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal zSinOMyBottom_uid58_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal excSelBitsSin_uid118_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal fpSin_uid134_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal join_uid143_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal fpCos_uid162_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int : std_logic_vector (107 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q : std_logic_vector (107 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal fracX_uid187_rrx_uid34_fpSinCosXTest_in : std_logic_vector (22 downto 0);
signal fracX_uid187_rrx_uid34_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal oFracXRRSmallXRR_uid90_fpSinCosXTest_in : std_logic_vector (53 downto 0);
signal oFracXRRSmallXRR_uid90_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal R_uid167_px_uid33_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal InvFracXIsZero_uid16_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid16_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fxpXShiftVal_uid46_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal fxpXShiftVal_uid46_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal addr_uid81_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal addr_uid81_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal zPsinPiZ_uid84_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal zPsinPiZ_uid84_fpSinCosXTest_b : std_logic_vector (14 downto 0);
signal rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (32 downto 0);
signal addr_uid83_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal addr_uid83_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal zPcosPiZ_uid87_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal zPcosPiZ_uid87_fpSinCosXTest_b : std_logic_vector (14 downto 0);
signal rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (32 downto 0);
signal expSinHCR_uid75_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expSinHCR_uid75_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal expPCos_uid79_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expPCos_uid79_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (66 downto 0);
signal LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (66 downto 0);
signal LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (65 downto 0);
signal LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (58 downto 0);
signal rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (58 downto 0);
signal rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (76 downto 0);
signal LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (76 downto 0);
signal LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (75 downto 0);
signal LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (75 downto 0);
signal LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (74 downto 0);
signal LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (74 downto 0);
signal X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (59 downto 0);
signal X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (59 downto 0);
signal X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (55 downto 0);
signal X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (55 downto 0);
signal fracRSinPreRnd_uid97_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal fracRSinPreRnd_uid97_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal fracRCosPreRnd_uid110_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal fracRCosPreRnd_uid110_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal cosRndOp_uid112_uid113_fpSinCosXTest_q : std_logic_vector (24 downto 0);
signal rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal lowRangeB_uid408_polyEvalsinPiZ_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid408_polyEvalsinPiZ_b : std_logic_vector (0 downto 0);
signal highBBits_uid409_polyEvalsinPiZ_in : std_logic_vector (13 downto 0);
signal highBBits_uid409_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid414_polyEvalsinPiZ_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid414_polyEvalsinPiZ_b : std_logic_vector (1 downto 0);
signal highBBits_uid415_polyEvalsinPiZ_in : std_logic_vector (23 downto 0);
signal highBBits_uid415_polyEvalsinPiZ_b : std_logic_vector (21 downto 0);
signal lowRangeB_uid421_polyEvalcosPiZ_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid421_polyEvalcosPiZ_b : std_logic_vector (0 downto 0);
signal highBBits_uid422_polyEvalcosPiZ_in : std_logic_vector (13 downto 0);
signal highBBits_uid422_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid427_polyEvalcosPiZ_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid427_polyEvalcosPiZ_b : std_logic_vector (1 downto 0);
signal highBBits_uid428_polyEvalcosPiZ_in : std_logic_vector (23 downto 0);
signal highBBits_uid428_polyEvalcosPiZ_b : std_logic_vector (21 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in : std_logic_vector (80 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b : std_logic_vector (26 downto 0);
signal fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in : std_logic_vector (76 downto 0);
signal fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b : std_logic_vector (52 downto 0);
signal intXParity_uid49_fpSinCosXTest_in : std_logic_vector (67 downto 0);
signal intXParity_uid49_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal y_uid50_fpSinCosXTest_in : std_logic_vector (66 downto 0);
signal y_uid50_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal sinRndOp_uid100_uid101_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal expSelBitsCos_uid144_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a : std_logic_vector(108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b : std_logic_vector(108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o : std_logic_vector (108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q : std_logic_vector (108 downto 0);
signal oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal expX_uid186_rrx_uid34_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal expX_uid186_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal exc_N_uid17_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal yT1_uid406_polyEvalsinPiZ_in : std_logic_vector (14 downto 0);
signal yT1_uid406_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal yT1_uid419_polyEvalcosPiZ_in : std_logic_vector (14 downto 0);
signal yT1_uid419_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_a : std_logic_vector(32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_b : std_logic_vector(32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_o : std_logic_vector (32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_q : std_logic_vector (30 downto 0);
signal finalFrac_uid208_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal finalFrac_uid208_rrx_uid34_fpSinCosXTest_q : std_logic_vector (52 downto 0);
signal signComp_uid129_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_a : std_logic_vector(32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_b : std_logic_vector(32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_o : std_logic_vector (32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_q : std_logic_vector (32 downto 0);
signal leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal multFracBits_uid199_rrx_uid34_fpSinCosXTest_in : std_logic_vector (77 downto 0);
signal multFracBits_uid199_rrx_uid34_fpSinCosXTest_b : std_logic_vector (77 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b : std_logic_vector (26 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (5 downto 0);
signal fracRCompCos_uid115_fpSinCosXTest_in : std_logic_vector (23 downto 0);
signal fracRCompCos_uid115_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal expRCompSin_uid116_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal expRCompSin_uid116_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal s1_uid408_uid411_polyEvalsinPiZ_q : std_logic_vector (22 downto 0);
signal s2_uid414_uid417_polyEvalsinPiZ_q : std_logic_vector (32 downto 0);
signal s1_uid421_uid424_polyEvalcosPiZ_q : std_logic_vector (22 downto 0);
signal s2_uid427_uid430_polyEvalcosPiZ_q : std_logic_vector (32 downto 0);
signal RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q : std_logic_vector (61 downto 0);
signal signR_uid130_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signR_uid130_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signR_uid130_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal fracRCompSin_uid103_fpSinCosXTest_in : std_logic_vector (23 downto 0);
signal fracRCompSin_uid103_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal expRCompSin_uid104_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal expRCompSin_uid104_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in : std_logic_vector (77 downto 0);
signal multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (61 downto 0);
signal X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (61 downto 0);
signal X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (45 downto 0);
signal X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (45 downto 0);
signal X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (29 downto 0);
signal X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (29 downto 0);
signal expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal polyEvalSigsinPiZ_uid86_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal polyEvalSigsinPiZ_uid86_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal polyEvalSigcosPiZ_uid89_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal polyEvalSigcosPiZ_uid89_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal expXRR_uid38_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal expXRR_uid38_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal fracXRR_uid39_fpSinCosXTest_in : std_logic_vector (52 downto 0);
signal fracXRR_uid39_fpSinCosXTest_b : std_logic_vector (52 downto 0);
signal pHigh_uid72_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal pHigh_uid72_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal pCos_uid77_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal pCos_uid77_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal r_uid277_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (6 downto 0);
signal r_uid356_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (6 downto 0);
signal expCompOut_uid205_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expCompOut_uid205_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (73 downto 0);
signal LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (73 downto 0);
signal LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (69 downto 0);
signal LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (69 downto 0);
signal LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (65 downto 0);
signal LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (56 downto 0);
signal LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (48 downto 0);
signal LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (48 downto 0);
signal LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (40 downto 0);
signal LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (40 downto 0);
signal LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (56 downto 0);
signal LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (48 downto 0);
signal LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (48 downto 0);
signal LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (40 downto 0);
signal LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (40 downto 0);
signal leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
begin
--xIn(GPIN,3)@0
--GND(CONSTANT,0)
GND_q <= "0";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable(LOGICAL,1282)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q <= not ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor(LOGICAL,1422)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q <= not (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a or ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b);
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top(CONSTANT,1418)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q <= "01011";
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp(LOGICAL,1419)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q <= "1" when ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a = ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b else "0";
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg(REG,1420)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena(REG,1423)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd(LOGICAL,1424)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b <= en;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a and ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b;
--expFracX_uid166_px_uid33_fpSinCosXTest(BITSELECT,165)@0
expFracX_uid166_px_uid33_fpSinCosXTest_in <= a(30 downto 0);
expFracX_uid166_px_uid33_fpSinCosXTest_b <= expFracX_uid166_px_uid33_fpSinCosXTest_in(30 downto 0);
--R_uid167_px_uid33_fpSinCosXTest(BITJOIN,166)@0
R_uid167_px_uid33_fpSinCosXTest_q <= GND_q & expFracX_uid166_px_uid33_fpSinCosXTest_b;
--expX_uid186_rrx_uid34_fpSinCosXTest(BITSELECT,185)@0
expX_uid186_rrx_uid34_fpSinCosXTest_in <= R_uid167_px_uid33_fpSinCosXTest_q(30 downto 0);
expX_uid186_rrx_uid34_fpSinCosXTest_b <= expX_uid186_rrx_uid34_fpSinCosXTest_in(30 downto 23);
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg(DELAY,1412)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid186_rrx_uid34_fpSinCosXTest_b, xout => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt(COUNTER,1414)
-- every=1, low=0, high=11, step=1, init=1
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i = 10 THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i - 11;
ELSE
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg(REG,1415)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux(MUX,1416)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem(DUALMEM,1413)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 12,
width_b => 8,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia
);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--zs_uid244_lzcZSin_uid66_fpSinCosXTest(CONSTANT,243)
zs_uid244_lzcZSin_uid66_fpSinCosXTest_q <= "00000000000000000000000000000000";
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor(LOGICAL,1396)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q <= not (ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a or ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b);
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg(REG,1318)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena(REG,1397)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q = "1") THEN
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd(LOGICAL,1398)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b <= en;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a and ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg(DELAY,1388)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid167_px_uid33_fpSinCosXTest_q, xout => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt(COUNTER,1314)
-- every=1, low=0, high=1, step=1, init=1
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i,1));
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg(REG,1315)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux(MUX,1316)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s <= en;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux: PROCESS (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s, ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q, ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q)
BEGIN
CASE ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s IS
WHEN "0" => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
WHEN "1" => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem(DUALMEM,1389)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 1,
numwords_a => 2,
width_b => 32,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq,
address_a => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa,
data_a => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia
);
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0 <= areset;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq(31 downto 0);
--fracX_uid187_rrx_uid34_fpSinCosXTest(BITSELECT,186)@4
fracX_uid187_rrx_uid34_fpSinCosXTest_in <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q(22 downto 0);
fracX_uid187_rrx_uid34_fpSinCosXTest_b <= fracX_uid187_rrx_uid34_fpSinCosXTest_in(22 downto 0);
--oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest(BITJOIN,196)@4
oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q <= VCC_q & fracX_uid187_rrx_uid34_fpSinCosXTest_b;
--prod_uid198_rrx_uid34_fpSinCosXTest_b_0(BITSELECT,518)@4
prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in <= STD_LOGIC_VECTOR("000" & oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q);
prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b <= prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in(26 downto 0);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1(REG,539)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q <= prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShift_uid24_fpSinCosXTest(CONSTANT,23)
cstBiasMwShift_uid24_fpSinCosXTest_q <= "01110011";
--expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest(SUB,191)@0
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expX_uid186_rrx_uid34_fpSinCosXTest_b);
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0" & cstBiasMwShift_uid24_fpSinCosXTest_q);
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b));
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q <= expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o(8 downto 0);
--expXTableAddr_uid193_rrx_uid34_fpSinCosXTest(BITSELECT,192)@0
expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in <= expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q(7 downto 0);
expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b <= expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0(REG,534)@0
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q <= expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem(DUALMEM,514)@1
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia <= (others => '0');
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa <= (others => '0');
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab <= reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q;
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq,
address_a => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa,
data_a => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia
);
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0 <= areset;
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q <= rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1(REG,537)@3
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q <= rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem(DUALMEM,513)@1
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia <= (others => '0');
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa <= (others => '0');
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab <= reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q;
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq,
address_a => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa,
data_a => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia
);
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0 <= areset;
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q <= rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0(REG,536)@3
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q <= rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid196_rrx_uid34_fpSinCosXTest(BITJOIN,195)@4
os_uid196_rrx_uid34_fpSinCosXTest_q <= reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q & reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q;
--prod_uid198_rrx_uid34_fpSinCosXTest_a_2(BITSELECT,517)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in <= STD_LOGIC_VECTOR("0" & os_uid196_rrx_uid34_fpSinCosXTest_q);
prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in(80 downto 54);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0(REG,542)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0(MULT,521)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1;
END IF;
END IF;
END PROCESS;
--ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a(DELAY,1145)@8
ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a : dspba_delay
GENERIC MAP ( width => 54, depth => 1 )
PORT MAP ( xin => prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q, xout => ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--prod_uid198_rrx_uid34_fpSinCosXTest_align_2(BITSHIFT,524)@9
prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int <= ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int(107 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_a_1(BITSELECT,516)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in <= os_uid196_rrx_uid34_fpSinCosXTest_q(53 downto 0);
prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in(53 downto 27);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0(REG,540)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0(MULT,520)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_align_1(BITSHIFT,523)@8
prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int <= prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q & "000000000000000000000000000";
prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int(80 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_a_0(BITSELECT,515)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in <= os_uid196_rrx_uid34_fpSinCosXTest_q(26 downto 0);
prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in(26 downto 0);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0(REG,538)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0(MULT,519)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_align_0(BITSHIFT,522)@8
prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int <= prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int(53 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0(ADD,525)@8
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a <= STD_LOGIC_VECTOR("0000000000000000000000000000" & prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b <= STD_LOGIC_VECTOR("0" & prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a) + UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b));
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o(81 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0(ADD,526)@9
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a <= STD_LOGIC_VECTOR("000000000000000000000000000" & prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b <= STD_LOGIC_VECTOR("0" & prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a) + UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b));
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o(108 downto 0);
--multFracBits_uid199_rrx_uid34_fpSinCosXTest(BITSELECT,198)@9
multFracBits_uid199_rrx_uid34_fpSinCosXTest_in <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q(77 downto 0);
multFracBits_uid199_rrx_uid34_fpSinCosXTest_b <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_in(77 downto 0);
--multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest(BITSELECT,199)@9
multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b;
multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b <= multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in(77 downto 46);
--reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1(REG,544)@9
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,433)@10
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a(DELAY,1178)@10
ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xout => ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5(REG,555)@12
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q <= ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q;
END IF;
END IF;
END PROCESS;
--zs_uid250_lzcZSin_uid66_fpSinCosXTest(CONSTANT,249)
zs_uid250_lzcZSin_uid66_fpSinCosXTest_q <= "0000000000000000";
--mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest(CONSTANT,434)
mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "11111111111111111111111111111111";
--vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,436)@10
vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q, mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,438)@10
rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in(31 downto 16);
--reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1(REG,546)@10
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,439)@11
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4(REG,554)@11
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q <= vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e(DELAY,1081)@12
ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWE_uid8_fpSinCosXTest(CONSTANT,7)
cstAllZWE_uid8_fpSinCosXTest_q <= "00000000";
--vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,440)@10
vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q(15 downto 0);
vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in(15 downto 0);
--reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,548)@10
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,442)@11
vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q, reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,444)@11
rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in(15 downto 8);
--vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,445)@11
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i <= "1" when vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xin => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d(DELAY,1080)@12
ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xout => ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest(CONSTANT,212)
leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q <= "0000";
--vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,446)@11
vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q(7 downto 0);
vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,550)@11
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,549)@11
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,448)@12
vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q, reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,450)@12
rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in(7 downto 4);
--vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,451)@12
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,553)@12
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest(CONSTANT,226)
leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q <= "00";
--vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,452)@12
vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q(3 downto 0);
vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in(3 downto 0);
--vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,454)@12
vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b, vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
WHEN "1" => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,456)@12
rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in(3 downto 2);
--vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,457)@12
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i <= "1" when vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xin => vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,458)@12
vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q(1 downto 0);
vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in(1 downto 0);
--reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,552)@12
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,551)@12
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,460)@13
vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q, reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,462)@13
rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in(1 downto 1);
--vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,463)@13
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= GND_q;
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest(BITJOIN,464)@13
r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q & ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q & ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q & reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q & vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q & vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
--cstBiasM1_uid23_fpSinCosXTest(CONSTANT,22)
cstBiasM1_uid23_fpSinCosXTest_q <= "01111110";
--expCompOutExt_uid204_rrx_uid34_fpSinCosXTest(SUB,203)@13
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("000" & r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q);
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b));
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q <= expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o(8 downto 0);
--expCompOut_uid205_rrx_uid34_fpSinCosXTest(BITSELECT,204)@13
expCompOut_uid205_rrx_uid34_fpSinCosXTest_in <= expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q(7 downto 0);
expCompOut_uid205_rrx_uid34_fpSinCosXTest_b <= expCompOut_uid205_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2(REG,564)@13
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q <= expCompOut_uid205_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--xBranch_uid191_rrx_uid34_fpSinCosXTest(COMPARE,190)@0
xBranch_uid191_rrx_uid34_fpSinCosXTest_cin <= GND_q;
xBranch_uid191_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid24_fpSinCosXTest_q) & '0';
xBranch_uid191_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & expX_uid186_rrx_uid34_fpSinCosXTest_b) & xBranch_uid191_rrx_uid34_fpSinCosXTest_cin(0);
xBranch_uid191_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xBranch_uid191_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(xBranch_uid191_rrx_uid34_fpSinCosXTest_b));
xBranch_uid191_rrx_uid34_fpSinCosXTest_n(0) <= not xBranch_uid191_rrx_uid34_fpSinCosXTest_o(10);
--reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1(REG,563)@0
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q <= xBranch_uid191_rrx_uid34_fpSinCosXTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b(DELAY,829)@1
ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q, xout => ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalExp_uid209_rrx_uid34_fpSinCosXTest(MUX,208)@14
finalExp_uid209_rrx_uid34_fpSinCosXTest_s <= ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q;
finalExp_uid209_rrx_uid34_fpSinCosXTest: PROCESS (finalExp_uid209_rrx_uid34_fpSinCosXTest_s, en, reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q)
BEGIN
CASE finalExp_uid209_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b(DELAY,833)@14
ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => finalExp_uid209_rrx_uid34_fpSinCosXTest_q, xout => ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1409)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a or ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top(CONSTANT,1279)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q <= "01000";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp(LOGICAL,1280)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q <= "1" when ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a = ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b else "0";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg(REG,1281)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1410)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1411)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1399)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid187_rrx_uid34_fpSinCosXTest_b, xout => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt(COUNTER,1275)
-- every=1, low=0, high=8, step=1, init=1
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i = 7 THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i - 8;
ELSE
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg(REG,1276)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux(MUX,1277)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s, ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q, ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1400)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 4,
numwords_a => 9,
width_b => 23,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(22 downto 0);
--ZerosGB_uid206_rrx_uid34_fpSinCosXTest(CONSTANT,205)
ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q <= "000000000000000000000000000000";
--fracXRExt_uid207_rrx_uid34_fpSinCosXTest(BITJOIN,206)@15
fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q & ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q;
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1499)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1500)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1501)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,474)@9
X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(29 downto 0);
X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in(29 downto 0);
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1491)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 30, depth => 1 )
PORT MAP ( xin => X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1492)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 1,
numwords_a => 2,
width_b => 30,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(29 downto 0);
--leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest(CONSTANT,473)
leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,475)@13
leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1488)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1489)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1490)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,471)@9
X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(45 downto 0);
X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in(45 downto 0);
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1480)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1481)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 1,
numwords_a => 2,
width_b => 46,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(45 downto 0);
--leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,472)@13
leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1477)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1478)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1479)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,468)@9
X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(61 downto 0);
X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in(61 downto 0);
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1469)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1470)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 62,
widthad_a => 1,
numwords_a => 2,
width_b => 62,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(61 downto 0);
--leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,469)@13
leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor(LOGICAL,1510)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q <= not (ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a or ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b);
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena(REG,1511)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q = "1") THEN
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd(LOGICAL,1512)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b <= en;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a and ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg(DELAY,1502)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 78, depth => 1 )
PORT MAP ( xin => multFracBits_uid199_rrx_uid34_fpSinCosXTest_b, xout => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem(DUALMEM,1503)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 78,
widthad_a => 1,
numwords_a => 2,
width_b => 78,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia
);
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq(77 downto 0);
--leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,476)@13
leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in(5 downto 4);
--leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,477)@13
leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b;
leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,485)@13
LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(65 downto 0);
LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in(65 downto 0);
--leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest(CONSTANT,218)
leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q <= "000000000000";
--leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,486)@13
leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b & leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5(REG,560)@13
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,482)@13
LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(69 downto 0);
LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in(69 downto 0);
--leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,483)@13
leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4(REG,559)@13
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,479)@13
LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(73 downto 0);
LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in(73 downto 0);
--leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,480)@13
leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3(REG,558)@13
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2(REG,557)@13
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,487)@13
leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1(REG,556)@13
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,488)@14
leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q;
leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,496)@14
LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(74 downto 0);
LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in(74 downto 0);
--ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1112)@14
ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 75, depth => 1 )
PORT MAP ( xin => LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest(CONSTANT,229)
leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q <= "000";
--leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,497)@15
leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,493)@14
LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(75 downto 0);
LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in(75 downto 0);
--ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1110)@14
ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 76, depth => 1 )
PORT MAP ( xin => LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,494)@15
leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,490)@14
LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(76 downto 0);
LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in(76 downto 0);
--ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1108)@14
ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 77, depth => 1 )
PORT MAP ( xin => LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,491)@15
leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & GND_q;
--reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2(REG,562)@14
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,498)@13
leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a(DELAY,1184)@13
ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1(REG,561)@14
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,499)@15
leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q;
leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracCompOut_uid203_rrx_uid34_fpSinCosXTest(BITSELECT,202)@15
fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in <= leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q(76 downto 0);
fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b <= fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in(76 downto 24);
--ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b(DELAY,826)@0
ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => xBranch_uid191_rrx_uid34_fpSinCosXTest_n, xout => ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalFrac_uid208_rrx_uid34_fpSinCosXTest(MUX,207)@15
finalFrac_uid208_rrx_uid34_fpSinCosXTest_s <= ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q;
finalFrac_uid208_rrx_uid34_fpSinCosXTest: PROCESS (finalFrac_uid208_rrx_uid34_fpSinCosXTest_s, en, fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b, fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE finalFrac_uid208_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b;
WHEN "1" => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RRangeRed_uid210_rrx_uid34_fpSinCosXTest(BITJOIN,209)@15
RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q <= GND_q & ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q & finalFrac_uid208_rrx_uid34_fpSinCosXTest_q;
--expXRR_uid38_fpSinCosXTest(BITSELECT,37)@15
expXRR_uid38_fpSinCosXTest_in <= RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q(60 downto 0);
expXRR_uid38_fpSinCosXTest_b <= expXRR_uid38_fpSinCosXTest_in(60 downto 53);
--reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1(REG,565)@15
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q <= expXRR_uid38_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShiftM2_uid26_fpSinCosXTest(CONSTANT,25)
cstBiasMwShiftM2_uid26_fpSinCosXTest_q <= "01110000";
--cosXIsOneXRR_uid42_fpSinCosXTest(COMPARE,41)@16
cosXIsOneXRR_uid42_fpSinCosXTest_cin <= GND_q;
cosXIsOneXRR_uid42_fpSinCosXTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid26_fpSinCosXTest_q) & '0';
cosXIsOneXRR_uid42_fpSinCosXTest_b <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q) & cosXIsOneXRR_uid42_fpSinCosXTest_cin(0);
cosXIsOneXRR_uid42_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(cosXIsOneXRR_uid42_fpSinCosXTest_a) - SIGNED(cosXIsOneXRR_uid42_fpSinCosXTest_b));
cosXIsOneXRR_uid42_fpSinCosXTest_n(0) <= not cosXIsOneXRR_uid42_fpSinCosXTest_o(11);
--exp_uid9_fpSinCosXTest(BITSELECT,8)@0
exp_uid9_fpSinCosXTest_in <= a(30 downto 0);
exp_uid9_fpSinCosXTest_b <= exp_uid9_fpSinCosXTest_in(30 downto 23);
--sinXIsX_uid40_fpSinCosXTest(COMPARE,39)@0
sinXIsX_uid40_fpSinCosXTest_cin <= GND_q;
sinXIsX_uid40_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid24_fpSinCosXTest_q) & '0';
sinXIsX_uid40_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & exp_uid9_fpSinCosXTest_b) & sinXIsX_uid40_fpSinCosXTest_cin(0);
sinXIsX_uid40_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid40_fpSinCosXTest_a) - UNSIGNED(sinXIsX_uid40_fpSinCosXTest_b));
sinXIsX_uid40_fpSinCosXTest_n(0) <= not sinXIsX_uid40_fpSinCosXTest_o(10);
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a(DELAY,789)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--cosXONe_uid148_fpSinCosXTest(LOGICAL,147)@16
cosXONe_uid148_fpSinCosXTest_a <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q;
cosXONe_uid148_fpSinCosXTest_b <= cosXIsOneXRR_uid42_fpSinCosXTest_n;
cosXONe_uid148_fpSinCosXTest_q <= cosXONe_uid148_fpSinCosXTest_a or cosXONe_uid148_fpSinCosXTest_b;
--ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a(DELAY,791)@16
ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => cosXONe_uid148_fpSinCosXTest_q, xout => ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvCosXONe_uid149_fpSinCosXTest(LOGICAL,148)@20
InvCosXONe_uid149_fpSinCosXTest_a <= ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q;
InvCosXONe_uid149_fpSinCosXTest_q <= not InvCosXONe_uid149_fpSinCosXTest_a;
--cstZwShiftP1_uid27_fpSinCosXTest(CONSTANT,26)
cstZwShiftP1_uid27_fpSinCosXTest_q <= "00000000000000";
--fracXRR_uid39_fpSinCosXTest(BITSELECT,38)@15
fracXRR_uid39_fpSinCosXTest_in <= RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q(52 downto 0);
fracXRR_uid39_fpSinCosXTest_b <= fracXRR_uid39_fpSinCosXTest_in(52 downto 0);
--ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a(DELAY,668)@15
ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => fracXRR_uid39_fpSinCosXTest_b, xout => ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracXRR_uid43_uid43_fpSinCosXTest(BITJOIN,42)@16
oFracXRR_uid43_uid43_fpSinCosXTest_q <= VCC_q & ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q;
--extendedFracX_uid47_fpSinCosXTest(BITJOIN,46)@16
extendedFracX_uid47_fpSinCosXTest_q <= cstZwShiftP1_uid27_fpSinCosXTest_q & oFracXRR_uid43_uid43_fpSinCosXTest_q;
--X55dto0_uid220_fxpX_uid48_fpSinCosXTest(BITSELECT,219)@16
X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(55 downto 0);
X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b <= X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in(55 downto 0);
--leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest(BITJOIN,220)@16
leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q <= X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b & leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5(REG,571)@16
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q <= leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--X59dto0_uid217_fxpX_uid48_fpSinCosXTest(BITSELECT,216)@16
X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(59 downto 0);
X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b <= X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in(59 downto 0);
--leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest(BITJOIN,217)@16
leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q <= X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4(REG,570)@16
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q <= leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--X63dto0_uid214_fxpX_uid48_fpSinCosXTest(BITSELECT,213)@16
X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(63 downto 0);
X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b <= X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in(63 downto 0);
--leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest(BITJOIN,214)@16
leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q <= X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3(REG,569)@16
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q <= leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2(REG,568)@16
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q <= extendedFracX_uid47_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--fxpXShiftValExt_uid45_fpSinCosXTest(SUB,44)@16
fxpXShiftValExt_uid45_fpSinCosXTest_a <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q);
fxpXShiftValExt_uid45_fpSinCosXTest_b <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid26_fpSinCosXTest_q);
fxpXShiftValExt_uid45_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(fxpXShiftValExt_uid45_fpSinCosXTest_a) - SIGNED(fxpXShiftValExt_uid45_fpSinCosXTest_b));
fxpXShiftValExt_uid45_fpSinCosXTest_q <= fxpXShiftValExt_uid45_fpSinCosXTest_o(9 downto 0);
--fxpXShiftVal_uid46_fpSinCosXTest(BITSELECT,45)@16
fxpXShiftVal_uid46_fpSinCosXTest_in <= fxpXShiftValExt_uid45_fpSinCosXTest_q(3 downto 0);
fxpXShiftVal_uid46_fpSinCosXTest_b <= fxpXShiftVal_uid46_fpSinCosXTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest(BITSELECT,221)@16
leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in <= fxpXShiftVal_uid46_fpSinCosXTest_b;
leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b <= leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1(REG,567)@16
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q <= leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest(MUX,222)@17
leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s <= reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q;
leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest: PROCESS (leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s, en, reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q, reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q, reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q, reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest(BITSELECT,230)@17
LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(64 downto 0);
LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in(64 downto 0);
--ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b(DELAY,851)@17
ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest(BITJOIN,231)@18
leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q & leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest(BITSELECT,227)@17
LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(65 downto 0);
LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in(65 downto 0);
--ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b(DELAY,849)@17
ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 66, depth => 1 )
PORT MAP ( xin => LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest(BITJOIN,228)@18
leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest(BITSELECT,224)@17
LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(66 downto 0);
LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in(66 downto 0);
--ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b(DELAY,847)@17
ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 67, depth => 1 )
PORT MAP ( xin => LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest(BITJOIN,225)@18
leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q & GND_q;
--reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2(REG,573)@17
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest(BITSELECT,232)@16
leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in <= fxpXShiftVal_uid46_fpSinCosXTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b <= leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a(DELAY,1195)@16
ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b, xout => ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1(REG,572)@17
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q <= ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest(MUX,233)@18
leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s <= reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q;
leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest: PROCESS (leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s, en, reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q, leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q, leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q, leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q;
WHEN "10" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q;
WHEN "11" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid50_fpSinCosXTest(BITSELECT,49)@18
y_uid50_fpSinCosXTest_in <= leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q(66 downto 0);
y_uid50_fpSinCosXTest_b <= y_uid50_fpSinCosXTest_in(66 downto 1);
--ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b(DELAY,680)@18
ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 66, depth => 2 )
PORT MAP ( xin => y_uid50_fpSinCosXTest_b, xout => ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1(REG,575)@18
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q <= y_uid50_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--pad_one_uid55_fpSinCosXTest(BITJOIN,54)@18
pad_one_uid55_fpSinCosXTest_q <= VCC_q & STD_LOGIC_VECTOR((65 downto 1 => GND_q(0)) & GND_q);
--reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0(REG,574)@18
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q <= pad_one_uid55_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--oneMinusY_uid55_fpSinCosXTest(SUB,55)@19
oneMinusY_uid55_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q);
oneMinusY_uid55_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q);
oneMinusY_uid55_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid55_fpSinCosXTest_a) - UNSIGNED(oneMinusY_uid55_fpSinCosXTest_b));
oneMinusY_uid55_fpSinCosXTest_q <= oneMinusY_uid55_fpSinCosXTest_o(67 downto 0);
--reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0(REG,576)@19
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q <= oneMinusY_uid55_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid57_fpSinCosXTest(COMPARE,56)@20
cmpYToOneMinusY_uid57_fpSinCosXTest_cin <= GND_q;
cmpYToOneMinusY_uid57_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q) & '0';
cmpYToOneMinusY_uid57_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q) & cmpYToOneMinusY_uid57_fpSinCosXTest_cin(0);
cmpYToOneMinusY_uid57_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid57_fpSinCosXTest_a) - UNSIGNED(cmpYToOneMinusY_uid57_fpSinCosXTest_b));
cmpYToOneMinusY_uid57_fpSinCosXTest_c(0) <= cmpYToOneMinusY_uid57_fpSinCosXTest_o(70);
--InvCmpYToOneMinusY_uid61_fpSinCosXTest(LOGICAL,60)@20
InvCmpYToOneMinusY_uid61_fpSinCosXTest_a <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
InvCmpYToOneMinusY_uid61_fpSinCosXTest_q <= not InvCmpYToOneMinusY_uid61_fpSinCosXTest_a;
--intXParity_uid49_fpSinCosXTest(BITSELECT,48)@18
intXParity_uid49_fpSinCosXTest_in <= leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q;
intXParity_uid49_fpSinCosXTest_b <= intXParity_uid49_fpSinCosXTest_in(67 downto 67);
--ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b(DELAY,794)@18
ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => intXParity_uid49_fpSinCosXTest_b, xout => ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--yIsZero_uid51_fpSinCosXTest(LOGICAL,50)@19
yIsZero_uid51_fpSinCosXTest_a <= reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q;
yIsZero_uid51_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000000000000000000000000000000000" & GND_q);
yIsZero_uid51_fpSinCosXTest_q <= "1" when yIsZero_uid51_fpSinCosXTest_a = yIsZero_uid51_fpSinCosXTest_b else "0";
--ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a(DELAY,792)@19
ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => yIsZero_uid51_fpSinCosXTest_q, xout => ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvYIsZero_uid151_fpSinCosXTest(LOGICAL,150)@20
InvYIsZero_uid151_fpSinCosXTest_a <= ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q;
InvYIsZero_uid151_fpSinCosXTest_q <= not InvYIsZero_uid151_fpSinCosXTest_a;
--signRCond2_uid152_fpSinCosXTest(LOGICAL,151)@20
signRCond2_uid152_fpSinCosXTest_a <= InvYIsZero_uid151_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_b <= ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q;
signRCond2_uid152_fpSinCosXTest_c <= InvCmpYToOneMinusY_uid61_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_d <= InvCosXONe_uid149_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_q_i <= signRCond2_uid152_fpSinCosXTest_a and signRCond2_uid152_fpSinCosXTest_b and signRCond2_uid152_fpSinCosXTest_c and signRCond2_uid152_fpSinCosXTest_d;
signRCond2_uid152_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRCond2_uid152_fpSinCosXTest_q, xin => signRCond2_uid152_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--InvIntXParity_uid155_fpSinCosXTest(LOGICAL,154)@20
InvIntXParity_uid155_fpSinCosXTest_a <= ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q;
InvIntXParity_uid155_fpSinCosXTest_q <= not InvIntXParity_uid155_fpSinCosXTest_a;
--signRCond1_uid157_fpSinCosXTest(LOGICAL,156)@20
signRCond1_uid157_fpSinCosXTest_a <= InvYIsZero_uid151_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_b <= InvIntXParity_uid155_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_c <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
signRCond1_uid157_fpSinCosXTest_d <= InvCosXONe_uid149_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_q_i <= signRCond1_uid157_fpSinCosXTest_a and signRCond1_uid157_fpSinCosXTest_b and signRCond1_uid157_fpSinCosXTest_c and signRCond1_uid157_fpSinCosXTest_d;
signRCond1_uid157_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRCond1_uid157_fpSinCosXTest_q, xin => signRCond1_uid157_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--signRCos_uid158_fpSinCosXTest(LOGICAL,157)@21
signRCos_uid158_fpSinCosXTest_a <= signRCond1_uid157_fpSinCosXTest_q;
signRCos_uid158_fpSinCosXTest_b <= signRCond2_uid152_fpSinCosXTest_q;
signRCos_uid158_fpSinCosXTest_q <= signRCos_uid158_fpSinCosXTest_a or signRCos_uid158_fpSinCosXTest_b;
--cstAllZWF_uid7_fpSinCosXTest(CONSTANT,6)
cstAllZWF_uid7_fpSinCosXTest_q <= "00000000000000000000000";
--frac_uid13_fpSinCosXTest(BITSELECT,12)@0
frac_uid13_fpSinCosXTest_in <= a(22 downto 0);
frac_uid13_fpSinCosXTest_b <= frac_uid13_fpSinCosXTest_in(22 downto 0);
--fracXIsZero_uid14_fpSinCosXTest(LOGICAL,13)@0
fracXIsZero_uid14_fpSinCosXTest_a <= frac_uid13_fpSinCosXTest_b;
fracXIsZero_uid14_fpSinCosXTest_b <= cstAllZWF_uid7_fpSinCosXTest_q;
fracXIsZero_uid14_fpSinCosXTest_q <= "1" when fracXIsZero_uid14_fpSinCosXTest_a = fracXIsZero_uid14_fpSinCosXTest_b else "0";
--cstAllOWE_uid6_fpSinCosXTest(CONSTANT,5)
cstAllOWE_uid6_fpSinCosXTest_q <= "11111111";
--expXIsMax_uid12_fpSinCosXTest(LOGICAL,11)@0
expXIsMax_uid12_fpSinCosXTest_a <= exp_uid9_fpSinCosXTest_b;
expXIsMax_uid12_fpSinCosXTest_b <= cstAllOWE_uid6_fpSinCosXTest_q;
expXIsMax_uid12_fpSinCosXTest_q <= "1" when expXIsMax_uid12_fpSinCosXTest_a = expXIsMax_uid12_fpSinCosXTest_b else "0";
--exc_I_uid15_fpSinCosXTest(LOGICAL,14)@0
exc_I_uid15_fpSinCosXTest_a <= expXIsMax_uid12_fpSinCosXTest_q;
exc_I_uid15_fpSinCosXTest_b <= fracXIsZero_uid14_fpSinCosXTest_q;
exc_I_uid15_fpSinCosXTest_q <= exc_I_uid15_fpSinCosXTest_a and exc_I_uid15_fpSinCosXTest_b;
--ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a(DELAY,762)@0
ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 20 )
PORT MAP ( xin => exc_I_uid15_fpSinCosXTest_q, xout => ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_I_uid131_fpSinCosXTest(LOGICAL,130)@20
InvExc_I_uid131_fpSinCosXTest_a <= ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q;
InvExc_I_uid131_fpSinCosXTest_q <= not InvExc_I_uid131_fpSinCosXTest_a;
--reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2(REG,649)@20
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q <= InvExc_I_uid131_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--InvFracXIsZero_uid16_fpSinCosXTest(LOGICAL,15)@0
InvFracXIsZero_uid16_fpSinCosXTest_a <= fracXIsZero_uid14_fpSinCosXTest_q;
InvFracXIsZero_uid16_fpSinCosXTest_q <= not InvFracXIsZero_uid16_fpSinCosXTest_a;
--exc_N_uid17_fpSinCosXTest(LOGICAL,16)@0
exc_N_uid17_fpSinCosXTest_a <= expXIsMax_uid12_fpSinCosXTest_q;
exc_N_uid17_fpSinCosXTest_b <= InvFracXIsZero_uid16_fpSinCosXTest_q;
exc_N_uid17_fpSinCosXTest_q <= exc_N_uid17_fpSinCosXTest_a and exc_N_uid17_fpSinCosXTest_b;
--ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a(DELAY,763)@0
ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 20 )
PORT MAP ( xin => exc_N_uid17_fpSinCosXTest_q, xout => ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid132_fpSinCosXTest(LOGICAL,131)@20
InvExc_N_uid132_fpSinCosXTest_a <= ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q;
InvExc_N_uid132_fpSinCosXTest_q <= not InvExc_N_uid132_fpSinCosXTest_a;
--reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1(REG,648)@20
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q <= InvExc_N_uid132_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--signRCosFull_uid161_fpSinCosXTest(LOGICAL,160)@21
signRCosFull_uid161_fpSinCosXTest_a <= reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q;
signRCosFull_uid161_fpSinCosXTest_b <= reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q;
signRCosFull_uid161_fpSinCosXTest_c <= signRCos_uid158_fpSinCosXTest_q;
signRCosFull_uid161_fpSinCosXTest_q <= signRCosFull_uid161_fpSinCosXTest_a and signRCosFull_uid161_fpSinCosXTest_b and signRCosFull_uid161_fpSinCosXTest_c;
--ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c(DELAY,809)@21
ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signRCosFull_uid161_fpSinCosXTest_q, xout => ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid22_fpSinCosXTest(CONSTANT,21)
cstBias_uid22_fpSinCosXTest_q <= "01111111";
--ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a(DELAY,681)@19
ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 68, depth => 1 )
PORT MAP ( xin => oneMinusY_uid55_fpSinCosXTest_q, xout => ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--zSinOMyBottom_uid58_fpSinCosXTest(BITSELECT,57)@20
zSinOMyBottom_uid58_fpSinCosXTest_in <= ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q(64 downto 0);
zSinOMyBottom_uid58_fpSinCosXTest_b <= zSinOMyBottom_uid58_fpSinCosXTest_in(64 downto 0);
--reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3(REG,579)@20
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q <= zSinOMyBottom_uid58_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--zSinYBottom_uid59_fpSinCosXTest(BITSELECT,58)@20
zSinYBottom_uid59_fpSinCosXTest_in <= ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q(64 downto 0);
zSinYBottom_uid59_fpSinCosXTest_b <= zSinYBottom_uid59_fpSinCosXTest_in(64 downto 0);
--reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2(REG,578)@20
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q <= zSinYBottom_uid59_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1(REG,614)@20
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q <= InvCmpYToOneMinusY_uid61_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--zCos_uid64_fpSinCosXTest(MUX,63)@21
zCos_uid64_fpSinCosXTest_s <= reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q;
zCos_uid64_fpSinCosXTest: PROCESS (zCos_uid64_fpSinCosXTest_s, en, reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q, reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q)
BEGIN
CASE zCos_uid64_fpSinCosXTest_s IS
WHEN "0" => zCos_uid64_fpSinCosXTest_q <= reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q;
WHEN "1" => zCos_uid64_fpSinCosXTest_q <= reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q;
WHEN OTHERS => zCos_uid64_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--addr_uid83_fpSinCosXTest(BITSELECT,82)@21
addr_uid83_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q;
addr_uid83_fpSinCosXTest_b <= addr_uid83_fpSinCosXTest_in(64 downto 57);
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0(REG,630)@21
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q <= addr_uid83_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid404_tableGencosPiZ_lutmem(DUALMEM,532)@22
memoryC2_uid404_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC2_uid404_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC2_uid404_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q;
memoryC2_uid404_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC2_uid404_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid404_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid404_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid404_tableGencosPiZ_lutmem_iq,
address_a => memoryC2_uid404_tableGencosPiZ_lutmem_aa,
data_a => memoryC2_uid404_tableGencosPiZ_lutmem_ia
);
memoryC2_uid404_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC2_uid404_tableGencosPiZ_lutmem_q <= memoryC2_uid404_tableGencosPiZ_lutmem_iq(12 downto 0);
--reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1(REG,632)@24
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q <= memoryC2_uid404_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPcosPiZ_uid87_fpSinCosXTest(BITSELECT,86)@21
zPcosPiZ_uid87_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(56 downto 0);
zPcosPiZ_uid87_fpSinCosXTest_b <= zPcosPiZ_uid87_fpSinCosXTest_in(56 downto 42);
--yT1_uid419_polyEvalcosPiZ(BITSELECT,418)@21
yT1_uid419_polyEvalcosPiZ_in <= zPcosPiZ_uid87_fpSinCosXTest_b;
yT1_uid419_polyEvalcosPiZ_b <= yT1_uid419_polyEvalcosPiZ_in(14 downto 2);
--reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0(REG,631)@21
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q <= yT1_uid419_polyEvalcosPiZ_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg(DELAY,1513)
ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q, xout => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a(DELAY,1125)@22
ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q, xout => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid508_pT1_uid420_polyEvalcosPiZ(MULT,507)@25
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a),14)) * SIGNED(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b);
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a <= (others => '0');
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b <= (others => '0');
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a <= ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b <= reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q <= prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ(BITSELECT,508)@28
prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in <= prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q;
prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in(25 downto 12);
--highBBits_uid422_polyEvalcosPiZ(BITSELECT,421)@28
highBBits_uid422_polyEvalcosPiZ_in <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b;
highBBits_uid422_polyEvalcosPiZ_b <= highBBits_uid422_polyEvalcosPiZ_in(13 downto 1);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a(DELAY,1256)@21
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => addr_uid83_fpSinCosXTest_b, xout => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0(REG,633)@24
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid402_tableGencosPiZ_lutmem(DUALMEM,531)@25
memoryC1_uid402_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC1_uid402_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC1_uid402_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q;
memoryC1_uid402_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC1_uid402_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid402_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid402_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid402_tableGencosPiZ_lutmem_iq,
address_a => memoryC1_uid402_tableGencosPiZ_lutmem_aa,
data_a => memoryC1_uid402_tableGencosPiZ_lutmem_ia
);
memoryC1_uid402_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC1_uid402_tableGencosPiZ_lutmem_q <= memoryC1_uid402_tableGencosPiZ_lutmem_iq(20 downto 0);
--reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0(REG,634)@27
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q <= memoryC1_uid402_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid423_polyEvalcosPiZ(ADD,422)@28
sumAHighB_uid423_polyEvalcosPiZ_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q(20)) & reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q);
sumAHighB_uid423_polyEvalcosPiZ_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid422_polyEvalcosPiZ_b(12)) & highBBits_uid422_polyEvalcosPiZ_b);
sumAHighB_uid423_polyEvalcosPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid423_polyEvalcosPiZ_a) + SIGNED(sumAHighB_uid423_polyEvalcosPiZ_b));
sumAHighB_uid423_polyEvalcosPiZ_q <= sumAHighB_uid423_polyEvalcosPiZ_o(21 downto 0);
--lowRangeB_uid421_polyEvalcosPiZ(BITSELECT,420)@28
lowRangeB_uid421_polyEvalcosPiZ_in <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b(0 downto 0);
lowRangeB_uid421_polyEvalcosPiZ_b <= lowRangeB_uid421_polyEvalcosPiZ_in(0 downto 0);
--s1_uid421_uid424_polyEvalcosPiZ(BITJOIN,423)@28
s1_uid421_uid424_polyEvalcosPiZ_q <= sumAHighB_uid423_polyEvalcosPiZ_q & lowRangeB_uid421_polyEvalcosPiZ_b;
--reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1(REG,636)@28
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q <= s1_uid421_uid424_polyEvalcosPiZ_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor(LOGICAL,1524)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q <= not (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a or ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b);
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top(CONSTANT,1520)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q <= "0100";
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp(LOGICAL,1521)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q <= "1" when ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a = ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b else "0";
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg(REG,1522)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena(REG,1525)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd(LOGICAL,1526)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b <= en;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a and ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b;
--reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0(REG,635)@21
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q <= zPcosPiZ_uid87_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg(DELAY,1514)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q, xout => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt(COUNTER,1516)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i = 3 THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i,3));
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg(REG,1517)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux(MUX,1518)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s <= en;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux: PROCESS (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s, ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q, ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem(DUALMEM,1515)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq,
address_a => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa,
data_a => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia
);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0 <= areset;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq(14 downto 0);
--prodXY_uid511_pT2_uid426_polyEvalcosPiZ(MULT,510)@29
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a),16)) * SIGNED(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b);
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a <= (others => '0');
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b <= (others => '0');
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b <= reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q <= prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ(BITSELECT,511)@32
prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in <= prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q;
prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in(37 downto 14);
--highBBits_uid428_polyEvalcosPiZ(BITSELECT,427)@32
highBBits_uid428_polyEvalcosPiZ_in <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b;
highBBits_uid428_polyEvalcosPiZ_b <= highBBits_uid428_polyEvalcosPiZ_in(23 downto 2);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor(LOGICAL,1577)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q <= not (ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a or ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena(REG,1578)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q = "1") THEN
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd(LOGICAL,1579)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b <= en;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a and ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b;
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg(DELAY,1567)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addr_uid83_fpSinCosXTest_b, xout => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem(DUALMEM,1568)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq,
address_a => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa,
data_a => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia
);
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0(REG,637)@28
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid400_tableGencosPiZ_lutmem(DUALMEM,530)@29
memoryC0_uid400_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC0_uid400_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC0_uid400_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q;
memoryC0_uid400_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC0_uid400_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid400_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid400_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid400_tableGencosPiZ_lutmem_iq,
address_a => memoryC0_uid400_tableGencosPiZ_lutmem_aa,
data_a => memoryC0_uid400_tableGencosPiZ_lutmem_ia
);
memoryC0_uid400_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC0_uid400_tableGencosPiZ_lutmem_q <= memoryC0_uid400_tableGencosPiZ_lutmem_iq(29 downto 0);
--reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0(REG,638)@31
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q <= memoryC0_uid400_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid429_polyEvalcosPiZ(ADD,428)@32
sumAHighB_uid429_polyEvalcosPiZ_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q(29)) & reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q);
sumAHighB_uid429_polyEvalcosPiZ_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid428_polyEvalcosPiZ_b(21)) & highBBits_uid428_polyEvalcosPiZ_b);
sumAHighB_uid429_polyEvalcosPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid429_polyEvalcosPiZ_a) + SIGNED(sumAHighB_uid429_polyEvalcosPiZ_b));
sumAHighB_uid429_polyEvalcosPiZ_q <= sumAHighB_uid429_polyEvalcosPiZ_o(30 downto 0);
--lowRangeB_uid427_polyEvalcosPiZ(BITSELECT,426)@32
lowRangeB_uid427_polyEvalcosPiZ_in <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b(1 downto 0);
lowRangeB_uid427_polyEvalcosPiZ_b <= lowRangeB_uid427_polyEvalcosPiZ_in(1 downto 0);
--s2_uid427_uid430_polyEvalcosPiZ(BITJOIN,429)@32
s2_uid427_uid430_polyEvalcosPiZ_q <= sumAHighB_uid429_polyEvalcosPiZ_q & lowRangeB_uid427_polyEvalcosPiZ_b;
--polyEvalSigcosPiZ_uid89_fpSinCosXTest(BITSELECT,88)@32
polyEvalSigcosPiZ_uid89_fpSinCosXTest_in <= s2_uid427_uid430_polyEvalcosPiZ_q(30 downto 0);
polyEvalSigcosPiZ_uid89_fpSinCosXTest_b <= polyEvalSigcosPiZ_uid89_fpSinCosXTest_in(30 downto 5);
--reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1(REG,640)@32
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q <= polyEvalSigcosPiZ_uid89_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor(LOGICAL,1590)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q <= not (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a or ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b);
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top(CONSTANT,1586)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q <= "010";
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp(LOGICAL,1587)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q <= "1" when ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a = ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b else "0";
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg(REG,1588)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena(REG,1591)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd(LOGICAL,1592)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b <= en;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a and ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b;
--LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest(BITSELECT,388)@27
LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q(63 downto 0);
LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in(63 downto 0);
--leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest(BITJOIN,389)@27
leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b & GND_q;
--cstZmwFRRPwSM1_uid52_fpSinCosXTest(CONSTANT,51)
cstZmwFRRPwSM1_uid52_fpSinCosXTest_q <= "00000000000000000000000000000000000000000000000000000000000000000";
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor(LOGICAL,1455)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q <= not (ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a or ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b);
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena(REG,1456)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q = "1") THEN
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd(LOGICAL,1457)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b <= en;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a and ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b;
--X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest(BITSELECT,359)@21
X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(32 downto 0);
X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b <= X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in(32 downto 0);
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg(DELAY,1447)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem(DUALMEM,1448)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 33,
widthad_a => 1,
numwords_a => 2,
width_b => 33,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia
);
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq(32 downto 0);
--leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest(BITJOIN,360)@25
leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor(LOGICAL,1466)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q <= not (ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a or ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b);
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena(REG,1467)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q = "1") THEN
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd(LOGICAL,1468)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b <= en;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a and ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg(DELAY,1458)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => zCos_uid64_fpSinCosXTest_q, xout => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem(DUALMEM,1459)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 65,
widthad_a => 1,
numwords_a => 2,
width_b => 65,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia
);
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq(64 downto 0);
--zs_uid236_lzcZSin_uid66_fpSinCosXTest(CONSTANT,235)
zs_uid236_lzcZSin_uid66_fpSinCosXTest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--rVStage_uid316_lzcZCos_uid69_fpSinCosXTest(BITSELECT,315)@21
rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q;
rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in(64 downto 1);
--vCount_uid317_lzcZCos_uid69_fpSinCosXTest(LOGICAL,316)@21
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid236_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g(DELAY,985)@22
ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid319_lzcZCos_uid69_fpSinCosXTest(BITSELECT,318)@21
vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(0 downto 0);
vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in(0 downto 0);
--ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b(DELAY,943)@21
ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid239_lzcZSin_uid66_fpSinCosXTest(CONSTANT,238)
mO_uid239_lzcZSin_uid66_fpSinCosXTest_q <= "111111111111111111111111111111111111111111111111111111111111111";
--cStage_uid320_lzcZCos_uid69_fpSinCosXTest(BITJOIN,319)@22
cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q <= ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q & mO_uid239_lzcZSin_uid66_fpSinCosXTest_q;
--ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c(DELAY,945)@21
ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid322_lzcZCos_uid69_fpSinCosXTest(MUX,321)@22
vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid322_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s, en, ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q, cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid324_lzcZCos_uid69_fpSinCosXTest(BITSELECT,323)@22
rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in(63 downto 32);
--vCount_uid325_lzcZCos_uid69_fpSinCosXTest(LOGICAL,324)@22
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f(DELAY,984)@23
ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid326_lzcZCos_uid69_fpSinCosXTest(BITSELECT,325)@22
vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q(31 downto 0);
vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in(31 downto 0);
--ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d(DELAY,952)@22
ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c(DELAY,951)@22
ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid328_lzcZCos_uid69_fpSinCosXTest(MUX,327)@23
vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid328_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s, en, ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q, ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q)
BEGIN
CASE vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q;
WHEN OTHERS => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid330_lzcZCos_uid69_fpSinCosXTest(BITSELECT,329)@23
rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in(31 downto 16);
--vCount_uid331_lzcZCos_uid69_fpSinCosXTest(LOGICAL,330)@23
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b else "0";
--reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4(REG,622)@23
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q <= vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e(DELAY,983)@24
ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid332_lzcZCos_uid69_fpSinCosXTest(BITSELECT,331)@23
vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q(15 downto 0);
vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in(15 downto 0);
--vStagei_uid334_lzcZCos_uid69_fpSinCosXTest(MUX,333)@23
vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid334_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s, en, rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b, vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b;
WHEN "1" => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid336_lzcZCos_uid69_fpSinCosXTest(BITSELECT,335)@23
rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in(15 downto 8);
--reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1(REG,617)@23
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q <= rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid337_lzcZCos_uid69_fpSinCosXTest(LOGICAL,336)@24
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a <= reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q;
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b else "0";
--ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d(DELAY,982)@24
ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid338_lzcZCos_uid69_fpSinCosXTest(BITSELECT,337)@23
vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q(7 downto 0);
vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3(REG,619)@23
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q <= vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid340_lzcZCos_uid69_fpSinCosXTest(MUX,339)@24
vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid340_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s, en, reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q, reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid342_lzcZCos_uid69_fpSinCosXTest(BITSELECT,341)@24
rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in(7 downto 4);
--vCount_uid343_lzcZCos_uid69_fpSinCosXTest(LOGICAL,342)@24
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid344_lzcZCos_uid69_fpSinCosXTest(BITSELECT,343)@24
vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q(3 downto 0);
vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in(3 downto 0);
--reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3(REG,621)@24
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q <= vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2(REG,620)@24
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid346_lzcZCos_uid69_fpSinCosXTest(MUX,345)@25
vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid346_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s, en, reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q, reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid348_lzcZCos_uid69_fpSinCosXTest(BITSELECT,347)@25
rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in(3 downto 2);
--vCount_uid349_lzcZCos_uid69_fpSinCosXTest(LOGICAL,348)@25
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b else "0";
--vStage_uid350_lzcZCos_uid69_fpSinCosXTest(BITSELECT,349)@25
vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q(1 downto 0);
vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in(1 downto 0);
--vStagei_uid352_lzcZCos_uid69_fpSinCosXTest(MUX,351)@25
vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid352_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s, en, rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b, vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b;
WHEN "1" => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid354_lzcZCos_uid69_fpSinCosXTest(BITSELECT,353)@25
rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in(1 downto 1);
--vCount_uid355_lzcZCos_uid69_fpSinCosXTest(LOGICAL,354)@25
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b <= GND_q;
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b else "0";
--r_uid356_lzcZCos_uid69_fpSinCosXTest(BITJOIN,355)@25
r_uid356_lzcZCos_uid69_fpSinCosXTest_q <= ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q & ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q & ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q & ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q & vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q & vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q & vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q;
--leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest(BITSELECT,363)@25
leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q;
leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in(6 downto 5);
--leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest(MUX,364)@25
leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s <= leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b;
leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s, en, ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest(BITSELECT,372)@25
LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(40 downto 0);
LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in(40 downto 0);
--leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest(CONSTANT,292)
leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q <= "000000000000000000000000";
--leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest(BITJOIN,373)@25
leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b & leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5(REG,627)@25
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest(BITSELECT,369)@25
LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(48 downto 0);
LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in(48 downto 0);
--leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest(BITJOIN,370)@25
leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4(REG,626)@25
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest(BITSELECT,366)@25
LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(56 downto 0);
LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in(56 downto 0);
--leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest(BITJOIN,367)@25
leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3(REG,625)@25
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2(REG,624)@25
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest(BITSELECT,374)@25
leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1(REG,623)@25
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q <= leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest(MUX,375)@26
leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s <= reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q;
leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s, en, reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest(BITSELECT,383)@26
LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(58 downto 0);
LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1009)@26
ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest(CONSTANT,303)
leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q <= "000000";
--leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest(BITJOIN,384)@27
leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q;
--LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest(BITSELECT,380)@26
LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(60 downto 0);
LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1007)@26
ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest(BITJOIN,381)@27
leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest(BITSELECT,377)@26
LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(62 downto 0);
LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in(62 downto 0);
--ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1005)@26
ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest(BITJOIN,378)@27
leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2(REG,629)@26
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest(BITSELECT,385)@25
leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1(REG,628)@25
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q <= leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1011)@26
ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest(MUX,386)@27
leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s <= ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q;
leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s, en, reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest(BITSELECT,390)@25
leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1019)@25
ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest(MUX,391)@27
leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s <= ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q;
leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s, en, leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "0" => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "1" => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--pCos_uid77_fpSinCosXTest(BITSELECT,76)@27
pCos_uid77_fpSinCosXTest_in <= leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q;
pCos_uid77_fpSinCosXTest_b <= pCos_uid77_fpSinCosXTest_in(64 downto 39);
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg(DELAY,1580)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => pCos_uid77_fpSinCosXTest_b, xout => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt(COUNTER,1582)
-- every=1, low=0, high=2, step=1, init=1
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i = 1 THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i - 2;
ELSE
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i,2));
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg(REG,1583)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux(MUX,1584)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s <= en;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux: PROCESS (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s, ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q, ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q)
BEGIN
CASE ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s IS
WHEN "0" => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q;
WHEN "1" => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem(DUALMEM,1581)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 2,
numwords_a => 3,
width_b => 26,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq,
address_a => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa,
data_a => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia
);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0 <= areset;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq(25 downto 0);
--reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0(REG,639)@32
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--mulCos_uid105_fpSinCosXTest(MULT,104)@33
mulCos_uid105_fpSinCosXTest_pr <= UNSIGNED(mulCos_uid105_fpSinCosXTest_a) * UNSIGNED(mulCos_uid105_fpSinCosXTest_b);
mulCos_uid105_fpSinCosXTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulCos_uid105_fpSinCosXTest_a <= (others => '0');
mulCos_uid105_fpSinCosXTest_b <= (others => '0');
mulCos_uid105_fpSinCosXTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulCos_uid105_fpSinCosXTest_a <= reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q;
mulCos_uid105_fpSinCosXTest_b <= reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q;
mulCos_uid105_fpSinCosXTest_s1 <= STD_LOGIC_VECTOR(mulCos_uid105_fpSinCosXTest_pr);
END IF;
END IF;
END PROCESS;
mulCos_uid105_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulCos_uid105_fpSinCosXTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulCos_uid105_fpSinCosXTest_q <= mulCos_uid105_fpSinCosXTest_s1;
END IF;
END IF;
END PROCESS;
--normBitCos_uid106_fpSinCosXTest(BITSELECT,105)@36
normBitCos_uid106_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q;
normBitCos_uid106_fpSinCosXTest_b <= normBitCos_uid106_fpSinCosXTest_in(51 downto 51);
--cosRndOp_uid112_uid113_fpSinCosXTest(BITJOIN,112)@36
cosRndOp_uid112_uid113_fpSinCosXTest_q <= normBitCos_uid106_fpSinCosXTest_b & cstAllZWF_uid7_fpSinCosXTest_q & VCC_q;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor(LOGICAL,1296)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q <= not (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a or ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b);
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top(CONSTANT,1292)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q <= "0110";
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp(LOGICAL,1293)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q <= "1" when ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a = ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b else "0";
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg(REG,1294)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena(REG,1297)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd(LOGICAL,1298)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b <= en;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a and ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b;
--reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1(REG,641)@25
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg(DELAY,1286)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q, xout => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt(COUNTER,1288)
-- every=1, low=0, high=6, step=1, init=1
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i = 5 THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i - 6;
ELSE
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i,3));
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg(REG,1289)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux(MUX,1290)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s <= en;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux: PROCESS (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s, ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q, ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem(DUALMEM,1287)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 7,
width_b => 7,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia
);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq(6 downto 0);
--expHardCase_uid78_fpSinCosXTest(SUB,77)@35
expHardCase_uid78_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expHardCase_uid78_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q);
expHardCase_uid78_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid78_fpSinCosXTest_a) - UNSIGNED(expHardCase_uid78_fpSinCosXTest_b));
expHardCase_uid78_fpSinCosXTest_q <= expHardCase_uid78_fpSinCosXTest_o(8 downto 0);
--expPCos_uid79_fpSinCosXTest(BITSELECT,78)@35
expPCos_uid79_fpSinCosXTest_in <= expHardCase_uid78_fpSinCosXTest_q(7 downto 0);
expPCos_uid79_fpSinCosXTest_b <= expPCos_uid79_fpSinCosXTest_in(7 downto 0);
--reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1(REG,642)@35
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q <= expPCos_uid79_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--fracRCosPreRndHigh_uid108_fpSinCosXTest(BITSELECT,107)@36
fracRCosPreRndHigh_uid108_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q(50 downto 0);
fracRCosPreRndHigh_uid108_fpSinCosXTest_b <= fracRCosPreRndHigh_uid108_fpSinCosXTest_in(50 downto 27);
--fracRCosPreRndLow_uid109_fpSinCosXTest(BITSELECT,108)@36
fracRCosPreRndLow_uid109_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q(49 downto 0);
fracRCosPreRndLow_uid109_fpSinCosXTest_b <= fracRCosPreRndLow_uid109_fpSinCosXTest_in(49 downto 26);
--fracRCosPreRnd_uid110_fpSinCosXTest(MUX,109)@36
fracRCosPreRnd_uid110_fpSinCosXTest_s <= normBitCos_uid106_fpSinCosXTest_b;
fracRCosPreRnd_uid110_fpSinCosXTest: PROCESS (fracRCosPreRnd_uid110_fpSinCosXTest_s, en, fracRCosPreRndLow_uid109_fpSinCosXTest_b, fracRCosPreRndHigh_uid108_fpSinCosXTest_b)
BEGIN
CASE fracRCosPreRnd_uid110_fpSinCosXTest_s IS
WHEN "0" => fracRCosPreRnd_uid110_fpSinCosXTest_q <= fracRCosPreRndLow_uid109_fpSinCosXTest_b;
WHEN "1" => fracRCosPreRnd_uid110_fpSinCosXTest_q <= fracRCosPreRndHigh_uid108_fpSinCosXTest_b;
WHEN OTHERS => fracRCosPreRnd_uid110_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracRCosPreRnd_uid111_uid111_fpSinCosXTest(BITJOIN,110)@36
expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q <= reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q & fracRCosPreRnd_uid110_fpSinCosXTest_q;
--expFracRCos_uid114_fpSinCosXTest(ADD,113)@36
expFracRCos_uid114_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q);
expFracRCos_uid114_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00000000" & cosRndOp_uid112_uid113_fpSinCosXTest_q);
expFracRCos_uid114_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRCos_uid114_fpSinCosXTest_a) + UNSIGNED(expFracRCos_uid114_fpSinCosXTest_b));
expFracRCos_uid114_fpSinCosXTest_q <= expFracRCos_uid114_fpSinCosXTest_o(32 downto 0);
--expRCompSin_uid116_fpSinCosXTest(BITSELECT,115)@36
expRCompSin_uid116_fpSinCosXTest_in <= expFracRCos_uid114_fpSinCosXTest_q(31 downto 0);
expRCompSin_uid116_fpSinCosXTest_b <= expRCompSin_uid116_fpSinCosXTest_in(31 downto 24);
--reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2(REG,646)@36
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q <= expRCompSin_uid116_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor(LOGICAL,1385)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q <= not (ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a or ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top(CONSTANT,1305)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q <= "01101";
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp(LOGICAL,1306)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q <= "1" when ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a = ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b else "0";
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg(REG,1307)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena(REG,1386)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q = "1") THEN
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd(LOGICAL,1387)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b <= en;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a and ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b;
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a(DELAY,745)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c(DELAY,783)@16
ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => cosXIsOneXRR_uid42_fpSinCosXTest_n, xout => ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--InvCosXIsOneXRR_uid136_fpSinCosXTest(LOGICAL,135)@16
InvCosXIsOneXRR_uid136_fpSinCosXTest_a <= cosXIsOneXRR_uid42_fpSinCosXTest_n;
InvCosXIsOneXRR_uid136_fpSinCosXTest_q <= not InvCosXIsOneXRR_uid136_fpSinCosXTest_a;
--ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c(DELAY,773)@16
ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => InvCosXIsOneXRR_uid136_fpSinCosXTest_q, xout => ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a(DELAY,755)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsX_uid127_fpSinCosXTest(LOGICAL,126)@18
InvSinXIsX_uid127_fpSinCosXTest_a <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q;
InvSinXIsX_uid127_fpSinCosXTest_q <= not InvSinXIsX_uid127_fpSinCosXTest_a;
--ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b(DELAY,772)@18
ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => InvSinXIsX_uid127_fpSinCosXTest_q, xout => ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--half_uid53_fpSinCosXTest(BITJOIN,52)@19
half_uid53_fpSinCosXTest_q <= VCC_q & cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
--yIsHalf_uid54_fpSinCosXTest(LOGICAL,53)@19
yIsHalf_uid54_fpSinCosXTest_a <= reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q;
yIsHalf_uid54_fpSinCosXTest_b <= half_uid53_fpSinCosXTest_q;
yIsHalf_uid54_fpSinCosXTest_q <= "1" when yIsHalf_uid54_fpSinCosXTest_a = yIsHalf_uid54_fpSinCosXTest_b else "0";
--yHalfCosXNotOne_uid138_fpSinCosXTest(LOGICAL,137)@19
yHalfCosXNotOne_uid138_fpSinCosXTest_a <= yIsHalf_uid54_fpSinCosXTest_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_b <= ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_c <= ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_q <= yHalfCosXNotOne_uid138_fpSinCosXTest_a and yHalfCosXNotOne_uid138_fpSinCosXTest_b and yHalfCosXNotOne_uid138_fpSinCosXTest_c;
--ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b(DELAY,744)@0
ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => exc_I_uid15_fpSinCosXTest_q, xout => ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a(DELAY,743)@0
ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => exc_N_uid17_fpSinCosXTest_q, xout => ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRNaN_uid117_fpSinCosXTest(LOGICAL,116)@19
excRNaN_uid117_fpSinCosXTest_a <= ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q;
excRNaN_uid117_fpSinCosXTest_b <= ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q;
excRNaN_uid117_fpSinCosXTest_q <= excRNaN_uid117_fpSinCosXTest_a or excRNaN_uid117_fpSinCosXTest_b;
--join_uid143_fpSinCosXTest(BITJOIN,142)@19
join_uid143_fpSinCosXTest_q <= ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q & yHalfCosXNotOne_uid138_fpSinCosXTest_q & excRNaN_uid117_fpSinCosXTest_q;
--expSelBitsCos_uid144_fpSinCosXTest(BITJOIN,143)@19
expSelBitsCos_uid144_fpSinCosXTest_q <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q & join_uid143_fpSinCosXTest_q;
--reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0(REG,645)@19
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q <= expSelBitsCos_uid144_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--expSelectorCos_uid145_fpSinCosXTest(LOOKUP,144)@20
expSelectorCos_uid145_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSelectorCos_uid145_fpSinCosXTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q) IS
WHEN "0000" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "0001" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "0010" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "0011" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "0100" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "0101" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "0110" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "0111" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "1000" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "1001" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "1010" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "1011" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "1100" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "1101" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "1110" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "1111" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN OTHERS =>
expSelectorCos_uid145_fpSinCosXTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg(DELAY,1375)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => expSelectorCos_uid145_fpSinCosXTest_q, xout => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt(COUNTER,1301)
-- every=1, low=0, high=13, step=1, init=1
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i = 12 THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i - 13;
ELSE
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg(REG,1302)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux(MUX,1303)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s, ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q, ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem(DUALMEM,1376)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia
);
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq(1 downto 0);
--expRPostExcCos_uid147_fpSinCosXTest(MUX,146)@37
expRPostExcCos_uid147_fpSinCosXTest_s <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q;
expRPostExcCos_uid147_fpSinCosXTest: PROCESS (expRPostExcCos_uid147_fpSinCosXTest_s, en, reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q, cstBias_uid22_fpSinCosXTest_q, cstAllZWE_uid8_fpSinCosXTest_q, cstAllOWE_uid6_fpSinCosXTest_q)
BEGIN
CASE expRPostExcCos_uid147_fpSinCosXTest_s IS
WHEN "00" => expRPostExcCos_uid147_fpSinCosXTest_q <= reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q;
WHEN "01" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstBias_uid22_fpSinCosXTest_q;
WHEN "10" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstAllZWE_uid8_fpSinCosXTest_q;
WHEN "11" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstAllOWE_uid6_fpSinCosXTest_q;
WHEN OTHERS => expRPostExcCos_uid147_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstNaNwF_uid32_fpSinCosXTest(CONSTANT,31)
cstNaNwF_uid32_fpSinCosXTest_q <= "00000000000000000000001";
--fracRCompCos_uid115_fpSinCosXTest(BITSELECT,114)@36
fracRCompCos_uid115_fpSinCosXTest_in <= expFracRCos_uid114_fpSinCosXTest_q(23 downto 0);
fracRCompCos_uid115_fpSinCosXTest_b <= fracRCompCos_uid115_fpSinCosXTest_in(23 downto 1);
--reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2(REG,644)@36
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q <= fracRCompCos_uid115_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor(LOGICAL,1372)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q <= not (ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a or ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b);
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena(REG,1373)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q = "1") THEN
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd(LOGICAL,1374)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b <= en;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a and ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b;
--reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1(REG,613)@19
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q <= excRNaN_uid117_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3(REG,612)@19
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q <= ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q;
END IF;
END IF;
END PROCESS;
--reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2(REG,611)@19
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q;
END IF;
END IF;
END PROCESS;
--reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1(REG,610)@19
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q <= yHalfCosXNotOne_uid138_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--rZOrOne_uid140_fpSinCosXTest(LOGICAL,139)@20
rZOrOne_uid140_fpSinCosXTest_a <= reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q;
rZOrOne_uid140_fpSinCosXTest_b <= reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q;
rZOrOne_uid140_fpSinCosXTest_c <= reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q;
rZOrOne_uid140_fpSinCosXTest_q <= rZOrOne_uid140_fpSinCosXTest_a or rZOrOne_uid140_fpSinCosXTest_b or rZOrOne_uid140_fpSinCosXTest_c;
--join_uid141_fpSinCosXTest(BITJOIN,140)@20
join_uid141_fpSinCosXTest_q <= reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q & rZOrOne_uid140_fpSinCosXTest_q;
--reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1(REG,643)@20
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q <= join_uid141_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg(DELAY,1362)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q, xout => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem(DUALMEM,1363)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia
);
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq(1 downto 0);
--fracRPostExcCos_uid142_fpSinCosXTest(MUX,141)@37
fracRPostExcCos_uid142_fpSinCosXTest_s <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q;
fracRPostExcCos_uid142_fpSinCosXTest: PROCESS (fracRPostExcCos_uid142_fpSinCosXTest_s, en, reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q, cstAllZWF_uid7_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q)
BEGIN
CASE fracRPostExcCos_uid142_fpSinCosXTest_s IS
WHEN "00" => fracRPostExcCos_uid142_fpSinCosXTest_q <= reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q;
WHEN "01" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstAllZWF_uid7_fpSinCosXTest_q;
WHEN "10" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN "11" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN OTHERS => fracRPostExcCos_uid142_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpCos_uid162_fpSinCosXTest(BITJOIN,161)@37
fpCos_uid162_fpSinCosXTest_q <= ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q & expRPostExcCos_uid147_fpSinCosXTest_q & fracRPostExcCos_uid142_fpSinCosXTest_q;
--cstBiasMwShiftM2_uid25_fpSinCosXTest(CONSTANT,24)
cstBiasMwShiftM2_uid25_fpSinCosXTest_q <= "01110001";
--sinXIsXRR_uid41_fpSinCosXTest(COMPARE,40)@16
sinXIsXRR_uid41_fpSinCosXTest_cin <= GND_q;
sinXIsXRR_uid41_fpSinCosXTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid25_fpSinCosXTest_q) & '0';
sinXIsXRR_uid41_fpSinCosXTest_b <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q) & sinXIsXRR_uid41_fpSinCosXTest_cin(0);
sinXIsXRR_uid41_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(sinXIsXRR_uid41_fpSinCosXTest_a) - SIGNED(sinXIsXRR_uid41_fpSinCosXTest_b));
sinXIsXRR_uid41_fpSinCosXTest_n(0) <= not sinXIsXRR_uid41_fpSinCosXTest_o(11);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a(DELAY,756)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsXRR_uid128_fpSinCosXTest(LOGICAL,127)@18
InvSinXIsXRR_uid128_fpSinCosXTest_a <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q;
InvSinXIsXRR_uid128_fpSinCosXTest_q <= not InvSinXIsXRR_uid128_fpSinCosXTest_a;
--signComp_uid129_fpSinCosXTest(LOGICAL,128)@18
signComp_uid129_fpSinCosXTest_a <= InvSinXIsXRR_uid128_fpSinCosXTest_q;
signComp_uid129_fpSinCosXTest_b <= InvSinXIsX_uid127_fpSinCosXTest_q;
signComp_uid129_fpSinCosXTest_c <= intXParity_uid49_fpSinCosXTest_b;
signComp_uid129_fpSinCosXTest_q <= signComp_uid129_fpSinCosXTest_a and signComp_uid129_fpSinCosXTest_b and signComp_uid129_fpSinCosXTest_c;
--signX_uid37_fpSinCosXTest(BITSELECT,36)@0
signX_uid37_fpSinCosXTest_in <= a;
signX_uid37_fpSinCosXTest_b <= signX_uid37_fpSinCosXTest_in(31 downto 31);
--ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a(DELAY,760)@0
ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => signX_uid37_fpSinCosXTest_b, xout => ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid130_fpSinCosXTest(LOGICAL,129)@18
signR_uid130_fpSinCosXTest_a <= ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q;
signR_uid130_fpSinCosXTest_b <= signComp_uid129_fpSinCosXTest_q;
signR_uid130_fpSinCosXTest_q <= signR_uid130_fpSinCosXTest_a xor signR_uid130_fpSinCosXTest_b;
--ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c(DELAY,766)@18
ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => signR_uid130_fpSinCosXTest_q, xout => ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--signRSinFull_uid133_fpSinCosXTest(LOGICAL,132)@20
signRSinFull_uid133_fpSinCosXTest_a <= InvExc_N_uid132_fpSinCosXTest_q;
signRSinFull_uid133_fpSinCosXTest_b <= InvExc_I_uid131_fpSinCosXTest_q;
signRSinFull_uid133_fpSinCosXTest_c <= ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q;
signRSinFull_uid133_fpSinCosXTest_q_i <= signRSinFull_uid133_fpSinCosXTest_a and signRSinFull_uid133_fpSinCosXTest_b and signRSinFull_uid133_fpSinCosXTest_c;
signRSinFull_uid133_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRSinFull_uid133_fpSinCosXTest_q, xin => signRSinFull_uid133_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c(DELAY,769)@21
ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signRSinFull_uid133_fpSinCosXTest_q, xout => ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor(LOGICAL,1359)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q <= not (ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a or ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b);
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top(CONSTANT,1342)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q <= "0100010";
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp(LOGICAL,1343)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q <= "1" when ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a = ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b else "0";
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg(REG,1344)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena(REG,1360)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q = "1") THEN
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd(LOGICAL,1361)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b <= en;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a and ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg(DELAY,1349)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => exp_uid9_fpSinCosXTest_b, xout => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt(COUNTER,1338)
-- every=1, low=0, high=34, step=1, init=1
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i = 33 THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i - 34;
ELSE
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i,6));
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg(REG,1339)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux(MUX,1340)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem(DUALMEM,1350)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 6,
numwords_a => 35,
width_b => 8,
widthad_b => 6,
numwords_b => 35,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia
);
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a(DELAY,1228)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1(REG,605)@35
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor(LOGICAL,1309)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q <= not (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a or ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena(REG,1310)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd(LOGICAL,1311)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b <= en;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a and ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b;
--oFracXRRSmallXRR_uid90_fpSinCosXTest(BITSELECT,89)@16
oFracXRRSmallXRR_uid90_fpSinCosXTest_in <= oFracXRR_uid43_uid43_fpSinCosXTest_q;
oFracXRRSmallXRR_uid90_fpSinCosXTest_b <= oFracXRRSmallXRR_uid90_fpSinCosXTest_in(53 downto 28);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg(DELAY,1299)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => oFracXRRSmallXRR_uid90_fpSinCosXTest_b, xout => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem(DUALMEM,1300)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 4,
numwords_a => 14,
width_b => 26,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia
);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq(25 downto 0);
--reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1(REG,577)@20
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
END IF;
END IF;
END PROCESS;
--zSin_uid60_fpSinCosXTest(MUX,59)@21
zSin_uid60_fpSinCosXTest_s <= reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q;
zSin_uid60_fpSinCosXTest: PROCESS (zSin_uid60_fpSinCosXTest_s, en, reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q, reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q)
BEGIN
CASE zSin_uid60_fpSinCosXTest_s IS
WHEN "0" => zSin_uid60_fpSinCosXTest_q <= reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q;
WHEN "1" => zSin_uid60_fpSinCosXTest_q <= reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q;
WHEN OTHERS => zSin_uid60_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--addr_uid81_fpSinCosXTest(BITSELECT,80)@21
addr_uid81_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q;
addr_uid81_fpSinCosXTest_b <= addr_uid81_fpSinCosXTest_in(64 downto 57);
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0(REG,595)@21
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q <= addr_uid81_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid398_tableGensinPiZ_lutmem(DUALMEM,529)@22
memoryC2_uid398_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC2_uid398_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC2_uid398_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q;
memoryC2_uid398_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC2_uid398_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid398_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid398_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid398_tableGensinPiZ_lutmem_iq,
address_a => memoryC2_uid398_tableGensinPiZ_lutmem_aa,
data_a => memoryC2_uid398_tableGensinPiZ_lutmem_ia
);
memoryC2_uid398_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC2_uid398_tableGensinPiZ_lutmem_q <= memoryC2_uid398_tableGensinPiZ_lutmem_iq(12 downto 0);
--reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1(REG,597)@24
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q <= memoryC2_uid398_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPsinPiZ_uid84_fpSinCosXTest(BITSELECT,83)@21
zPsinPiZ_uid84_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(56 downto 0);
zPsinPiZ_uid84_fpSinCosXTest_b <= zPsinPiZ_uid84_fpSinCosXTest_in(56 downto 42);
--yT1_uid406_polyEvalsinPiZ(BITSELECT,405)@21
yT1_uid406_polyEvalsinPiZ_in <= zPsinPiZ_uid84_fpSinCosXTest_b;
yT1_uid406_polyEvalsinPiZ_b <= yT1_uid406_polyEvalsinPiZ_in(14 downto 2);
--ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg(DELAY,1540)
ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => yT1_uid406_polyEvalsinPiZ_b, xout => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a(DELAY,1219)@21
ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q, xout => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0(REG,596)@24
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q <= ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid502_pT1_uid407_polyEvalsinPiZ(MULT,501)@25
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a),14)) * SIGNED(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b);
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a <= (others => '0');
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b <= (others => '0');
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a <= reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b <= reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q <= prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ(BITSELECT,502)@28
prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in <= prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q;
prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in(25 downto 12);
--highBBits_uid409_polyEvalsinPiZ(BITSELECT,408)@28
highBBits_uid409_polyEvalsinPiZ_in <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b;
highBBits_uid409_polyEvalsinPiZ_b <= highBBits_uid409_polyEvalsinPiZ_in(13 downto 1);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a(DELAY,1221)@21
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => addr_uid81_fpSinCosXTest_b, xout => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0(REG,598)@24
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid396_tableGensinPiZ_lutmem(DUALMEM,528)@25
memoryC1_uid396_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC1_uid396_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC1_uid396_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q;
memoryC1_uid396_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC1_uid396_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid396_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid396_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid396_tableGensinPiZ_lutmem_iq,
address_a => memoryC1_uid396_tableGensinPiZ_lutmem_aa,
data_a => memoryC1_uid396_tableGensinPiZ_lutmem_ia
);
memoryC1_uid396_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC1_uid396_tableGensinPiZ_lutmem_q <= memoryC1_uid396_tableGensinPiZ_lutmem_iq(20 downto 0);
--reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0(REG,599)@27
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q <= memoryC1_uid396_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid410_polyEvalsinPiZ(ADD,409)@28
sumAHighB_uid410_polyEvalsinPiZ_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q(20)) & reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q);
sumAHighB_uid410_polyEvalsinPiZ_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid409_polyEvalsinPiZ_b(12)) & highBBits_uid409_polyEvalsinPiZ_b);
sumAHighB_uid410_polyEvalsinPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid410_polyEvalsinPiZ_a) + SIGNED(sumAHighB_uid410_polyEvalsinPiZ_b));
sumAHighB_uid410_polyEvalsinPiZ_q <= sumAHighB_uid410_polyEvalsinPiZ_o(21 downto 0);
--lowRangeB_uid408_polyEvalsinPiZ(BITSELECT,407)@28
lowRangeB_uid408_polyEvalsinPiZ_in <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b(0 downto 0);
lowRangeB_uid408_polyEvalsinPiZ_b <= lowRangeB_uid408_polyEvalsinPiZ_in(0 downto 0);
--s1_uid408_uid411_polyEvalsinPiZ(BITJOIN,410)@28
s1_uid408_uid411_polyEvalsinPiZ_q <= sumAHighB_uid410_polyEvalsinPiZ_q & lowRangeB_uid408_polyEvalsinPiZ_b;
--reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1(REG,601)@28
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q <= s1_uid408_uid411_polyEvalsinPiZ_q;
END IF;
END IF;
END PROCESS;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor(LOGICAL,1551)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q <= not (ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a or ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b);
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena(REG,1552)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q = "1") THEN
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd(LOGICAL,1553)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b <= en;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a and ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg(DELAY,1541)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => zPsinPiZ_uid84_fpSinCosXTest_b, xout => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem(DUALMEM,1542)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq,
address_a => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa,
data_a => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia
);
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0 <= areset;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq(14 downto 0);
--reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0(REG,600)@28
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid505_pT2_uid413_polyEvalsinPiZ(MULT,504)@29
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a),16)) * SIGNED(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b);
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a <= (others => '0');
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b <= (others => '0');
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a <= reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b <= reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q <= prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ(BITSELECT,505)@32
prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in <= prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q;
prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in(37 downto 14);
--highBBits_uid415_polyEvalsinPiZ(BITSELECT,414)@32
highBBits_uid415_polyEvalsinPiZ_in <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b;
highBBits_uid415_polyEvalsinPiZ_b <= highBBits_uid415_polyEvalsinPiZ_in(23 downto 2);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor(LOGICAL,1564)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q <= not (ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a or ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena(REG,1565)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q = "1") THEN
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd(LOGICAL,1566)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b <= en;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a and ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b;
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg(DELAY,1554)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addr_uid81_fpSinCosXTest_b, xout => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem(DUALMEM,1555)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq,
address_a => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa,
data_a => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia
);
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0(REG,602)@28
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid394_tableGensinPiZ_lutmem(DUALMEM,527)@29
memoryC0_uid394_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC0_uid394_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC0_uid394_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q;
memoryC0_uid394_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC0_uid394_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid394_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid394_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid394_tableGensinPiZ_lutmem_iq,
address_a => memoryC0_uid394_tableGensinPiZ_lutmem_aa,
data_a => memoryC0_uid394_tableGensinPiZ_lutmem_ia
);
memoryC0_uid394_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC0_uid394_tableGensinPiZ_lutmem_q <= memoryC0_uid394_tableGensinPiZ_lutmem_iq(29 downto 0);
--reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0(REG,603)@31
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q <= memoryC0_uid394_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid416_polyEvalsinPiZ(ADD,415)@32
sumAHighB_uid416_polyEvalsinPiZ_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q(29)) & reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q);
sumAHighB_uid416_polyEvalsinPiZ_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid415_polyEvalsinPiZ_b(21)) & highBBits_uid415_polyEvalsinPiZ_b);
sumAHighB_uid416_polyEvalsinPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid416_polyEvalsinPiZ_a) + SIGNED(sumAHighB_uid416_polyEvalsinPiZ_b));
sumAHighB_uid416_polyEvalsinPiZ_q <= sumAHighB_uid416_polyEvalsinPiZ_o(30 downto 0);
--lowRangeB_uid414_polyEvalsinPiZ(BITSELECT,413)@32
lowRangeB_uid414_polyEvalsinPiZ_in <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b(1 downto 0);
lowRangeB_uid414_polyEvalsinPiZ_b <= lowRangeB_uid414_polyEvalsinPiZ_in(1 downto 0);
--s2_uid414_uid417_polyEvalsinPiZ(BITJOIN,416)@32
s2_uid414_uid417_polyEvalsinPiZ_q <= sumAHighB_uid416_polyEvalsinPiZ_q & lowRangeB_uid414_polyEvalsinPiZ_b;
--polyEvalSigsinPiZ_uid86_fpSinCosXTest(BITSELECT,85)@32
polyEvalSigsinPiZ_uid86_fpSinCosXTest_in <= s2_uid414_uid417_polyEvalsinPiZ_q(30 downto 0);
polyEvalSigsinPiZ_uid86_fpSinCosXTest_b <= polyEvalSigsinPiZ_uid86_fpSinCosXTest_in(30 downto 5);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b(DELAY,708)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--multSinOp2_uid91_fpSinCosXTest(MUX,90)@32
multSinOp2_uid91_fpSinCosXTest_s <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q;
multSinOp2_uid91_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSinOp2_uid91_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE multSinOp2_uid91_fpSinCosXTest_s IS
WHEN "0" => multSinOp2_uid91_fpSinCosXTest_q <= polyEvalSigsinPiZ_uid86_fpSinCosXTest_b;
WHEN "1" => multSinOp2_uid91_fpSinCosXTest_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => multSinOp2_uid91_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor(LOGICAL,1320)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q <= not (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a or ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b);
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena(REG,1321)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd(LOGICAL,1322)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b <= en;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a and ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b;
--cPi_uid71_fpSinCosXTest(CONSTANT,70)
cPi_uid71_fpSinCosXTest_q <= "11001001000011111101101011";
--LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest(BITSELECT,309)@27
LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q(63 downto 0);
LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in(63 downto 0);
--leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest(BITJOIN,310)@27
leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b & GND_q;
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor(LOGICAL,1433)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q <= not (ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a or ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b);
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena(REG,1434)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q = "1") THEN
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd(LOGICAL,1435)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b <= en;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a and ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b;
--X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest(BITSELECT,280)@21
X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(32 downto 0);
X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b <= X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in(32 downto 0);
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg(DELAY,1425)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem(DUALMEM,1426)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 33,
widthad_a => 1,
numwords_a => 2,
width_b => 33,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia
);
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq(32 downto 0);
--leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest(BITJOIN,281)@25
leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor(LOGICAL,1444)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q <= not (ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a or ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b);
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena(REG,1445)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q = "1") THEN
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd(LOGICAL,1446)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b <= en;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a and ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg(DELAY,1436)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => zSin_uid60_fpSinCosXTest_q, xout => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem(DUALMEM,1437)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 65,
widthad_a => 1,
numwords_a => 2,
width_b => 65,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia
);
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq(64 downto 0);
--rVStage_uid237_lzcZSin_uid66_fpSinCosXTest(BITSELECT,236)@21
rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q;
rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in(64 downto 1);
--vCount_uid238_lzcZSin_uid66_fpSinCosXTest(LOGICAL,237)@21
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid236_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g(DELAY,903)@22
ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid240_lzcZSin_uid66_fpSinCosXTest(BITSELECT,239)@21
vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(0 downto 0);
vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in(0 downto 0);
--ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b(DELAY,861)@21
ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cStage_uid241_lzcZSin_uid66_fpSinCosXTest(BITJOIN,240)@22
cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q <= ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q & mO_uid239_lzcZSin_uid66_fpSinCosXTest_q;
--ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c(DELAY,863)@21
ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid243_lzcZSin_uid66_fpSinCosXTest(MUX,242)@22
vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid243_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s, en, ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q, cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid245_lzcZSin_uid66_fpSinCosXTest(BITSELECT,244)@22
rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in(63 downto 32);
--vCount_uid246_lzcZSin_uid66_fpSinCosXTest(LOGICAL,245)@22
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f(DELAY,902)@23
ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid247_lzcZSin_uid66_fpSinCosXTest(BITSELECT,246)@22
vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q(31 downto 0);
vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in(31 downto 0);
--ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d(DELAY,870)@22
ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c(DELAY,869)@22
ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid249_lzcZSin_uid66_fpSinCosXTest(MUX,248)@23
vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid249_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s, en, ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q, ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q)
BEGIN
CASE vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q;
WHEN OTHERS => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid251_lzcZSin_uid66_fpSinCosXTest(BITSELECT,250)@23
rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in(31 downto 16);
--vCount_uid252_lzcZSin_uid66_fpSinCosXTest(LOGICAL,251)@23
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b else "0";
--reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4(REG,585)@23
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q <= vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e(DELAY,901)@24
ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid253_lzcZSin_uid66_fpSinCosXTest(BITSELECT,252)@23
vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q(15 downto 0);
vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in(15 downto 0);
--vStagei_uid255_lzcZSin_uid66_fpSinCosXTest(MUX,254)@23
vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid255_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s, en, rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b, vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b;
WHEN "1" => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid257_lzcZSin_uid66_fpSinCosXTest(BITSELECT,256)@23
rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in(15 downto 8);
--reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1(REG,580)@23
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q <= rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid258_lzcZSin_uid66_fpSinCosXTest(LOGICAL,257)@24
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a <= reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q;
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b else "0";
--ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d(DELAY,900)@24
ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid259_lzcZSin_uid66_fpSinCosXTest(BITSELECT,258)@23
vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q(7 downto 0);
vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3(REG,582)@23
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q <= vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid261_lzcZSin_uid66_fpSinCosXTest(MUX,260)@24
vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid261_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s, en, reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q, reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid263_lzcZSin_uid66_fpSinCosXTest(BITSELECT,262)@24
rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in(7 downto 4);
--vCount_uid264_lzcZSin_uid66_fpSinCosXTest(LOGICAL,263)@24
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid265_lzcZSin_uid66_fpSinCosXTest(BITSELECT,264)@24
vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q(3 downto 0);
vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in(3 downto 0);
--reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3(REG,584)@24
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q <= vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2(REG,583)@24
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid267_lzcZSin_uid66_fpSinCosXTest(MUX,266)@25
vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid267_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s, en, reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q, reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid269_lzcZSin_uid66_fpSinCosXTest(BITSELECT,268)@25
rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in(3 downto 2);
--vCount_uid270_lzcZSin_uid66_fpSinCosXTest(LOGICAL,269)@25
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b else "0";
--vStage_uid271_lzcZSin_uid66_fpSinCosXTest(BITSELECT,270)@25
vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q(1 downto 0);
vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in(1 downto 0);
--vStagei_uid273_lzcZSin_uid66_fpSinCosXTest(MUX,272)@25
vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid273_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s, en, rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b, vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b;
WHEN "1" => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid275_lzcZSin_uid66_fpSinCosXTest(BITSELECT,274)@25
rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in(1 downto 1);
--vCount_uid276_lzcZSin_uid66_fpSinCosXTest(LOGICAL,275)@25
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b <= GND_q;
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b else "0";
--r_uid277_lzcZSin_uid66_fpSinCosXTest(BITJOIN,276)@25
r_uid277_lzcZSin_uid66_fpSinCosXTest_q <= ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q & ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q & ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q & ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q & vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q & vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q & vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q;
--leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest(BITSELECT,284)@25
leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q;
leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in(6 downto 5);
--leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest(MUX,285)@25
leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s <= leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b;
leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s, en, ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest(BITSELECT,293)@25
LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(40 downto 0);
LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in(40 downto 0);
--leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest(BITJOIN,294)@25
leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b & leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5(REG,590)@25
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest(BITSELECT,290)@25
LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(48 downto 0);
LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in(48 downto 0);
--leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest(BITJOIN,291)@25
leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4(REG,589)@25
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest(BITSELECT,287)@25
LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(56 downto 0);
LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in(56 downto 0);
--leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest(BITJOIN,288)@25
leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3(REG,588)@25
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2(REG,587)@25
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest(BITSELECT,295)@25
leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1(REG,586)@25
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q <= leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest(MUX,296)@26
leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s <= reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q;
leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s, en, reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest(BITSELECT,304)@26
LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(58 downto 0);
LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b(DELAY,927)@26
ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest(BITJOIN,305)@27
leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q;
--LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest(BITSELECT,301)@26
LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(60 downto 0);
LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b(DELAY,925)@26
ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest(BITJOIN,302)@27
leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest(BITSELECT,298)@26
LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(62 downto 0);
LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in(62 downto 0);
--ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b(DELAY,923)@26
ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest(BITJOIN,299)@27
leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2(REG,592)@26
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest(BITSELECT,306)@25
leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in(2 downto 1);
--ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a(DELAY,1214)@25
ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1(REG,591)@26
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q <= ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest(MUX,307)@27
leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s <= reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q;
leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s, en, reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest(BITSELECT,311)@25
leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b(DELAY,937)@25
ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest(MUX,312)@27
leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s <= ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q;
leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s, en, leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "0" => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "1" => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--pHigh_uid72_fpSinCosXTest(BITSELECT,71)@27
pHigh_uid72_fpSinCosXTest_in <= leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q;
pHigh_uid72_fpSinCosXTest_b <= pHigh_uid72_fpSinCosXTest_in(64 downto 39);
--reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2(REG,594)@27
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q <= pHigh_uid72_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a(DELAY,1216)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1(REG,593)@27
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--p_uid73_fpSinCosXTest(MUX,72)@28
p_uid73_fpSinCosXTest_s <= reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q;
p_uid73_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p_uid73_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE p_uid73_fpSinCosXTest_s IS
WHEN "0" => p_uid73_fpSinCosXTest_q <= reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q;
WHEN "1" => p_uid73_fpSinCosXTest_q <= cPi_uid71_fpSinCosXTest_q;
WHEN OTHERS => p_uid73_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg(DELAY,1312)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => p_uid73_fpSinCosXTest_q, xout => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem(DUALMEM,1313)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 1,
numwords_a => 2,
width_b => 26,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq,
address_a => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa,
data_a => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia
);
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0 <= areset;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq(25 downto 0);
--mulSin_uid92_fpSinCosXTest(MULT,91)@33
mulSin_uid92_fpSinCosXTest_pr <= UNSIGNED(mulSin_uid92_fpSinCosXTest_a) * UNSIGNED(mulSin_uid92_fpSinCosXTest_b);
mulSin_uid92_fpSinCosXTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulSin_uid92_fpSinCosXTest_a <= (others => '0');
mulSin_uid92_fpSinCosXTest_b <= (others => '0');
mulSin_uid92_fpSinCosXTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulSin_uid92_fpSinCosXTest_a <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q;
mulSin_uid92_fpSinCosXTest_b <= multSinOp2_uid91_fpSinCosXTest_q;
mulSin_uid92_fpSinCosXTest_s1 <= STD_LOGIC_VECTOR(mulSin_uid92_fpSinCosXTest_pr);
END IF;
END IF;
END PROCESS;
mulSin_uid92_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulSin_uid92_fpSinCosXTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulSin_uid92_fpSinCosXTest_q <= mulSin_uid92_fpSinCosXTest_s1;
END IF;
END IF;
END PROCESS;
--normBitSin_uid93_fpSinCosXTest(BITSELECT,92)@36
normBitSin_uid93_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q;
normBitSin_uid93_fpSinCosXTest_b <= normBitSin_uid93_fpSinCosXTest_in(51 downto 51);
--join_uid99_fpSinCosXTest(BITJOIN,98)@36
join_uid99_fpSinCosXTest_q <= reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q & normBitSin_uid93_fpSinCosXTest_b;
--sinRndOp_uid100_uid101_fpSinCosXTest(BITJOIN,100)@36
sinRndOp_uid100_uid101_fpSinCosXTest_q <= join_uid99_fpSinCosXTest_q & cstAllZWF_uid7_fpSinCosXTest_q & VCC_q;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor(LOGICAL,1333)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q <= not (ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a or ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b);
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena(REG,1334)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q = "1") THEN
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd(LOGICAL,1335)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b <= en;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a and ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor(LOGICAL,1283)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q <= not (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a or ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b);
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena(REG,1284)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd(LOGICAL,1285)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a and ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg(DELAY,1273)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expXRR_uid38_fpSinCosXTest_b, xout => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem(DUALMEM,1274)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 9,
width_b => 8,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia
);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1(REG,604)@25
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--expSinHC_uid74_fpSinCosXTest(SUB,73)@26
expSinHC_uid74_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expSinHC_uid74_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q);
expSinHC_uid74_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSinHC_uid74_fpSinCosXTest_a) - UNSIGNED(expSinHC_uid74_fpSinCosXTest_b));
expSinHC_uid74_fpSinCosXTest_q <= expSinHC_uid74_fpSinCosXTest_o(8 downto 0);
--expSinHCR_uid75_fpSinCosXTest(BITSELECT,74)@26
expSinHCR_uid75_fpSinCosXTest_in <= expSinHC_uid74_fpSinCosXTest_q(7 downto 0);
expSinHCR_uid75_fpSinCosXTest_b <= expSinHCR_uid75_fpSinCosXTest_in(7 downto 0);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b(DELAY,695)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expPSin_uid76_fpSinCosXTest(MUX,75)@26
expPSin_uid76_fpSinCosXTest_s <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q;
expPSin_uid76_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expPSin_uid76_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expPSin_uid76_fpSinCosXTest_s IS
WHEN "0" => expPSin_uid76_fpSinCosXTest_q <= expSinHCR_uid75_fpSinCosXTest_b;
WHEN "1" => expPSin_uid76_fpSinCosXTest_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => expPSin_uid76_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg(DELAY,1323)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expPSin_uid76_fpSinCosXTest_q, xout => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem(DUALMEM,1324)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 7,
width_b => 8,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia
);
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq(7 downto 0);
--fracRSinPreRndHigh_uid95_fpSinCosXTest(BITSELECT,94)@36
fracRSinPreRndHigh_uid95_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q(50 downto 0);
fracRSinPreRndHigh_uid95_fpSinCosXTest_b <= fracRSinPreRndHigh_uid95_fpSinCosXTest_in(50 downto 27);
--fracRSinPreRndLow_uid96_fpSinCosXTest(BITSELECT,95)@36
fracRSinPreRndLow_uid96_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q(49 downto 0);
fracRSinPreRndLow_uid96_fpSinCosXTest_b <= fracRSinPreRndLow_uid96_fpSinCosXTest_in(49 downto 26);
--fracRSinPreRnd_uid97_fpSinCosXTest(MUX,96)@36
fracRSinPreRnd_uid97_fpSinCosXTest_s <= normBitSin_uid93_fpSinCosXTest_b;
fracRSinPreRnd_uid97_fpSinCosXTest: PROCESS (fracRSinPreRnd_uid97_fpSinCosXTest_s, en, fracRSinPreRndLow_uid96_fpSinCosXTest_b, fracRSinPreRndHigh_uid95_fpSinCosXTest_b)
BEGIN
CASE fracRSinPreRnd_uid97_fpSinCosXTest_s IS
WHEN "0" => fracRSinPreRnd_uid97_fpSinCosXTest_q <= fracRSinPreRndLow_uid96_fpSinCosXTest_b;
WHEN "1" => fracRSinPreRnd_uid97_fpSinCosXTest_q <= fracRSinPreRndHigh_uid95_fpSinCosXTest_b;
WHEN OTHERS => fracRSinPreRnd_uid97_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracRSinPreRnd_uid98_uid98_fpSinCosXTest(BITJOIN,97)@36
expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q & fracRSinPreRnd_uid97_fpSinCosXTest_q;
--expFracRSin_uid102_fpSinCosXTest(ADD,101)@36
expFracRSin_uid102_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q);
expFracRSin_uid102_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0000000" & sinRndOp_uid100_uid101_fpSinCosXTest_q);
expFracRSin_uid102_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRSin_uid102_fpSinCosXTest_a) + UNSIGNED(expFracRSin_uid102_fpSinCosXTest_b));
expFracRSin_uid102_fpSinCosXTest_q <= expFracRSin_uid102_fpSinCosXTest_o(32 downto 0);
--expRCompSin_uid104_fpSinCosXTest(BITSELECT,103)@36
expRCompSin_uid104_fpSinCosXTest_in <= expFracRSin_uid102_fpSinCosXTest_q(31 downto 0);
expRCompSin_uid104_fpSinCosXTest_b <= expRCompSin_uid104_fpSinCosXTest_in(31 downto 24);
--reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2(REG,607)@36
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q <= expRCompSin_uid104_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor(LOGICAL,1537)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q <= not (ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a or ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b);
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena(REG,1538)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q = "1") THEN
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd(LOGICAL,1539)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b <= en;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a and ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b;
--expXIsZero_uid10_fpSinCosXTest(LOGICAL,9)@0
expXIsZero_uid10_fpSinCosXTest_a <= exp_uid9_fpSinCosXTest_b;
expXIsZero_uid10_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
expXIsZero_uid10_fpSinCosXTest_q <= "1" when expXIsZero_uid10_fpSinCosXTest_a = expXIsZero_uid10_fpSinCosXTest_b else "0";
--ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b(DELAY,746)@0
ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => expXIsZero_uid10_fpSinCosXTest_q, xout => ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excSelBitsSin_uid118_fpSinCosXTest(BITJOIN,117)@19
excSelBitsSin_uid118_fpSinCosXTest_q <= excRNaN_uid117_fpSinCosXTest_q & ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q & ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg(DELAY,1527)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => excSelBitsSin_uid118_fpSinCosXTest_q, xout => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem(DUALMEM,1528)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 4,
numwords_a => 14,
width_b => 3,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq,
address_a => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa,
data_a => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia
);
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0 <= areset;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq(2 downto 0);
--reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0(REG,533)@35
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--excSelSin_uid119_fpSinCosXTest(LOOKUP,118)@36
excSelSin_uid119_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excSelSin_uid119_fpSinCosXTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q) IS
WHEN "000" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN "001" => excSelSin_uid119_fpSinCosXTest_q <= "01";
WHEN "010" => excSelSin_uid119_fpSinCosXTest_q <= "10";
WHEN "011" => excSelSin_uid119_fpSinCosXTest_q <= "10";
WHEN "100" => excSelSin_uid119_fpSinCosXTest_q <= "11";
WHEN "101" => excSelSin_uid119_fpSinCosXTest_q <= "11";
WHEN "110" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN "111" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN OTHERS =>
excSelSin_uid119_fpSinCosXTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRPostExcSin_uid126_fpSinCosXTest(MUX,125)@37
expRPostExcSin_uid126_fpSinCosXTest_s <= excSelSin_uid119_fpSinCosXTest_q;
expRPostExcSin_uid126_fpSinCosXTest: PROCESS (expRPostExcSin_uid126_fpSinCosXTest_s, en, reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q, ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q, cstAllZWE_uid8_fpSinCosXTest_q, cstAllOWE_uid6_fpSinCosXTest_q)
BEGIN
CASE expRPostExcSin_uid126_fpSinCosXTest_s IS
WHEN "00" => expRPostExcSin_uid126_fpSinCosXTest_q <= reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q;
WHEN "01" => expRPostExcSin_uid126_fpSinCosXTest_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q;
WHEN "10" => expRPostExcSin_uid126_fpSinCosXTest_q <= cstAllZWE_uid8_fpSinCosXTest_q;
WHEN "11" => expRPostExcSin_uid126_fpSinCosXTest_q <= cstAllOWE_uid6_fpSinCosXTest_q;
WHEN OTHERS => expRPostExcSin_uid126_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor(LOGICAL,1346)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q <= not (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a or ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b);
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena(REG,1347)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd(LOGICAL,1348)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b <= en;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a and ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg(DELAY,1336)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => frac_uid13_fpSinCosXTest_b, xout => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem(DUALMEM,1337)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 6,
numwords_a => 35,
width_b => 23,
widthad_b => 6,
numwords_b => 35,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia
);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq(22 downto 0);
--fracRCompSin_uid103_fpSinCosXTest(BITSELECT,102)@36
fracRCompSin_uid103_fpSinCosXTest_in <= expFracRSin_uid102_fpSinCosXTest_q(23 downto 0);
fracRCompSin_uid103_fpSinCosXTest_b <= fracRCompSin_uid103_fpSinCosXTest_in(23 downto 1);
--reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2(REG,606)@36
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q <= fracRCompSin_uid103_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--fracRPostExcSin_uid122_fpSinCosXTest(MUX,121)@37
fracRPostExcSin_uid122_fpSinCosXTest_s <= excSelSin_uid119_fpSinCosXTest_q;
fracRPostExcSin_uid122_fpSinCosXTest: PROCESS (fracRPostExcSin_uid122_fpSinCosXTest_s, en, reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q, cstAllZWF_uid7_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q)
BEGIN
CASE fracRPostExcSin_uid122_fpSinCosXTest_s IS
WHEN "00" => fracRPostExcSin_uid122_fpSinCosXTest_q <= reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q;
WHEN "01" => fracRPostExcSin_uid122_fpSinCosXTest_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q;
WHEN "10" => fracRPostExcSin_uid122_fpSinCosXTest_q <= cstAllZWF_uid7_fpSinCosXTest_q;
WHEN "11" => fracRPostExcSin_uid122_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN OTHERS => fracRPostExcSin_uid122_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpSin_uid134_fpSinCosXTest(BITJOIN,133)@37
fpSin_uid134_fpSinCosXTest_q <= ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q & expRPostExcSin_uid126_fpSinCosXTest_q & fracRPostExcSin_uid122_fpSinCosXTest_q;
--xOut(GPOUT,4)@37
s <= fpSin_uid134_fpSinCosXTest_q;
c <= fpCos_uid162_fpSinCosXTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_sincos_s5
-- VHDL created on Wed Mar 27 09:55:14 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_sincos_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
s : out std_logic_vector(31 downto 0);
c : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_sincos_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid8_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid22_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid23_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShift_uid24_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid25_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid26_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstZwShiftP1_uid27_fpSinCosXTest_q : std_logic_vector (13 downto 0);
signal cstNaNwF_uid32_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal cstZmwFRRPwSM1_uid52_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal cPi_uid71_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal p_uid73_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal p_uid73_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal expPSin_uid76_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal expPSin_uid76_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal multSinOp2_uid91_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal multSinOp2_uid91_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_a : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_s1 : std_logic_vector (51 downto 0);
signal mulSin_uid92_fpSinCosXTest_pr : UNSIGNED (51 downto 0);
signal mulSin_uid92_fpSinCosXTest_q : std_logic_vector (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_a : std_logic_vector (25 downto 0);
signal mulCos_uid105_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal mulCos_uid105_fpSinCosXTest_s1 : std_logic_vector (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_pr : UNSIGNED (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_q : std_logic_vector (51 downto 0);
signal excSelSin_uid119_fpSinCosXTest_q : std_logic_vector(1 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expSelectorCos_uid145_fpSinCosXTest_q : std_logic_vector(1 downto 0);
signal signRCond2_uid152_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_d : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_d : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q : std_logic_vector (29 downto 0);
signal leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal zs_uid236_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal mO_uid239_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (62 downto 0);
signal zs_uid244_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal zs_uid250_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (5 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(63 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(63 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (47 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a : std_logic_vector (12 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr : SIGNED (26 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q : std_logic_vector (25 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a : std_logic_vector (14 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b : std_logic_vector (22 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr : SIGNED (38 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q : std_logic_vector (37 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a : std_logic_vector (12 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr : SIGNED (26 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q : std_logic_vector (25 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a : std_logic_vector (14 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b : std_logic_vector (22 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr : SIGNED (38 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q : std_logic_vector (37 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0 : std_logic;
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0 : std_logic;
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q : std_logic_vector (39 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a : std_logic_vector(81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b : std_logic_vector(81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o : std_logic_vector (81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q : std_logic_vector (81 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC0_uid394_tableGensinPiZ_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC1_uid396_tableGensinPiZ_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC2_uid398_tableGensinPiZ_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_q : std_logic_vector (12 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC0_uid400_tableGencosPiZ_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC1_uid402_tableGencosPiZ_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC2_uid404_tableGencosPiZ_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_q : std_logic_vector (12 downto 0);
signal reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q : std_logic_vector (2 downto 0);
signal reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q : std_logic_vector (39 downto 0);
signal reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (39 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q : std_logic_vector (26 downto 0);
signal reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (77 downto 0);
signal reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q : std_logic_vector (67 downto 0);
signal reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q : std_logic_vector (66 downto 0);
signal reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q : std_logic_vector (65 downto 0);
signal reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q : std_logic_vector (67 downto 0);
signal reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q : std_logic_vector (25 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q : std_logic_vector (12 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q : std_logic_vector (20 downto 0);
signal reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q : std_logic_vector (22 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q : std_logic_vector (29 downto 0);
signal reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q : std_logic_vector (6 downto 0);
signal reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q : std_logic_vector (22 downto 0);
signal reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q : std_logic_vector (0 downto 0);
signal reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q : std_logic_vector (12 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q : std_logic_vector (20 downto 0);
signal reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q : std_logic_vector (22 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q : std_logic_vector (29 downto 0);
signal reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q : std_logic_vector (25 downto 0);
signal reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q : std_logic_vector (25 downto 0);
signal reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q : std_logic_vector (6 downto 0);
signal reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q : std_logic_vector (22 downto 0);
signal reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q : std_logic_vector (3 downto 0);
signal reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q : std_logic_vector (52 downto 0);
signal ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q : std_logic_vector (65 downto 0);
signal ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q : std_logic_vector (67 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (7 downto 0);
signal ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (66 downto 0);
signal ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (65 downto 0);
signal ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (64 downto 0);
signal ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q : std_logic_vector (63 downto 0);
signal ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q : std_logic_vector (31 downto 0);
signal ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (58 downto 0);
signal ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q : std_logic_vector (63 downto 0);
signal ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q : std_logic_vector (31 downto 0);
signal ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (58 downto 0);
signal ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (76 downto 0);
signal ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (75 downto 0);
signal ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (74 downto 0);
signal ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q : std_logic_vector (12 downto 0);
signal ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q : std_logic_vector (53 downto 0);
signal ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q : std_logic_vector (12 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0 : std_logic;
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q : signal is true;
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q : std_logic_vector (6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0 : std_logic;
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q : signal is true;
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q : signal is true;
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0 : std_logic;
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0 : std_logic;
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0 : std_logic;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq : std_logic;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q : signal is true;
signal sinXIsXRR_uid41_fpSinCosXTest_a : std_logic_vector(11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_b : std_logic_vector(11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_o : std_logic_vector (11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_a : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_b : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_o : std_logic_vector (11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal yIsZero_uid51_fpSinCosXTest_a : std_logic_vector(65 downto 0);
signal yIsZero_uid51_fpSinCosXTest_b : std_logic_vector(65 downto 0);
signal yIsZero_uid51_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal pad_one_uid55_fpSinCosXTest_q : std_logic_vector (66 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_a : std_logic_vector(70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_b : std_logic_vector(70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_o : std_logic_vector (70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_c : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal InvCmpYToOneMinusY_uid61_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCmpYToOneMinusY_uid61_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid127_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid127_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvSinXIsXRR_uid128_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsXRR_uid128_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid131_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid131_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid132_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid132_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid136_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid136_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvCosXONe_uid149_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCosXONe_uid149_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid151_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid151_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvIntXParity_uid155_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvIntXParity_uid155_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal oFracXRR_uid43_uid43_fpSinCosXTest_q : std_logic_vector (53 downto 0);
signal half_uid53_fpSinCosXTest_q : std_logic_vector (65 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal exp_uid9_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal exp_uid9_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal frac_uid13_fpSinCosXTest_in : std_logic_vector (22 downto 0);
signal frac_uid13_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal signX_uid37_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal signX_uid37_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal expFracX_uid166_px_uid33_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal expFracX_uid166_px_uid33_fpSinCosXTest_b : std_logic_vector (30 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_q : std_logic_vector (9 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_a : std_logic_vector(65 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_b : std_logic_vector(65 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_a : std_logic_vector(67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_b : std_logic_vector(67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_o : std_logic_vector (67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal zSin_uid60_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal zSin_uid60_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal zCos_uid64_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal zCos_uid64_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal expSinHC_uid74_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal excRNaN_uid117_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid117_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid117_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracRPostExcSin_uid122_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExcSin_uid122_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal expRPostExcSin_uid126_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExcSin_uid126_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracRPostExcCos_uid142_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExcCos_uid142_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal expRPostExcCos_uid147_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExcCos_uid147_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cosXONe_uid148_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal cosXONe_uid148_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal cosXONe_uid148_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal finalExp_uid209_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal finalExp_uid209_rrx_uid34_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal extendedFracX_uid47_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal normBitSin_uid93_fpSinCosXTest_in : std_logic_vector (51 downto 0);
signal normBitSin_uid93_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal fracRSinPreRndHigh_uid95_fpSinCosXTest_in : std_logic_vector (50 downto 0);
signal fracRSinPreRndHigh_uid95_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracRSinPreRndLow_uid96_fpSinCosXTest_in : std_logic_vector (49 downto 0);
signal fracRSinPreRndLow_uid96_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal normBitCos_uid106_fpSinCosXTest_in : std_logic_vector (51 downto 0);
signal normBitCos_uid106_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal fracRCosPreRndHigh_uid108_fpSinCosXTest_in : std_logic_vector (50 downto 0);
signal fracRCosPreRndHigh_uid108_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracRCosPreRndLow_uid109_fpSinCosXTest_in : std_logic_vector (49 downto 0);
signal fracRCosPreRndLow_uid109_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q : std_logic_vector (52 downto 0);
signal leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b : std_logic_vector (23 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int : std_logic_vector (80 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q : std_logic_vector (80 downto 0);
signal os_uid196_rrx_uid34_fpSinCosXTest_q : std_logic_vector (79 downto 0);
signal leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal join_uid99_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal join_uid141_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal zSinYBottom_uid59_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal zSinYBottom_uid59_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal zSinOMyBottom_uid58_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal zSinOMyBottom_uid58_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal excSelBitsSin_uid118_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal fpSin_uid134_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal join_uid143_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal fpCos_uid162_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int : std_logic_vector (107 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q : std_logic_vector (107 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal fracX_uid187_rrx_uid34_fpSinCosXTest_in : std_logic_vector (22 downto 0);
signal fracX_uid187_rrx_uid34_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal oFracXRRSmallXRR_uid90_fpSinCosXTest_in : std_logic_vector (53 downto 0);
signal oFracXRRSmallXRR_uid90_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal R_uid167_px_uid33_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal InvFracXIsZero_uid16_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid16_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fxpXShiftVal_uid46_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal fxpXShiftVal_uid46_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal addr_uid81_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal addr_uid81_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal zPsinPiZ_uid84_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal zPsinPiZ_uid84_fpSinCosXTest_b : std_logic_vector (14 downto 0);
signal rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (32 downto 0);
signal addr_uid83_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal addr_uid83_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal zPcosPiZ_uid87_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal zPcosPiZ_uid87_fpSinCosXTest_b : std_logic_vector (14 downto 0);
signal rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (32 downto 0);
signal expSinHCR_uid75_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expSinHCR_uid75_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal expPCos_uid79_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expPCos_uid79_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (66 downto 0);
signal LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (66 downto 0);
signal LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (65 downto 0);
signal LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (58 downto 0);
signal rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (58 downto 0);
signal rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (76 downto 0);
signal LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (76 downto 0);
signal LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (75 downto 0);
signal LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (75 downto 0);
signal LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (74 downto 0);
signal LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (74 downto 0);
signal X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (59 downto 0);
signal X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (59 downto 0);
signal X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (55 downto 0);
signal X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (55 downto 0);
signal fracRSinPreRnd_uid97_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal fracRSinPreRnd_uid97_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal fracRCosPreRnd_uid110_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal fracRCosPreRnd_uid110_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal cosRndOp_uid112_uid113_fpSinCosXTest_q : std_logic_vector (24 downto 0);
signal rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal lowRangeB_uid408_polyEvalsinPiZ_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid408_polyEvalsinPiZ_b : std_logic_vector (0 downto 0);
signal highBBits_uid409_polyEvalsinPiZ_in : std_logic_vector (13 downto 0);
signal highBBits_uid409_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid414_polyEvalsinPiZ_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid414_polyEvalsinPiZ_b : std_logic_vector (1 downto 0);
signal highBBits_uid415_polyEvalsinPiZ_in : std_logic_vector (23 downto 0);
signal highBBits_uid415_polyEvalsinPiZ_b : std_logic_vector (21 downto 0);
signal lowRangeB_uid421_polyEvalcosPiZ_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid421_polyEvalcosPiZ_b : std_logic_vector (0 downto 0);
signal highBBits_uid422_polyEvalcosPiZ_in : std_logic_vector (13 downto 0);
signal highBBits_uid422_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid427_polyEvalcosPiZ_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid427_polyEvalcosPiZ_b : std_logic_vector (1 downto 0);
signal highBBits_uid428_polyEvalcosPiZ_in : std_logic_vector (23 downto 0);
signal highBBits_uid428_polyEvalcosPiZ_b : std_logic_vector (21 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in : std_logic_vector (80 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b : std_logic_vector (26 downto 0);
signal fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in : std_logic_vector (76 downto 0);
signal fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b : std_logic_vector (52 downto 0);
signal intXParity_uid49_fpSinCosXTest_in : std_logic_vector (67 downto 0);
signal intXParity_uid49_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal y_uid50_fpSinCosXTest_in : std_logic_vector (66 downto 0);
signal y_uid50_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal sinRndOp_uid100_uid101_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal expSelBitsCos_uid144_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a : std_logic_vector(108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b : std_logic_vector(108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o : std_logic_vector (108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q : std_logic_vector (108 downto 0);
signal oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal expX_uid186_rrx_uid34_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal expX_uid186_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal exc_N_uid17_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal yT1_uid406_polyEvalsinPiZ_in : std_logic_vector (14 downto 0);
signal yT1_uid406_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal yT1_uid419_polyEvalcosPiZ_in : std_logic_vector (14 downto 0);
signal yT1_uid419_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_a : std_logic_vector(32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_b : std_logic_vector(32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_o : std_logic_vector (32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_q : std_logic_vector (30 downto 0);
signal finalFrac_uid208_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal finalFrac_uid208_rrx_uid34_fpSinCosXTest_q : std_logic_vector (52 downto 0);
signal signComp_uid129_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_a : std_logic_vector(32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_b : std_logic_vector(32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_o : std_logic_vector (32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_q : std_logic_vector (32 downto 0);
signal leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal multFracBits_uid199_rrx_uid34_fpSinCosXTest_in : std_logic_vector (77 downto 0);
signal multFracBits_uid199_rrx_uid34_fpSinCosXTest_b : std_logic_vector (77 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b : std_logic_vector (26 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (5 downto 0);
signal fracRCompCos_uid115_fpSinCosXTest_in : std_logic_vector (23 downto 0);
signal fracRCompCos_uid115_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal expRCompSin_uid116_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal expRCompSin_uid116_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal s1_uid408_uid411_polyEvalsinPiZ_q : std_logic_vector (22 downto 0);
signal s2_uid414_uid417_polyEvalsinPiZ_q : std_logic_vector (32 downto 0);
signal s1_uid421_uid424_polyEvalcosPiZ_q : std_logic_vector (22 downto 0);
signal s2_uid427_uid430_polyEvalcosPiZ_q : std_logic_vector (32 downto 0);
signal RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q : std_logic_vector (61 downto 0);
signal signR_uid130_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signR_uid130_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signR_uid130_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal fracRCompSin_uid103_fpSinCosXTest_in : std_logic_vector (23 downto 0);
signal fracRCompSin_uid103_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal expRCompSin_uid104_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal expRCompSin_uid104_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in : std_logic_vector (77 downto 0);
signal multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (61 downto 0);
signal X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (61 downto 0);
signal X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (45 downto 0);
signal X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (45 downto 0);
signal X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (29 downto 0);
signal X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (29 downto 0);
signal expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal polyEvalSigsinPiZ_uid86_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal polyEvalSigsinPiZ_uid86_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal polyEvalSigcosPiZ_uid89_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal polyEvalSigcosPiZ_uid89_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal expXRR_uid38_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal expXRR_uid38_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal fracXRR_uid39_fpSinCosXTest_in : std_logic_vector (52 downto 0);
signal fracXRR_uid39_fpSinCosXTest_b : std_logic_vector (52 downto 0);
signal pHigh_uid72_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal pHigh_uid72_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal pCos_uid77_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal pCos_uid77_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal r_uid277_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (6 downto 0);
signal r_uid356_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (6 downto 0);
signal expCompOut_uid205_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expCompOut_uid205_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (73 downto 0);
signal LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (73 downto 0);
signal LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (69 downto 0);
signal LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (69 downto 0);
signal LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (65 downto 0);
signal LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (56 downto 0);
signal LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (48 downto 0);
signal LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (48 downto 0);
signal LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (40 downto 0);
signal LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (40 downto 0);
signal LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (56 downto 0);
signal LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (48 downto 0);
signal LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (48 downto 0);
signal LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (40 downto 0);
signal LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (40 downto 0);
signal leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
begin
--xIn(GPIN,3)@0
--GND(CONSTANT,0)
GND_q <= "0";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable(LOGICAL,1282)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q <= not ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor(LOGICAL,1422)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q <= not (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a or ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b);
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top(CONSTANT,1418)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q <= "01011";
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp(LOGICAL,1419)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q <= "1" when ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a = ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b else "0";
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg(REG,1420)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena(REG,1423)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd(LOGICAL,1424)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b <= en;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a and ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b;
--expFracX_uid166_px_uid33_fpSinCosXTest(BITSELECT,165)@0
expFracX_uid166_px_uid33_fpSinCosXTest_in <= a(30 downto 0);
expFracX_uid166_px_uid33_fpSinCosXTest_b <= expFracX_uid166_px_uid33_fpSinCosXTest_in(30 downto 0);
--R_uid167_px_uid33_fpSinCosXTest(BITJOIN,166)@0
R_uid167_px_uid33_fpSinCosXTest_q <= GND_q & expFracX_uid166_px_uid33_fpSinCosXTest_b;
--expX_uid186_rrx_uid34_fpSinCosXTest(BITSELECT,185)@0
expX_uid186_rrx_uid34_fpSinCosXTest_in <= R_uid167_px_uid33_fpSinCosXTest_q(30 downto 0);
expX_uid186_rrx_uid34_fpSinCosXTest_b <= expX_uid186_rrx_uid34_fpSinCosXTest_in(30 downto 23);
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg(DELAY,1412)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid186_rrx_uid34_fpSinCosXTest_b, xout => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt(COUNTER,1414)
-- every=1, low=0, high=11, step=1, init=1
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i = 10 THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i - 11;
ELSE
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg(REG,1415)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux(MUX,1416)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem(DUALMEM,1413)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 12,
width_b => 8,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia
);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--zs_uid244_lzcZSin_uid66_fpSinCosXTest(CONSTANT,243)
zs_uid244_lzcZSin_uid66_fpSinCosXTest_q <= "00000000000000000000000000000000";
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor(LOGICAL,1396)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q <= not (ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a or ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b);
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg(REG,1318)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena(REG,1397)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q = "1") THEN
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd(LOGICAL,1398)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b <= en;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a and ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg(DELAY,1388)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid167_px_uid33_fpSinCosXTest_q, xout => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt(COUNTER,1314)
-- every=1, low=0, high=1, step=1, init=1
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i,1));
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg(REG,1315)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux(MUX,1316)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s <= en;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux: PROCESS (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s, ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q, ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q)
BEGIN
CASE ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s IS
WHEN "0" => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
WHEN "1" => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem(DUALMEM,1389)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 1,
numwords_a => 2,
width_b => 32,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq,
address_a => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa,
data_a => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia
);
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0 <= areset;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq(31 downto 0);
--fracX_uid187_rrx_uid34_fpSinCosXTest(BITSELECT,186)@4
fracX_uid187_rrx_uid34_fpSinCosXTest_in <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q(22 downto 0);
fracX_uid187_rrx_uid34_fpSinCosXTest_b <= fracX_uid187_rrx_uid34_fpSinCosXTest_in(22 downto 0);
--oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest(BITJOIN,196)@4
oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q <= VCC_q & fracX_uid187_rrx_uid34_fpSinCosXTest_b;
--prod_uid198_rrx_uid34_fpSinCosXTest_b_0(BITSELECT,518)@4
prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in <= STD_LOGIC_VECTOR("000" & oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q);
prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b <= prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in(26 downto 0);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1(REG,539)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q <= prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShift_uid24_fpSinCosXTest(CONSTANT,23)
cstBiasMwShift_uid24_fpSinCosXTest_q <= "01110011";
--expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest(SUB,191)@0
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expX_uid186_rrx_uid34_fpSinCosXTest_b);
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0" & cstBiasMwShift_uid24_fpSinCosXTest_q);
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b));
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q <= expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o(8 downto 0);
--expXTableAddr_uid193_rrx_uid34_fpSinCosXTest(BITSELECT,192)@0
expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in <= expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q(7 downto 0);
expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b <= expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0(REG,534)@0
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q <= expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem(DUALMEM,514)@1
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia <= (others => '0');
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa <= (others => '0');
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab <= reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q;
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq,
address_a => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa,
data_a => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia
);
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0 <= areset;
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q <= rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1(REG,537)@3
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q <= rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem(DUALMEM,513)@1
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia <= (others => '0');
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa <= (others => '0');
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab <= reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q;
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq,
address_a => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa,
data_a => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia
);
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0 <= areset;
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q <= rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0(REG,536)@3
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q <= rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid196_rrx_uid34_fpSinCosXTest(BITJOIN,195)@4
os_uid196_rrx_uid34_fpSinCosXTest_q <= reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q & reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q;
--prod_uid198_rrx_uid34_fpSinCosXTest_a_2(BITSELECT,517)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in <= STD_LOGIC_VECTOR("0" & os_uid196_rrx_uid34_fpSinCosXTest_q);
prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in(80 downto 54);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0(REG,542)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0(MULT,521)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1;
END IF;
END IF;
END PROCESS;
--ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a(DELAY,1145)@8
ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a : dspba_delay
GENERIC MAP ( width => 54, depth => 1 )
PORT MAP ( xin => prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q, xout => ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--prod_uid198_rrx_uid34_fpSinCosXTest_align_2(BITSHIFT,524)@9
prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int <= ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int(107 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_a_1(BITSELECT,516)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in <= os_uid196_rrx_uid34_fpSinCosXTest_q(53 downto 0);
prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in(53 downto 27);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0(REG,540)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0(MULT,520)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_align_1(BITSHIFT,523)@8
prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int <= prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q & "000000000000000000000000000";
prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int(80 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_a_0(BITSELECT,515)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in <= os_uid196_rrx_uid34_fpSinCosXTest_q(26 downto 0);
prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in(26 downto 0);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0(REG,538)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0(MULT,519)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_align_0(BITSHIFT,522)@8
prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int <= prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int(53 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0(ADD,525)@8
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a <= STD_LOGIC_VECTOR("0000000000000000000000000000" & prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b <= STD_LOGIC_VECTOR("0" & prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a) + UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b));
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o(81 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0(ADD,526)@9
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a <= STD_LOGIC_VECTOR("000000000000000000000000000" & prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b <= STD_LOGIC_VECTOR("0" & prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a) + UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b));
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o(108 downto 0);
--multFracBits_uid199_rrx_uid34_fpSinCosXTest(BITSELECT,198)@9
multFracBits_uid199_rrx_uid34_fpSinCosXTest_in <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q(77 downto 0);
multFracBits_uid199_rrx_uid34_fpSinCosXTest_b <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_in(77 downto 0);
--multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest(BITSELECT,199)@9
multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b;
multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b <= multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in(77 downto 46);
--reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1(REG,544)@9
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,433)@10
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a(DELAY,1178)@10
ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xout => ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5(REG,555)@12
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q <= ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q;
END IF;
END IF;
END PROCESS;
--zs_uid250_lzcZSin_uid66_fpSinCosXTest(CONSTANT,249)
zs_uid250_lzcZSin_uid66_fpSinCosXTest_q <= "0000000000000000";
--mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest(CONSTANT,434)
mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "11111111111111111111111111111111";
--vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,436)@10
vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q, mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,438)@10
rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in(31 downto 16);
--reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1(REG,546)@10
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,439)@11
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4(REG,554)@11
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q <= vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e(DELAY,1081)@12
ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWE_uid8_fpSinCosXTest(CONSTANT,7)
cstAllZWE_uid8_fpSinCosXTest_q <= "00000000";
--vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,440)@10
vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q(15 downto 0);
vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in(15 downto 0);
--reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,548)@10
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,442)@11
vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q, reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,444)@11
rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in(15 downto 8);
--vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,445)@11
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i <= "1" when vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xin => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d(DELAY,1080)@12
ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xout => ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest(CONSTANT,212)
leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q <= "0000";
--vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,446)@11
vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q(7 downto 0);
vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,550)@11
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,549)@11
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,448)@12
vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q, reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,450)@12
rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in(7 downto 4);
--vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,451)@12
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,553)@12
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest(CONSTANT,226)
leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q <= "00";
--vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,452)@12
vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q(3 downto 0);
vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in(3 downto 0);
--vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,454)@12
vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b, vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
WHEN "1" => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,456)@12
rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in(3 downto 2);
--vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,457)@12
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i <= "1" when vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xin => vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,458)@12
vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q(1 downto 0);
vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in(1 downto 0);
--reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,552)@12
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,551)@12
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,460)@13
vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q, reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,462)@13
rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in(1 downto 1);
--vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,463)@13
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= GND_q;
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest(BITJOIN,464)@13
r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q & ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q & ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q & reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q & vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q & vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
--cstBiasM1_uid23_fpSinCosXTest(CONSTANT,22)
cstBiasM1_uid23_fpSinCosXTest_q <= "01111110";
--expCompOutExt_uid204_rrx_uid34_fpSinCosXTest(SUB,203)@13
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("000" & r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q);
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b));
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q <= expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o(8 downto 0);
--expCompOut_uid205_rrx_uid34_fpSinCosXTest(BITSELECT,204)@13
expCompOut_uid205_rrx_uid34_fpSinCosXTest_in <= expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q(7 downto 0);
expCompOut_uid205_rrx_uid34_fpSinCosXTest_b <= expCompOut_uid205_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2(REG,564)@13
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q <= expCompOut_uid205_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--xBranch_uid191_rrx_uid34_fpSinCosXTest(COMPARE,190)@0
xBranch_uid191_rrx_uid34_fpSinCosXTest_cin <= GND_q;
xBranch_uid191_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid24_fpSinCosXTest_q) & '0';
xBranch_uid191_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & expX_uid186_rrx_uid34_fpSinCosXTest_b) & xBranch_uid191_rrx_uid34_fpSinCosXTest_cin(0);
xBranch_uid191_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xBranch_uid191_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(xBranch_uid191_rrx_uid34_fpSinCosXTest_b));
xBranch_uid191_rrx_uid34_fpSinCosXTest_n(0) <= not xBranch_uid191_rrx_uid34_fpSinCosXTest_o(10);
--reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1(REG,563)@0
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q <= xBranch_uid191_rrx_uid34_fpSinCosXTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b(DELAY,829)@1
ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q, xout => ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalExp_uid209_rrx_uid34_fpSinCosXTest(MUX,208)@14
finalExp_uid209_rrx_uid34_fpSinCosXTest_s <= ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q;
finalExp_uid209_rrx_uid34_fpSinCosXTest: PROCESS (finalExp_uid209_rrx_uid34_fpSinCosXTest_s, en, reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q)
BEGIN
CASE finalExp_uid209_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b(DELAY,833)@14
ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => finalExp_uid209_rrx_uid34_fpSinCosXTest_q, xout => ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1409)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a or ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top(CONSTANT,1279)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q <= "01000";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp(LOGICAL,1280)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q <= "1" when ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a = ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b else "0";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg(REG,1281)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1410)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1411)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1399)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid187_rrx_uid34_fpSinCosXTest_b, xout => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt(COUNTER,1275)
-- every=1, low=0, high=8, step=1, init=1
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i = 7 THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i - 8;
ELSE
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg(REG,1276)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux(MUX,1277)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s, ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q, ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1400)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 4,
numwords_a => 9,
width_b => 23,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(22 downto 0);
--ZerosGB_uid206_rrx_uid34_fpSinCosXTest(CONSTANT,205)
ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q <= "000000000000000000000000000000";
--fracXRExt_uid207_rrx_uid34_fpSinCosXTest(BITJOIN,206)@15
fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q & ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q;
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1499)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1500)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1501)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,474)@9
X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(29 downto 0);
X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in(29 downto 0);
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1491)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 30, depth => 1 )
PORT MAP ( xin => X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1492)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 1,
numwords_a => 2,
width_b => 30,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(29 downto 0);
--leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest(CONSTANT,473)
leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,475)@13
leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1488)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1489)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1490)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,471)@9
X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(45 downto 0);
X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in(45 downto 0);
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1480)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1481)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 1,
numwords_a => 2,
width_b => 46,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(45 downto 0);
--leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,472)@13
leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1477)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1478)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1479)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,468)@9
X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(61 downto 0);
X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in(61 downto 0);
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1469)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1470)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 62,
widthad_a => 1,
numwords_a => 2,
width_b => 62,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(61 downto 0);
--leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,469)@13
leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor(LOGICAL,1510)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q <= not (ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a or ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b);
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena(REG,1511)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q = "1") THEN
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd(LOGICAL,1512)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b <= en;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a and ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg(DELAY,1502)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 78, depth => 1 )
PORT MAP ( xin => multFracBits_uid199_rrx_uid34_fpSinCosXTest_b, xout => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem(DUALMEM,1503)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 78,
widthad_a => 1,
numwords_a => 2,
width_b => 78,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia
);
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq(77 downto 0);
--leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,476)@13
leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in(5 downto 4);
--leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,477)@13
leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b;
leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,485)@13
LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(65 downto 0);
LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in(65 downto 0);
--leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest(CONSTANT,218)
leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q <= "000000000000";
--leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,486)@13
leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b & leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5(REG,560)@13
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,482)@13
LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(69 downto 0);
LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in(69 downto 0);
--leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,483)@13
leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4(REG,559)@13
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,479)@13
LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(73 downto 0);
LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in(73 downto 0);
--leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,480)@13
leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3(REG,558)@13
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2(REG,557)@13
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,487)@13
leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1(REG,556)@13
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,488)@14
leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q;
leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,496)@14
LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(74 downto 0);
LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in(74 downto 0);
--ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1112)@14
ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 75, depth => 1 )
PORT MAP ( xin => LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest(CONSTANT,229)
leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q <= "000";
--leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,497)@15
leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,493)@14
LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(75 downto 0);
LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in(75 downto 0);
--ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1110)@14
ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 76, depth => 1 )
PORT MAP ( xin => LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,494)@15
leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,490)@14
LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(76 downto 0);
LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in(76 downto 0);
--ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1108)@14
ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 77, depth => 1 )
PORT MAP ( xin => LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,491)@15
leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & GND_q;
--reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2(REG,562)@14
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,498)@13
leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a(DELAY,1184)@13
ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1(REG,561)@14
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,499)@15
leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q;
leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracCompOut_uid203_rrx_uid34_fpSinCosXTest(BITSELECT,202)@15
fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in <= leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q(76 downto 0);
fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b <= fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in(76 downto 24);
--ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b(DELAY,826)@0
ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => xBranch_uid191_rrx_uid34_fpSinCosXTest_n, xout => ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalFrac_uid208_rrx_uid34_fpSinCosXTest(MUX,207)@15
finalFrac_uid208_rrx_uid34_fpSinCosXTest_s <= ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q;
finalFrac_uid208_rrx_uid34_fpSinCosXTest: PROCESS (finalFrac_uid208_rrx_uid34_fpSinCosXTest_s, en, fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b, fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE finalFrac_uid208_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b;
WHEN "1" => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RRangeRed_uid210_rrx_uid34_fpSinCosXTest(BITJOIN,209)@15
RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q <= GND_q & ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q & finalFrac_uid208_rrx_uid34_fpSinCosXTest_q;
--expXRR_uid38_fpSinCosXTest(BITSELECT,37)@15
expXRR_uid38_fpSinCosXTest_in <= RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q(60 downto 0);
expXRR_uid38_fpSinCosXTest_b <= expXRR_uid38_fpSinCosXTest_in(60 downto 53);
--reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1(REG,565)@15
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q <= expXRR_uid38_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShiftM2_uid26_fpSinCosXTest(CONSTANT,25)
cstBiasMwShiftM2_uid26_fpSinCosXTest_q <= "01110000";
--cosXIsOneXRR_uid42_fpSinCosXTest(COMPARE,41)@16
cosXIsOneXRR_uid42_fpSinCosXTest_cin <= GND_q;
cosXIsOneXRR_uid42_fpSinCosXTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid26_fpSinCosXTest_q) & '0';
cosXIsOneXRR_uid42_fpSinCosXTest_b <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q) & cosXIsOneXRR_uid42_fpSinCosXTest_cin(0);
cosXIsOneXRR_uid42_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(cosXIsOneXRR_uid42_fpSinCosXTest_a) - SIGNED(cosXIsOneXRR_uid42_fpSinCosXTest_b));
cosXIsOneXRR_uid42_fpSinCosXTest_n(0) <= not cosXIsOneXRR_uid42_fpSinCosXTest_o(11);
--exp_uid9_fpSinCosXTest(BITSELECT,8)@0
exp_uid9_fpSinCosXTest_in <= a(30 downto 0);
exp_uid9_fpSinCosXTest_b <= exp_uid9_fpSinCosXTest_in(30 downto 23);
--sinXIsX_uid40_fpSinCosXTest(COMPARE,39)@0
sinXIsX_uid40_fpSinCosXTest_cin <= GND_q;
sinXIsX_uid40_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid24_fpSinCosXTest_q) & '0';
sinXIsX_uid40_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & exp_uid9_fpSinCosXTest_b) & sinXIsX_uid40_fpSinCosXTest_cin(0);
sinXIsX_uid40_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid40_fpSinCosXTest_a) - UNSIGNED(sinXIsX_uid40_fpSinCosXTest_b));
sinXIsX_uid40_fpSinCosXTest_n(0) <= not sinXIsX_uid40_fpSinCosXTest_o(10);
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a(DELAY,789)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--cosXONe_uid148_fpSinCosXTest(LOGICAL,147)@16
cosXONe_uid148_fpSinCosXTest_a <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q;
cosXONe_uid148_fpSinCosXTest_b <= cosXIsOneXRR_uid42_fpSinCosXTest_n;
cosXONe_uid148_fpSinCosXTest_q <= cosXONe_uid148_fpSinCosXTest_a or cosXONe_uid148_fpSinCosXTest_b;
--ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a(DELAY,791)@16
ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => cosXONe_uid148_fpSinCosXTest_q, xout => ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvCosXONe_uid149_fpSinCosXTest(LOGICAL,148)@20
InvCosXONe_uid149_fpSinCosXTest_a <= ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q;
InvCosXONe_uid149_fpSinCosXTest_q <= not InvCosXONe_uid149_fpSinCosXTest_a;
--cstZwShiftP1_uid27_fpSinCosXTest(CONSTANT,26)
cstZwShiftP1_uid27_fpSinCosXTest_q <= "00000000000000";
--fracXRR_uid39_fpSinCosXTest(BITSELECT,38)@15
fracXRR_uid39_fpSinCosXTest_in <= RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q(52 downto 0);
fracXRR_uid39_fpSinCosXTest_b <= fracXRR_uid39_fpSinCosXTest_in(52 downto 0);
--ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a(DELAY,668)@15
ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => fracXRR_uid39_fpSinCosXTest_b, xout => ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracXRR_uid43_uid43_fpSinCosXTest(BITJOIN,42)@16
oFracXRR_uid43_uid43_fpSinCosXTest_q <= VCC_q & ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q;
--extendedFracX_uid47_fpSinCosXTest(BITJOIN,46)@16
extendedFracX_uid47_fpSinCosXTest_q <= cstZwShiftP1_uid27_fpSinCosXTest_q & oFracXRR_uid43_uid43_fpSinCosXTest_q;
--X55dto0_uid220_fxpX_uid48_fpSinCosXTest(BITSELECT,219)@16
X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(55 downto 0);
X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b <= X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in(55 downto 0);
--leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest(BITJOIN,220)@16
leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q <= X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b & leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5(REG,571)@16
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q <= leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--X59dto0_uid217_fxpX_uid48_fpSinCosXTest(BITSELECT,216)@16
X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(59 downto 0);
X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b <= X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in(59 downto 0);
--leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest(BITJOIN,217)@16
leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q <= X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4(REG,570)@16
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q <= leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--X63dto0_uid214_fxpX_uid48_fpSinCosXTest(BITSELECT,213)@16
X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(63 downto 0);
X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b <= X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in(63 downto 0);
--leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest(BITJOIN,214)@16
leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q <= X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3(REG,569)@16
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q <= leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2(REG,568)@16
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q <= extendedFracX_uid47_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--fxpXShiftValExt_uid45_fpSinCosXTest(SUB,44)@16
fxpXShiftValExt_uid45_fpSinCosXTest_a <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q);
fxpXShiftValExt_uid45_fpSinCosXTest_b <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid26_fpSinCosXTest_q);
fxpXShiftValExt_uid45_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(fxpXShiftValExt_uid45_fpSinCosXTest_a) - SIGNED(fxpXShiftValExt_uid45_fpSinCosXTest_b));
fxpXShiftValExt_uid45_fpSinCosXTest_q <= fxpXShiftValExt_uid45_fpSinCosXTest_o(9 downto 0);
--fxpXShiftVal_uid46_fpSinCosXTest(BITSELECT,45)@16
fxpXShiftVal_uid46_fpSinCosXTest_in <= fxpXShiftValExt_uid45_fpSinCosXTest_q(3 downto 0);
fxpXShiftVal_uid46_fpSinCosXTest_b <= fxpXShiftVal_uid46_fpSinCosXTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest(BITSELECT,221)@16
leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in <= fxpXShiftVal_uid46_fpSinCosXTest_b;
leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b <= leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1(REG,567)@16
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q <= leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest(MUX,222)@17
leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s <= reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q;
leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest: PROCESS (leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s, en, reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q, reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q, reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q, reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest(BITSELECT,230)@17
LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(64 downto 0);
LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in(64 downto 0);
--ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b(DELAY,851)@17
ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest(BITJOIN,231)@18
leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q & leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest(BITSELECT,227)@17
LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(65 downto 0);
LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in(65 downto 0);
--ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b(DELAY,849)@17
ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 66, depth => 1 )
PORT MAP ( xin => LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest(BITJOIN,228)@18
leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest(BITSELECT,224)@17
LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(66 downto 0);
LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in(66 downto 0);
--ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b(DELAY,847)@17
ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 67, depth => 1 )
PORT MAP ( xin => LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest(BITJOIN,225)@18
leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q & GND_q;
--reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2(REG,573)@17
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest(BITSELECT,232)@16
leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in <= fxpXShiftVal_uid46_fpSinCosXTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b <= leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a(DELAY,1195)@16
ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b, xout => ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1(REG,572)@17
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q <= ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest(MUX,233)@18
leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s <= reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q;
leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest: PROCESS (leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s, en, reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q, leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q, leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q, leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q;
WHEN "10" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q;
WHEN "11" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid50_fpSinCosXTest(BITSELECT,49)@18
y_uid50_fpSinCosXTest_in <= leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q(66 downto 0);
y_uid50_fpSinCosXTest_b <= y_uid50_fpSinCosXTest_in(66 downto 1);
--ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b(DELAY,680)@18
ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 66, depth => 2 )
PORT MAP ( xin => y_uid50_fpSinCosXTest_b, xout => ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1(REG,575)@18
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q <= y_uid50_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--pad_one_uid55_fpSinCosXTest(BITJOIN,54)@18
pad_one_uid55_fpSinCosXTest_q <= VCC_q & STD_LOGIC_VECTOR((65 downto 1 => GND_q(0)) & GND_q);
--reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0(REG,574)@18
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q <= pad_one_uid55_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--oneMinusY_uid55_fpSinCosXTest(SUB,55)@19
oneMinusY_uid55_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q);
oneMinusY_uid55_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q);
oneMinusY_uid55_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid55_fpSinCosXTest_a) - UNSIGNED(oneMinusY_uid55_fpSinCosXTest_b));
oneMinusY_uid55_fpSinCosXTest_q <= oneMinusY_uid55_fpSinCosXTest_o(67 downto 0);
--reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0(REG,576)@19
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q <= oneMinusY_uid55_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid57_fpSinCosXTest(COMPARE,56)@20
cmpYToOneMinusY_uid57_fpSinCosXTest_cin <= GND_q;
cmpYToOneMinusY_uid57_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q) & '0';
cmpYToOneMinusY_uid57_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q) & cmpYToOneMinusY_uid57_fpSinCosXTest_cin(0);
cmpYToOneMinusY_uid57_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid57_fpSinCosXTest_a) - UNSIGNED(cmpYToOneMinusY_uid57_fpSinCosXTest_b));
cmpYToOneMinusY_uid57_fpSinCosXTest_c(0) <= cmpYToOneMinusY_uid57_fpSinCosXTest_o(70);
--InvCmpYToOneMinusY_uid61_fpSinCosXTest(LOGICAL,60)@20
InvCmpYToOneMinusY_uid61_fpSinCosXTest_a <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
InvCmpYToOneMinusY_uid61_fpSinCosXTest_q <= not InvCmpYToOneMinusY_uid61_fpSinCosXTest_a;
--intXParity_uid49_fpSinCosXTest(BITSELECT,48)@18
intXParity_uid49_fpSinCosXTest_in <= leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q;
intXParity_uid49_fpSinCosXTest_b <= intXParity_uid49_fpSinCosXTest_in(67 downto 67);
--ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b(DELAY,794)@18
ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => intXParity_uid49_fpSinCosXTest_b, xout => ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--yIsZero_uid51_fpSinCosXTest(LOGICAL,50)@19
yIsZero_uid51_fpSinCosXTest_a <= reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q;
yIsZero_uid51_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000000000000000000000000000000000" & GND_q);
yIsZero_uid51_fpSinCosXTest_q <= "1" when yIsZero_uid51_fpSinCosXTest_a = yIsZero_uid51_fpSinCosXTest_b else "0";
--ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a(DELAY,792)@19
ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => yIsZero_uid51_fpSinCosXTest_q, xout => ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvYIsZero_uid151_fpSinCosXTest(LOGICAL,150)@20
InvYIsZero_uid151_fpSinCosXTest_a <= ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q;
InvYIsZero_uid151_fpSinCosXTest_q <= not InvYIsZero_uid151_fpSinCosXTest_a;
--signRCond2_uid152_fpSinCosXTest(LOGICAL,151)@20
signRCond2_uid152_fpSinCosXTest_a <= InvYIsZero_uid151_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_b <= ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q;
signRCond2_uid152_fpSinCosXTest_c <= InvCmpYToOneMinusY_uid61_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_d <= InvCosXONe_uid149_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_q_i <= signRCond2_uid152_fpSinCosXTest_a and signRCond2_uid152_fpSinCosXTest_b and signRCond2_uid152_fpSinCosXTest_c and signRCond2_uid152_fpSinCosXTest_d;
signRCond2_uid152_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRCond2_uid152_fpSinCosXTest_q, xin => signRCond2_uid152_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--InvIntXParity_uid155_fpSinCosXTest(LOGICAL,154)@20
InvIntXParity_uid155_fpSinCosXTest_a <= ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q;
InvIntXParity_uid155_fpSinCosXTest_q <= not InvIntXParity_uid155_fpSinCosXTest_a;
--signRCond1_uid157_fpSinCosXTest(LOGICAL,156)@20
signRCond1_uid157_fpSinCosXTest_a <= InvYIsZero_uid151_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_b <= InvIntXParity_uid155_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_c <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
signRCond1_uid157_fpSinCosXTest_d <= InvCosXONe_uid149_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_q_i <= signRCond1_uid157_fpSinCosXTest_a and signRCond1_uid157_fpSinCosXTest_b and signRCond1_uid157_fpSinCosXTest_c and signRCond1_uid157_fpSinCosXTest_d;
signRCond1_uid157_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRCond1_uid157_fpSinCosXTest_q, xin => signRCond1_uid157_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--signRCos_uid158_fpSinCosXTest(LOGICAL,157)@21
signRCos_uid158_fpSinCosXTest_a <= signRCond1_uid157_fpSinCosXTest_q;
signRCos_uid158_fpSinCosXTest_b <= signRCond2_uid152_fpSinCosXTest_q;
signRCos_uid158_fpSinCosXTest_q <= signRCos_uid158_fpSinCosXTest_a or signRCos_uid158_fpSinCosXTest_b;
--cstAllZWF_uid7_fpSinCosXTest(CONSTANT,6)
cstAllZWF_uid7_fpSinCosXTest_q <= "00000000000000000000000";
--frac_uid13_fpSinCosXTest(BITSELECT,12)@0
frac_uid13_fpSinCosXTest_in <= a(22 downto 0);
frac_uid13_fpSinCosXTest_b <= frac_uid13_fpSinCosXTest_in(22 downto 0);
--fracXIsZero_uid14_fpSinCosXTest(LOGICAL,13)@0
fracXIsZero_uid14_fpSinCosXTest_a <= frac_uid13_fpSinCosXTest_b;
fracXIsZero_uid14_fpSinCosXTest_b <= cstAllZWF_uid7_fpSinCosXTest_q;
fracXIsZero_uid14_fpSinCosXTest_q <= "1" when fracXIsZero_uid14_fpSinCosXTest_a = fracXIsZero_uid14_fpSinCosXTest_b else "0";
--cstAllOWE_uid6_fpSinCosXTest(CONSTANT,5)
cstAllOWE_uid6_fpSinCosXTest_q <= "11111111";
--expXIsMax_uid12_fpSinCosXTest(LOGICAL,11)@0
expXIsMax_uid12_fpSinCosXTest_a <= exp_uid9_fpSinCosXTest_b;
expXIsMax_uid12_fpSinCosXTest_b <= cstAllOWE_uid6_fpSinCosXTest_q;
expXIsMax_uid12_fpSinCosXTest_q <= "1" when expXIsMax_uid12_fpSinCosXTest_a = expXIsMax_uid12_fpSinCosXTest_b else "0";
--exc_I_uid15_fpSinCosXTest(LOGICAL,14)@0
exc_I_uid15_fpSinCosXTest_a <= expXIsMax_uid12_fpSinCosXTest_q;
exc_I_uid15_fpSinCosXTest_b <= fracXIsZero_uid14_fpSinCosXTest_q;
exc_I_uid15_fpSinCosXTest_q <= exc_I_uid15_fpSinCosXTest_a and exc_I_uid15_fpSinCosXTest_b;
--ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a(DELAY,762)@0
ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 20 )
PORT MAP ( xin => exc_I_uid15_fpSinCosXTest_q, xout => ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_I_uid131_fpSinCosXTest(LOGICAL,130)@20
InvExc_I_uid131_fpSinCosXTest_a <= ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q;
InvExc_I_uid131_fpSinCosXTest_q <= not InvExc_I_uid131_fpSinCosXTest_a;
--reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2(REG,649)@20
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q <= InvExc_I_uid131_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--InvFracXIsZero_uid16_fpSinCosXTest(LOGICAL,15)@0
InvFracXIsZero_uid16_fpSinCosXTest_a <= fracXIsZero_uid14_fpSinCosXTest_q;
InvFracXIsZero_uid16_fpSinCosXTest_q <= not InvFracXIsZero_uid16_fpSinCosXTest_a;
--exc_N_uid17_fpSinCosXTest(LOGICAL,16)@0
exc_N_uid17_fpSinCosXTest_a <= expXIsMax_uid12_fpSinCosXTest_q;
exc_N_uid17_fpSinCosXTest_b <= InvFracXIsZero_uid16_fpSinCosXTest_q;
exc_N_uid17_fpSinCosXTest_q <= exc_N_uid17_fpSinCosXTest_a and exc_N_uid17_fpSinCosXTest_b;
--ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a(DELAY,763)@0
ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 20 )
PORT MAP ( xin => exc_N_uid17_fpSinCosXTest_q, xout => ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid132_fpSinCosXTest(LOGICAL,131)@20
InvExc_N_uid132_fpSinCosXTest_a <= ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q;
InvExc_N_uid132_fpSinCosXTest_q <= not InvExc_N_uid132_fpSinCosXTest_a;
--reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1(REG,648)@20
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q <= InvExc_N_uid132_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--signRCosFull_uid161_fpSinCosXTest(LOGICAL,160)@21
signRCosFull_uid161_fpSinCosXTest_a <= reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q;
signRCosFull_uid161_fpSinCosXTest_b <= reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q;
signRCosFull_uid161_fpSinCosXTest_c <= signRCos_uid158_fpSinCosXTest_q;
signRCosFull_uid161_fpSinCosXTest_q <= signRCosFull_uid161_fpSinCosXTest_a and signRCosFull_uid161_fpSinCosXTest_b and signRCosFull_uid161_fpSinCosXTest_c;
--ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c(DELAY,809)@21
ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signRCosFull_uid161_fpSinCosXTest_q, xout => ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid22_fpSinCosXTest(CONSTANT,21)
cstBias_uid22_fpSinCosXTest_q <= "01111111";
--ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a(DELAY,681)@19
ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 68, depth => 1 )
PORT MAP ( xin => oneMinusY_uid55_fpSinCosXTest_q, xout => ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--zSinOMyBottom_uid58_fpSinCosXTest(BITSELECT,57)@20
zSinOMyBottom_uid58_fpSinCosXTest_in <= ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q(64 downto 0);
zSinOMyBottom_uid58_fpSinCosXTest_b <= zSinOMyBottom_uid58_fpSinCosXTest_in(64 downto 0);
--reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3(REG,579)@20
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q <= zSinOMyBottom_uid58_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--zSinYBottom_uid59_fpSinCosXTest(BITSELECT,58)@20
zSinYBottom_uid59_fpSinCosXTest_in <= ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q(64 downto 0);
zSinYBottom_uid59_fpSinCosXTest_b <= zSinYBottom_uid59_fpSinCosXTest_in(64 downto 0);
--reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2(REG,578)@20
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q <= zSinYBottom_uid59_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1(REG,614)@20
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q <= InvCmpYToOneMinusY_uid61_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--zCos_uid64_fpSinCosXTest(MUX,63)@21
zCos_uid64_fpSinCosXTest_s <= reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q;
zCos_uid64_fpSinCosXTest: PROCESS (zCos_uid64_fpSinCosXTest_s, en, reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q, reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q)
BEGIN
CASE zCos_uid64_fpSinCosXTest_s IS
WHEN "0" => zCos_uid64_fpSinCosXTest_q <= reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q;
WHEN "1" => zCos_uid64_fpSinCosXTest_q <= reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q;
WHEN OTHERS => zCos_uid64_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--addr_uid83_fpSinCosXTest(BITSELECT,82)@21
addr_uid83_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q;
addr_uid83_fpSinCosXTest_b <= addr_uid83_fpSinCosXTest_in(64 downto 57);
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0(REG,630)@21
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q <= addr_uid83_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid404_tableGencosPiZ_lutmem(DUALMEM,532)@22
memoryC2_uid404_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC2_uid404_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC2_uid404_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q;
memoryC2_uid404_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC2_uid404_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid404_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid404_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid404_tableGencosPiZ_lutmem_iq,
address_a => memoryC2_uid404_tableGencosPiZ_lutmem_aa,
data_a => memoryC2_uid404_tableGencosPiZ_lutmem_ia
);
memoryC2_uid404_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC2_uid404_tableGencosPiZ_lutmem_q <= memoryC2_uid404_tableGencosPiZ_lutmem_iq(12 downto 0);
--reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1(REG,632)@24
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q <= memoryC2_uid404_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPcosPiZ_uid87_fpSinCosXTest(BITSELECT,86)@21
zPcosPiZ_uid87_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(56 downto 0);
zPcosPiZ_uid87_fpSinCosXTest_b <= zPcosPiZ_uid87_fpSinCosXTest_in(56 downto 42);
--yT1_uid419_polyEvalcosPiZ(BITSELECT,418)@21
yT1_uid419_polyEvalcosPiZ_in <= zPcosPiZ_uid87_fpSinCosXTest_b;
yT1_uid419_polyEvalcosPiZ_b <= yT1_uid419_polyEvalcosPiZ_in(14 downto 2);
--reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0(REG,631)@21
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q <= yT1_uid419_polyEvalcosPiZ_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg(DELAY,1513)
ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q, xout => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a(DELAY,1125)@22
ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q, xout => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid508_pT1_uid420_polyEvalcosPiZ(MULT,507)@25
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a),14)) * SIGNED(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b);
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a <= (others => '0');
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b <= (others => '0');
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a <= ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b <= reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q <= prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ(BITSELECT,508)@28
prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in <= prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q;
prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in(25 downto 12);
--highBBits_uid422_polyEvalcosPiZ(BITSELECT,421)@28
highBBits_uid422_polyEvalcosPiZ_in <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b;
highBBits_uid422_polyEvalcosPiZ_b <= highBBits_uid422_polyEvalcosPiZ_in(13 downto 1);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a(DELAY,1256)@21
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => addr_uid83_fpSinCosXTest_b, xout => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0(REG,633)@24
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid402_tableGencosPiZ_lutmem(DUALMEM,531)@25
memoryC1_uid402_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC1_uid402_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC1_uid402_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q;
memoryC1_uid402_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC1_uid402_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid402_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid402_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid402_tableGencosPiZ_lutmem_iq,
address_a => memoryC1_uid402_tableGencosPiZ_lutmem_aa,
data_a => memoryC1_uid402_tableGencosPiZ_lutmem_ia
);
memoryC1_uid402_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC1_uid402_tableGencosPiZ_lutmem_q <= memoryC1_uid402_tableGencosPiZ_lutmem_iq(20 downto 0);
--reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0(REG,634)@27
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q <= memoryC1_uid402_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid423_polyEvalcosPiZ(ADD,422)@28
sumAHighB_uid423_polyEvalcosPiZ_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q(20)) & reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q);
sumAHighB_uid423_polyEvalcosPiZ_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid422_polyEvalcosPiZ_b(12)) & highBBits_uid422_polyEvalcosPiZ_b);
sumAHighB_uid423_polyEvalcosPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid423_polyEvalcosPiZ_a) + SIGNED(sumAHighB_uid423_polyEvalcosPiZ_b));
sumAHighB_uid423_polyEvalcosPiZ_q <= sumAHighB_uid423_polyEvalcosPiZ_o(21 downto 0);
--lowRangeB_uid421_polyEvalcosPiZ(BITSELECT,420)@28
lowRangeB_uid421_polyEvalcosPiZ_in <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b(0 downto 0);
lowRangeB_uid421_polyEvalcosPiZ_b <= lowRangeB_uid421_polyEvalcosPiZ_in(0 downto 0);
--s1_uid421_uid424_polyEvalcosPiZ(BITJOIN,423)@28
s1_uid421_uid424_polyEvalcosPiZ_q <= sumAHighB_uid423_polyEvalcosPiZ_q & lowRangeB_uid421_polyEvalcosPiZ_b;
--reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1(REG,636)@28
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q <= s1_uid421_uid424_polyEvalcosPiZ_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor(LOGICAL,1524)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q <= not (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a or ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b);
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top(CONSTANT,1520)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q <= "0100";
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp(LOGICAL,1521)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q <= "1" when ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a = ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b else "0";
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg(REG,1522)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena(REG,1525)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd(LOGICAL,1526)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b <= en;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a and ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b;
--reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0(REG,635)@21
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q <= zPcosPiZ_uid87_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg(DELAY,1514)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q, xout => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt(COUNTER,1516)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i = 3 THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i,3));
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg(REG,1517)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux(MUX,1518)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s <= en;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux: PROCESS (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s, ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q, ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem(DUALMEM,1515)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq,
address_a => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa,
data_a => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia
);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0 <= areset;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq(14 downto 0);
--prodXY_uid511_pT2_uid426_polyEvalcosPiZ(MULT,510)@29
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a),16)) * SIGNED(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b);
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a <= (others => '0');
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b <= (others => '0');
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b <= reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q <= prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ(BITSELECT,511)@32
prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in <= prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q;
prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in(37 downto 14);
--highBBits_uid428_polyEvalcosPiZ(BITSELECT,427)@32
highBBits_uid428_polyEvalcosPiZ_in <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b;
highBBits_uid428_polyEvalcosPiZ_b <= highBBits_uid428_polyEvalcosPiZ_in(23 downto 2);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor(LOGICAL,1577)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q <= not (ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a or ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena(REG,1578)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q = "1") THEN
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd(LOGICAL,1579)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b <= en;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a and ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b;
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg(DELAY,1567)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addr_uid83_fpSinCosXTest_b, xout => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem(DUALMEM,1568)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq,
address_a => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa,
data_a => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia
);
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0(REG,637)@28
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid400_tableGencosPiZ_lutmem(DUALMEM,530)@29
memoryC0_uid400_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC0_uid400_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC0_uid400_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q;
memoryC0_uid400_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC0_uid400_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid400_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid400_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid400_tableGencosPiZ_lutmem_iq,
address_a => memoryC0_uid400_tableGencosPiZ_lutmem_aa,
data_a => memoryC0_uid400_tableGencosPiZ_lutmem_ia
);
memoryC0_uid400_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC0_uid400_tableGencosPiZ_lutmem_q <= memoryC0_uid400_tableGencosPiZ_lutmem_iq(29 downto 0);
--reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0(REG,638)@31
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q <= memoryC0_uid400_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid429_polyEvalcosPiZ(ADD,428)@32
sumAHighB_uid429_polyEvalcosPiZ_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q(29)) & reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q);
sumAHighB_uid429_polyEvalcosPiZ_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid428_polyEvalcosPiZ_b(21)) & highBBits_uid428_polyEvalcosPiZ_b);
sumAHighB_uid429_polyEvalcosPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid429_polyEvalcosPiZ_a) + SIGNED(sumAHighB_uid429_polyEvalcosPiZ_b));
sumAHighB_uid429_polyEvalcosPiZ_q <= sumAHighB_uid429_polyEvalcosPiZ_o(30 downto 0);
--lowRangeB_uid427_polyEvalcosPiZ(BITSELECT,426)@32
lowRangeB_uid427_polyEvalcosPiZ_in <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b(1 downto 0);
lowRangeB_uid427_polyEvalcosPiZ_b <= lowRangeB_uid427_polyEvalcosPiZ_in(1 downto 0);
--s2_uid427_uid430_polyEvalcosPiZ(BITJOIN,429)@32
s2_uid427_uid430_polyEvalcosPiZ_q <= sumAHighB_uid429_polyEvalcosPiZ_q & lowRangeB_uid427_polyEvalcosPiZ_b;
--polyEvalSigcosPiZ_uid89_fpSinCosXTest(BITSELECT,88)@32
polyEvalSigcosPiZ_uid89_fpSinCosXTest_in <= s2_uid427_uid430_polyEvalcosPiZ_q(30 downto 0);
polyEvalSigcosPiZ_uid89_fpSinCosXTest_b <= polyEvalSigcosPiZ_uid89_fpSinCosXTest_in(30 downto 5);
--reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1(REG,640)@32
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q <= polyEvalSigcosPiZ_uid89_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor(LOGICAL,1590)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q <= not (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a or ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b);
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top(CONSTANT,1586)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q <= "010";
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp(LOGICAL,1587)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q <= "1" when ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a = ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b else "0";
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg(REG,1588)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena(REG,1591)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd(LOGICAL,1592)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b <= en;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a and ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b;
--LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest(BITSELECT,388)@27
LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q(63 downto 0);
LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in(63 downto 0);
--leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest(BITJOIN,389)@27
leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b & GND_q;
--cstZmwFRRPwSM1_uid52_fpSinCosXTest(CONSTANT,51)
cstZmwFRRPwSM1_uid52_fpSinCosXTest_q <= "00000000000000000000000000000000000000000000000000000000000000000";
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor(LOGICAL,1455)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q <= not (ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a or ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b);
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena(REG,1456)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q = "1") THEN
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd(LOGICAL,1457)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b <= en;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a and ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b;
--X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest(BITSELECT,359)@21
X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(32 downto 0);
X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b <= X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in(32 downto 0);
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg(DELAY,1447)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem(DUALMEM,1448)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 33,
widthad_a => 1,
numwords_a => 2,
width_b => 33,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia
);
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq(32 downto 0);
--leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest(BITJOIN,360)@25
leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor(LOGICAL,1466)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q <= not (ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a or ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b);
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena(REG,1467)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q = "1") THEN
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd(LOGICAL,1468)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b <= en;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a and ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg(DELAY,1458)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => zCos_uid64_fpSinCosXTest_q, xout => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem(DUALMEM,1459)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 65,
widthad_a => 1,
numwords_a => 2,
width_b => 65,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia
);
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq(64 downto 0);
--zs_uid236_lzcZSin_uid66_fpSinCosXTest(CONSTANT,235)
zs_uid236_lzcZSin_uid66_fpSinCosXTest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--rVStage_uid316_lzcZCos_uid69_fpSinCosXTest(BITSELECT,315)@21
rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q;
rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in(64 downto 1);
--vCount_uid317_lzcZCos_uid69_fpSinCosXTest(LOGICAL,316)@21
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid236_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g(DELAY,985)@22
ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid319_lzcZCos_uid69_fpSinCosXTest(BITSELECT,318)@21
vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(0 downto 0);
vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in(0 downto 0);
--ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b(DELAY,943)@21
ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid239_lzcZSin_uid66_fpSinCosXTest(CONSTANT,238)
mO_uid239_lzcZSin_uid66_fpSinCosXTest_q <= "111111111111111111111111111111111111111111111111111111111111111";
--cStage_uid320_lzcZCos_uid69_fpSinCosXTest(BITJOIN,319)@22
cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q <= ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q & mO_uid239_lzcZSin_uid66_fpSinCosXTest_q;
--ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c(DELAY,945)@21
ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid322_lzcZCos_uid69_fpSinCosXTest(MUX,321)@22
vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid322_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s, en, ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q, cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid324_lzcZCos_uid69_fpSinCosXTest(BITSELECT,323)@22
rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in(63 downto 32);
--vCount_uid325_lzcZCos_uid69_fpSinCosXTest(LOGICAL,324)@22
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f(DELAY,984)@23
ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid326_lzcZCos_uid69_fpSinCosXTest(BITSELECT,325)@22
vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q(31 downto 0);
vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in(31 downto 0);
--ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d(DELAY,952)@22
ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c(DELAY,951)@22
ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid328_lzcZCos_uid69_fpSinCosXTest(MUX,327)@23
vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid328_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s, en, ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q, ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q)
BEGIN
CASE vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q;
WHEN OTHERS => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid330_lzcZCos_uid69_fpSinCosXTest(BITSELECT,329)@23
rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in(31 downto 16);
--vCount_uid331_lzcZCos_uid69_fpSinCosXTest(LOGICAL,330)@23
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b else "0";
--reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4(REG,622)@23
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q <= vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e(DELAY,983)@24
ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid332_lzcZCos_uid69_fpSinCosXTest(BITSELECT,331)@23
vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q(15 downto 0);
vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in(15 downto 0);
--vStagei_uid334_lzcZCos_uid69_fpSinCosXTest(MUX,333)@23
vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid334_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s, en, rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b, vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b;
WHEN "1" => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid336_lzcZCos_uid69_fpSinCosXTest(BITSELECT,335)@23
rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in(15 downto 8);
--reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1(REG,617)@23
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q <= rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid337_lzcZCos_uid69_fpSinCosXTest(LOGICAL,336)@24
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a <= reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q;
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b else "0";
--ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d(DELAY,982)@24
ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid338_lzcZCos_uid69_fpSinCosXTest(BITSELECT,337)@23
vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q(7 downto 0);
vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3(REG,619)@23
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q <= vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid340_lzcZCos_uid69_fpSinCosXTest(MUX,339)@24
vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid340_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s, en, reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q, reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid342_lzcZCos_uid69_fpSinCosXTest(BITSELECT,341)@24
rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in(7 downto 4);
--vCount_uid343_lzcZCos_uid69_fpSinCosXTest(LOGICAL,342)@24
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid344_lzcZCos_uid69_fpSinCosXTest(BITSELECT,343)@24
vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q(3 downto 0);
vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in(3 downto 0);
--reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3(REG,621)@24
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q <= vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2(REG,620)@24
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid346_lzcZCos_uid69_fpSinCosXTest(MUX,345)@25
vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid346_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s, en, reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q, reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid348_lzcZCos_uid69_fpSinCosXTest(BITSELECT,347)@25
rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in(3 downto 2);
--vCount_uid349_lzcZCos_uid69_fpSinCosXTest(LOGICAL,348)@25
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b else "0";
--vStage_uid350_lzcZCos_uid69_fpSinCosXTest(BITSELECT,349)@25
vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q(1 downto 0);
vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in(1 downto 0);
--vStagei_uid352_lzcZCos_uid69_fpSinCosXTest(MUX,351)@25
vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid352_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s, en, rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b, vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b;
WHEN "1" => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid354_lzcZCos_uid69_fpSinCosXTest(BITSELECT,353)@25
rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in(1 downto 1);
--vCount_uid355_lzcZCos_uid69_fpSinCosXTest(LOGICAL,354)@25
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b <= GND_q;
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b else "0";
--r_uid356_lzcZCos_uid69_fpSinCosXTest(BITJOIN,355)@25
r_uid356_lzcZCos_uid69_fpSinCosXTest_q <= ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q & ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q & ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q & ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q & vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q & vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q & vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q;
--leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest(BITSELECT,363)@25
leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q;
leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in(6 downto 5);
--leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest(MUX,364)@25
leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s <= leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b;
leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s, en, ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest(BITSELECT,372)@25
LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(40 downto 0);
LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in(40 downto 0);
--leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest(CONSTANT,292)
leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q <= "000000000000000000000000";
--leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest(BITJOIN,373)@25
leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b & leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5(REG,627)@25
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest(BITSELECT,369)@25
LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(48 downto 0);
LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in(48 downto 0);
--leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest(BITJOIN,370)@25
leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4(REG,626)@25
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest(BITSELECT,366)@25
LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(56 downto 0);
LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in(56 downto 0);
--leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest(BITJOIN,367)@25
leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3(REG,625)@25
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2(REG,624)@25
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest(BITSELECT,374)@25
leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1(REG,623)@25
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q <= leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest(MUX,375)@26
leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s <= reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q;
leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s, en, reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest(BITSELECT,383)@26
LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(58 downto 0);
LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1009)@26
ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest(CONSTANT,303)
leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q <= "000000";
--leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest(BITJOIN,384)@27
leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q;
--LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest(BITSELECT,380)@26
LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(60 downto 0);
LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1007)@26
ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest(BITJOIN,381)@27
leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest(BITSELECT,377)@26
LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(62 downto 0);
LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in(62 downto 0);
--ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1005)@26
ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest(BITJOIN,378)@27
leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2(REG,629)@26
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest(BITSELECT,385)@25
leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1(REG,628)@25
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q <= leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1011)@26
ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest(MUX,386)@27
leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s <= ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q;
leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s, en, reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest(BITSELECT,390)@25
leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1019)@25
ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest(MUX,391)@27
leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s <= ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q;
leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s, en, leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "0" => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "1" => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--pCos_uid77_fpSinCosXTest(BITSELECT,76)@27
pCos_uid77_fpSinCosXTest_in <= leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q;
pCos_uid77_fpSinCosXTest_b <= pCos_uid77_fpSinCosXTest_in(64 downto 39);
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg(DELAY,1580)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => pCos_uid77_fpSinCosXTest_b, xout => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt(COUNTER,1582)
-- every=1, low=0, high=2, step=1, init=1
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i = 1 THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i - 2;
ELSE
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i,2));
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg(REG,1583)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux(MUX,1584)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s <= en;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux: PROCESS (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s, ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q, ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q)
BEGIN
CASE ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s IS
WHEN "0" => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q;
WHEN "1" => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem(DUALMEM,1581)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 2,
numwords_a => 3,
width_b => 26,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq,
address_a => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa,
data_a => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia
);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0 <= areset;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq(25 downto 0);
--reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0(REG,639)@32
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--mulCos_uid105_fpSinCosXTest(MULT,104)@33
mulCos_uid105_fpSinCosXTest_pr <= UNSIGNED(mulCos_uid105_fpSinCosXTest_a) * UNSIGNED(mulCos_uid105_fpSinCosXTest_b);
mulCos_uid105_fpSinCosXTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulCos_uid105_fpSinCosXTest_a <= (others => '0');
mulCos_uid105_fpSinCosXTest_b <= (others => '0');
mulCos_uid105_fpSinCosXTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulCos_uid105_fpSinCosXTest_a <= reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q;
mulCos_uid105_fpSinCosXTest_b <= reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q;
mulCos_uid105_fpSinCosXTest_s1 <= STD_LOGIC_VECTOR(mulCos_uid105_fpSinCosXTest_pr);
END IF;
END IF;
END PROCESS;
mulCos_uid105_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulCos_uid105_fpSinCosXTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulCos_uid105_fpSinCosXTest_q <= mulCos_uid105_fpSinCosXTest_s1;
END IF;
END IF;
END PROCESS;
--normBitCos_uid106_fpSinCosXTest(BITSELECT,105)@36
normBitCos_uid106_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q;
normBitCos_uid106_fpSinCosXTest_b <= normBitCos_uid106_fpSinCosXTest_in(51 downto 51);
--cosRndOp_uid112_uid113_fpSinCosXTest(BITJOIN,112)@36
cosRndOp_uid112_uid113_fpSinCosXTest_q <= normBitCos_uid106_fpSinCosXTest_b & cstAllZWF_uid7_fpSinCosXTest_q & VCC_q;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor(LOGICAL,1296)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q <= not (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a or ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b);
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top(CONSTANT,1292)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q <= "0110";
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp(LOGICAL,1293)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q <= "1" when ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a = ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b else "0";
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg(REG,1294)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena(REG,1297)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd(LOGICAL,1298)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b <= en;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a and ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b;
--reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1(REG,641)@25
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg(DELAY,1286)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q, xout => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt(COUNTER,1288)
-- every=1, low=0, high=6, step=1, init=1
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i = 5 THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i - 6;
ELSE
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i,3));
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg(REG,1289)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux(MUX,1290)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s <= en;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux: PROCESS (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s, ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q, ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem(DUALMEM,1287)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 7,
width_b => 7,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia
);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq(6 downto 0);
--expHardCase_uid78_fpSinCosXTest(SUB,77)@35
expHardCase_uid78_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expHardCase_uid78_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q);
expHardCase_uid78_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid78_fpSinCosXTest_a) - UNSIGNED(expHardCase_uid78_fpSinCosXTest_b));
expHardCase_uid78_fpSinCosXTest_q <= expHardCase_uid78_fpSinCosXTest_o(8 downto 0);
--expPCos_uid79_fpSinCosXTest(BITSELECT,78)@35
expPCos_uid79_fpSinCosXTest_in <= expHardCase_uid78_fpSinCosXTest_q(7 downto 0);
expPCos_uid79_fpSinCosXTest_b <= expPCos_uid79_fpSinCosXTest_in(7 downto 0);
--reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1(REG,642)@35
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q <= expPCos_uid79_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--fracRCosPreRndHigh_uid108_fpSinCosXTest(BITSELECT,107)@36
fracRCosPreRndHigh_uid108_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q(50 downto 0);
fracRCosPreRndHigh_uid108_fpSinCosXTest_b <= fracRCosPreRndHigh_uid108_fpSinCosXTest_in(50 downto 27);
--fracRCosPreRndLow_uid109_fpSinCosXTest(BITSELECT,108)@36
fracRCosPreRndLow_uid109_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q(49 downto 0);
fracRCosPreRndLow_uid109_fpSinCosXTest_b <= fracRCosPreRndLow_uid109_fpSinCosXTest_in(49 downto 26);
--fracRCosPreRnd_uid110_fpSinCosXTest(MUX,109)@36
fracRCosPreRnd_uid110_fpSinCosXTest_s <= normBitCos_uid106_fpSinCosXTest_b;
fracRCosPreRnd_uid110_fpSinCosXTest: PROCESS (fracRCosPreRnd_uid110_fpSinCosXTest_s, en, fracRCosPreRndLow_uid109_fpSinCosXTest_b, fracRCosPreRndHigh_uid108_fpSinCosXTest_b)
BEGIN
CASE fracRCosPreRnd_uid110_fpSinCosXTest_s IS
WHEN "0" => fracRCosPreRnd_uid110_fpSinCosXTest_q <= fracRCosPreRndLow_uid109_fpSinCosXTest_b;
WHEN "1" => fracRCosPreRnd_uid110_fpSinCosXTest_q <= fracRCosPreRndHigh_uid108_fpSinCosXTest_b;
WHEN OTHERS => fracRCosPreRnd_uid110_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracRCosPreRnd_uid111_uid111_fpSinCosXTest(BITJOIN,110)@36
expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q <= reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q & fracRCosPreRnd_uid110_fpSinCosXTest_q;
--expFracRCos_uid114_fpSinCosXTest(ADD,113)@36
expFracRCos_uid114_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q);
expFracRCos_uid114_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00000000" & cosRndOp_uid112_uid113_fpSinCosXTest_q);
expFracRCos_uid114_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRCos_uid114_fpSinCosXTest_a) + UNSIGNED(expFracRCos_uid114_fpSinCosXTest_b));
expFracRCos_uid114_fpSinCosXTest_q <= expFracRCos_uid114_fpSinCosXTest_o(32 downto 0);
--expRCompSin_uid116_fpSinCosXTest(BITSELECT,115)@36
expRCompSin_uid116_fpSinCosXTest_in <= expFracRCos_uid114_fpSinCosXTest_q(31 downto 0);
expRCompSin_uid116_fpSinCosXTest_b <= expRCompSin_uid116_fpSinCosXTest_in(31 downto 24);
--reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2(REG,646)@36
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q <= expRCompSin_uid116_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor(LOGICAL,1385)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q <= not (ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a or ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top(CONSTANT,1305)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q <= "01101";
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp(LOGICAL,1306)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q <= "1" when ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a = ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b else "0";
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg(REG,1307)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena(REG,1386)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q = "1") THEN
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd(LOGICAL,1387)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b <= en;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a and ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b;
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a(DELAY,745)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c(DELAY,783)@16
ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => cosXIsOneXRR_uid42_fpSinCosXTest_n, xout => ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--InvCosXIsOneXRR_uid136_fpSinCosXTest(LOGICAL,135)@16
InvCosXIsOneXRR_uid136_fpSinCosXTest_a <= cosXIsOneXRR_uid42_fpSinCosXTest_n;
InvCosXIsOneXRR_uid136_fpSinCosXTest_q <= not InvCosXIsOneXRR_uid136_fpSinCosXTest_a;
--ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c(DELAY,773)@16
ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => InvCosXIsOneXRR_uid136_fpSinCosXTest_q, xout => ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a(DELAY,755)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsX_uid127_fpSinCosXTest(LOGICAL,126)@18
InvSinXIsX_uid127_fpSinCosXTest_a <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q;
InvSinXIsX_uid127_fpSinCosXTest_q <= not InvSinXIsX_uid127_fpSinCosXTest_a;
--ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b(DELAY,772)@18
ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => InvSinXIsX_uid127_fpSinCosXTest_q, xout => ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--half_uid53_fpSinCosXTest(BITJOIN,52)@19
half_uid53_fpSinCosXTest_q <= VCC_q & cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
--yIsHalf_uid54_fpSinCosXTest(LOGICAL,53)@19
yIsHalf_uid54_fpSinCosXTest_a <= reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q;
yIsHalf_uid54_fpSinCosXTest_b <= half_uid53_fpSinCosXTest_q;
yIsHalf_uid54_fpSinCosXTest_q <= "1" when yIsHalf_uid54_fpSinCosXTest_a = yIsHalf_uid54_fpSinCosXTest_b else "0";
--yHalfCosXNotOne_uid138_fpSinCosXTest(LOGICAL,137)@19
yHalfCosXNotOne_uid138_fpSinCosXTest_a <= yIsHalf_uid54_fpSinCosXTest_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_b <= ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_c <= ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_q <= yHalfCosXNotOne_uid138_fpSinCosXTest_a and yHalfCosXNotOne_uid138_fpSinCosXTest_b and yHalfCosXNotOne_uid138_fpSinCosXTest_c;
--ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b(DELAY,744)@0
ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => exc_I_uid15_fpSinCosXTest_q, xout => ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a(DELAY,743)@0
ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => exc_N_uid17_fpSinCosXTest_q, xout => ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRNaN_uid117_fpSinCosXTest(LOGICAL,116)@19
excRNaN_uid117_fpSinCosXTest_a <= ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q;
excRNaN_uid117_fpSinCosXTest_b <= ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q;
excRNaN_uid117_fpSinCosXTest_q <= excRNaN_uid117_fpSinCosXTest_a or excRNaN_uid117_fpSinCosXTest_b;
--join_uid143_fpSinCosXTest(BITJOIN,142)@19
join_uid143_fpSinCosXTest_q <= ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q & yHalfCosXNotOne_uid138_fpSinCosXTest_q & excRNaN_uid117_fpSinCosXTest_q;
--expSelBitsCos_uid144_fpSinCosXTest(BITJOIN,143)@19
expSelBitsCos_uid144_fpSinCosXTest_q <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q & join_uid143_fpSinCosXTest_q;
--reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0(REG,645)@19
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q <= expSelBitsCos_uid144_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--expSelectorCos_uid145_fpSinCosXTest(LOOKUP,144)@20
expSelectorCos_uid145_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSelectorCos_uid145_fpSinCosXTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q) IS
WHEN "0000" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "0001" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "0010" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "0011" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "0100" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "0101" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "0110" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "0111" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "1000" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "1001" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "1010" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "1011" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "1100" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "1101" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "1110" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "1111" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN OTHERS =>
expSelectorCos_uid145_fpSinCosXTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg(DELAY,1375)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => expSelectorCos_uid145_fpSinCosXTest_q, xout => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt(COUNTER,1301)
-- every=1, low=0, high=13, step=1, init=1
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i = 12 THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i - 13;
ELSE
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg(REG,1302)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux(MUX,1303)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s, ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q, ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem(DUALMEM,1376)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia
);
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq(1 downto 0);
--expRPostExcCos_uid147_fpSinCosXTest(MUX,146)@37
expRPostExcCos_uid147_fpSinCosXTest_s <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q;
expRPostExcCos_uid147_fpSinCosXTest: PROCESS (expRPostExcCos_uid147_fpSinCosXTest_s, en, reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q, cstBias_uid22_fpSinCosXTest_q, cstAllZWE_uid8_fpSinCosXTest_q, cstAllOWE_uid6_fpSinCosXTest_q)
BEGIN
CASE expRPostExcCos_uid147_fpSinCosXTest_s IS
WHEN "00" => expRPostExcCos_uid147_fpSinCosXTest_q <= reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q;
WHEN "01" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstBias_uid22_fpSinCosXTest_q;
WHEN "10" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstAllZWE_uid8_fpSinCosXTest_q;
WHEN "11" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstAllOWE_uid6_fpSinCosXTest_q;
WHEN OTHERS => expRPostExcCos_uid147_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstNaNwF_uid32_fpSinCosXTest(CONSTANT,31)
cstNaNwF_uid32_fpSinCosXTest_q <= "00000000000000000000001";
--fracRCompCos_uid115_fpSinCosXTest(BITSELECT,114)@36
fracRCompCos_uid115_fpSinCosXTest_in <= expFracRCos_uid114_fpSinCosXTest_q(23 downto 0);
fracRCompCos_uid115_fpSinCosXTest_b <= fracRCompCos_uid115_fpSinCosXTest_in(23 downto 1);
--reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2(REG,644)@36
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q <= fracRCompCos_uid115_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor(LOGICAL,1372)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q <= not (ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a or ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b);
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena(REG,1373)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q = "1") THEN
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd(LOGICAL,1374)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b <= en;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a and ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b;
--reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1(REG,613)@19
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q <= excRNaN_uid117_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3(REG,612)@19
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q <= ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q;
END IF;
END IF;
END PROCESS;
--reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2(REG,611)@19
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q;
END IF;
END IF;
END PROCESS;
--reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1(REG,610)@19
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q <= yHalfCosXNotOne_uid138_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--rZOrOne_uid140_fpSinCosXTest(LOGICAL,139)@20
rZOrOne_uid140_fpSinCosXTest_a <= reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q;
rZOrOne_uid140_fpSinCosXTest_b <= reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q;
rZOrOne_uid140_fpSinCosXTest_c <= reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q;
rZOrOne_uid140_fpSinCosXTest_q <= rZOrOne_uid140_fpSinCosXTest_a or rZOrOne_uid140_fpSinCosXTest_b or rZOrOne_uid140_fpSinCosXTest_c;
--join_uid141_fpSinCosXTest(BITJOIN,140)@20
join_uid141_fpSinCosXTest_q <= reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q & rZOrOne_uid140_fpSinCosXTest_q;
--reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1(REG,643)@20
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q <= join_uid141_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg(DELAY,1362)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q, xout => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem(DUALMEM,1363)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia
);
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq(1 downto 0);
--fracRPostExcCos_uid142_fpSinCosXTest(MUX,141)@37
fracRPostExcCos_uid142_fpSinCosXTest_s <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q;
fracRPostExcCos_uid142_fpSinCosXTest: PROCESS (fracRPostExcCos_uid142_fpSinCosXTest_s, en, reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q, cstAllZWF_uid7_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q)
BEGIN
CASE fracRPostExcCos_uid142_fpSinCosXTest_s IS
WHEN "00" => fracRPostExcCos_uid142_fpSinCosXTest_q <= reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q;
WHEN "01" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstAllZWF_uid7_fpSinCosXTest_q;
WHEN "10" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN "11" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN OTHERS => fracRPostExcCos_uid142_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpCos_uid162_fpSinCosXTest(BITJOIN,161)@37
fpCos_uid162_fpSinCosXTest_q <= ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q & expRPostExcCos_uid147_fpSinCosXTest_q & fracRPostExcCos_uid142_fpSinCosXTest_q;
--cstBiasMwShiftM2_uid25_fpSinCosXTest(CONSTANT,24)
cstBiasMwShiftM2_uid25_fpSinCosXTest_q <= "01110001";
--sinXIsXRR_uid41_fpSinCosXTest(COMPARE,40)@16
sinXIsXRR_uid41_fpSinCosXTest_cin <= GND_q;
sinXIsXRR_uid41_fpSinCosXTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid25_fpSinCosXTest_q) & '0';
sinXIsXRR_uid41_fpSinCosXTest_b <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q) & sinXIsXRR_uid41_fpSinCosXTest_cin(0);
sinXIsXRR_uid41_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(sinXIsXRR_uid41_fpSinCosXTest_a) - SIGNED(sinXIsXRR_uid41_fpSinCosXTest_b));
sinXIsXRR_uid41_fpSinCosXTest_n(0) <= not sinXIsXRR_uid41_fpSinCosXTest_o(11);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a(DELAY,756)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsXRR_uid128_fpSinCosXTest(LOGICAL,127)@18
InvSinXIsXRR_uid128_fpSinCosXTest_a <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q;
InvSinXIsXRR_uid128_fpSinCosXTest_q <= not InvSinXIsXRR_uid128_fpSinCosXTest_a;
--signComp_uid129_fpSinCosXTest(LOGICAL,128)@18
signComp_uid129_fpSinCosXTest_a <= InvSinXIsXRR_uid128_fpSinCosXTest_q;
signComp_uid129_fpSinCosXTest_b <= InvSinXIsX_uid127_fpSinCosXTest_q;
signComp_uid129_fpSinCosXTest_c <= intXParity_uid49_fpSinCosXTest_b;
signComp_uid129_fpSinCosXTest_q <= signComp_uid129_fpSinCosXTest_a and signComp_uid129_fpSinCosXTest_b and signComp_uid129_fpSinCosXTest_c;
--signX_uid37_fpSinCosXTest(BITSELECT,36)@0
signX_uid37_fpSinCosXTest_in <= a;
signX_uid37_fpSinCosXTest_b <= signX_uid37_fpSinCosXTest_in(31 downto 31);
--ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a(DELAY,760)@0
ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => signX_uid37_fpSinCosXTest_b, xout => ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid130_fpSinCosXTest(LOGICAL,129)@18
signR_uid130_fpSinCosXTest_a <= ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q;
signR_uid130_fpSinCosXTest_b <= signComp_uid129_fpSinCosXTest_q;
signR_uid130_fpSinCosXTest_q <= signR_uid130_fpSinCosXTest_a xor signR_uid130_fpSinCosXTest_b;
--ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c(DELAY,766)@18
ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => signR_uid130_fpSinCosXTest_q, xout => ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--signRSinFull_uid133_fpSinCosXTest(LOGICAL,132)@20
signRSinFull_uid133_fpSinCosXTest_a <= InvExc_N_uid132_fpSinCosXTest_q;
signRSinFull_uid133_fpSinCosXTest_b <= InvExc_I_uid131_fpSinCosXTest_q;
signRSinFull_uid133_fpSinCosXTest_c <= ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q;
signRSinFull_uid133_fpSinCosXTest_q_i <= signRSinFull_uid133_fpSinCosXTest_a and signRSinFull_uid133_fpSinCosXTest_b and signRSinFull_uid133_fpSinCosXTest_c;
signRSinFull_uid133_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRSinFull_uid133_fpSinCosXTest_q, xin => signRSinFull_uid133_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c(DELAY,769)@21
ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signRSinFull_uid133_fpSinCosXTest_q, xout => ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor(LOGICAL,1359)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q <= not (ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a or ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b);
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top(CONSTANT,1342)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q <= "0100010";
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp(LOGICAL,1343)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q <= "1" when ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a = ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b else "0";
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg(REG,1344)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena(REG,1360)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q = "1") THEN
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd(LOGICAL,1361)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b <= en;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a and ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg(DELAY,1349)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => exp_uid9_fpSinCosXTest_b, xout => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt(COUNTER,1338)
-- every=1, low=0, high=34, step=1, init=1
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i = 33 THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i - 34;
ELSE
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i,6));
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg(REG,1339)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux(MUX,1340)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem(DUALMEM,1350)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 6,
numwords_a => 35,
width_b => 8,
widthad_b => 6,
numwords_b => 35,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia
);
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a(DELAY,1228)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1(REG,605)@35
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor(LOGICAL,1309)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q <= not (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a or ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena(REG,1310)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd(LOGICAL,1311)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b <= en;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a and ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b;
--oFracXRRSmallXRR_uid90_fpSinCosXTest(BITSELECT,89)@16
oFracXRRSmallXRR_uid90_fpSinCosXTest_in <= oFracXRR_uid43_uid43_fpSinCosXTest_q;
oFracXRRSmallXRR_uid90_fpSinCosXTest_b <= oFracXRRSmallXRR_uid90_fpSinCosXTest_in(53 downto 28);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg(DELAY,1299)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => oFracXRRSmallXRR_uid90_fpSinCosXTest_b, xout => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem(DUALMEM,1300)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 4,
numwords_a => 14,
width_b => 26,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia
);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq(25 downto 0);
--reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1(REG,577)@20
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
END IF;
END IF;
END PROCESS;
--zSin_uid60_fpSinCosXTest(MUX,59)@21
zSin_uid60_fpSinCosXTest_s <= reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q;
zSin_uid60_fpSinCosXTest: PROCESS (zSin_uid60_fpSinCosXTest_s, en, reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q, reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q)
BEGIN
CASE zSin_uid60_fpSinCosXTest_s IS
WHEN "0" => zSin_uid60_fpSinCosXTest_q <= reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q;
WHEN "1" => zSin_uid60_fpSinCosXTest_q <= reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q;
WHEN OTHERS => zSin_uid60_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--addr_uid81_fpSinCosXTest(BITSELECT,80)@21
addr_uid81_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q;
addr_uid81_fpSinCosXTest_b <= addr_uid81_fpSinCosXTest_in(64 downto 57);
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0(REG,595)@21
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q <= addr_uid81_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid398_tableGensinPiZ_lutmem(DUALMEM,529)@22
memoryC2_uid398_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC2_uid398_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC2_uid398_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q;
memoryC2_uid398_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC2_uid398_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid398_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid398_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid398_tableGensinPiZ_lutmem_iq,
address_a => memoryC2_uid398_tableGensinPiZ_lutmem_aa,
data_a => memoryC2_uid398_tableGensinPiZ_lutmem_ia
);
memoryC2_uid398_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC2_uid398_tableGensinPiZ_lutmem_q <= memoryC2_uid398_tableGensinPiZ_lutmem_iq(12 downto 0);
--reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1(REG,597)@24
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q <= memoryC2_uid398_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPsinPiZ_uid84_fpSinCosXTest(BITSELECT,83)@21
zPsinPiZ_uid84_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(56 downto 0);
zPsinPiZ_uid84_fpSinCosXTest_b <= zPsinPiZ_uid84_fpSinCosXTest_in(56 downto 42);
--yT1_uid406_polyEvalsinPiZ(BITSELECT,405)@21
yT1_uid406_polyEvalsinPiZ_in <= zPsinPiZ_uid84_fpSinCosXTest_b;
yT1_uid406_polyEvalsinPiZ_b <= yT1_uid406_polyEvalsinPiZ_in(14 downto 2);
--ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg(DELAY,1540)
ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => yT1_uid406_polyEvalsinPiZ_b, xout => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a(DELAY,1219)@21
ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q, xout => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0(REG,596)@24
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q <= ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid502_pT1_uid407_polyEvalsinPiZ(MULT,501)@25
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a),14)) * SIGNED(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b);
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a <= (others => '0');
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b <= (others => '0');
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a <= reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b <= reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q <= prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ(BITSELECT,502)@28
prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in <= prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q;
prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in(25 downto 12);
--highBBits_uid409_polyEvalsinPiZ(BITSELECT,408)@28
highBBits_uid409_polyEvalsinPiZ_in <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b;
highBBits_uid409_polyEvalsinPiZ_b <= highBBits_uid409_polyEvalsinPiZ_in(13 downto 1);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a(DELAY,1221)@21
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => addr_uid81_fpSinCosXTest_b, xout => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0(REG,598)@24
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid396_tableGensinPiZ_lutmem(DUALMEM,528)@25
memoryC1_uid396_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC1_uid396_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC1_uid396_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q;
memoryC1_uid396_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC1_uid396_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid396_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid396_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid396_tableGensinPiZ_lutmem_iq,
address_a => memoryC1_uid396_tableGensinPiZ_lutmem_aa,
data_a => memoryC1_uid396_tableGensinPiZ_lutmem_ia
);
memoryC1_uid396_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC1_uid396_tableGensinPiZ_lutmem_q <= memoryC1_uid396_tableGensinPiZ_lutmem_iq(20 downto 0);
--reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0(REG,599)@27
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q <= memoryC1_uid396_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid410_polyEvalsinPiZ(ADD,409)@28
sumAHighB_uid410_polyEvalsinPiZ_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q(20)) & reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q);
sumAHighB_uid410_polyEvalsinPiZ_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid409_polyEvalsinPiZ_b(12)) & highBBits_uid409_polyEvalsinPiZ_b);
sumAHighB_uid410_polyEvalsinPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid410_polyEvalsinPiZ_a) + SIGNED(sumAHighB_uid410_polyEvalsinPiZ_b));
sumAHighB_uid410_polyEvalsinPiZ_q <= sumAHighB_uid410_polyEvalsinPiZ_o(21 downto 0);
--lowRangeB_uid408_polyEvalsinPiZ(BITSELECT,407)@28
lowRangeB_uid408_polyEvalsinPiZ_in <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b(0 downto 0);
lowRangeB_uid408_polyEvalsinPiZ_b <= lowRangeB_uid408_polyEvalsinPiZ_in(0 downto 0);
--s1_uid408_uid411_polyEvalsinPiZ(BITJOIN,410)@28
s1_uid408_uid411_polyEvalsinPiZ_q <= sumAHighB_uid410_polyEvalsinPiZ_q & lowRangeB_uid408_polyEvalsinPiZ_b;
--reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1(REG,601)@28
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q <= s1_uid408_uid411_polyEvalsinPiZ_q;
END IF;
END IF;
END PROCESS;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor(LOGICAL,1551)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q <= not (ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a or ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b);
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena(REG,1552)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q = "1") THEN
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd(LOGICAL,1553)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b <= en;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a and ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg(DELAY,1541)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => zPsinPiZ_uid84_fpSinCosXTest_b, xout => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem(DUALMEM,1542)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq,
address_a => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa,
data_a => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia
);
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0 <= areset;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq(14 downto 0);
--reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0(REG,600)@28
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid505_pT2_uid413_polyEvalsinPiZ(MULT,504)@29
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a),16)) * SIGNED(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b);
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a <= (others => '0');
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b <= (others => '0');
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a <= reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b <= reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q <= prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ(BITSELECT,505)@32
prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in <= prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q;
prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in(37 downto 14);
--highBBits_uid415_polyEvalsinPiZ(BITSELECT,414)@32
highBBits_uid415_polyEvalsinPiZ_in <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b;
highBBits_uid415_polyEvalsinPiZ_b <= highBBits_uid415_polyEvalsinPiZ_in(23 downto 2);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor(LOGICAL,1564)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q <= not (ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a or ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena(REG,1565)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q = "1") THEN
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd(LOGICAL,1566)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b <= en;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a and ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b;
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg(DELAY,1554)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addr_uid81_fpSinCosXTest_b, xout => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem(DUALMEM,1555)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq,
address_a => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa,
data_a => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia
);
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0(REG,602)@28
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid394_tableGensinPiZ_lutmem(DUALMEM,527)@29
memoryC0_uid394_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC0_uid394_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC0_uid394_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q;
memoryC0_uid394_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC0_uid394_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid394_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid394_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid394_tableGensinPiZ_lutmem_iq,
address_a => memoryC0_uid394_tableGensinPiZ_lutmem_aa,
data_a => memoryC0_uid394_tableGensinPiZ_lutmem_ia
);
memoryC0_uid394_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC0_uid394_tableGensinPiZ_lutmem_q <= memoryC0_uid394_tableGensinPiZ_lutmem_iq(29 downto 0);
--reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0(REG,603)@31
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q <= memoryC0_uid394_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid416_polyEvalsinPiZ(ADD,415)@32
sumAHighB_uid416_polyEvalsinPiZ_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q(29)) & reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q);
sumAHighB_uid416_polyEvalsinPiZ_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid415_polyEvalsinPiZ_b(21)) & highBBits_uid415_polyEvalsinPiZ_b);
sumAHighB_uid416_polyEvalsinPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid416_polyEvalsinPiZ_a) + SIGNED(sumAHighB_uid416_polyEvalsinPiZ_b));
sumAHighB_uid416_polyEvalsinPiZ_q <= sumAHighB_uid416_polyEvalsinPiZ_o(30 downto 0);
--lowRangeB_uid414_polyEvalsinPiZ(BITSELECT,413)@32
lowRangeB_uid414_polyEvalsinPiZ_in <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b(1 downto 0);
lowRangeB_uid414_polyEvalsinPiZ_b <= lowRangeB_uid414_polyEvalsinPiZ_in(1 downto 0);
--s2_uid414_uid417_polyEvalsinPiZ(BITJOIN,416)@32
s2_uid414_uid417_polyEvalsinPiZ_q <= sumAHighB_uid416_polyEvalsinPiZ_q & lowRangeB_uid414_polyEvalsinPiZ_b;
--polyEvalSigsinPiZ_uid86_fpSinCosXTest(BITSELECT,85)@32
polyEvalSigsinPiZ_uid86_fpSinCosXTest_in <= s2_uid414_uid417_polyEvalsinPiZ_q(30 downto 0);
polyEvalSigsinPiZ_uid86_fpSinCosXTest_b <= polyEvalSigsinPiZ_uid86_fpSinCosXTest_in(30 downto 5);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b(DELAY,708)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--multSinOp2_uid91_fpSinCosXTest(MUX,90)@32
multSinOp2_uid91_fpSinCosXTest_s <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q;
multSinOp2_uid91_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSinOp2_uid91_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE multSinOp2_uid91_fpSinCosXTest_s IS
WHEN "0" => multSinOp2_uid91_fpSinCosXTest_q <= polyEvalSigsinPiZ_uid86_fpSinCosXTest_b;
WHEN "1" => multSinOp2_uid91_fpSinCosXTest_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => multSinOp2_uid91_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor(LOGICAL,1320)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q <= not (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a or ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b);
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena(REG,1321)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd(LOGICAL,1322)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b <= en;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a and ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b;
--cPi_uid71_fpSinCosXTest(CONSTANT,70)
cPi_uid71_fpSinCosXTest_q <= "11001001000011111101101011";
--LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest(BITSELECT,309)@27
LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q(63 downto 0);
LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in(63 downto 0);
--leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest(BITJOIN,310)@27
leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b & GND_q;
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor(LOGICAL,1433)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q <= not (ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a or ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b);
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena(REG,1434)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q = "1") THEN
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd(LOGICAL,1435)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b <= en;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a and ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b;
--X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest(BITSELECT,280)@21
X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(32 downto 0);
X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b <= X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in(32 downto 0);
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg(DELAY,1425)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem(DUALMEM,1426)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 33,
widthad_a => 1,
numwords_a => 2,
width_b => 33,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia
);
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq(32 downto 0);
--leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest(BITJOIN,281)@25
leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor(LOGICAL,1444)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q <= not (ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a or ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b);
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena(REG,1445)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q = "1") THEN
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd(LOGICAL,1446)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b <= en;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a and ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg(DELAY,1436)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => zSin_uid60_fpSinCosXTest_q, xout => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem(DUALMEM,1437)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 65,
widthad_a => 1,
numwords_a => 2,
width_b => 65,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia
);
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq(64 downto 0);
--rVStage_uid237_lzcZSin_uid66_fpSinCosXTest(BITSELECT,236)@21
rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q;
rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in(64 downto 1);
--vCount_uid238_lzcZSin_uid66_fpSinCosXTest(LOGICAL,237)@21
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid236_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g(DELAY,903)@22
ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid240_lzcZSin_uid66_fpSinCosXTest(BITSELECT,239)@21
vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(0 downto 0);
vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in(0 downto 0);
--ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b(DELAY,861)@21
ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cStage_uid241_lzcZSin_uid66_fpSinCosXTest(BITJOIN,240)@22
cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q <= ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q & mO_uid239_lzcZSin_uid66_fpSinCosXTest_q;
--ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c(DELAY,863)@21
ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid243_lzcZSin_uid66_fpSinCosXTest(MUX,242)@22
vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid243_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s, en, ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q, cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid245_lzcZSin_uid66_fpSinCosXTest(BITSELECT,244)@22
rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in(63 downto 32);
--vCount_uid246_lzcZSin_uid66_fpSinCosXTest(LOGICAL,245)@22
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f(DELAY,902)@23
ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid247_lzcZSin_uid66_fpSinCosXTest(BITSELECT,246)@22
vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q(31 downto 0);
vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in(31 downto 0);
--ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d(DELAY,870)@22
ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c(DELAY,869)@22
ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid249_lzcZSin_uid66_fpSinCosXTest(MUX,248)@23
vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid249_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s, en, ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q, ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q)
BEGIN
CASE vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q;
WHEN OTHERS => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid251_lzcZSin_uid66_fpSinCosXTest(BITSELECT,250)@23
rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in(31 downto 16);
--vCount_uid252_lzcZSin_uid66_fpSinCosXTest(LOGICAL,251)@23
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b else "0";
--reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4(REG,585)@23
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q <= vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e(DELAY,901)@24
ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid253_lzcZSin_uid66_fpSinCosXTest(BITSELECT,252)@23
vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q(15 downto 0);
vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in(15 downto 0);
--vStagei_uid255_lzcZSin_uid66_fpSinCosXTest(MUX,254)@23
vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid255_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s, en, rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b, vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b;
WHEN "1" => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid257_lzcZSin_uid66_fpSinCosXTest(BITSELECT,256)@23
rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in(15 downto 8);
--reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1(REG,580)@23
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q <= rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid258_lzcZSin_uid66_fpSinCosXTest(LOGICAL,257)@24
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a <= reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q;
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b else "0";
--ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d(DELAY,900)@24
ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid259_lzcZSin_uid66_fpSinCosXTest(BITSELECT,258)@23
vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q(7 downto 0);
vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3(REG,582)@23
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q <= vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid261_lzcZSin_uid66_fpSinCosXTest(MUX,260)@24
vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid261_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s, en, reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q, reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid263_lzcZSin_uid66_fpSinCosXTest(BITSELECT,262)@24
rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in(7 downto 4);
--vCount_uid264_lzcZSin_uid66_fpSinCosXTest(LOGICAL,263)@24
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid265_lzcZSin_uid66_fpSinCosXTest(BITSELECT,264)@24
vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q(3 downto 0);
vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in(3 downto 0);
--reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3(REG,584)@24
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q <= vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2(REG,583)@24
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid267_lzcZSin_uid66_fpSinCosXTest(MUX,266)@25
vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid267_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s, en, reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q, reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid269_lzcZSin_uid66_fpSinCosXTest(BITSELECT,268)@25
rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in(3 downto 2);
--vCount_uid270_lzcZSin_uid66_fpSinCosXTest(LOGICAL,269)@25
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b else "0";
--vStage_uid271_lzcZSin_uid66_fpSinCosXTest(BITSELECT,270)@25
vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q(1 downto 0);
vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in(1 downto 0);
--vStagei_uid273_lzcZSin_uid66_fpSinCosXTest(MUX,272)@25
vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid273_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s, en, rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b, vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b;
WHEN "1" => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid275_lzcZSin_uid66_fpSinCosXTest(BITSELECT,274)@25
rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in(1 downto 1);
--vCount_uid276_lzcZSin_uid66_fpSinCosXTest(LOGICAL,275)@25
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b <= GND_q;
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b else "0";
--r_uid277_lzcZSin_uid66_fpSinCosXTest(BITJOIN,276)@25
r_uid277_lzcZSin_uid66_fpSinCosXTest_q <= ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q & ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q & ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q & ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q & vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q & vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q & vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q;
--leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest(BITSELECT,284)@25
leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q;
leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in(6 downto 5);
--leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest(MUX,285)@25
leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s <= leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b;
leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s, en, ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest(BITSELECT,293)@25
LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(40 downto 0);
LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in(40 downto 0);
--leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest(BITJOIN,294)@25
leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b & leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5(REG,590)@25
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest(BITSELECT,290)@25
LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(48 downto 0);
LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in(48 downto 0);
--leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest(BITJOIN,291)@25
leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4(REG,589)@25
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest(BITSELECT,287)@25
LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(56 downto 0);
LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in(56 downto 0);
--leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest(BITJOIN,288)@25
leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3(REG,588)@25
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2(REG,587)@25
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest(BITSELECT,295)@25
leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1(REG,586)@25
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q <= leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest(MUX,296)@26
leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s <= reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q;
leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s, en, reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest(BITSELECT,304)@26
LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(58 downto 0);
LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b(DELAY,927)@26
ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest(BITJOIN,305)@27
leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q;
--LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest(BITSELECT,301)@26
LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(60 downto 0);
LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b(DELAY,925)@26
ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest(BITJOIN,302)@27
leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest(BITSELECT,298)@26
LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(62 downto 0);
LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in(62 downto 0);
--ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b(DELAY,923)@26
ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest(BITJOIN,299)@27
leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2(REG,592)@26
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest(BITSELECT,306)@25
leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in(2 downto 1);
--ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a(DELAY,1214)@25
ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1(REG,591)@26
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q <= ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest(MUX,307)@27
leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s <= reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q;
leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s, en, reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest(BITSELECT,311)@25
leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b(DELAY,937)@25
ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest(MUX,312)@27
leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s <= ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q;
leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s, en, leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "0" => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "1" => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--pHigh_uid72_fpSinCosXTest(BITSELECT,71)@27
pHigh_uid72_fpSinCosXTest_in <= leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q;
pHigh_uid72_fpSinCosXTest_b <= pHigh_uid72_fpSinCosXTest_in(64 downto 39);
--reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2(REG,594)@27
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q <= pHigh_uid72_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a(DELAY,1216)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1(REG,593)@27
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--p_uid73_fpSinCosXTest(MUX,72)@28
p_uid73_fpSinCosXTest_s <= reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q;
p_uid73_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p_uid73_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE p_uid73_fpSinCosXTest_s IS
WHEN "0" => p_uid73_fpSinCosXTest_q <= reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q;
WHEN "1" => p_uid73_fpSinCosXTest_q <= cPi_uid71_fpSinCosXTest_q;
WHEN OTHERS => p_uid73_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg(DELAY,1312)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => p_uid73_fpSinCosXTest_q, xout => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem(DUALMEM,1313)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 1,
numwords_a => 2,
width_b => 26,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq,
address_a => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa,
data_a => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia
);
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0 <= areset;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq(25 downto 0);
--mulSin_uid92_fpSinCosXTest(MULT,91)@33
mulSin_uid92_fpSinCosXTest_pr <= UNSIGNED(mulSin_uid92_fpSinCosXTest_a) * UNSIGNED(mulSin_uid92_fpSinCosXTest_b);
mulSin_uid92_fpSinCosXTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulSin_uid92_fpSinCosXTest_a <= (others => '0');
mulSin_uid92_fpSinCosXTest_b <= (others => '0');
mulSin_uid92_fpSinCosXTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulSin_uid92_fpSinCosXTest_a <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q;
mulSin_uid92_fpSinCosXTest_b <= multSinOp2_uid91_fpSinCosXTest_q;
mulSin_uid92_fpSinCosXTest_s1 <= STD_LOGIC_VECTOR(mulSin_uid92_fpSinCosXTest_pr);
END IF;
END IF;
END PROCESS;
mulSin_uid92_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulSin_uid92_fpSinCosXTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulSin_uid92_fpSinCosXTest_q <= mulSin_uid92_fpSinCosXTest_s1;
END IF;
END IF;
END PROCESS;
--normBitSin_uid93_fpSinCosXTest(BITSELECT,92)@36
normBitSin_uid93_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q;
normBitSin_uid93_fpSinCosXTest_b <= normBitSin_uid93_fpSinCosXTest_in(51 downto 51);
--join_uid99_fpSinCosXTest(BITJOIN,98)@36
join_uid99_fpSinCosXTest_q <= reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q & normBitSin_uid93_fpSinCosXTest_b;
--sinRndOp_uid100_uid101_fpSinCosXTest(BITJOIN,100)@36
sinRndOp_uid100_uid101_fpSinCosXTest_q <= join_uid99_fpSinCosXTest_q & cstAllZWF_uid7_fpSinCosXTest_q & VCC_q;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor(LOGICAL,1333)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q <= not (ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a or ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b);
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena(REG,1334)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q = "1") THEN
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd(LOGICAL,1335)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b <= en;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a and ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor(LOGICAL,1283)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q <= not (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a or ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b);
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena(REG,1284)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd(LOGICAL,1285)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a and ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg(DELAY,1273)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expXRR_uid38_fpSinCosXTest_b, xout => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem(DUALMEM,1274)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 9,
width_b => 8,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia
);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1(REG,604)@25
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--expSinHC_uid74_fpSinCosXTest(SUB,73)@26
expSinHC_uid74_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expSinHC_uid74_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q);
expSinHC_uid74_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSinHC_uid74_fpSinCosXTest_a) - UNSIGNED(expSinHC_uid74_fpSinCosXTest_b));
expSinHC_uid74_fpSinCosXTest_q <= expSinHC_uid74_fpSinCosXTest_o(8 downto 0);
--expSinHCR_uid75_fpSinCosXTest(BITSELECT,74)@26
expSinHCR_uid75_fpSinCosXTest_in <= expSinHC_uid74_fpSinCosXTest_q(7 downto 0);
expSinHCR_uid75_fpSinCosXTest_b <= expSinHCR_uid75_fpSinCosXTest_in(7 downto 0);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b(DELAY,695)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expPSin_uid76_fpSinCosXTest(MUX,75)@26
expPSin_uid76_fpSinCosXTest_s <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q;
expPSin_uid76_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expPSin_uid76_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expPSin_uid76_fpSinCosXTest_s IS
WHEN "0" => expPSin_uid76_fpSinCosXTest_q <= expSinHCR_uid75_fpSinCosXTest_b;
WHEN "1" => expPSin_uid76_fpSinCosXTest_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => expPSin_uid76_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg(DELAY,1323)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expPSin_uid76_fpSinCosXTest_q, xout => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem(DUALMEM,1324)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 7,
width_b => 8,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia
);
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq(7 downto 0);
--fracRSinPreRndHigh_uid95_fpSinCosXTest(BITSELECT,94)@36
fracRSinPreRndHigh_uid95_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q(50 downto 0);
fracRSinPreRndHigh_uid95_fpSinCosXTest_b <= fracRSinPreRndHigh_uid95_fpSinCosXTest_in(50 downto 27);
--fracRSinPreRndLow_uid96_fpSinCosXTest(BITSELECT,95)@36
fracRSinPreRndLow_uid96_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q(49 downto 0);
fracRSinPreRndLow_uid96_fpSinCosXTest_b <= fracRSinPreRndLow_uid96_fpSinCosXTest_in(49 downto 26);
--fracRSinPreRnd_uid97_fpSinCosXTest(MUX,96)@36
fracRSinPreRnd_uid97_fpSinCosXTest_s <= normBitSin_uid93_fpSinCosXTest_b;
fracRSinPreRnd_uid97_fpSinCosXTest: PROCESS (fracRSinPreRnd_uid97_fpSinCosXTest_s, en, fracRSinPreRndLow_uid96_fpSinCosXTest_b, fracRSinPreRndHigh_uid95_fpSinCosXTest_b)
BEGIN
CASE fracRSinPreRnd_uid97_fpSinCosXTest_s IS
WHEN "0" => fracRSinPreRnd_uid97_fpSinCosXTest_q <= fracRSinPreRndLow_uid96_fpSinCosXTest_b;
WHEN "1" => fracRSinPreRnd_uid97_fpSinCosXTest_q <= fracRSinPreRndHigh_uid95_fpSinCosXTest_b;
WHEN OTHERS => fracRSinPreRnd_uid97_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracRSinPreRnd_uid98_uid98_fpSinCosXTest(BITJOIN,97)@36
expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q & fracRSinPreRnd_uid97_fpSinCosXTest_q;
--expFracRSin_uid102_fpSinCosXTest(ADD,101)@36
expFracRSin_uid102_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q);
expFracRSin_uid102_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0000000" & sinRndOp_uid100_uid101_fpSinCosXTest_q);
expFracRSin_uid102_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRSin_uid102_fpSinCosXTest_a) + UNSIGNED(expFracRSin_uid102_fpSinCosXTest_b));
expFracRSin_uid102_fpSinCosXTest_q <= expFracRSin_uid102_fpSinCosXTest_o(32 downto 0);
--expRCompSin_uid104_fpSinCosXTest(BITSELECT,103)@36
expRCompSin_uid104_fpSinCosXTest_in <= expFracRSin_uid102_fpSinCosXTest_q(31 downto 0);
expRCompSin_uid104_fpSinCosXTest_b <= expRCompSin_uid104_fpSinCosXTest_in(31 downto 24);
--reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2(REG,607)@36
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q <= expRCompSin_uid104_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor(LOGICAL,1537)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q <= not (ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a or ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b);
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena(REG,1538)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q = "1") THEN
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd(LOGICAL,1539)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b <= en;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a and ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b;
--expXIsZero_uid10_fpSinCosXTest(LOGICAL,9)@0
expXIsZero_uid10_fpSinCosXTest_a <= exp_uid9_fpSinCosXTest_b;
expXIsZero_uid10_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
expXIsZero_uid10_fpSinCosXTest_q <= "1" when expXIsZero_uid10_fpSinCosXTest_a = expXIsZero_uid10_fpSinCosXTest_b else "0";
--ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b(DELAY,746)@0
ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => expXIsZero_uid10_fpSinCosXTest_q, xout => ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excSelBitsSin_uid118_fpSinCosXTest(BITJOIN,117)@19
excSelBitsSin_uid118_fpSinCosXTest_q <= excRNaN_uid117_fpSinCosXTest_q & ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q & ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg(DELAY,1527)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => excSelBitsSin_uid118_fpSinCosXTest_q, xout => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem(DUALMEM,1528)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 4,
numwords_a => 14,
width_b => 3,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq,
address_a => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa,
data_a => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia
);
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0 <= areset;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq(2 downto 0);
--reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0(REG,533)@35
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--excSelSin_uid119_fpSinCosXTest(LOOKUP,118)@36
excSelSin_uid119_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excSelSin_uid119_fpSinCosXTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q) IS
WHEN "000" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN "001" => excSelSin_uid119_fpSinCosXTest_q <= "01";
WHEN "010" => excSelSin_uid119_fpSinCosXTest_q <= "10";
WHEN "011" => excSelSin_uid119_fpSinCosXTest_q <= "10";
WHEN "100" => excSelSin_uid119_fpSinCosXTest_q <= "11";
WHEN "101" => excSelSin_uid119_fpSinCosXTest_q <= "11";
WHEN "110" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN "111" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN OTHERS =>
excSelSin_uid119_fpSinCosXTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRPostExcSin_uid126_fpSinCosXTest(MUX,125)@37
expRPostExcSin_uid126_fpSinCosXTest_s <= excSelSin_uid119_fpSinCosXTest_q;
expRPostExcSin_uid126_fpSinCosXTest: PROCESS (expRPostExcSin_uid126_fpSinCosXTest_s, en, reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q, ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q, cstAllZWE_uid8_fpSinCosXTest_q, cstAllOWE_uid6_fpSinCosXTest_q)
BEGIN
CASE expRPostExcSin_uid126_fpSinCosXTest_s IS
WHEN "00" => expRPostExcSin_uid126_fpSinCosXTest_q <= reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q;
WHEN "01" => expRPostExcSin_uid126_fpSinCosXTest_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q;
WHEN "10" => expRPostExcSin_uid126_fpSinCosXTest_q <= cstAllZWE_uid8_fpSinCosXTest_q;
WHEN "11" => expRPostExcSin_uid126_fpSinCosXTest_q <= cstAllOWE_uid6_fpSinCosXTest_q;
WHEN OTHERS => expRPostExcSin_uid126_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor(LOGICAL,1346)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q <= not (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a or ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b);
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena(REG,1347)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd(LOGICAL,1348)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b <= en;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a and ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg(DELAY,1336)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => frac_uid13_fpSinCosXTest_b, xout => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem(DUALMEM,1337)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 6,
numwords_a => 35,
width_b => 23,
widthad_b => 6,
numwords_b => 35,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia
);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq(22 downto 0);
--fracRCompSin_uid103_fpSinCosXTest(BITSELECT,102)@36
fracRCompSin_uid103_fpSinCosXTest_in <= expFracRSin_uid102_fpSinCosXTest_q(23 downto 0);
fracRCompSin_uid103_fpSinCosXTest_b <= fracRCompSin_uid103_fpSinCosXTest_in(23 downto 1);
--reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2(REG,606)@36
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q <= fracRCompSin_uid103_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--fracRPostExcSin_uid122_fpSinCosXTest(MUX,121)@37
fracRPostExcSin_uid122_fpSinCosXTest_s <= excSelSin_uid119_fpSinCosXTest_q;
fracRPostExcSin_uid122_fpSinCosXTest: PROCESS (fracRPostExcSin_uid122_fpSinCosXTest_s, en, reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q, cstAllZWF_uid7_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q)
BEGIN
CASE fracRPostExcSin_uid122_fpSinCosXTest_s IS
WHEN "00" => fracRPostExcSin_uid122_fpSinCosXTest_q <= reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q;
WHEN "01" => fracRPostExcSin_uid122_fpSinCosXTest_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q;
WHEN "10" => fracRPostExcSin_uid122_fpSinCosXTest_q <= cstAllZWF_uid7_fpSinCosXTest_q;
WHEN "11" => fracRPostExcSin_uid122_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN OTHERS => fracRPostExcSin_uid122_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpSin_uid134_fpSinCosXTest(BITJOIN,133)@37
fpSin_uid134_fpSinCosXTest_q <= ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q & expRPostExcSin_uid126_fpSinCosXTest_q & fracRPostExcSin_uid122_fpSinCosXTest_q;
--xOut(GPOUT,4)@37
s <= fpSin_uid134_fpSinCosXTest_q;
c <= fpCos_uid162_fpSinCosXTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_sincos_s5
-- VHDL created on Wed Mar 27 09:55:14 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_sincos_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
s : out std_logic_vector(31 downto 0);
c : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_sincos_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid8_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid22_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid23_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShift_uid24_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid25_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid26_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstZwShiftP1_uid27_fpSinCosXTest_q : std_logic_vector (13 downto 0);
signal cstNaNwF_uid32_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal cstZmwFRRPwSM1_uid52_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal cPi_uid71_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal p_uid73_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal p_uid73_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal expPSin_uid76_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal expPSin_uid76_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal multSinOp2_uid91_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal multSinOp2_uid91_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_a : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_s1 : std_logic_vector (51 downto 0);
signal mulSin_uid92_fpSinCosXTest_pr : UNSIGNED (51 downto 0);
signal mulSin_uid92_fpSinCosXTest_q : std_logic_vector (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_a : std_logic_vector (25 downto 0);
signal mulCos_uid105_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal mulCos_uid105_fpSinCosXTest_s1 : std_logic_vector (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_pr : UNSIGNED (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_q : std_logic_vector (51 downto 0);
signal excSelSin_uid119_fpSinCosXTest_q : std_logic_vector(1 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expSelectorCos_uid145_fpSinCosXTest_q : std_logic_vector(1 downto 0);
signal signRCond2_uid152_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_d : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_d : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q : std_logic_vector (29 downto 0);
signal leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal zs_uid236_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal mO_uid239_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (62 downto 0);
signal zs_uid244_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal zs_uid250_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (5 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(63 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(63 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (47 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a : std_logic_vector (12 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr : SIGNED (26 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q : std_logic_vector (25 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a : std_logic_vector (14 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b : std_logic_vector (22 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr : SIGNED (38 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q : std_logic_vector (37 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a : std_logic_vector (12 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr : SIGNED (26 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q : std_logic_vector (25 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a : std_logic_vector (14 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b : std_logic_vector (22 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr : SIGNED (38 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q : std_logic_vector (37 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0 : std_logic;
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0 : std_logic;
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q : std_logic_vector (39 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a : std_logic_vector(81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b : std_logic_vector(81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o : std_logic_vector (81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q : std_logic_vector (81 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC0_uid394_tableGensinPiZ_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC1_uid396_tableGensinPiZ_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC2_uid398_tableGensinPiZ_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_q : std_logic_vector (12 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC0_uid400_tableGencosPiZ_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC1_uid402_tableGencosPiZ_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC2_uid404_tableGencosPiZ_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_q : std_logic_vector (12 downto 0);
signal reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q : std_logic_vector (2 downto 0);
signal reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q : std_logic_vector (39 downto 0);
signal reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (39 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q : std_logic_vector (26 downto 0);
signal reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (77 downto 0);
signal reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q : std_logic_vector (67 downto 0);
signal reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q : std_logic_vector (66 downto 0);
signal reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q : std_logic_vector (65 downto 0);
signal reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q : std_logic_vector (67 downto 0);
signal reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q : std_logic_vector (25 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q : std_logic_vector (12 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q : std_logic_vector (20 downto 0);
signal reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q : std_logic_vector (22 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q : std_logic_vector (29 downto 0);
signal reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q : std_logic_vector (6 downto 0);
signal reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q : std_logic_vector (22 downto 0);
signal reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q : std_logic_vector (0 downto 0);
signal reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q : std_logic_vector (12 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q : std_logic_vector (20 downto 0);
signal reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q : std_logic_vector (22 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q : std_logic_vector (29 downto 0);
signal reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q : std_logic_vector (25 downto 0);
signal reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q : std_logic_vector (25 downto 0);
signal reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q : std_logic_vector (6 downto 0);
signal reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q : std_logic_vector (22 downto 0);
signal reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q : std_logic_vector (3 downto 0);
signal reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q : std_logic_vector (52 downto 0);
signal ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q : std_logic_vector (65 downto 0);
signal ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q : std_logic_vector (67 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (7 downto 0);
signal ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (66 downto 0);
signal ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (65 downto 0);
signal ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (64 downto 0);
signal ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q : std_logic_vector (63 downto 0);
signal ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q : std_logic_vector (31 downto 0);
signal ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (58 downto 0);
signal ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q : std_logic_vector (63 downto 0);
signal ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q : std_logic_vector (31 downto 0);
signal ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (58 downto 0);
signal ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (76 downto 0);
signal ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (75 downto 0);
signal ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (74 downto 0);
signal ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q : std_logic_vector (12 downto 0);
signal ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q : std_logic_vector (53 downto 0);
signal ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q : std_logic_vector (12 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0 : std_logic;
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q : signal is true;
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q : std_logic_vector (6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0 : std_logic;
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q : signal is true;
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q : signal is true;
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0 : std_logic;
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0 : std_logic;
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0 : std_logic;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq : std_logic;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q : signal is true;
signal sinXIsXRR_uid41_fpSinCosXTest_a : std_logic_vector(11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_b : std_logic_vector(11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_o : std_logic_vector (11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_a : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_b : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_o : std_logic_vector (11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal yIsZero_uid51_fpSinCosXTest_a : std_logic_vector(65 downto 0);
signal yIsZero_uid51_fpSinCosXTest_b : std_logic_vector(65 downto 0);
signal yIsZero_uid51_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal pad_one_uid55_fpSinCosXTest_q : std_logic_vector (66 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_a : std_logic_vector(70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_b : std_logic_vector(70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_o : std_logic_vector (70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_c : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal InvCmpYToOneMinusY_uid61_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCmpYToOneMinusY_uid61_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid127_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid127_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvSinXIsXRR_uid128_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsXRR_uid128_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid131_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid131_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid132_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid132_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid136_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid136_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvCosXONe_uid149_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCosXONe_uid149_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid151_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid151_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvIntXParity_uid155_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvIntXParity_uid155_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal oFracXRR_uid43_uid43_fpSinCosXTest_q : std_logic_vector (53 downto 0);
signal half_uid53_fpSinCosXTest_q : std_logic_vector (65 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal exp_uid9_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal exp_uid9_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal frac_uid13_fpSinCosXTest_in : std_logic_vector (22 downto 0);
signal frac_uid13_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal signX_uid37_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal signX_uid37_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal expFracX_uid166_px_uid33_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal expFracX_uid166_px_uid33_fpSinCosXTest_b : std_logic_vector (30 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_q : std_logic_vector (9 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_a : std_logic_vector(65 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_b : std_logic_vector(65 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_a : std_logic_vector(67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_b : std_logic_vector(67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_o : std_logic_vector (67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal zSin_uid60_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal zSin_uid60_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal zCos_uid64_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal zCos_uid64_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal expSinHC_uid74_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal excRNaN_uid117_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid117_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid117_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracRPostExcSin_uid122_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExcSin_uid122_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal expRPostExcSin_uid126_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExcSin_uid126_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracRPostExcCos_uid142_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExcCos_uid142_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal expRPostExcCos_uid147_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExcCos_uid147_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cosXONe_uid148_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal cosXONe_uid148_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal cosXONe_uid148_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal finalExp_uid209_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal finalExp_uid209_rrx_uid34_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal extendedFracX_uid47_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal normBitSin_uid93_fpSinCosXTest_in : std_logic_vector (51 downto 0);
signal normBitSin_uid93_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal fracRSinPreRndHigh_uid95_fpSinCosXTest_in : std_logic_vector (50 downto 0);
signal fracRSinPreRndHigh_uid95_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracRSinPreRndLow_uid96_fpSinCosXTest_in : std_logic_vector (49 downto 0);
signal fracRSinPreRndLow_uid96_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal normBitCos_uid106_fpSinCosXTest_in : std_logic_vector (51 downto 0);
signal normBitCos_uid106_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal fracRCosPreRndHigh_uid108_fpSinCosXTest_in : std_logic_vector (50 downto 0);
signal fracRCosPreRndHigh_uid108_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracRCosPreRndLow_uid109_fpSinCosXTest_in : std_logic_vector (49 downto 0);
signal fracRCosPreRndLow_uid109_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q : std_logic_vector (52 downto 0);
signal leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b : std_logic_vector (23 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int : std_logic_vector (80 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q : std_logic_vector (80 downto 0);
signal os_uid196_rrx_uid34_fpSinCosXTest_q : std_logic_vector (79 downto 0);
signal leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal join_uid99_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal join_uid141_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal zSinYBottom_uid59_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal zSinYBottom_uid59_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal zSinOMyBottom_uid58_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal zSinOMyBottom_uid58_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal excSelBitsSin_uid118_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal fpSin_uid134_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal join_uid143_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal fpCos_uid162_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int : std_logic_vector (107 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q : std_logic_vector (107 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal fracX_uid187_rrx_uid34_fpSinCosXTest_in : std_logic_vector (22 downto 0);
signal fracX_uid187_rrx_uid34_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal oFracXRRSmallXRR_uid90_fpSinCosXTest_in : std_logic_vector (53 downto 0);
signal oFracXRRSmallXRR_uid90_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal R_uid167_px_uid33_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal InvFracXIsZero_uid16_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid16_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fxpXShiftVal_uid46_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal fxpXShiftVal_uid46_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal addr_uid81_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal addr_uid81_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal zPsinPiZ_uid84_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal zPsinPiZ_uid84_fpSinCosXTest_b : std_logic_vector (14 downto 0);
signal rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (32 downto 0);
signal addr_uid83_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal addr_uid83_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal zPcosPiZ_uid87_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal zPcosPiZ_uid87_fpSinCosXTest_b : std_logic_vector (14 downto 0);
signal rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (32 downto 0);
signal expSinHCR_uid75_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expSinHCR_uid75_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal expPCos_uid79_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expPCos_uid79_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (66 downto 0);
signal LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (66 downto 0);
signal LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (65 downto 0);
signal LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (58 downto 0);
signal rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (58 downto 0);
signal rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (76 downto 0);
signal LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (76 downto 0);
signal LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (75 downto 0);
signal LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (75 downto 0);
signal LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (74 downto 0);
signal LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (74 downto 0);
signal X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (59 downto 0);
signal X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (59 downto 0);
signal X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (55 downto 0);
signal X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (55 downto 0);
signal fracRSinPreRnd_uid97_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal fracRSinPreRnd_uid97_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal fracRCosPreRnd_uid110_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal fracRCosPreRnd_uid110_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal cosRndOp_uid112_uid113_fpSinCosXTest_q : std_logic_vector (24 downto 0);
signal rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal lowRangeB_uid408_polyEvalsinPiZ_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid408_polyEvalsinPiZ_b : std_logic_vector (0 downto 0);
signal highBBits_uid409_polyEvalsinPiZ_in : std_logic_vector (13 downto 0);
signal highBBits_uid409_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid414_polyEvalsinPiZ_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid414_polyEvalsinPiZ_b : std_logic_vector (1 downto 0);
signal highBBits_uid415_polyEvalsinPiZ_in : std_logic_vector (23 downto 0);
signal highBBits_uid415_polyEvalsinPiZ_b : std_logic_vector (21 downto 0);
signal lowRangeB_uid421_polyEvalcosPiZ_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid421_polyEvalcosPiZ_b : std_logic_vector (0 downto 0);
signal highBBits_uid422_polyEvalcosPiZ_in : std_logic_vector (13 downto 0);
signal highBBits_uid422_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid427_polyEvalcosPiZ_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid427_polyEvalcosPiZ_b : std_logic_vector (1 downto 0);
signal highBBits_uid428_polyEvalcosPiZ_in : std_logic_vector (23 downto 0);
signal highBBits_uid428_polyEvalcosPiZ_b : std_logic_vector (21 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in : std_logic_vector (80 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b : std_logic_vector (26 downto 0);
signal fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in : std_logic_vector (76 downto 0);
signal fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b : std_logic_vector (52 downto 0);
signal intXParity_uid49_fpSinCosXTest_in : std_logic_vector (67 downto 0);
signal intXParity_uid49_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal y_uid50_fpSinCosXTest_in : std_logic_vector (66 downto 0);
signal y_uid50_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal sinRndOp_uid100_uid101_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal expSelBitsCos_uid144_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a : std_logic_vector(108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b : std_logic_vector(108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o : std_logic_vector (108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q : std_logic_vector (108 downto 0);
signal oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal expX_uid186_rrx_uid34_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal expX_uid186_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal exc_N_uid17_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal yT1_uid406_polyEvalsinPiZ_in : std_logic_vector (14 downto 0);
signal yT1_uid406_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal yT1_uid419_polyEvalcosPiZ_in : std_logic_vector (14 downto 0);
signal yT1_uid419_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_a : std_logic_vector(32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_b : std_logic_vector(32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_o : std_logic_vector (32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_q : std_logic_vector (30 downto 0);
signal finalFrac_uid208_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal finalFrac_uid208_rrx_uid34_fpSinCosXTest_q : std_logic_vector (52 downto 0);
signal signComp_uid129_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_a : std_logic_vector(32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_b : std_logic_vector(32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_o : std_logic_vector (32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_q : std_logic_vector (32 downto 0);
signal leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal multFracBits_uid199_rrx_uid34_fpSinCosXTest_in : std_logic_vector (77 downto 0);
signal multFracBits_uid199_rrx_uid34_fpSinCosXTest_b : std_logic_vector (77 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b : std_logic_vector (26 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (5 downto 0);
signal fracRCompCos_uid115_fpSinCosXTest_in : std_logic_vector (23 downto 0);
signal fracRCompCos_uid115_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal expRCompSin_uid116_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal expRCompSin_uid116_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal s1_uid408_uid411_polyEvalsinPiZ_q : std_logic_vector (22 downto 0);
signal s2_uid414_uid417_polyEvalsinPiZ_q : std_logic_vector (32 downto 0);
signal s1_uid421_uid424_polyEvalcosPiZ_q : std_logic_vector (22 downto 0);
signal s2_uid427_uid430_polyEvalcosPiZ_q : std_logic_vector (32 downto 0);
signal RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q : std_logic_vector (61 downto 0);
signal signR_uid130_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signR_uid130_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signR_uid130_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal fracRCompSin_uid103_fpSinCosXTest_in : std_logic_vector (23 downto 0);
signal fracRCompSin_uid103_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal expRCompSin_uid104_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal expRCompSin_uid104_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in : std_logic_vector (77 downto 0);
signal multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (61 downto 0);
signal X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (61 downto 0);
signal X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (45 downto 0);
signal X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (45 downto 0);
signal X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (29 downto 0);
signal X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (29 downto 0);
signal expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal polyEvalSigsinPiZ_uid86_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal polyEvalSigsinPiZ_uid86_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal polyEvalSigcosPiZ_uid89_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal polyEvalSigcosPiZ_uid89_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal expXRR_uid38_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal expXRR_uid38_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal fracXRR_uid39_fpSinCosXTest_in : std_logic_vector (52 downto 0);
signal fracXRR_uid39_fpSinCosXTest_b : std_logic_vector (52 downto 0);
signal pHigh_uid72_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal pHigh_uid72_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal pCos_uid77_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal pCos_uid77_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal r_uid277_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (6 downto 0);
signal r_uid356_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (6 downto 0);
signal expCompOut_uid205_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expCompOut_uid205_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (73 downto 0);
signal LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (73 downto 0);
signal LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (69 downto 0);
signal LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (69 downto 0);
signal LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (65 downto 0);
signal LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (56 downto 0);
signal LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (48 downto 0);
signal LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (48 downto 0);
signal LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (40 downto 0);
signal LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (40 downto 0);
signal LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (56 downto 0);
signal LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (48 downto 0);
signal LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (48 downto 0);
signal LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (40 downto 0);
signal LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (40 downto 0);
signal leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
begin
--xIn(GPIN,3)@0
--GND(CONSTANT,0)
GND_q <= "0";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable(LOGICAL,1282)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q <= not ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor(LOGICAL,1422)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q <= not (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a or ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b);
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top(CONSTANT,1418)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q <= "01011";
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp(LOGICAL,1419)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q <= "1" when ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a = ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b else "0";
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg(REG,1420)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena(REG,1423)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd(LOGICAL,1424)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b <= en;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a and ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b;
--expFracX_uid166_px_uid33_fpSinCosXTest(BITSELECT,165)@0
expFracX_uid166_px_uid33_fpSinCosXTest_in <= a(30 downto 0);
expFracX_uid166_px_uid33_fpSinCosXTest_b <= expFracX_uid166_px_uid33_fpSinCosXTest_in(30 downto 0);
--R_uid167_px_uid33_fpSinCosXTest(BITJOIN,166)@0
R_uid167_px_uid33_fpSinCosXTest_q <= GND_q & expFracX_uid166_px_uid33_fpSinCosXTest_b;
--expX_uid186_rrx_uid34_fpSinCosXTest(BITSELECT,185)@0
expX_uid186_rrx_uid34_fpSinCosXTest_in <= R_uid167_px_uid33_fpSinCosXTest_q(30 downto 0);
expX_uid186_rrx_uid34_fpSinCosXTest_b <= expX_uid186_rrx_uid34_fpSinCosXTest_in(30 downto 23);
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg(DELAY,1412)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid186_rrx_uid34_fpSinCosXTest_b, xout => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt(COUNTER,1414)
-- every=1, low=0, high=11, step=1, init=1
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i = 10 THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i - 11;
ELSE
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg(REG,1415)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux(MUX,1416)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem(DUALMEM,1413)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 12,
width_b => 8,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia
);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--zs_uid244_lzcZSin_uid66_fpSinCosXTest(CONSTANT,243)
zs_uid244_lzcZSin_uid66_fpSinCosXTest_q <= "00000000000000000000000000000000";
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor(LOGICAL,1396)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q <= not (ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a or ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b);
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg(REG,1318)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena(REG,1397)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q = "1") THEN
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd(LOGICAL,1398)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b <= en;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a and ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg(DELAY,1388)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid167_px_uid33_fpSinCosXTest_q, xout => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt(COUNTER,1314)
-- every=1, low=0, high=1, step=1, init=1
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i,1));
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg(REG,1315)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux(MUX,1316)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s <= en;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux: PROCESS (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s, ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q, ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q)
BEGIN
CASE ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s IS
WHEN "0" => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
WHEN "1" => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem(DUALMEM,1389)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 1,
numwords_a => 2,
width_b => 32,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq,
address_a => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa,
data_a => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia
);
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0 <= areset;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq(31 downto 0);
--fracX_uid187_rrx_uid34_fpSinCosXTest(BITSELECT,186)@4
fracX_uid187_rrx_uid34_fpSinCosXTest_in <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q(22 downto 0);
fracX_uid187_rrx_uid34_fpSinCosXTest_b <= fracX_uid187_rrx_uid34_fpSinCosXTest_in(22 downto 0);
--oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest(BITJOIN,196)@4
oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q <= VCC_q & fracX_uid187_rrx_uid34_fpSinCosXTest_b;
--prod_uid198_rrx_uid34_fpSinCosXTest_b_0(BITSELECT,518)@4
prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in <= STD_LOGIC_VECTOR("000" & oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q);
prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b <= prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in(26 downto 0);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1(REG,539)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q <= prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShift_uid24_fpSinCosXTest(CONSTANT,23)
cstBiasMwShift_uid24_fpSinCosXTest_q <= "01110011";
--expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest(SUB,191)@0
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expX_uid186_rrx_uid34_fpSinCosXTest_b);
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0" & cstBiasMwShift_uid24_fpSinCosXTest_q);
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b));
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q <= expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o(8 downto 0);
--expXTableAddr_uid193_rrx_uid34_fpSinCosXTest(BITSELECT,192)@0
expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in <= expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q(7 downto 0);
expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b <= expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0(REG,534)@0
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q <= expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem(DUALMEM,514)@1
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia <= (others => '0');
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa <= (others => '0');
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab <= reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q;
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq,
address_a => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa,
data_a => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia
);
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0 <= areset;
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q <= rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1(REG,537)@3
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q <= rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem(DUALMEM,513)@1
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia <= (others => '0');
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa <= (others => '0');
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab <= reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q;
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq,
address_a => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa,
data_a => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia
);
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0 <= areset;
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q <= rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0(REG,536)@3
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q <= rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid196_rrx_uid34_fpSinCosXTest(BITJOIN,195)@4
os_uid196_rrx_uid34_fpSinCosXTest_q <= reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q & reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q;
--prod_uid198_rrx_uid34_fpSinCosXTest_a_2(BITSELECT,517)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in <= STD_LOGIC_VECTOR("0" & os_uid196_rrx_uid34_fpSinCosXTest_q);
prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in(80 downto 54);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0(REG,542)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0(MULT,521)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1;
END IF;
END IF;
END PROCESS;
--ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a(DELAY,1145)@8
ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a : dspba_delay
GENERIC MAP ( width => 54, depth => 1 )
PORT MAP ( xin => prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q, xout => ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--prod_uid198_rrx_uid34_fpSinCosXTest_align_2(BITSHIFT,524)@9
prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int <= ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int(107 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_a_1(BITSELECT,516)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in <= os_uid196_rrx_uid34_fpSinCosXTest_q(53 downto 0);
prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in(53 downto 27);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0(REG,540)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0(MULT,520)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_align_1(BITSHIFT,523)@8
prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int <= prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q & "000000000000000000000000000";
prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int(80 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_a_0(BITSELECT,515)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in <= os_uid196_rrx_uid34_fpSinCosXTest_q(26 downto 0);
prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in(26 downto 0);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0(REG,538)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0(MULT,519)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_align_0(BITSHIFT,522)@8
prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int <= prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int(53 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0(ADD,525)@8
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a <= STD_LOGIC_VECTOR("0000000000000000000000000000" & prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b <= STD_LOGIC_VECTOR("0" & prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a) + UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b));
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o(81 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0(ADD,526)@9
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a <= STD_LOGIC_VECTOR("000000000000000000000000000" & prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b <= STD_LOGIC_VECTOR("0" & prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a) + UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b));
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o(108 downto 0);
--multFracBits_uid199_rrx_uid34_fpSinCosXTest(BITSELECT,198)@9
multFracBits_uid199_rrx_uid34_fpSinCosXTest_in <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q(77 downto 0);
multFracBits_uid199_rrx_uid34_fpSinCosXTest_b <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_in(77 downto 0);
--multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest(BITSELECT,199)@9
multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b;
multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b <= multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in(77 downto 46);
--reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1(REG,544)@9
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,433)@10
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a(DELAY,1178)@10
ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xout => ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5(REG,555)@12
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q <= ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q;
END IF;
END IF;
END PROCESS;
--zs_uid250_lzcZSin_uid66_fpSinCosXTest(CONSTANT,249)
zs_uid250_lzcZSin_uid66_fpSinCosXTest_q <= "0000000000000000";
--mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest(CONSTANT,434)
mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "11111111111111111111111111111111";
--vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,436)@10
vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q, mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,438)@10
rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in(31 downto 16);
--reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1(REG,546)@10
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,439)@11
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4(REG,554)@11
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q <= vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e(DELAY,1081)@12
ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWE_uid8_fpSinCosXTest(CONSTANT,7)
cstAllZWE_uid8_fpSinCosXTest_q <= "00000000";
--vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,440)@10
vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q(15 downto 0);
vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in(15 downto 0);
--reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,548)@10
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,442)@11
vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q, reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,444)@11
rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in(15 downto 8);
--vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,445)@11
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i <= "1" when vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xin => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d(DELAY,1080)@12
ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xout => ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest(CONSTANT,212)
leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q <= "0000";
--vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,446)@11
vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q(7 downto 0);
vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,550)@11
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,549)@11
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,448)@12
vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q, reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,450)@12
rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in(7 downto 4);
--vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,451)@12
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,553)@12
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest(CONSTANT,226)
leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q <= "00";
--vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,452)@12
vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q(3 downto 0);
vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in(3 downto 0);
--vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,454)@12
vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b, vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
WHEN "1" => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,456)@12
rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in(3 downto 2);
--vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,457)@12
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i <= "1" when vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xin => vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,458)@12
vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q(1 downto 0);
vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in(1 downto 0);
--reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,552)@12
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,551)@12
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,460)@13
vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q, reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,462)@13
rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in(1 downto 1);
--vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,463)@13
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= GND_q;
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest(BITJOIN,464)@13
r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q & ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q & ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q & reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q & vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q & vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
--cstBiasM1_uid23_fpSinCosXTest(CONSTANT,22)
cstBiasM1_uid23_fpSinCosXTest_q <= "01111110";
--expCompOutExt_uid204_rrx_uid34_fpSinCosXTest(SUB,203)@13
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("000" & r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q);
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b));
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q <= expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o(8 downto 0);
--expCompOut_uid205_rrx_uid34_fpSinCosXTest(BITSELECT,204)@13
expCompOut_uid205_rrx_uid34_fpSinCosXTest_in <= expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q(7 downto 0);
expCompOut_uid205_rrx_uid34_fpSinCosXTest_b <= expCompOut_uid205_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2(REG,564)@13
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q <= expCompOut_uid205_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--xBranch_uid191_rrx_uid34_fpSinCosXTest(COMPARE,190)@0
xBranch_uid191_rrx_uid34_fpSinCosXTest_cin <= GND_q;
xBranch_uid191_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid24_fpSinCosXTest_q) & '0';
xBranch_uid191_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & expX_uid186_rrx_uid34_fpSinCosXTest_b) & xBranch_uid191_rrx_uid34_fpSinCosXTest_cin(0);
xBranch_uid191_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xBranch_uid191_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(xBranch_uid191_rrx_uid34_fpSinCosXTest_b));
xBranch_uid191_rrx_uid34_fpSinCosXTest_n(0) <= not xBranch_uid191_rrx_uid34_fpSinCosXTest_o(10);
--reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1(REG,563)@0
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q <= xBranch_uid191_rrx_uid34_fpSinCosXTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b(DELAY,829)@1
ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q, xout => ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalExp_uid209_rrx_uid34_fpSinCosXTest(MUX,208)@14
finalExp_uid209_rrx_uid34_fpSinCosXTest_s <= ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q;
finalExp_uid209_rrx_uid34_fpSinCosXTest: PROCESS (finalExp_uid209_rrx_uid34_fpSinCosXTest_s, en, reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q)
BEGIN
CASE finalExp_uid209_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b(DELAY,833)@14
ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => finalExp_uid209_rrx_uid34_fpSinCosXTest_q, xout => ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1409)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a or ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top(CONSTANT,1279)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q <= "01000";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp(LOGICAL,1280)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q <= "1" when ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a = ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b else "0";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg(REG,1281)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1410)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1411)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1399)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid187_rrx_uid34_fpSinCosXTest_b, xout => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt(COUNTER,1275)
-- every=1, low=0, high=8, step=1, init=1
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i = 7 THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i - 8;
ELSE
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg(REG,1276)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux(MUX,1277)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s, ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q, ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1400)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 4,
numwords_a => 9,
width_b => 23,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(22 downto 0);
--ZerosGB_uid206_rrx_uid34_fpSinCosXTest(CONSTANT,205)
ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q <= "000000000000000000000000000000";
--fracXRExt_uid207_rrx_uid34_fpSinCosXTest(BITJOIN,206)@15
fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q & ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q;
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1499)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1500)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1501)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,474)@9
X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(29 downto 0);
X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in(29 downto 0);
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1491)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 30, depth => 1 )
PORT MAP ( xin => X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1492)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 1,
numwords_a => 2,
width_b => 30,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(29 downto 0);
--leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest(CONSTANT,473)
leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,475)@13
leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1488)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1489)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1490)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,471)@9
X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(45 downto 0);
X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in(45 downto 0);
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1480)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1481)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 1,
numwords_a => 2,
width_b => 46,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(45 downto 0);
--leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,472)@13
leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1477)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1478)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1479)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,468)@9
X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(61 downto 0);
X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in(61 downto 0);
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1469)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1470)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 62,
widthad_a => 1,
numwords_a => 2,
width_b => 62,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(61 downto 0);
--leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,469)@13
leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor(LOGICAL,1510)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q <= not (ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a or ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b);
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena(REG,1511)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q = "1") THEN
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd(LOGICAL,1512)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b <= en;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a and ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg(DELAY,1502)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 78, depth => 1 )
PORT MAP ( xin => multFracBits_uid199_rrx_uid34_fpSinCosXTest_b, xout => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem(DUALMEM,1503)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 78,
widthad_a => 1,
numwords_a => 2,
width_b => 78,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia
);
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq(77 downto 0);
--leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,476)@13
leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in(5 downto 4);
--leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,477)@13
leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b;
leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,485)@13
LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(65 downto 0);
LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in(65 downto 0);
--leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest(CONSTANT,218)
leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q <= "000000000000";
--leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,486)@13
leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b & leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5(REG,560)@13
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,482)@13
LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(69 downto 0);
LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in(69 downto 0);
--leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,483)@13
leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4(REG,559)@13
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,479)@13
LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(73 downto 0);
LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in(73 downto 0);
--leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,480)@13
leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3(REG,558)@13
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2(REG,557)@13
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,487)@13
leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1(REG,556)@13
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,488)@14
leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q;
leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,496)@14
LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(74 downto 0);
LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in(74 downto 0);
--ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1112)@14
ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 75, depth => 1 )
PORT MAP ( xin => LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest(CONSTANT,229)
leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q <= "000";
--leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,497)@15
leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,493)@14
LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(75 downto 0);
LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in(75 downto 0);
--ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1110)@14
ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 76, depth => 1 )
PORT MAP ( xin => LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,494)@15
leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,490)@14
LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(76 downto 0);
LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in(76 downto 0);
--ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1108)@14
ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 77, depth => 1 )
PORT MAP ( xin => LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,491)@15
leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & GND_q;
--reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2(REG,562)@14
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,498)@13
leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a(DELAY,1184)@13
ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1(REG,561)@14
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,499)@15
leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q;
leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracCompOut_uid203_rrx_uid34_fpSinCosXTest(BITSELECT,202)@15
fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in <= leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q(76 downto 0);
fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b <= fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in(76 downto 24);
--ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b(DELAY,826)@0
ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => xBranch_uid191_rrx_uid34_fpSinCosXTest_n, xout => ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalFrac_uid208_rrx_uid34_fpSinCosXTest(MUX,207)@15
finalFrac_uid208_rrx_uid34_fpSinCosXTest_s <= ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q;
finalFrac_uid208_rrx_uid34_fpSinCosXTest: PROCESS (finalFrac_uid208_rrx_uid34_fpSinCosXTest_s, en, fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b, fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE finalFrac_uid208_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b;
WHEN "1" => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RRangeRed_uid210_rrx_uid34_fpSinCosXTest(BITJOIN,209)@15
RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q <= GND_q & ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q & finalFrac_uid208_rrx_uid34_fpSinCosXTest_q;
--expXRR_uid38_fpSinCosXTest(BITSELECT,37)@15
expXRR_uid38_fpSinCosXTest_in <= RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q(60 downto 0);
expXRR_uid38_fpSinCosXTest_b <= expXRR_uid38_fpSinCosXTest_in(60 downto 53);
--reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1(REG,565)@15
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q <= expXRR_uid38_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShiftM2_uid26_fpSinCosXTest(CONSTANT,25)
cstBiasMwShiftM2_uid26_fpSinCosXTest_q <= "01110000";
--cosXIsOneXRR_uid42_fpSinCosXTest(COMPARE,41)@16
cosXIsOneXRR_uid42_fpSinCosXTest_cin <= GND_q;
cosXIsOneXRR_uid42_fpSinCosXTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid26_fpSinCosXTest_q) & '0';
cosXIsOneXRR_uid42_fpSinCosXTest_b <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q) & cosXIsOneXRR_uid42_fpSinCosXTest_cin(0);
cosXIsOneXRR_uid42_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(cosXIsOneXRR_uid42_fpSinCosXTest_a) - SIGNED(cosXIsOneXRR_uid42_fpSinCosXTest_b));
cosXIsOneXRR_uid42_fpSinCosXTest_n(0) <= not cosXIsOneXRR_uid42_fpSinCosXTest_o(11);
--exp_uid9_fpSinCosXTest(BITSELECT,8)@0
exp_uid9_fpSinCosXTest_in <= a(30 downto 0);
exp_uid9_fpSinCosXTest_b <= exp_uid9_fpSinCosXTest_in(30 downto 23);
--sinXIsX_uid40_fpSinCosXTest(COMPARE,39)@0
sinXIsX_uid40_fpSinCosXTest_cin <= GND_q;
sinXIsX_uid40_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid24_fpSinCosXTest_q) & '0';
sinXIsX_uid40_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & exp_uid9_fpSinCosXTest_b) & sinXIsX_uid40_fpSinCosXTest_cin(0);
sinXIsX_uid40_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid40_fpSinCosXTest_a) - UNSIGNED(sinXIsX_uid40_fpSinCosXTest_b));
sinXIsX_uid40_fpSinCosXTest_n(0) <= not sinXIsX_uid40_fpSinCosXTest_o(10);
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a(DELAY,789)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--cosXONe_uid148_fpSinCosXTest(LOGICAL,147)@16
cosXONe_uid148_fpSinCosXTest_a <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q;
cosXONe_uid148_fpSinCosXTest_b <= cosXIsOneXRR_uid42_fpSinCosXTest_n;
cosXONe_uid148_fpSinCosXTest_q <= cosXONe_uid148_fpSinCosXTest_a or cosXONe_uid148_fpSinCosXTest_b;
--ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a(DELAY,791)@16
ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => cosXONe_uid148_fpSinCosXTest_q, xout => ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvCosXONe_uid149_fpSinCosXTest(LOGICAL,148)@20
InvCosXONe_uid149_fpSinCosXTest_a <= ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q;
InvCosXONe_uid149_fpSinCosXTest_q <= not InvCosXONe_uid149_fpSinCosXTest_a;
--cstZwShiftP1_uid27_fpSinCosXTest(CONSTANT,26)
cstZwShiftP1_uid27_fpSinCosXTest_q <= "00000000000000";
--fracXRR_uid39_fpSinCosXTest(BITSELECT,38)@15
fracXRR_uid39_fpSinCosXTest_in <= RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q(52 downto 0);
fracXRR_uid39_fpSinCosXTest_b <= fracXRR_uid39_fpSinCosXTest_in(52 downto 0);
--ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a(DELAY,668)@15
ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => fracXRR_uid39_fpSinCosXTest_b, xout => ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracXRR_uid43_uid43_fpSinCosXTest(BITJOIN,42)@16
oFracXRR_uid43_uid43_fpSinCosXTest_q <= VCC_q & ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q;
--extendedFracX_uid47_fpSinCosXTest(BITJOIN,46)@16
extendedFracX_uid47_fpSinCosXTest_q <= cstZwShiftP1_uid27_fpSinCosXTest_q & oFracXRR_uid43_uid43_fpSinCosXTest_q;
--X55dto0_uid220_fxpX_uid48_fpSinCosXTest(BITSELECT,219)@16
X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(55 downto 0);
X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b <= X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in(55 downto 0);
--leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest(BITJOIN,220)@16
leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q <= X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b & leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5(REG,571)@16
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q <= leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--X59dto0_uid217_fxpX_uid48_fpSinCosXTest(BITSELECT,216)@16
X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(59 downto 0);
X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b <= X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in(59 downto 0);
--leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest(BITJOIN,217)@16
leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q <= X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4(REG,570)@16
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q <= leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--X63dto0_uid214_fxpX_uid48_fpSinCosXTest(BITSELECT,213)@16
X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(63 downto 0);
X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b <= X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in(63 downto 0);
--leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest(BITJOIN,214)@16
leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q <= X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3(REG,569)@16
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q <= leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2(REG,568)@16
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q <= extendedFracX_uid47_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--fxpXShiftValExt_uid45_fpSinCosXTest(SUB,44)@16
fxpXShiftValExt_uid45_fpSinCosXTest_a <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q);
fxpXShiftValExt_uid45_fpSinCosXTest_b <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid26_fpSinCosXTest_q);
fxpXShiftValExt_uid45_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(fxpXShiftValExt_uid45_fpSinCosXTest_a) - SIGNED(fxpXShiftValExt_uid45_fpSinCosXTest_b));
fxpXShiftValExt_uid45_fpSinCosXTest_q <= fxpXShiftValExt_uid45_fpSinCosXTest_o(9 downto 0);
--fxpXShiftVal_uid46_fpSinCosXTest(BITSELECT,45)@16
fxpXShiftVal_uid46_fpSinCosXTest_in <= fxpXShiftValExt_uid45_fpSinCosXTest_q(3 downto 0);
fxpXShiftVal_uid46_fpSinCosXTest_b <= fxpXShiftVal_uid46_fpSinCosXTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest(BITSELECT,221)@16
leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in <= fxpXShiftVal_uid46_fpSinCosXTest_b;
leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b <= leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1(REG,567)@16
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q <= leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest(MUX,222)@17
leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s <= reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q;
leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest: PROCESS (leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s, en, reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q, reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q, reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q, reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest(BITSELECT,230)@17
LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(64 downto 0);
LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in(64 downto 0);
--ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b(DELAY,851)@17
ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest(BITJOIN,231)@18
leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q & leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest(BITSELECT,227)@17
LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(65 downto 0);
LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in(65 downto 0);
--ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b(DELAY,849)@17
ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 66, depth => 1 )
PORT MAP ( xin => LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest(BITJOIN,228)@18
leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest(BITSELECT,224)@17
LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(66 downto 0);
LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in(66 downto 0);
--ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b(DELAY,847)@17
ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 67, depth => 1 )
PORT MAP ( xin => LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest(BITJOIN,225)@18
leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q & GND_q;
--reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2(REG,573)@17
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest(BITSELECT,232)@16
leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in <= fxpXShiftVal_uid46_fpSinCosXTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b <= leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a(DELAY,1195)@16
ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b, xout => ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1(REG,572)@17
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q <= ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest(MUX,233)@18
leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s <= reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q;
leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest: PROCESS (leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s, en, reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q, leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q, leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q, leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q;
WHEN "10" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q;
WHEN "11" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid50_fpSinCosXTest(BITSELECT,49)@18
y_uid50_fpSinCosXTest_in <= leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q(66 downto 0);
y_uid50_fpSinCosXTest_b <= y_uid50_fpSinCosXTest_in(66 downto 1);
--ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b(DELAY,680)@18
ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 66, depth => 2 )
PORT MAP ( xin => y_uid50_fpSinCosXTest_b, xout => ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1(REG,575)@18
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q <= y_uid50_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--pad_one_uid55_fpSinCosXTest(BITJOIN,54)@18
pad_one_uid55_fpSinCosXTest_q <= VCC_q & STD_LOGIC_VECTOR((65 downto 1 => GND_q(0)) & GND_q);
--reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0(REG,574)@18
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q <= pad_one_uid55_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--oneMinusY_uid55_fpSinCosXTest(SUB,55)@19
oneMinusY_uid55_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q);
oneMinusY_uid55_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q);
oneMinusY_uid55_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid55_fpSinCosXTest_a) - UNSIGNED(oneMinusY_uid55_fpSinCosXTest_b));
oneMinusY_uid55_fpSinCosXTest_q <= oneMinusY_uid55_fpSinCosXTest_o(67 downto 0);
--reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0(REG,576)@19
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q <= oneMinusY_uid55_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid57_fpSinCosXTest(COMPARE,56)@20
cmpYToOneMinusY_uid57_fpSinCosXTest_cin <= GND_q;
cmpYToOneMinusY_uid57_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q) & '0';
cmpYToOneMinusY_uid57_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q) & cmpYToOneMinusY_uid57_fpSinCosXTest_cin(0);
cmpYToOneMinusY_uid57_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid57_fpSinCosXTest_a) - UNSIGNED(cmpYToOneMinusY_uid57_fpSinCosXTest_b));
cmpYToOneMinusY_uid57_fpSinCosXTest_c(0) <= cmpYToOneMinusY_uid57_fpSinCosXTest_o(70);
--InvCmpYToOneMinusY_uid61_fpSinCosXTest(LOGICAL,60)@20
InvCmpYToOneMinusY_uid61_fpSinCosXTest_a <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
InvCmpYToOneMinusY_uid61_fpSinCosXTest_q <= not InvCmpYToOneMinusY_uid61_fpSinCosXTest_a;
--intXParity_uid49_fpSinCosXTest(BITSELECT,48)@18
intXParity_uid49_fpSinCosXTest_in <= leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q;
intXParity_uid49_fpSinCosXTest_b <= intXParity_uid49_fpSinCosXTest_in(67 downto 67);
--ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b(DELAY,794)@18
ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => intXParity_uid49_fpSinCosXTest_b, xout => ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--yIsZero_uid51_fpSinCosXTest(LOGICAL,50)@19
yIsZero_uid51_fpSinCosXTest_a <= reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q;
yIsZero_uid51_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000000000000000000000000000000000" & GND_q);
yIsZero_uid51_fpSinCosXTest_q <= "1" when yIsZero_uid51_fpSinCosXTest_a = yIsZero_uid51_fpSinCosXTest_b else "0";
--ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a(DELAY,792)@19
ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => yIsZero_uid51_fpSinCosXTest_q, xout => ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvYIsZero_uid151_fpSinCosXTest(LOGICAL,150)@20
InvYIsZero_uid151_fpSinCosXTest_a <= ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q;
InvYIsZero_uid151_fpSinCosXTest_q <= not InvYIsZero_uid151_fpSinCosXTest_a;
--signRCond2_uid152_fpSinCosXTest(LOGICAL,151)@20
signRCond2_uid152_fpSinCosXTest_a <= InvYIsZero_uid151_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_b <= ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q;
signRCond2_uid152_fpSinCosXTest_c <= InvCmpYToOneMinusY_uid61_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_d <= InvCosXONe_uid149_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_q_i <= signRCond2_uid152_fpSinCosXTest_a and signRCond2_uid152_fpSinCosXTest_b and signRCond2_uid152_fpSinCosXTest_c and signRCond2_uid152_fpSinCosXTest_d;
signRCond2_uid152_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRCond2_uid152_fpSinCosXTest_q, xin => signRCond2_uid152_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--InvIntXParity_uid155_fpSinCosXTest(LOGICAL,154)@20
InvIntXParity_uid155_fpSinCosXTest_a <= ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q;
InvIntXParity_uid155_fpSinCosXTest_q <= not InvIntXParity_uid155_fpSinCosXTest_a;
--signRCond1_uid157_fpSinCosXTest(LOGICAL,156)@20
signRCond1_uid157_fpSinCosXTest_a <= InvYIsZero_uid151_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_b <= InvIntXParity_uid155_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_c <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
signRCond1_uid157_fpSinCosXTest_d <= InvCosXONe_uid149_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_q_i <= signRCond1_uid157_fpSinCosXTest_a and signRCond1_uid157_fpSinCosXTest_b and signRCond1_uid157_fpSinCosXTest_c and signRCond1_uid157_fpSinCosXTest_d;
signRCond1_uid157_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRCond1_uid157_fpSinCosXTest_q, xin => signRCond1_uid157_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--signRCos_uid158_fpSinCosXTest(LOGICAL,157)@21
signRCos_uid158_fpSinCosXTest_a <= signRCond1_uid157_fpSinCosXTest_q;
signRCos_uid158_fpSinCosXTest_b <= signRCond2_uid152_fpSinCosXTest_q;
signRCos_uid158_fpSinCosXTest_q <= signRCos_uid158_fpSinCosXTest_a or signRCos_uid158_fpSinCosXTest_b;
--cstAllZWF_uid7_fpSinCosXTest(CONSTANT,6)
cstAllZWF_uid7_fpSinCosXTest_q <= "00000000000000000000000";
--frac_uid13_fpSinCosXTest(BITSELECT,12)@0
frac_uid13_fpSinCosXTest_in <= a(22 downto 0);
frac_uid13_fpSinCosXTest_b <= frac_uid13_fpSinCosXTest_in(22 downto 0);
--fracXIsZero_uid14_fpSinCosXTest(LOGICAL,13)@0
fracXIsZero_uid14_fpSinCosXTest_a <= frac_uid13_fpSinCosXTest_b;
fracXIsZero_uid14_fpSinCosXTest_b <= cstAllZWF_uid7_fpSinCosXTest_q;
fracXIsZero_uid14_fpSinCosXTest_q <= "1" when fracXIsZero_uid14_fpSinCosXTest_a = fracXIsZero_uid14_fpSinCosXTest_b else "0";
--cstAllOWE_uid6_fpSinCosXTest(CONSTANT,5)
cstAllOWE_uid6_fpSinCosXTest_q <= "11111111";
--expXIsMax_uid12_fpSinCosXTest(LOGICAL,11)@0
expXIsMax_uid12_fpSinCosXTest_a <= exp_uid9_fpSinCosXTest_b;
expXIsMax_uid12_fpSinCosXTest_b <= cstAllOWE_uid6_fpSinCosXTest_q;
expXIsMax_uid12_fpSinCosXTest_q <= "1" when expXIsMax_uid12_fpSinCosXTest_a = expXIsMax_uid12_fpSinCosXTest_b else "0";
--exc_I_uid15_fpSinCosXTest(LOGICAL,14)@0
exc_I_uid15_fpSinCosXTest_a <= expXIsMax_uid12_fpSinCosXTest_q;
exc_I_uid15_fpSinCosXTest_b <= fracXIsZero_uid14_fpSinCosXTest_q;
exc_I_uid15_fpSinCosXTest_q <= exc_I_uid15_fpSinCosXTest_a and exc_I_uid15_fpSinCosXTest_b;
--ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a(DELAY,762)@0
ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 20 )
PORT MAP ( xin => exc_I_uid15_fpSinCosXTest_q, xout => ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_I_uid131_fpSinCosXTest(LOGICAL,130)@20
InvExc_I_uid131_fpSinCosXTest_a <= ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q;
InvExc_I_uid131_fpSinCosXTest_q <= not InvExc_I_uid131_fpSinCosXTest_a;
--reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2(REG,649)@20
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q <= InvExc_I_uid131_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--InvFracXIsZero_uid16_fpSinCosXTest(LOGICAL,15)@0
InvFracXIsZero_uid16_fpSinCosXTest_a <= fracXIsZero_uid14_fpSinCosXTest_q;
InvFracXIsZero_uid16_fpSinCosXTest_q <= not InvFracXIsZero_uid16_fpSinCosXTest_a;
--exc_N_uid17_fpSinCosXTest(LOGICAL,16)@0
exc_N_uid17_fpSinCosXTest_a <= expXIsMax_uid12_fpSinCosXTest_q;
exc_N_uid17_fpSinCosXTest_b <= InvFracXIsZero_uid16_fpSinCosXTest_q;
exc_N_uid17_fpSinCosXTest_q <= exc_N_uid17_fpSinCosXTest_a and exc_N_uid17_fpSinCosXTest_b;
--ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a(DELAY,763)@0
ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 20 )
PORT MAP ( xin => exc_N_uid17_fpSinCosXTest_q, xout => ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid132_fpSinCosXTest(LOGICAL,131)@20
InvExc_N_uid132_fpSinCosXTest_a <= ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q;
InvExc_N_uid132_fpSinCosXTest_q <= not InvExc_N_uid132_fpSinCosXTest_a;
--reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1(REG,648)@20
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q <= InvExc_N_uid132_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--signRCosFull_uid161_fpSinCosXTest(LOGICAL,160)@21
signRCosFull_uid161_fpSinCosXTest_a <= reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q;
signRCosFull_uid161_fpSinCosXTest_b <= reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q;
signRCosFull_uid161_fpSinCosXTest_c <= signRCos_uid158_fpSinCosXTest_q;
signRCosFull_uid161_fpSinCosXTest_q <= signRCosFull_uid161_fpSinCosXTest_a and signRCosFull_uid161_fpSinCosXTest_b and signRCosFull_uid161_fpSinCosXTest_c;
--ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c(DELAY,809)@21
ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signRCosFull_uid161_fpSinCosXTest_q, xout => ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid22_fpSinCosXTest(CONSTANT,21)
cstBias_uid22_fpSinCosXTest_q <= "01111111";
--ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a(DELAY,681)@19
ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 68, depth => 1 )
PORT MAP ( xin => oneMinusY_uid55_fpSinCosXTest_q, xout => ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--zSinOMyBottom_uid58_fpSinCosXTest(BITSELECT,57)@20
zSinOMyBottom_uid58_fpSinCosXTest_in <= ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q(64 downto 0);
zSinOMyBottom_uid58_fpSinCosXTest_b <= zSinOMyBottom_uid58_fpSinCosXTest_in(64 downto 0);
--reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3(REG,579)@20
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q <= zSinOMyBottom_uid58_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--zSinYBottom_uid59_fpSinCosXTest(BITSELECT,58)@20
zSinYBottom_uid59_fpSinCosXTest_in <= ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q(64 downto 0);
zSinYBottom_uid59_fpSinCosXTest_b <= zSinYBottom_uid59_fpSinCosXTest_in(64 downto 0);
--reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2(REG,578)@20
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q <= zSinYBottom_uid59_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1(REG,614)@20
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q <= InvCmpYToOneMinusY_uid61_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--zCos_uid64_fpSinCosXTest(MUX,63)@21
zCos_uid64_fpSinCosXTest_s <= reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q;
zCos_uid64_fpSinCosXTest: PROCESS (zCos_uid64_fpSinCosXTest_s, en, reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q, reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q)
BEGIN
CASE zCos_uid64_fpSinCosXTest_s IS
WHEN "0" => zCos_uid64_fpSinCosXTest_q <= reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q;
WHEN "1" => zCos_uid64_fpSinCosXTest_q <= reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q;
WHEN OTHERS => zCos_uid64_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--addr_uid83_fpSinCosXTest(BITSELECT,82)@21
addr_uid83_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q;
addr_uid83_fpSinCosXTest_b <= addr_uid83_fpSinCosXTest_in(64 downto 57);
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0(REG,630)@21
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q <= addr_uid83_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid404_tableGencosPiZ_lutmem(DUALMEM,532)@22
memoryC2_uid404_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC2_uid404_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC2_uid404_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q;
memoryC2_uid404_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC2_uid404_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid404_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid404_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid404_tableGencosPiZ_lutmem_iq,
address_a => memoryC2_uid404_tableGencosPiZ_lutmem_aa,
data_a => memoryC2_uid404_tableGencosPiZ_lutmem_ia
);
memoryC2_uid404_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC2_uid404_tableGencosPiZ_lutmem_q <= memoryC2_uid404_tableGencosPiZ_lutmem_iq(12 downto 0);
--reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1(REG,632)@24
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q <= memoryC2_uid404_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPcosPiZ_uid87_fpSinCosXTest(BITSELECT,86)@21
zPcosPiZ_uid87_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(56 downto 0);
zPcosPiZ_uid87_fpSinCosXTest_b <= zPcosPiZ_uid87_fpSinCosXTest_in(56 downto 42);
--yT1_uid419_polyEvalcosPiZ(BITSELECT,418)@21
yT1_uid419_polyEvalcosPiZ_in <= zPcosPiZ_uid87_fpSinCosXTest_b;
yT1_uid419_polyEvalcosPiZ_b <= yT1_uid419_polyEvalcosPiZ_in(14 downto 2);
--reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0(REG,631)@21
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q <= yT1_uid419_polyEvalcosPiZ_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg(DELAY,1513)
ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q, xout => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a(DELAY,1125)@22
ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q, xout => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid508_pT1_uid420_polyEvalcosPiZ(MULT,507)@25
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a),14)) * SIGNED(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b);
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a <= (others => '0');
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b <= (others => '0');
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a <= ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b <= reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q <= prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ(BITSELECT,508)@28
prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in <= prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q;
prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in(25 downto 12);
--highBBits_uid422_polyEvalcosPiZ(BITSELECT,421)@28
highBBits_uid422_polyEvalcosPiZ_in <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b;
highBBits_uid422_polyEvalcosPiZ_b <= highBBits_uid422_polyEvalcosPiZ_in(13 downto 1);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a(DELAY,1256)@21
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => addr_uid83_fpSinCosXTest_b, xout => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0(REG,633)@24
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid402_tableGencosPiZ_lutmem(DUALMEM,531)@25
memoryC1_uid402_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC1_uid402_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC1_uid402_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q;
memoryC1_uid402_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC1_uid402_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid402_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid402_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid402_tableGencosPiZ_lutmem_iq,
address_a => memoryC1_uid402_tableGencosPiZ_lutmem_aa,
data_a => memoryC1_uid402_tableGencosPiZ_lutmem_ia
);
memoryC1_uid402_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC1_uid402_tableGencosPiZ_lutmem_q <= memoryC1_uid402_tableGencosPiZ_lutmem_iq(20 downto 0);
--reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0(REG,634)@27
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q <= memoryC1_uid402_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid423_polyEvalcosPiZ(ADD,422)@28
sumAHighB_uid423_polyEvalcosPiZ_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q(20)) & reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q);
sumAHighB_uid423_polyEvalcosPiZ_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid422_polyEvalcosPiZ_b(12)) & highBBits_uid422_polyEvalcosPiZ_b);
sumAHighB_uid423_polyEvalcosPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid423_polyEvalcosPiZ_a) + SIGNED(sumAHighB_uid423_polyEvalcosPiZ_b));
sumAHighB_uid423_polyEvalcosPiZ_q <= sumAHighB_uid423_polyEvalcosPiZ_o(21 downto 0);
--lowRangeB_uid421_polyEvalcosPiZ(BITSELECT,420)@28
lowRangeB_uid421_polyEvalcosPiZ_in <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b(0 downto 0);
lowRangeB_uid421_polyEvalcosPiZ_b <= lowRangeB_uid421_polyEvalcosPiZ_in(0 downto 0);
--s1_uid421_uid424_polyEvalcosPiZ(BITJOIN,423)@28
s1_uid421_uid424_polyEvalcosPiZ_q <= sumAHighB_uid423_polyEvalcosPiZ_q & lowRangeB_uid421_polyEvalcosPiZ_b;
--reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1(REG,636)@28
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q <= s1_uid421_uid424_polyEvalcosPiZ_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor(LOGICAL,1524)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q <= not (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a or ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b);
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top(CONSTANT,1520)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q <= "0100";
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp(LOGICAL,1521)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q <= "1" when ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a = ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b else "0";
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg(REG,1522)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena(REG,1525)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd(LOGICAL,1526)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b <= en;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a and ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b;
--reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0(REG,635)@21
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q <= zPcosPiZ_uid87_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg(DELAY,1514)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q, xout => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt(COUNTER,1516)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i = 3 THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i,3));
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg(REG,1517)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux(MUX,1518)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s <= en;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux: PROCESS (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s, ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q, ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem(DUALMEM,1515)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq,
address_a => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa,
data_a => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia
);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0 <= areset;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq(14 downto 0);
--prodXY_uid511_pT2_uid426_polyEvalcosPiZ(MULT,510)@29
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a),16)) * SIGNED(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b);
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a <= (others => '0');
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b <= (others => '0');
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b <= reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q <= prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ(BITSELECT,511)@32
prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in <= prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q;
prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in(37 downto 14);
--highBBits_uid428_polyEvalcosPiZ(BITSELECT,427)@32
highBBits_uid428_polyEvalcosPiZ_in <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b;
highBBits_uid428_polyEvalcosPiZ_b <= highBBits_uid428_polyEvalcosPiZ_in(23 downto 2);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor(LOGICAL,1577)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q <= not (ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a or ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena(REG,1578)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q = "1") THEN
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd(LOGICAL,1579)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b <= en;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a and ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b;
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg(DELAY,1567)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addr_uid83_fpSinCosXTest_b, xout => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem(DUALMEM,1568)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq,
address_a => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa,
data_a => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia
);
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0(REG,637)@28
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid400_tableGencosPiZ_lutmem(DUALMEM,530)@29
memoryC0_uid400_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC0_uid400_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC0_uid400_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q;
memoryC0_uid400_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC0_uid400_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid400_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid400_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid400_tableGencosPiZ_lutmem_iq,
address_a => memoryC0_uid400_tableGencosPiZ_lutmem_aa,
data_a => memoryC0_uid400_tableGencosPiZ_lutmem_ia
);
memoryC0_uid400_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC0_uid400_tableGencosPiZ_lutmem_q <= memoryC0_uid400_tableGencosPiZ_lutmem_iq(29 downto 0);
--reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0(REG,638)@31
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q <= memoryC0_uid400_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid429_polyEvalcosPiZ(ADD,428)@32
sumAHighB_uid429_polyEvalcosPiZ_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q(29)) & reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q);
sumAHighB_uid429_polyEvalcosPiZ_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid428_polyEvalcosPiZ_b(21)) & highBBits_uid428_polyEvalcosPiZ_b);
sumAHighB_uid429_polyEvalcosPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid429_polyEvalcosPiZ_a) + SIGNED(sumAHighB_uid429_polyEvalcosPiZ_b));
sumAHighB_uid429_polyEvalcosPiZ_q <= sumAHighB_uid429_polyEvalcosPiZ_o(30 downto 0);
--lowRangeB_uid427_polyEvalcosPiZ(BITSELECT,426)@32
lowRangeB_uid427_polyEvalcosPiZ_in <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b(1 downto 0);
lowRangeB_uid427_polyEvalcosPiZ_b <= lowRangeB_uid427_polyEvalcosPiZ_in(1 downto 0);
--s2_uid427_uid430_polyEvalcosPiZ(BITJOIN,429)@32
s2_uid427_uid430_polyEvalcosPiZ_q <= sumAHighB_uid429_polyEvalcosPiZ_q & lowRangeB_uid427_polyEvalcosPiZ_b;
--polyEvalSigcosPiZ_uid89_fpSinCosXTest(BITSELECT,88)@32
polyEvalSigcosPiZ_uid89_fpSinCosXTest_in <= s2_uid427_uid430_polyEvalcosPiZ_q(30 downto 0);
polyEvalSigcosPiZ_uid89_fpSinCosXTest_b <= polyEvalSigcosPiZ_uid89_fpSinCosXTest_in(30 downto 5);
--reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1(REG,640)@32
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q <= polyEvalSigcosPiZ_uid89_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor(LOGICAL,1590)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q <= not (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a or ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b);
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top(CONSTANT,1586)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q <= "010";
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp(LOGICAL,1587)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q <= "1" when ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a = ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b else "0";
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg(REG,1588)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena(REG,1591)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd(LOGICAL,1592)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b <= en;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a and ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b;
--LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest(BITSELECT,388)@27
LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q(63 downto 0);
LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in(63 downto 0);
--leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest(BITJOIN,389)@27
leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b & GND_q;
--cstZmwFRRPwSM1_uid52_fpSinCosXTest(CONSTANT,51)
cstZmwFRRPwSM1_uid52_fpSinCosXTest_q <= "00000000000000000000000000000000000000000000000000000000000000000";
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor(LOGICAL,1455)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q <= not (ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a or ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b);
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena(REG,1456)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q = "1") THEN
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd(LOGICAL,1457)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b <= en;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a and ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b;
--X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest(BITSELECT,359)@21
X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(32 downto 0);
X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b <= X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in(32 downto 0);
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg(DELAY,1447)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem(DUALMEM,1448)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 33,
widthad_a => 1,
numwords_a => 2,
width_b => 33,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia
);
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq(32 downto 0);
--leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest(BITJOIN,360)@25
leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor(LOGICAL,1466)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q <= not (ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a or ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b);
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena(REG,1467)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q = "1") THEN
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd(LOGICAL,1468)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b <= en;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a and ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg(DELAY,1458)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => zCos_uid64_fpSinCosXTest_q, xout => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem(DUALMEM,1459)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 65,
widthad_a => 1,
numwords_a => 2,
width_b => 65,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia
);
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq(64 downto 0);
--zs_uid236_lzcZSin_uid66_fpSinCosXTest(CONSTANT,235)
zs_uid236_lzcZSin_uid66_fpSinCosXTest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--rVStage_uid316_lzcZCos_uid69_fpSinCosXTest(BITSELECT,315)@21
rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q;
rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in(64 downto 1);
--vCount_uid317_lzcZCos_uid69_fpSinCosXTest(LOGICAL,316)@21
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid236_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g(DELAY,985)@22
ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid319_lzcZCos_uid69_fpSinCosXTest(BITSELECT,318)@21
vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(0 downto 0);
vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in(0 downto 0);
--ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b(DELAY,943)@21
ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid239_lzcZSin_uid66_fpSinCosXTest(CONSTANT,238)
mO_uid239_lzcZSin_uid66_fpSinCosXTest_q <= "111111111111111111111111111111111111111111111111111111111111111";
--cStage_uid320_lzcZCos_uid69_fpSinCosXTest(BITJOIN,319)@22
cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q <= ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q & mO_uid239_lzcZSin_uid66_fpSinCosXTest_q;
--ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c(DELAY,945)@21
ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid322_lzcZCos_uid69_fpSinCosXTest(MUX,321)@22
vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid322_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s, en, ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q, cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid324_lzcZCos_uid69_fpSinCosXTest(BITSELECT,323)@22
rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in(63 downto 32);
--vCount_uid325_lzcZCos_uid69_fpSinCosXTest(LOGICAL,324)@22
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f(DELAY,984)@23
ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid326_lzcZCos_uid69_fpSinCosXTest(BITSELECT,325)@22
vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q(31 downto 0);
vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in(31 downto 0);
--ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d(DELAY,952)@22
ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c(DELAY,951)@22
ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid328_lzcZCos_uid69_fpSinCosXTest(MUX,327)@23
vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid328_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s, en, ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q, ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q)
BEGIN
CASE vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q;
WHEN OTHERS => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid330_lzcZCos_uid69_fpSinCosXTest(BITSELECT,329)@23
rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in(31 downto 16);
--vCount_uid331_lzcZCos_uid69_fpSinCosXTest(LOGICAL,330)@23
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b else "0";
--reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4(REG,622)@23
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q <= vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e(DELAY,983)@24
ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid332_lzcZCos_uid69_fpSinCosXTest(BITSELECT,331)@23
vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q(15 downto 0);
vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in(15 downto 0);
--vStagei_uid334_lzcZCos_uid69_fpSinCosXTest(MUX,333)@23
vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid334_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s, en, rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b, vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b;
WHEN "1" => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid336_lzcZCos_uid69_fpSinCosXTest(BITSELECT,335)@23
rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in(15 downto 8);
--reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1(REG,617)@23
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q <= rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid337_lzcZCos_uid69_fpSinCosXTest(LOGICAL,336)@24
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a <= reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q;
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b else "0";
--ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d(DELAY,982)@24
ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid338_lzcZCos_uid69_fpSinCosXTest(BITSELECT,337)@23
vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q(7 downto 0);
vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3(REG,619)@23
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q <= vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid340_lzcZCos_uid69_fpSinCosXTest(MUX,339)@24
vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid340_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s, en, reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q, reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid342_lzcZCos_uid69_fpSinCosXTest(BITSELECT,341)@24
rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in(7 downto 4);
--vCount_uid343_lzcZCos_uid69_fpSinCosXTest(LOGICAL,342)@24
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid344_lzcZCos_uid69_fpSinCosXTest(BITSELECT,343)@24
vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q(3 downto 0);
vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in(3 downto 0);
--reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3(REG,621)@24
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q <= vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2(REG,620)@24
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid346_lzcZCos_uid69_fpSinCosXTest(MUX,345)@25
vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid346_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s, en, reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q, reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid348_lzcZCos_uid69_fpSinCosXTest(BITSELECT,347)@25
rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in(3 downto 2);
--vCount_uid349_lzcZCos_uid69_fpSinCosXTest(LOGICAL,348)@25
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b else "0";
--vStage_uid350_lzcZCos_uid69_fpSinCosXTest(BITSELECT,349)@25
vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q(1 downto 0);
vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in(1 downto 0);
--vStagei_uid352_lzcZCos_uid69_fpSinCosXTest(MUX,351)@25
vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid352_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s, en, rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b, vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b;
WHEN "1" => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid354_lzcZCos_uid69_fpSinCosXTest(BITSELECT,353)@25
rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in(1 downto 1);
--vCount_uid355_lzcZCos_uid69_fpSinCosXTest(LOGICAL,354)@25
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b <= GND_q;
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b else "0";
--r_uid356_lzcZCos_uid69_fpSinCosXTest(BITJOIN,355)@25
r_uid356_lzcZCos_uid69_fpSinCosXTest_q <= ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q & ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q & ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q & ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q & vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q & vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q & vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q;
--leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest(BITSELECT,363)@25
leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q;
leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in(6 downto 5);
--leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest(MUX,364)@25
leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s <= leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b;
leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s, en, ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest(BITSELECT,372)@25
LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(40 downto 0);
LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in(40 downto 0);
--leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest(CONSTANT,292)
leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q <= "000000000000000000000000";
--leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest(BITJOIN,373)@25
leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b & leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5(REG,627)@25
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest(BITSELECT,369)@25
LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(48 downto 0);
LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in(48 downto 0);
--leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest(BITJOIN,370)@25
leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4(REG,626)@25
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest(BITSELECT,366)@25
LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(56 downto 0);
LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in(56 downto 0);
--leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest(BITJOIN,367)@25
leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3(REG,625)@25
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2(REG,624)@25
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest(BITSELECT,374)@25
leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1(REG,623)@25
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q <= leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest(MUX,375)@26
leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s <= reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q;
leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s, en, reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest(BITSELECT,383)@26
LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(58 downto 0);
LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1009)@26
ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest(CONSTANT,303)
leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q <= "000000";
--leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest(BITJOIN,384)@27
leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q;
--LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest(BITSELECT,380)@26
LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(60 downto 0);
LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1007)@26
ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest(BITJOIN,381)@27
leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest(BITSELECT,377)@26
LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(62 downto 0);
LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in(62 downto 0);
--ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1005)@26
ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest(BITJOIN,378)@27
leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2(REG,629)@26
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest(BITSELECT,385)@25
leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1(REG,628)@25
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q <= leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1011)@26
ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest(MUX,386)@27
leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s <= ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q;
leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s, en, reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest(BITSELECT,390)@25
leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1019)@25
ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest(MUX,391)@27
leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s <= ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q;
leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s, en, leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "0" => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "1" => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--pCos_uid77_fpSinCosXTest(BITSELECT,76)@27
pCos_uid77_fpSinCosXTest_in <= leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q;
pCos_uid77_fpSinCosXTest_b <= pCos_uid77_fpSinCosXTest_in(64 downto 39);
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg(DELAY,1580)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => pCos_uid77_fpSinCosXTest_b, xout => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt(COUNTER,1582)
-- every=1, low=0, high=2, step=1, init=1
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i = 1 THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i - 2;
ELSE
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i,2));
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg(REG,1583)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux(MUX,1584)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s <= en;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux: PROCESS (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s, ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q, ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q)
BEGIN
CASE ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s IS
WHEN "0" => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q;
WHEN "1" => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem(DUALMEM,1581)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 2,
numwords_a => 3,
width_b => 26,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq,
address_a => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa,
data_a => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia
);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0 <= areset;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq(25 downto 0);
--reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0(REG,639)@32
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--mulCos_uid105_fpSinCosXTest(MULT,104)@33
mulCos_uid105_fpSinCosXTest_pr <= UNSIGNED(mulCos_uid105_fpSinCosXTest_a) * UNSIGNED(mulCos_uid105_fpSinCosXTest_b);
mulCos_uid105_fpSinCosXTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulCos_uid105_fpSinCosXTest_a <= (others => '0');
mulCos_uid105_fpSinCosXTest_b <= (others => '0');
mulCos_uid105_fpSinCosXTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulCos_uid105_fpSinCosXTest_a <= reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q;
mulCos_uid105_fpSinCosXTest_b <= reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q;
mulCos_uid105_fpSinCosXTest_s1 <= STD_LOGIC_VECTOR(mulCos_uid105_fpSinCosXTest_pr);
END IF;
END IF;
END PROCESS;
mulCos_uid105_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulCos_uid105_fpSinCosXTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulCos_uid105_fpSinCosXTest_q <= mulCos_uid105_fpSinCosXTest_s1;
END IF;
END IF;
END PROCESS;
--normBitCos_uid106_fpSinCosXTest(BITSELECT,105)@36
normBitCos_uid106_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q;
normBitCos_uid106_fpSinCosXTest_b <= normBitCos_uid106_fpSinCosXTest_in(51 downto 51);
--cosRndOp_uid112_uid113_fpSinCosXTest(BITJOIN,112)@36
cosRndOp_uid112_uid113_fpSinCosXTest_q <= normBitCos_uid106_fpSinCosXTest_b & cstAllZWF_uid7_fpSinCosXTest_q & VCC_q;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor(LOGICAL,1296)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q <= not (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a or ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b);
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top(CONSTANT,1292)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q <= "0110";
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp(LOGICAL,1293)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q <= "1" when ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a = ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b else "0";
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg(REG,1294)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena(REG,1297)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd(LOGICAL,1298)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b <= en;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a and ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b;
--reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1(REG,641)@25
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg(DELAY,1286)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q, xout => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt(COUNTER,1288)
-- every=1, low=0, high=6, step=1, init=1
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i = 5 THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i - 6;
ELSE
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i,3));
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg(REG,1289)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux(MUX,1290)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s <= en;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux: PROCESS (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s, ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q, ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem(DUALMEM,1287)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 7,
width_b => 7,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia
);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq(6 downto 0);
--expHardCase_uid78_fpSinCosXTest(SUB,77)@35
expHardCase_uid78_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expHardCase_uid78_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q);
expHardCase_uid78_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid78_fpSinCosXTest_a) - UNSIGNED(expHardCase_uid78_fpSinCosXTest_b));
expHardCase_uid78_fpSinCosXTest_q <= expHardCase_uid78_fpSinCosXTest_o(8 downto 0);
--expPCos_uid79_fpSinCosXTest(BITSELECT,78)@35
expPCos_uid79_fpSinCosXTest_in <= expHardCase_uid78_fpSinCosXTest_q(7 downto 0);
expPCos_uid79_fpSinCosXTest_b <= expPCos_uid79_fpSinCosXTest_in(7 downto 0);
--reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1(REG,642)@35
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q <= expPCos_uid79_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--fracRCosPreRndHigh_uid108_fpSinCosXTest(BITSELECT,107)@36
fracRCosPreRndHigh_uid108_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q(50 downto 0);
fracRCosPreRndHigh_uid108_fpSinCosXTest_b <= fracRCosPreRndHigh_uid108_fpSinCosXTest_in(50 downto 27);
--fracRCosPreRndLow_uid109_fpSinCosXTest(BITSELECT,108)@36
fracRCosPreRndLow_uid109_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q(49 downto 0);
fracRCosPreRndLow_uid109_fpSinCosXTest_b <= fracRCosPreRndLow_uid109_fpSinCosXTest_in(49 downto 26);
--fracRCosPreRnd_uid110_fpSinCosXTest(MUX,109)@36
fracRCosPreRnd_uid110_fpSinCosXTest_s <= normBitCos_uid106_fpSinCosXTest_b;
fracRCosPreRnd_uid110_fpSinCosXTest: PROCESS (fracRCosPreRnd_uid110_fpSinCosXTest_s, en, fracRCosPreRndLow_uid109_fpSinCosXTest_b, fracRCosPreRndHigh_uid108_fpSinCosXTest_b)
BEGIN
CASE fracRCosPreRnd_uid110_fpSinCosXTest_s IS
WHEN "0" => fracRCosPreRnd_uid110_fpSinCosXTest_q <= fracRCosPreRndLow_uid109_fpSinCosXTest_b;
WHEN "1" => fracRCosPreRnd_uid110_fpSinCosXTest_q <= fracRCosPreRndHigh_uid108_fpSinCosXTest_b;
WHEN OTHERS => fracRCosPreRnd_uid110_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracRCosPreRnd_uid111_uid111_fpSinCosXTest(BITJOIN,110)@36
expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q <= reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q & fracRCosPreRnd_uid110_fpSinCosXTest_q;
--expFracRCos_uid114_fpSinCosXTest(ADD,113)@36
expFracRCos_uid114_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q);
expFracRCos_uid114_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00000000" & cosRndOp_uid112_uid113_fpSinCosXTest_q);
expFracRCos_uid114_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRCos_uid114_fpSinCosXTest_a) + UNSIGNED(expFracRCos_uid114_fpSinCosXTest_b));
expFracRCos_uid114_fpSinCosXTest_q <= expFracRCos_uid114_fpSinCosXTest_o(32 downto 0);
--expRCompSin_uid116_fpSinCosXTest(BITSELECT,115)@36
expRCompSin_uid116_fpSinCosXTest_in <= expFracRCos_uid114_fpSinCosXTest_q(31 downto 0);
expRCompSin_uid116_fpSinCosXTest_b <= expRCompSin_uid116_fpSinCosXTest_in(31 downto 24);
--reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2(REG,646)@36
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q <= expRCompSin_uid116_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor(LOGICAL,1385)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q <= not (ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a or ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top(CONSTANT,1305)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q <= "01101";
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp(LOGICAL,1306)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q <= "1" when ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a = ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b else "0";
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg(REG,1307)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena(REG,1386)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q = "1") THEN
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd(LOGICAL,1387)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b <= en;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a and ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b;
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a(DELAY,745)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c(DELAY,783)@16
ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => cosXIsOneXRR_uid42_fpSinCosXTest_n, xout => ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--InvCosXIsOneXRR_uid136_fpSinCosXTest(LOGICAL,135)@16
InvCosXIsOneXRR_uid136_fpSinCosXTest_a <= cosXIsOneXRR_uid42_fpSinCosXTest_n;
InvCosXIsOneXRR_uid136_fpSinCosXTest_q <= not InvCosXIsOneXRR_uid136_fpSinCosXTest_a;
--ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c(DELAY,773)@16
ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => InvCosXIsOneXRR_uid136_fpSinCosXTest_q, xout => ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a(DELAY,755)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsX_uid127_fpSinCosXTest(LOGICAL,126)@18
InvSinXIsX_uid127_fpSinCosXTest_a <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q;
InvSinXIsX_uid127_fpSinCosXTest_q <= not InvSinXIsX_uid127_fpSinCosXTest_a;
--ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b(DELAY,772)@18
ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => InvSinXIsX_uid127_fpSinCosXTest_q, xout => ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--half_uid53_fpSinCosXTest(BITJOIN,52)@19
half_uid53_fpSinCosXTest_q <= VCC_q & cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
--yIsHalf_uid54_fpSinCosXTest(LOGICAL,53)@19
yIsHalf_uid54_fpSinCosXTest_a <= reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q;
yIsHalf_uid54_fpSinCosXTest_b <= half_uid53_fpSinCosXTest_q;
yIsHalf_uid54_fpSinCosXTest_q <= "1" when yIsHalf_uid54_fpSinCosXTest_a = yIsHalf_uid54_fpSinCosXTest_b else "0";
--yHalfCosXNotOne_uid138_fpSinCosXTest(LOGICAL,137)@19
yHalfCosXNotOne_uid138_fpSinCosXTest_a <= yIsHalf_uid54_fpSinCosXTest_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_b <= ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_c <= ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_q <= yHalfCosXNotOne_uid138_fpSinCosXTest_a and yHalfCosXNotOne_uid138_fpSinCosXTest_b and yHalfCosXNotOne_uid138_fpSinCosXTest_c;
--ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b(DELAY,744)@0
ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => exc_I_uid15_fpSinCosXTest_q, xout => ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a(DELAY,743)@0
ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => exc_N_uid17_fpSinCosXTest_q, xout => ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRNaN_uid117_fpSinCosXTest(LOGICAL,116)@19
excRNaN_uid117_fpSinCosXTest_a <= ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q;
excRNaN_uid117_fpSinCosXTest_b <= ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q;
excRNaN_uid117_fpSinCosXTest_q <= excRNaN_uid117_fpSinCosXTest_a or excRNaN_uid117_fpSinCosXTest_b;
--join_uid143_fpSinCosXTest(BITJOIN,142)@19
join_uid143_fpSinCosXTest_q <= ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q & yHalfCosXNotOne_uid138_fpSinCosXTest_q & excRNaN_uid117_fpSinCosXTest_q;
--expSelBitsCos_uid144_fpSinCosXTest(BITJOIN,143)@19
expSelBitsCos_uid144_fpSinCosXTest_q <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q & join_uid143_fpSinCosXTest_q;
--reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0(REG,645)@19
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q <= expSelBitsCos_uid144_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--expSelectorCos_uid145_fpSinCosXTest(LOOKUP,144)@20
expSelectorCos_uid145_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSelectorCos_uid145_fpSinCosXTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q) IS
WHEN "0000" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "0001" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "0010" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "0011" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "0100" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "0101" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "0110" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "0111" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "1000" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "1001" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "1010" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "1011" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "1100" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "1101" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "1110" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "1111" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN OTHERS =>
expSelectorCos_uid145_fpSinCosXTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg(DELAY,1375)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => expSelectorCos_uid145_fpSinCosXTest_q, xout => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt(COUNTER,1301)
-- every=1, low=0, high=13, step=1, init=1
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i = 12 THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i - 13;
ELSE
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg(REG,1302)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux(MUX,1303)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s, ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q, ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem(DUALMEM,1376)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia
);
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq(1 downto 0);
--expRPostExcCos_uid147_fpSinCosXTest(MUX,146)@37
expRPostExcCos_uid147_fpSinCosXTest_s <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q;
expRPostExcCos_uid147_fpSinCosXTest: PROCESS (expRPostExcCos_uid147_fpSinCosXTest_s, en, reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q, cstBias_uid22_fpSinCosXTest_q, cstAllZWE_uid8_fpSinCosXTest_q, cstAllOWE_uid6_fpSinCosXTest_q)
BEGIN
CASE expRPostExcCos_uid147_fpSinCosXTest_s IS
WHEN "00" => expRPostExcCos_uid147_fpSinCosXTest_q <= reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q;
WHEN "01" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstBias_uid22_fpSinCosXTest_q;
WHEN "10" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstAllZWE_uid8_fpSinCosXTest_q;
WHEN "11" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstAllOWE_uid6_fpSinCosXTest_q;
WHEN OTHERS => expRPostExcCos_uid147_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstNaNwF_uid32_fpSinCosXTest(CONSTANT,31)
cstNaNwF_uid32_fpSinCosXTest_q <= "00000000000000000000001";
--fracRCompCos_uid115_fpSinCosXTest(BITSELECT,114)@36
fracRCompCos_uid115_fpSinCosXTest_in <= expFracRCos_uid114_fpSinCosXTest_q(23 downto 0);
fracRCompCos_uid115_fpSinCosXTest_b <= fracRCompCos_uid115_fpSinCosXTest_in(23 downto 1);
--reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2(REG,644)@36
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q <= fracRCompCos_uid115_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor(LOGICAL,1372)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q <= not (ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a or ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b);
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena(REG,1373)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q = "1") THEN
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd(LOGICAL,1374)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b <= en;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a and ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b;
--reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1(REG,613)@19
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q <= excRNaN_uid117_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3(REG,612)@19
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q <= ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q;
END IF;
END IF;
END PROCESS;
--reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2(REG,611)@19
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q;
END IF;
END IF;
END PROCESS;
--reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1(REG,610)@19
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q <= yHalfCosXNotOne_uid138_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--rZOrOne_uid140_fpSinCosXTest(LOGICAL,139)@20
rZOrOne_uid140_fpSinCosXTest_a <= reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q;
rZOrOne_uid140_fpSinCosXTest_b <= reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q;
rZOrOne_uid140_fpSinCosXTest_c <= reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q;
rZOrOne_uid140_fpSinCosXTest_q <= rZOrOne_uid140_fpSinCosXTest_a or rZOrOne_uid140_fpSinCosXTest_b or rZOrOne_uid140_fpSinCosXTest_c;
--join_uid141_fpSinCosXTest(BITJOIN,140)@20
join_uid141_fpSinCosXTest_q <= reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q & rZOrOne_uid140_fpSinCosXTest_q;
--reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1(REG,643)@20
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q <= join_uid141_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg(DELAY,1362)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q, xout => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem(DUALMEM,1363)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia
);
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq(1 downto 0);
--fracRPostExcCos_uid142_fpSinCosXTest(MUX,141)@37
fracRPostExcCos_uid142_fpSinCosXTest_s <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q;
fracRPostExcCos_uid142_fpSinCosXTest: PROCESS (fracRPostExcCos_uid142_fpSinCosXTest_s, en, reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q, cstAllZWF_uid7_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q)
BEGIN
CASE fracRPostExcCos_uid142_fpSinCosXTest_s IS
WHEN "00" => fracRPostExcCos_uid142_fpSinCosXTest_q <= reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q;
WHEN "01" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstAllZWF_uid7_fpSinCosXTest_q;
WHEN "10" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN "11" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN OTHERS => fracRPostExcCos_uid142_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpCos_uid162_fpSinCosXTest(BITJOIN,161)@37
fpCos_uid162_fpSinCosXTest_q <= ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q & expRPostExcCos_uid147_fpSinCosXTest_q & fracRPostExcCos_uid142_fpSinCosXTest_q;
--cstBiasMwShiftM2_uid25_fpSinCosXTest(CONSTANT,24)
cstBiasMwShiftM2_uid25_fpSinCosXTest_q <= "01110001";
--sinXIsXRR_uid41_fpSinCosXTest(COMPARE,40)@16
sinXIsXRR_uid41_fpSinCosXTest_cin <= GND_q;
sinXIsXRR_uid41_fpSinCosXTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid25_fpSinCosXTest_q) & '0';
sinXIsXRR_uid41_fpSinCosXTest_b <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q) & sinXIsXRR_uid41_fpSinCosXTest_cin(0);
sinXIsXRR_uid41_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(sinXIsXRR_uid41_fpSinCosXTest_a) - SIGNED(sinXIsXRR_uid41_fpSinCosXTest_b));
sinXIsXRR_uid41_fpSinCosXTest_n(0) <= not sinXIsXRR_uid41_fpSinCosXTest_o(11);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a(DELAY,756)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsXRR_uid128_fpSinCosXTest(LOGICAL,127)@18
InvSinXIsXRR_uid128_fpSinCosXTest_a <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q;
InvSinXIsXRR_uid128_fpSinCosXTest_q <= not InvSinXIsXRR_uid128_fpSinCosXTest_a;
--signComp_uid129_fpSinCosXTest(LOGICAL,128)@18
signComp_uid129_fpSinCosXTest_a <= InvSinXIsXRR_uid128_fpSinCosXTest_q;
signComp_uid129_fpSinCosXTest_b <= InvSinXIsX_uid127_fpSinCosXTest_q;
signComp_uid129_fpSinCosXTest_c <= intXParity_uid49_fpSinCosXTest_b;
signComp_uid129_fpSinCosXTest_q <= signComp_uid129_fpSinCosXTest_a and signComp_uid129_fpSinCosXTest_b and signComp_uid129_fpSinCosXTest_c;
--signX_uid37_fpSinCosXTest(BITSELECT,36)@0
signX_uid37_fpSinCosXTest_in <= a;
signX_uid37_fpSinCosXTest_b <= signX_uid37_fpSinCosXTest_in(31 downto 31);
--ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a(DELAY,760)@0
ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => signX_uid37_fpSinCosXTest_b, xout => ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid130_fpSinCosXTest(LOGICAL,129)@18
signR_uid130_fpSinCosXTest_a <= ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q;
signR_uid130_fpSinCosXTest_b <= signComp_uid129_fpSinCosXTest_q;
signR_uid130_fpSinCosXTest_q <= signR_uid130_fpSinCosXTest_a xor signR_uid130_fpSinCosXTest_b;
--ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c(DELAY,766)@18
ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => signR_uid130_fpSinCosXTest_q, xout => ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--signRSinFull_uid133_fpSinCosXTest(LOGICAL,132)@20
signRSinFull_uid133_fpSinCosXTest_a <= InvExc_N_uid132_fpSinCosXTest_q;
signRSinFull_uid133_fpSinCosXTest_b <= InvExc_I_uid131_fpSinCosXTest_q;
signRSinFull_uid133_fpSinCosXTest_c <= ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q;
signRSinFull_uid133_fpSinCosXTest_q_i <= signRSinFull_uid133_fpSinCosXTest_a and signRSinFull_uid133_fpSinCosXTest_b and signRSinFull_uid133_fpSinCosXTest_c;
signRSinFull_uid133_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRSinFull_uid133_fpSinCosXTest_q, xin => signRSinFull_uid133_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c(DELAY,769)@21
ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signRSinFull_uid133_fpSinCosXTest_q, xout => ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor(LOGICAL,1359)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q <= not (ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a or ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b);
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top(CONSTANT,1342)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q <= "0100010";
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp(LOGICAL,1343)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q <= "1" when ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a = ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b else "0";
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg(REG,1344)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena(REG,1360)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q = "1") THEN
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd(LOGICAL,1361)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b <= en;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a and ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg(DELAY,1349)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => exp_uid9_fpSinCosXTest_b, xout => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt(COUNTER,1338)
-- every=1, low=0, high=34, step=1, init=1
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i = 33 THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i - 34;
ELSE
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i,6));
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg(REG,1339)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux(MUX,1340)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem(DUALMEM,1350)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 6,
numwords_a => 35,
width_b => 8,
widthad_b => 6,
numwords_b => 35,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia
);
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a(DELAY,1228)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1(REG,605)@35
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor(LOGICAL,1309)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q <= not (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a or ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena(REG,1310)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd(LOGICAL,1311)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b <= en;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a and ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b;
--oFracXRRSmallXRR_uid90_fpSinCosXTest(BITSELECT,89)@16
oFracXRRSmallXRR_uid90_fpSinCosXTest_in <= oFracXRR_uid43_uid43_fpSinCosXTest_q;
oFracXRRSmallXRR_uid90_fpSinCosXTest_b <= oFracXRRSmallXRR_uid90_fpSinCosXTest_in(53 downto 28);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg(DELAY,1299)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => oFracXRRSmallXRR_uid90_fpSinCosXTest_b, xout => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem(DUALMEM,1300)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 4,
numwords_a => 14,
width_b => 26,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia
);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq(25 downto 0);
--reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1(REG,577)@20
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
END IF;
END IF;
END PROCESS;
--zSin_uid60_fpSinCosXTest(MUX,59)@21
zSin_uid60_fpSinCosXTest_s <= reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q;
zSin_uid60_fpSinCosXTest: PROCESS (zSin_uid60_fpSinCosXTest_s, en, reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q, reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q)
BEGIN
CASE zSin_uid60_fpSinCosXTest_s IS
WHEN "0" => zSin_uid60_fpSinCosXTest_q <= reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q;
WHEN "1" => zSin_uid60_fpSinCosXTest_q <= reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q;
WHEN OTHERS => zSin_uid60_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--addr_uid81_fpSinCosXTest(BITSELECT,80)@21
addr_uid81_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q;
addr_uid81_fpSinCosXTest_b <= addr_uid81_fpSinCosXTest_in(64 downto 57);
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0(REG,595)@21
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q <= addr_uid81_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid398_tableGensinPiZ_lutmem(DUALMEM,529)@22
memoryC2_uid398_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC2_uid398_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC2_uid398_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q;
memoryC2_uid398_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC2_uid398_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid398_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid398_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid398_tableGensinPiZ_lutmem_iq,
address_a => memoryC2_uid398_tableGensinPiZ_lutmem_aa,
data_a => memoryC2_uid398_tableGensinPiZ_lutmem_ia
);
memoryC2_uid398_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC2_uid398_tableGensinPiZ_lutmem_q <= memoryC2_uid398_tableGensinPiZ_lutmem_iq(12 downto 0);
--reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1(REG,597)@24
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q <= memoryC2_uid398_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPsinPiZ_uid84_fpSinCosXTest(BITSELECT,83)@21
zPsinPiZ_uid84_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(56 downto 0);
zPsinPiZ_uid84_fpSinCosXTest_b <= zPsinPiZ_uid84_fpSinCosXTest_in(56 downto 42);
--yT1_uid406_polyEvalsinPiZ(BITSELECT,405)@21
yT1_uid406_polyEvalsinPiZ_in <= zPsinPiZ_uid84_fpSinCosXTest_b;
yT1_uid406_polyEvalsinPiZ_b <= yT1_uid406_polyEvalsinPiZ_in(14 downto 2);
--ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg(DELAY,1540)
ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => yT1_uid406_polyEvalsinPiZ_b, xout => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a(DELAY,1219)@21
ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q, xout => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0(REG,596)@24
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q <= ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid502_pT1_uid407_polyEvalsinPiZ(MULT,501)@25
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a),14)) * SIGNED(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b);
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a <= (others => '0');
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b <= (others => '0');
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a <= reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b <= reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q <= prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ(BITSELECT,502)@28
prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in <= prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q;
prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in(25 downto 12);
--highBBits_uid409_polyEvalsinPiZ(BITSELECT,408)@28
highBBits_uid409_polyEvalsinPiZ_in <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b;
highBBits_uid409_polyEvalsinPiZ_b <= highBBits_uid409_polyEvalsinPiZ_in(13 downto 1);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a(DELAY,1221)@21
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => addr_uid81_fpSinCosXTest_b, xout => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0(REG,598)@24
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid396_tableGensinPiZ_lutmem(DUALMEM,528)@25
memoryC1_uid396_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC1_uid396_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC1_uid396_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q;
memoryC1_uid396_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC1_uid396_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid396_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid396_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid396_tableGensinPiZ_lutmem_iq,
address_a => memoryC1_uid396_tableGensinPiZ_lutmem_aa,
data_a => memoryC1_uid396_tableGensinPiZ_lutmem_ia
);
memoryC1_uid396_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC1_uid396_tableGensinPiZ_lutmem_q <= memoryC1_uid396_tableGensinPiZ_lutmem_iq(20 downto 0);
--reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0(REG,599)@27
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q <= memoryC1_uid396_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid410_polyEvalsinPiZ(ADD,409)@28
sumAHighB_uid410_polyEvalsinPiZ_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q(20)) & reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q);
sumAHighB_uid410_polyEvalsinPiZ_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid409_polyEvalsinPiZ_b(12)) & highBBits_uid409_polyEvalsinPiZ_b);
sumAHighB_uid410_polyEvalsinPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid410_polyEvalsinPiZ_a) + SIGNED(sumAHighB_uid410_polyEvalsinPiZ_b));
sumAHighB_uid410_polyEvalsinPiZ_q <= sumAHighB_uid410_polyEvalsinPiZ_o(21 downto 0);
--lowRangeB_uid408_polyEvalsinPiZ(BITSELECT,407)@28
lowRangeB_uid408_polyEvalsinPiZ_in <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b(0 downto 0);
lowRangeB_uid408_polyEvalsinPiZ_b <= lowRangeB_uid408_polyEvalsinPiZ_in(0 downto 0);
--s1_uid408_uid411_polyEvalsinPiZ(BITJOIN,410)@28
s1_uid408_uid411_polyEvalsinPiZ_q <= sumAHighB_uid410_polyEvalsinPiZ_q & lowRangeB_uid408_polyEvalsinPiZ_b;
--reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1(REG,601)@28
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q <= s1_uid408_uid411_polyEvalsinPiZ_q;
END IF;
END IF;
END PROCESS;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor(LOGICAL,1551)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q <= not (ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a or ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b);
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena(REG,1552)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q = "1") THEN
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd(LOGICAL,1553)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b <= en;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a and ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg(DELAY,1541)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => zPsinPiZ_uid84_fpSinCosXTest_b, xout => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem(DUALMEM,1542)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq,
address_a => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa,
data_a => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia
);
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0 <= areset;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq(14 downto 0);
--reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0(REG,600)@28
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid505_pT2_uid413_polyEvalsinPiZ(MULT,504)@29
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a),16)) * SIGNED(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b);
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a <= (others => '0');
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b <= (others => '0');
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a <= reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b <= reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q <= prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ(BITSELECT,505)@32
prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in <= prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q;
prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in(37 downto 14);
--highBBits_uid415_polyEvalsinPiZ(BITSELECT,414)@32
highBBits_uid415_polyEvalsinPiZ_in <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b;
highBBits_uid415_polyEvalsinPiZ_b <= highBBits_uid415_polyEvalsinPiZ_in(23 downto 2);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor(LOGICAL,1564)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q <= not (ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a or ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena(REG,1565)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q = "1") THEN
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd(LOGICAL,1566)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b <= en;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a and ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b;
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg(DELAY,1554)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addr_uid81_fpSinCosXTest_b, xout => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem(DUALMEM,1555)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq,
address_a => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa,
data_a => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia
);
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0(REG,602)@28
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid394_tableGensinPiZ_lutmem(DUALMEM,527)@29
memoryC0_uid394_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC0_uid394_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC0_uid394_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q;
memoryC0_uid394_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC0_uid394_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid394_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid394_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid394_tableGensinPiZ_lutmem_iq,
address_a => memoryC0_uid394_tableGensinPiZ_lutmem_aa,
data_a => memoryC0_uid394_tableGensinPiZ_lutmem_ia
);
memoryC0_uid394_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC0_uid394_tableGensinPiZ_lutmem_q <= memoryC0_uid394_tableGensinPiZ_lutmem_iq(29 downto 0);
--reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0(REG,603)@31
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q <= memoryC0_uid394_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid416_polyEvalsinPiZ(ADD,415)@32
sumAHighB_uid416_polyEvalsinPiZ_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q(29)) & reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q);
sumAHighB_uid416_polyEvalsinPiZ_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid415_polyEvalsinPiZ_b(21)) & highBBits_uid415_polyEvalsinPiZ_b);
sumAHighB_uid416_polyEvalsinPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid416_polyEvalsinPiZ_a) + SIGNED(sumAHighB_uid416_polyEvalsinPiZ_b));
sumAHighB_uid416_polyEvalsinPiZ_q <= sumAHighB_uid416_polyEvalsinPiZ_o(30 downto 0);
--lowRangeB_uid414_polyEvalsinPiZ(BITSELECT,413)@32
lowRangeB_uid414_polyEvalsinPiZ_in <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b(1 downto 0);
lowRangeB_uid414_polyEvalsinPiZ_b <= lowRangeB_uid414_polyEvalsinPiZ_in(1 downto 0);
--s2_uid414_uid417_polyEvalsinPiZ(BITJOIN,416)@32
s2_uid414_uid417_polyEvalsinPiZ_q <= sumAHighB_uid416_polyEvalsinPiZ_q & lowRangeB_uid414_polyEvalsinPiZ_b;
--polyEvalSigsinPiZ_uid86_fpSinCosXTest(BITSELECT,85)@32
polyEvalSigsinPiZ_uid86_fpSinCosXTest_in <= s2_uid414_uid417_polyEvalsinPiZ_q(30 downto 0);
polyEvalSigsinPiZ_uid86_fpSinCosXTest_b <= polyEvalSigsinPiZ_uid86_fpSinCosXTest_in(30 downto 5);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b(DELAY,708)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--multSinOp2_uid91_fpSinCosXTest(MUX,90)@32
multSinOp2_uid91_fpSinCosXTest_s <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q;
multSinOp2_uid91_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSinOp2_uid91_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE multSinOp2_uid91_fpSinCosXTest_s IS
WHEN "0" => multSinOp2_uid91_fpSinCosXTest_q <= polyEvalSigsinPiZ_uid86_fpSinCosXTest_b;
WHEN "1" => multSinOp2_uid91_fpSinCosXTest_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => multSinOp2_uid91_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor(LOGICAL,1320)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q <= not (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a or ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b);
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena(REG,1321)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd(LOGICAL,1322)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b <= en;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a and ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b;
--cPi_uid71_fpSinCosXTest(CONSTANT,70)
cPi_uid71_fpSinCosXTest_q <= "11001001000011111101101011";
--LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest(BITSELECT,309)@27
LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q(63 downto 0);
LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in(63 downto 0);
--leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest(BITJOIN,310)@27
leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b & GND_q;
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor(LOGICAL,1433)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q <= not (ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a or ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b);
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena(REG,1434)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q = "1") THEN
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd(LOGICAL,1435)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b <= en;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a and ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b;
--X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest(BITSELECT,280)@21
X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(32 downto 0);
X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b <= X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in(32 downto 0);
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg(DELAY,1425)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem(DUALMEM,1426)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 33,
widthad_a => 1,
numwords_a => 2,
width_b => 33,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia
);
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq(32 downto 0);
--leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest(BITJOIN,281)@25
leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor(LOGICAL,1444)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q <= not (ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a or ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b);
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena(REG,1445)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q = "1") THEN
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd(LOGICAL,1446)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b <= en;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a and ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg(DELAY,1436)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => zSin_uid60_fpSinCosXTest_q, xout => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem(DUALMEM,1437)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 65,
widthad_a => 1,
numwords_a => 2,
width_b => 65,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia
);
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq(64 downto 0);
--rVStage_uid237_lzcZSin_uid66_fpSinCosXTest(BITSELECT,236)@21
rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q;
rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in(64 downto 1);
--vCount_uid238_lzcZSin_uid66_fpSinCosXTest(LOGICAL,237)@21
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid236_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g(DELAY,903)@22
ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid240_lzcZSin_uid66_fpSinCosXTest(BITSELECT,239)@21
vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(0 downto 0);
vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in(0 downto 0);
--ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b(DELAY,861)@21
ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cStage_uid241_lzcZSin_uid66_fpSinCosXTest(BITJOIN,240)@22
cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q <= ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q & mO_uid239_lzcZSin_uid66_fpSinCosXTest_q;
--ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c(DELAY,863)@21
ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid243_lzcZSin_uid66_fpSinCosXTest(MUX,242)@22
vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid243_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s, en, ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q, cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid245_lzcZSin_uid66_fpSinCosXTest(BITSELECT,244)@22
rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in(63 downto 32);
--vCount_uid246_lzcZSin_uid66_fpSinCosXTest(LOGICAL,245)@22
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f(DELAY,902)@23
ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid247_lzcZSin_uid66_fpSinCosXTest(BITSELECT,246)@22
vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q(31 downto 0);
vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in(31 downto 0);
--ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d(DELAY,870)@22
ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c(DELAY,869)@22
ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid249_lzcZSin_uid66_fpSinCosXTest(MUX,248)@23
vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid249_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s, en, ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q, ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q)
BEGIN
CASE vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q;
WHEN OTHERS => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid251_lzcZSin_uid66_fpSinCosXTest(BITSELECT,250)@23
rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in(31 downto 16);
--vCount_uid252_lzcZSin_uid66_fpSinCosXTest(LOGICAL,251)@23
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b else "0";
--reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4(REG,585)@23
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q <= vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e(DELAY,901)@24
ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid253_lzcZSin_uid66_fpSinCosXTest(BITSELECT,252)@23
vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q(15 downto 0);
vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in(15 downto 0);
--vStagei_uid255_lzcZSin_uid66_fpSinCosXTest(MUX,254)@23
vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid255_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s, en, rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b, vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b;
WHEN "1" => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid257_lzcZSin_uid66_fpSinCosXTest(BITSELECT,256)@23
rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in(15 downto 8);
--reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1(REG,580)@23
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q <= rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid258_lzcZSin_uid66_fpSinCosXTest(LOGICAL,257)@24
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a <= reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q;
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b else "0";
--ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d(DELAY,900)@24
ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid259_lzcZSin_uid66_fpSinCosXTest(BITSELECT,258)@23
vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q(7 downto 0);
vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3(REG,582)@23
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q <= vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid261_lzcZSin_uid66_fpSinCosXTest(MUX,260)@24
vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid261_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s, en, reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q, reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid263_lzcZSin_uid66_fpSinCosXTest(BITSELECT,262)@24
rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in(7 downto 4);
--vCount_uid264_lzcZSin_uid66_fpSinCosXTest(LOGICAL,263)@24
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid265_lzcZSin_uid66_fpSinCosXTest(BITSELECT,264)@24
vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q(3 downto 0);
vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in(3 downto 0);
--reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3(REG,584)@24
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q <= vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2(REG,583)@24
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid267_lzcZSin_uid66_fpSinCosXTest(MUX,266)@25
vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid267_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s, en, reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q, reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid269_lzcZSin_uid66_fpSinCosXTest(BITSELECT,268)@25
rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in(3 downto 2);
--vCount_uid270_lzcZSin_uid66_fpSinCosXTest(LOGICAL,269)@25
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b else "0";
--vStage_uid271_lzcZSin_uid66_fpSinCosXTest(BITSELECT,270)@25
vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q(1 downto 0);
vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in(1 downto 0);
--vStagei_uid273_lzcZSin_uid66_fpSinCosXTest(MUX,272)@25
vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid273_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s, en, rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b, vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b;
WHEN "1" => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid275_lzcZSin_uid66_fpSinCosXTest(BITSELECT,274)@25
rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in(1 downto 1);
--vCount_uid276_lzcZSin_uid66_fpSinCosXTest(LOGICAL,275)@25
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b <= GND_q;
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b else "0";
--r_uid277_lzcZSin_uid66_fpSinCosXTest(BITJOIN,276)@25
r_uid277_lzcZSin_uid66_fpSinCosXTest_q <= ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q & ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q & ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q & ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q & vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q & vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q & vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q;
--leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest(BITSELECT,284)@25
leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q;
leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in(6 downto 5);
--leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest(MUX,285)@25
leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s <= leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b;
leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s, en, ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest(BITSELECT,293)@25
LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(40 downto 0);
LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in(40 downto 0);
--leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest(BITJOIN,294)@25
leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b & leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5(REG,590)@25
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest(BITSELECT,290)@25
LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(48 downto 0);
LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in(48 downto 0);
--leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest(BITJOIN,291)@25
leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4(REG,589)@25
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest(BITSELECT,287)@25
LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(56 downto 0);
LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in(56 downto 0);
--leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest(BITJOIN,288)@25
leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3(REG,588)@25
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2(REG,587)@25
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest(BITSELECT,295)@25
leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1(REG,586)@25
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q <= leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest(MUX,296)@26
leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s <= reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q;
leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s, en, reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest(BITSELECT,304)@26
LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(58 downto 0);
LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b(DELAY,927)@26
ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest(BITJOIN,305)@27
leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q;
--LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest(BITSELECT,301)@26
LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(60 downto 0);
LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b(DELAY,925)@26
ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest(BITJOIN,302)@27
leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest(BITSELECT,298)@26
LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(62 downto 0);
LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in(62 downto 0);
--ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b(DELAY,923)@26
ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest(BITJOIN,299)@27
leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2(REG,592)@26
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest(BITSELECT,306)@25
leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in(2 downto 1);
--ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a(DELAY,1214)@25
ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1(REG,591)@26
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q <= ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest(MUX,307)@27
leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s <= reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q;
leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s, en, reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest(BITSELECT,311)@25
leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b(DELAY,937)@25
ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest(MUX,312)@27
leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s <= ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q;
leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s, en, leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "0" => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "1" => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--pHigh_uid72_fpSinCosXTest(BITSELECT,71)@27
pHigh_uid72_fpSinCosXTest_in <= leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q;
pHigh_uid72_fpSinCosXTest_b <= pHigh_uid72_fpSinCosXTest_in(64 downto 39);
--reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2(REG,594)@27
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q <= pHigh_uid72_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a(DELAY,1216)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1(REG,593)@27
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--p_uid73_fpSinCosXTest(MUX,72)@28
p_uid73_fpSinCosXTest_s <= reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q;
p_uid73_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p_uid73_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE p_uid73_fpSinCosXTest_s IS
WHEN "0" => p_uid73_fpSinCosXTest_q <= reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q;
WHEN "1" => p_uid73_fpSinCosXTest_q <= cPi_uid71_fpSinCosXTest_q;
WHEN OTHERS => p_uid73_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg(DELAY,1312)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => p_uid73_fpSinCosXTest_q, xout => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem(DUALMEM,1313)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 1,
numwords_a => 2,
width_b => 26,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq,
address_a => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa,
data_a => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia
);
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0 <= areset;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq(25 downto 0);
--mulSin_uid92_fpSinCosXTest(MULT,91)@33
mulSin_uid92_fpSinCosXTest_pr <= UNSIGNED(mulSin_uid92_fpSinCosXTest_a) * UNSIGNED(mulSin_uid92_fpSinCosXTest_b);
mulSin_uid92_fpSinCosXTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulSin_uid92_fpSinCosXTest_a <= (others => '0');
mulSin_uid92_fpSinCosXTest_b <= (others => '0');
mulSin_uid92_fpSinCosXTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulSin_uid92_fpSinCosXTest_a <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q;
mulSin_uid92_fpSinCosXTest_b <= multSinOp2_uid91_fpSinCosXTest_q;
mulSin_uid92_fpSinCosXTest_s1 <= STD_LOGIC_VECTOR(mulSin_uid92_fpSinCosXTest_pr);
END IF;
END IF;
END PROCESS;
mulSin_uid92_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulSin_uid92_fpSinCosXTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulSin_uid92_fpSinCosXTest_q <= mulSin_uid92_fpSinCosXTest_s1;
END IF;
END IF;
END PROCESS;
--normBitSin_uid93_fpSinCosXTest(BITSELECT,92)@36
normBitSin_uid93_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q;
normBitSin_uid93_fpSinCosXTest_b <= normBitSin_uid93_fpSinCosXTest_in(51 downto 51);
--join_uid99_fpSinCosXTest(BITJOIN,98)@36
join_uid99_fpSinCosXTest_q <= reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q & normBitSin_uid93_fpSinCosXTest_b;
--sinRndOp_uid100_uid101_fpSinCosXTest(BITJOIN,100)@36
sinRndOp_uid100_uid101_fpSinCosXTest_q <= join_uid99_fpSinCosXTest_q & cstAllZWF_uid7_fpSinCosXTest_q & VCC_q;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor(LOGICAL,1333)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q <= not (ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a or ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b);
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena(REG,1334)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q = "1") THEN
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd(LOGICAL,1335)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b <= en;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a and ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor(LOGICAL,1283)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q <= not (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a or ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b);
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena(REG,1284)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd(LOGICAL,1285)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a and ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg(DELAY,1273)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expXRR_uid38_fpSinCosXTest_b, xout => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem(DUALMEM,1274)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 9,
width_b => 8,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia
);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1(REG,604)@25
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--expSinHC_uid74_fpSinCosXTest(SUB,73)@26
expSinHC_uid74_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expSinHC_uid74_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q);
expSinHC_uid74_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSinHC_uid74_fpSinCosXTest_a) - UNSIGNED(expSinHC_uid74_fpSinCosXTest_b));
expSinHC_uid74_fpSinCosXTest_q <= expSinHC_uid74_fpSinCosXTest_o(8 downto 0);
--expSinHCR_uid75_fpSinCosXTest(BITSELECT,74)@26
expSinHCR_uid75_fpSinCosXTest_in <= expSinHC_uid74_fpSinCosXTest_q(7 downto 0);
expSinHCR_uid75_fpSinCosXTest_b <= expSinHCR_uid75_fpSinCosXTest_in(7 downto 0);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b(DELAY,695)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expPSin_uid76_fpSinCosXTest(MUX,75)@26
expPSin_uid76_fpSinCosXTest_s <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q;
expPSin_uid76_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expPSin_uid76_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expPSin_uid76_fpSinCosXTest_s IS
WHEN "0" => expPSin_uid76_fpSinCosXTest_q <= expSinHCR_uid75_fpSinCosXTest_b;
WHEN "1" => expPSin_uid76_fpSinCosXTest_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => expPSin_uid76_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg(DELAY,1323)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expPSin_uid76_fpSinCosXTest_q, xout => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem(DUALMEM,1324)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 7,
width_b => 8,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia
);
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq(7 downto 0);
--fracRSinPreRndHigh_uid95_fpSinCosXTest(BITSELECT,94)@36
fracRSinPreRndHigh_uid95_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q(50 downto 0);
fracRSinPreRndHigh_uid95_fpSinCosXTest_b <= fracRSinPreRndHigh_uid95_fpSinCosXTest_in(50 downto 27);
--fracRSinPreRndLow_uid96_fpSinCosXTest(BITSELECT,95)@36
fracRSinPreRndLow_uid96_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q(49 downto 0);
fracRSinPreRndLow_uid96_fpSinCosXTest_b <= fracRSinPreRndLow_uid96_fpSinCosXTest_in(49 downto 26);
--fracRSinPreRnd_uid97_fpSinCosXTest(MUX,96)@36
fracRSinPreRnd_uid97_fpSinCosXTest_s <= normBitSin_uid93_fpSinCosXTest_b;
fracRSinPreRnd_uid97_fpSinCosXTest: PROCESS (fracRSinPreRnd_uid97_fpSinCosXTest_s, en, fracRSinPreRndLow_uid96_fpSinCosXTest_b, fracRSinPreRndHigh_uid95_fpSinCosXTest_b)
BEGIN
CASE fracRSinPreRnd_uid97_fpSinCosXTest_s IS
WHEN "0" => fracRSinPreRnd_uid97_fpSinCosXTest_q <= fracRSinPreRndLow_uid96_fpSinCosXTest_b;
WHEN "1" => fracRSinPreRnd_uid97_fpSinCosXTest_q <= fracRSinPreRndHigh_uid95_fpSinCosXTest_b;
WHEN OTHERS => fracRSinPreRnd_uid97_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracRSinPreRnd_uid98_uid98_fpSinCosXTest(BITJOIN,97)@36
expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q & fracRSinPreRnd_uid97_fpSinCosXTest_q;
--expFracRSin_uid102_fpSinCosXTest(ADD,101)@36
expFracRSin_uid102_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q);
expFracRSin_uid102_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0000000" & sinRndOp_uid100_uid101_fpSinCosXTest_q);
expFracRSin_uid102_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRSin_uid102_fpSinCosXTest_a) + UNSIGNED(expFracRSin_uid102_fpSinCosXTest_b));
expFracRSin_uid102_fpSinCosXTest_q <= expFracRSin_uid102_fpSinCosXTest_o(32 downto 0);
--expRCompSin_uid104_fpSinCosXTest(BITSELECT,103)@36
expRCompSin_uid104_fpSinCosXTest_in <= expFracRSin_uid102_fpSinCosXTest_q(31 downto 0);
expRCompSin_uid104_fpSinCosXTest_b <= expRCompSin_uid104_fpSinCosXTest_in(31 downto 24);
--reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2(REG,607)@36
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q <= expRCompSin_uid104_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor(LOGICAL,1537)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q <= not (ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a or ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b);
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena(REG,1538)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q = "1") THEN
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd(LOGICAL,1539)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b <= en;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a and ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b;
--expXIsZero_uid10_fpSinCosXTest(LOGICAL,9)@0
expXIsZero_uid10_fpSinCosXTest_a <= exp_uid9_fpSinCosXTest_b;
expXIsZero_uid10_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
expXIsZero_uid10_fpSinCosXTest_q <= "1" when expXIsZero_uid10_fpSinCosXTest_a = expXIsZero_uid10_fpSinCosXTest_b else "0";
--ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b(DELAY,746)@0
ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => expXIsZero_uid10_fpSinCosXTest_q, xout => ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excSelBitsSin_uid118_fpSinCosXTest(BITJOIN,117)@19
excSelBitsSin_uid118_fpSinCosXTest_q <= excRNaN_uid117_fpSinCosXTest_q & ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q & ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg(DELAY,1527)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => excSelBitsSin_uid118_fpSinCosXTest_q, xout => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem(DUALMEM,1528)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 4,
numwords_a => 14,
width_b => 3,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq,
address_a => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa,
data_a => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia
);
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0 <= areset;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq(2 downto 0);
--reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0(REG,533)@35
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--excSelSin_uid119_fpSinCosXTest(LOOKUP,118)@36
excSelSin_uid119_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excSelSin_uid119_fpSinCosXTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q) IS
WHEN "000" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN "001" => excSelSin_uid119_fpSinCosXTest_q <= "01";
WHEN "010" => excSelSin_uid119_fpSinCosXTest_q <= "10";
WHEN "011" => excSelSin_uid119_fpSinCosXTest_q <= "10";
WHEN "100" => excSelSin_uid119_fpSinCosXTest_q <= "11";
WHEN "101" => excSelSin_uid119_fpSinCosXTest_q <= "11";
WHEN "110" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN "111" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN OTHERS =>
excSelSin_uid119_fpSinCosXTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRPostExcSin_uid126_fpSinCosXTest(MUX,125)@37
expRPostExcSin_uid126_fpSinCosXTest_s <= excSelSin_uid119_fpSinCosXTest_q;
expRPostExcSin_uid126_fpSinCosXTest: PROCESS (expRPostExcSin_uid126_fpSinCosXTest_s, en, reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q, ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q, cstAllZWE_uid8_fpSinCosXTest_q, cstAllOWE_uid6_fpSinCosXTest_q)
BEGIN
CASE expRPostExcSin_uid126_fpSinCosXTest_s IS
WHEN "00" => expRPostExcSin_uid126_fpSinCosXTest_q <= reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q;
WHEN "01" => expRPostExcSin_uid126_fpSinCosXTest_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q;
WHEN "10" => expRPostExcSin_uid126_fpSinCosXTest_q <= cstAllZWE_uid8_fpSinCosXTest_q;
WHEN "11" => expRPostExcSin_uid126_fpSinCosXTest_q <= cstAllOWE_uid6_fpSinCosXTest_q;
WHEN OTHERS => expRPostExcSin_uid126_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor(LOGICAL,1346)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q <= not (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a or ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b);
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena(REG,1347)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd(LOGICAL,1348)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b <= en;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a and ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg(DELAY,1336)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => frac_uid13_fpSinCosXTest_b, xout => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem(DUALMEM,1337)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 6,
numwords_a => 35,
width_b => 23,
widthad_b => 6,
numwords_b => 35,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia
);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq(22 downto 0);
--fracRCompSin_uid103_fpSinCosXTest(BITSELECT,102)@36
fracRCompSin_uid103_fpSinCosXTest_in <= expFracRSin_uid102_fpSinCosXTest_q(23 downto 0);
fracRCompSin_uid103_fpSinCosXTest_b <= fracRCompSin_uid103_fpSinCosXTest_in(23 downto 1);
--reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2(REG,606)@36
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q <= fracRCompSin_uid103_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--fracRPostExcSin_uid122_fpSinCosXTest(MUX,121)@37
fracRPostExcSin_uid122_fpSinCosXTest_s <= excSelSin_uid119_fpSinCosXTest_q;
fracRPostExcSin_uid122_fpSinCosXTest: PROCESS (fracRPostExcSin_uid122_fpSinCosXTest_s, en, reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q, cstAllZWF_uid7_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q)
BEGIN
CASE fracRPostExcSin_uid122_fpSinCosXTest_s IS
WHEN "00" => fracRPostExcSin_uid122_fpSinCosXTest_q <= reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q;
WHEN "01" => fracRPostExcSin_uid122_fpSinCosXTest_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q;
WHEN "10" => fracRPostExcSin_uid122_fpSinCosXTest_q <= cstAllZWF_uid7_fpSinCosXTest_q;
WHEN "11" => fracRPostExcSin_uid122_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN OTHERS => fracRPostExcSin_uid122_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpSin_uid134_fpSinCosXTest(BITJOIN,133)@37
fpSin_uid134_fpSinCosXTest_q <= ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q & expRPostExcSin_uid126_fpSinCosXTest_q & fracRPostExcSin_uid122_fpSinCosXTest_q;
--xOut(GPOUT,4)@37
s <= fpSin_uid134_fpSinCosXTest_q;
c <= fpCos_uid162_fpSinCosXTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_sincos_s5
-- VHDL created on Wed Mar 27 09:55:14 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_sincos_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
s : out std_logic_vector(31 downto 0);
c : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_sincos_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid8_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid22_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid23_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShift_uid24_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid25_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid26_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstZwShiftP1_uid27_fpSinCosXTest_q : std_logic_vector (13 downto 0);
signal cstNaNwF_uid32_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal cstZmwFRRPwSM1_uid52_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal cPi_uid71_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal p_uid73_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal p_uid73_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal expPSin_uid76_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal expPSin_uid76_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal multSinOp2_uid91_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal multSinOp2_uid91_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_a : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_s1 : std_logic_vector (51 downto 0);
signal mulSin_uid92_fpSinCosXTest_pr : UNSIGNED (51 downto 0);
signal mulSin_uid92_fpSinCosXTest_q : std_logic_vector (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_a : std_logic_vector (25 downto 0);
signal mulCos_uid105_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal mulCos_uid105_fpSinCosXTest_s1 : std_logic_vector (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_pr : UNSIGNED (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_q : std_logic_vector (51 downto 0);
signal excSelSin_uid119_fpSinCosXTest_q : std_logic_vector(1 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expSelectorCos_uid145_fpSinCosXTest_q : std_logic_vector(1 downto 0);
signal signRCond2_uid152_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_d : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_d : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q : std_logic_vector (29 downto 0);
signal leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal zs_uid236_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal mO_uid239_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (62 downto 0);
signal zs_uid244_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal zs_uid250_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (5 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(63 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(63 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (47 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a : std_logic_vector (12 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr : SIGNED (26 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q : std_logic_vector (25 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a : std_logic_vector (14 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b : std_logic_vector (22 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr : SIGNED (38 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q : std_logic_vector (37 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a : std_logic_vector (12 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr : SIGNED (26 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q : std_logic_vector (25 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a : std_logic_vector (14 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b : std_logic_vector (22 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr : SIGNED (38 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q : std_logic_vector (37 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0 : std_logic;
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0 : std_logic;
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q : std_logic_vector (39 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a : std_logic_vector(81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b : std_logic_vector(81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o : std_logic_vector (81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q : std_logic_vector (81 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC0_uid394_tableGensinPiZ_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC1_uid396_tableGensinPiZ_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC2_uid398_tableGensinPiZ_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_q : std_logic_vector (12 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC0_uid400_tableGencosPiZ_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC1_uid402_tableGencosPiZ_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC2_uid404_tableGencosPiZ_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_q : std_logic_vector (12 downto 0);
signal reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q : std_logic_vector (2 downto 0);
signal reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q : std_logic_vector (39 downto 0);
signal reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (39 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q : std_logic_vector (26 downto 0);
signal reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (77 downto 0);
signal reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q : std_logic_vector (67 downto 0);
signal reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q : std_logic_vector (66 downto 0);
signal reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q : std_logic_vector (65 downto 0);
signal reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q : std_logic_vector (67 downto 0);
signal reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q : std_logic_vector (25 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q : std_logic_vector (12 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q : std_logic_vector (20 downto 0);
signal reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q : std_logic_vector (22 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q : std_logic_vector (29 downto 0);
signal reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q : std_logic_vector (6 downto 0);
signal reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q : std_logic_vector (22 downto 0);
signal reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q : std_logic_vector (0 downto 0);
signal reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q : std_logic_vector (12 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q : std_logic_vector (20 downto 0);
signal reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q : std_logic_vector (22 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q : std_logic_vector (29 downto 0);
signal reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q : std_logic_vector (25 downto 0);
signal reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q : std_logic_vector (25 downto 0);
signal reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q : std_logic_vector (6 downto 0);
signal reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q : std_logic_vector (22 downto 0);
signal reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q : std_logic_vector (3 downto 0);
signal reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q : std_logic_vector (52 downto 0);
signal ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q : std_logic_vector (65 downto 0);
signal ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q : std_logic_vector (67 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (7 downto 0);
signal ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (66 downto 0);
signal ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (65 downto 0);
signal ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (64 downto 0);
signal ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q : std_logic_vector (63 downto 0);
signal ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q : std_logic_vector (31 downto 0);
signal ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (58 downto 0);
signal ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q : std_logic_vector (63 downto 0);
signal ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q : std_logic_vector (31 downto 0);
signal ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (58 downto 0);
signal ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (76 downto 0);
signal ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (75 downto 0);
signal ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (74 downto 0);
signal ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q : std_logic_vector (12 downto 0);
signal ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q : std_logic_vector (53 downto 0);
signal ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q : std_logic_vector (12 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0 : std_logic;
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q : signal is true;
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q : std_logic_vector (6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0 : std_logic;
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q : signal is true;
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q : signal is true;
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0 : std_logic;
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0 : std_logic;
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0 : std_logic;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq : std_logic;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q : signal is true;
signal sinXIsXRR_uid41_fpSinCosXTest_a : std_logic_vector(11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_b : std_logic_vector(11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_o : std_logic_vector (11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_a : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_b : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_o : std_logic_vector (11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal yIsZero_uid51_fpSinCosXTest_a : std_logic_vector(65 downto 0);
signal yIsZero_uid51_fpSinCosXTest_b : std_logic_vector(65 downto 0);
signal yIsZero_uid51_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal pad_one_uid55_fpSinCosXTest_q : std_logic_vector (66 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_a : std_logic_vector(70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_b : std_logic_vector(70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_o : std_logic_vector (70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_c : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal InvCmpYToOneMinusY_uid61_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCmpYToOneMinusY_uid61_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid127_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid127_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvSinXIsXRR_uid128_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsXRR_uid128_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid131_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid131_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid132_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid132_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid136_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid136_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvCosXONe_uid149_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCosXONe_uid149_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid151_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid151_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvIntXParity_uid155_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvIntXParity_uid155_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal oFracXRR_uid43_uid43_fpSinCosXTest_q : std_logic_vector (53 downto 0);
signal half_uid53_fpSinCosXTest_q : std_logic_vector (65 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal exp_uid9_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal exp_uid9_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal frac_uid13_fpSinCosXTest_in : std_logic_vector (22 downto 0);
signal frac_uid13_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal signX_uid37_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal signX_uid37_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal expFracX_uid166_px_uid33_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal expFracX_uid166_px_uid33_fpSinCosXTest_b : std_logic_vector (30 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_q : std_logic_vector (9 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_a : std_logic_vector(65 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_b : std_logic_vector(65 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_a : std_logic_vector(67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_b : std_logic_vector(67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_o : std_logic_vector (67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal zSin_uid60_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal zSin_uid60_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal zCos_uid64_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal zCos_uid64_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal expSinHC_uid74_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal excRNaN_uid117_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid117_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid117_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracRPostExcSin_uid122_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExcSin_uid122_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal expRPostExcSin_uid126_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExcSin_uid126_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracRPostExcCos_uid142_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExcCos_uid142_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal expRPostExcCos_uid147_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExcCos_uid147_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cosXONe_uid148_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal cosXONe_uid148_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal cosXONe_uid148_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal finalExp_uid209_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal finalExp_uid209_rrx_uid34_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal extendedFracX_uid47_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal normBitSin_uid93_fpSinCosXTest_in : std_logic_vector (51 downto 0);
signal normBitSin_uid93_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal fracRSinPreRndHigh_uid95_fpSinCosXTest_in : std_logic_vector (50 downto 0);
signal fracRSinPreRndHigh_uid95_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracRSinPreRndLow_uid96_fpSinCosXTest_in : std_logic_vector (49 downto 0);
signal fracRSinPreRndLow_uid96_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal normBitCos_uid106_fpSinCosXTest_in : std_logic_vector (51 downto 0);
signal normBitCos_uid106_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal fracRCosPreRndHigh_uid108_fpSinCosXTest_in : std_logic_vector (50 downto 0);
signal fracRCosPreRndHigh_uid108_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracRCosPreRndLow_uid109_fpSinCosXTest_in : std_logic_vector (49 downto 0);
signal fracRCosPreRndLow_uid109_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q : std_logic_vector (52 downto 0);
signal leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b : std_logic_vector (23 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int : std_logic_vector (80 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q : std_logic_vector (80 downto 0);
signal os_uid196_rrx_uid34_fpSinCosXTest_q : std_logic_vector (79 downto 0);
signal leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal join_uid99_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal join_uid141_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal zSinYBottom_uid59_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal zSinYBottom_uid59_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal zSinOMyBottom_uid58_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal zSinOMyBottom_uid58_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal excSelBitsSin_uid118_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal fpSin_uid134_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal join_uid143_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal fpCos_uid162_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int : std_logic_vector (107 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q : std_logic_vector (107 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal fracX_uid187_rrx_uid34_fpSinCosXTest_in : std_logic_vector (22 downto 0);
signal fracX_uid187_rrx_uid34_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal oFracXRRSmallXRR_uid90_fpSinCosXTest_in : std_logic_vector (53 downto 0);
signal oFracXRRSmallXRR_uid90_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal R_uid167_px_uid33_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal InvFracXIsZero_uid16_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid16_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fxpXShiftVal_uid46_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal fxpXShiftVal_uid46_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal addr_uid81_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal addr_uid81_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal zPsinPiZ_uid84_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal zPsinPiZ_uid84_fpSinCosXTest_b : std_logic_vector (14 downto 0);
signal rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (32 downto 0);
signal addr_uid83_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal addr_uid83_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal zPcosPiZ_uid87_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal zPcosPiZ_uid87_fpSinCosXTest_b : std_logic_vector (14 downto 0);
signal rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (32 downto 0);
signal expSinHCR_uid75_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expSinHCR_uid75_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal expPCos_uid79_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expPCos_uid79_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (66 downto 0);
signal LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (66 downto 0);
signal LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (65 downto 0);
signal LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (58 downto 0);
signal rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (58 downto 0);
signal rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (76 downto 0);
signal LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (76 downto 0);
signal LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (75 downto 0);
signal LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (75 downto 0);
signal LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (74 downto 0);
signal LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (74 downto 0);
signal X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (59 downto 0);
signal X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (59 downto 0);
signal X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (55 downto 0);
signal X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (55 downto 0);
signal fracRSinPreRnd_uid97_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal fracRSinPreRnd_uid97_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal fracRCosPreRnd_uid110_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal fracRCosPreRnd_uid110_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal cosRndOp_uid112_uid113_fpSinCosXTest_q : std_logic_vector (24 downto 0);
signal rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal lowRangeB_uid408_polyEvalsinPiZ_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid408_polyEvalsinPiZ_b : std_logic_vector (0 downto 0);
signal highBBits_uid409_polyEvalsinPiZ_in : std_logic_vector (13 downto 0);
signal highBBits_uid409_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid414_polyEvalsinPiZ_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid414_polyEvalsinPiZ_b : std_logic_vector (1 downto 0);
signal highBBits_uid415_polyEvalsinPiZ_in : std_logic_vector (23 downto 0);
signal highBBits_uid415_polyEvalsinPiZ_b : std_logic_vector (21 downto 0);
signal lowRangeB_uid421_polyEvalcosPiZ_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid421_polyEvalcosPiZ_b : std_logic_vector (0 downto 0);
signal highBBits_uid422_polyEvalcosPiZ_in : std_logic_vector (13 downto 0);
signal highBBits_uid422_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid427_polyEvalcosPiZ_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid427_polyEvalcosPiZ_b : std_logic_vector (1 downto 0);
signal highBBits_uid428_polyEvalcosPiZ_in : std_logic_vector (23 downto 0);
signal highBBits_uid428_polyEvalcosPiZ_b : std_logic_vector (21 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in : std_logic_vector (80 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b : std_logic_vector (26 downto 0);
signal fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in : std_logic_vector (76 downto 0);
signal fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b : std_logic_vector (52 downto 0);
signal intXParity_uid49_fpSinCosXTest_in : std_logic_vector (67 downto 0);
signal intXParity_uid49_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal y_uid50_fpSinCosXTest_in : std_logic_vector (66 downto 0);
signal y_uid50_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal sinRndOp_uid100_uid101_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal expSelBitsCos_uid144_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a : std_logic_vector(108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b : std_logic_vector(108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o : std_logic_vector (108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q : std_logic_vector (108 downto 0);
signal oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal expX_uid186_rrx_uid34_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal expX_uid186_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal exc_N_uid17_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal yT1_uid406_polyEvalsinPiZ_in : std_logic_vector (14 downto 0);
signal yT1_uid406_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal yT1_uid419_polyEvalcosPiZ_in : std_logic_vector (14 downto 0);
signal yT1_uid419_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_a : std_logic_vector(32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_b : std_logic_vector(32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_o : std_logic_vector (32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_q : std_logic_vector (30 downto 0);
signal finalFrac_uid208_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal finalFrac_uid208_rrx_uid34_fpSinCosXTest_q : std_logic_vector (52 downto 0);
signal signComp_uid129_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_a : std_logic_vector(32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_b : std_logic_vector(32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_o : std_logic_vector (32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_q : std_logic_vector (32 downto 0);
signal leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal multFracBits_uid199_rrx_uid34_fpSinCosXTest_in : std_logic_vector (77 downto 0);
signal multFracBits_uid199_rrx_uid34_fpSinCosXTest_b : std_logic_vector (77 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b : std_logic_vector (26 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (5 downto 0);
signal fracRCompCos_uid115_fpSinCosXTest_in : std_logic_vector (23 downto 0);
signal fracRCompCos_uid115_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal expRCompSin_uid116_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal expRCompSin_uid116_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal s1_uid408_uid411_polyEvalsinPiZ_q : std_logic_vector (22 downto 0);
signal s2_uid414_uid417_polyEvalsinPiZ_q : std_logic_vector (32 downto 0);
signal s1_uid421_uid424_polyEvalcosPiZ_q : std_logic_vector (22 downto 0);
signal s2_uid427_uid430_polyEvalcosPiZ_q : std_logic_vector (32 downto 0);
signal RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q : std_logic_vector (61 downto 0);
signal signR_uid130_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signR_uid130_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signR_uid130_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal fracRCompSin_uid103_fpSinCosXTest_in : std_logic_vector (23 downto 0);
signal fracRCompSin_uid103_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal expRCompSin_uid104_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal expRCompSin_uid104_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in : std_logic_vector (77 downto 0);
signal multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (61 downto 0);
signal X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (61 downto 0);
signal X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (45 downto 0);
signal X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (45 downto 0);
signal X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (29 downto 0);
signal X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (29 downto 0);
signal expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal polyEvalSigsinPiZ_uid86_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal polyEvalSigsinPiZ_uid86_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal polyEvalSigcosPiZ_uid89_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal polyEvalSigcosPiZ_uid89_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal expXRR_uid38_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal expXRR_uid38_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal fracXRR_uid39_fpSinCosXTest_in : std_logic_vector (52 downto 0);
signal fracXRR_uid39_fpSinCosXTest_b : std_logic_vector (52 downto 0);
signal pHigh_uid72_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal pHigh_uid72_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal pCos_uid77_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal pCos_uid77_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal r_uid277_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (6 downto 0);
signal r_uid356_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (6 downto 0);
signal expCompOut_uid205_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expCompOut_uid205_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (73 downto 0);
signal LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (73 downto 0);
signal LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (69 downto 0);
signal LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (69 downto 0);
signal LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (65 downto 0);
signal LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (56 downto 0);
signal LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (48 downto 0);
signal LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (48 downto 0);
signal LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (40 downto 0);
signal LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (40 downto 0);
signal LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (56 downto 0);
signal LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (48 downto 0);
signal LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (48 downto 0);
signal LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (40 downto 0);
signal LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (40 downto 0);
signal leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
begin
--xIn(GPIN,3)@0
--GND(CONSTANT,0)
GND_q <= "0";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable(LOGICAL,1282)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q <= not ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor(LOGICAL,1422)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q <= not (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a or ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b);
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top(CONSTANT,1418)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q <= "01011";
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp(LOGICAL,1419)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q <= "1" when ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a = ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b else "0";
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg(REG,1420)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena(REG,1423)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd(LOGICAL,1424)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b <= en;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a and ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b;
--expFracX_uid166_px_uid33_fpSinCosXTest(BITSELECT,165)@0
expFracX_uid166_px_uid33_fpSinCosXTest_in <= a(30 downto 0);
expFracX_uid166_px_uid33_fpSinCosXTest_b <= expFracX_uid166_px_uid33_fpSinCosXTest_in(30 downto 0);
--R_uid167_px_uid33_fpSinCosXTest(BITJOIN,166)@0
R_uid167_px_uid33_fpSinCosXTest_q <= GND_q & expFracX_uid166_px_uid33_fpSinCosXTest_b;
--expX_uid186_rrx_uid34_fpSinCosXTest(BITSELECT,185)@0
expX_uid186_rrx_uid34_fpSinCosXTest_in <= R_uid167_px_uid33_fpSinCosXTest_q(30 downto 0);
expX_uid186_rrx_uid34_fpSinCosXTest_b <= expX_uid186_rrx_uid34_fpSinCosXTest_in(30 downto 23);
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg(DELAY,1412)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid186_rrx_uid34_fpSinCosXTest_b, xout => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt(COUNTER,1414)
-- every=1, low=0, high=11, step=1, init=1
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i = 10 THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i - 11;
ELSE
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg(REG,1415)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux(MUX,1416)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem(DUALMEM,1413)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 12,
width_b => 8,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia
);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--zs_uid244_lzcZSin_uid66_fpSinCosXTest(CONSTANT,243)
zs_uid244_lzcZSin_uid66_fpSinCosXTest_q <= "00000000000000000000000000000000";
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor(LOGICAL,1396)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q <= not (ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a or ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b);
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg(REG,1318)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena(REG,1397)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q = "1") THEN
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd(LOGICAL,1398)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b <= en;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a and ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg(DELAY,1388)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid167_px_uid33_fpSinCosXTest_q, xout => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt(COUNTER,1314)
-- every=1, low=0, high=1, step=1, init=1
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i,1));
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg(REG,1315)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux(MUX,1316)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s <= en;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux: PROCESS (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s, ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q, ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q)
BEGIN
CASE ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s IS
WHEN "0" => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
WHEN "1" => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem(DUALMEM,1389)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 1,
numwords_a => 2,
width_b => 32,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq,
address_a => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa,
data_a => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia
);
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0 <= areset;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq(31 downto 0);
--fracX_uid187_rrx_uid34_fpSinCosXTest(BITSELECT,186)@4
fracX_uid187_rrx_uid34_fpSinCosXTest_in <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q(22 downto 0);
fracX_uid187_rrx_uid34_fpSinCosXTest_b <= fracX_uid187_rrx_uid34_fpSinCosXTest_in(22 downto 0);
--oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest(BITJOIN,196)@4
oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q <= VCC_q & fracX_uid187_rrx_uid34_fpSinCosXTest_b;
--prod_uid198_rrx_uid34_fpSinCosXTest_b_0(BITSELECT,518)@4
prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in <= STD_LOGIC_VECTOR("000" & oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q);
prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b <= prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in(26 downto 0);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1(REG,539)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q <= prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShift_uid24_fpSinCosXTest(CONSTANT,23)
cstBiasMwShift_uid24_fpSinCosXTest_q <= "01110011";
--expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest(SUB,191)@0
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expX_uid186_rrx_uid34_fpSinCosXTest_b);
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0" & cstBiasMwShift_uid24_fpSinCosXTest_q);
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b));
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q <= expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o(8 downto 0);
--expXTableAddr_uid193_rrx_uid34_fpSinCosXTest(BITSELECT,192)@0
expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in <= expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q(7 downto 0);
expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b <= expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0(REG,534)@0
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q <= expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem(DUALMEM,514)@1
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia <= (others => '0');
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa <= (others => '0');
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab <= reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q;
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq,
address_a => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa,
data_a => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia
);
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0 <= areset;
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q <= rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1(REG,537)@3
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q <= rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem(DUALMEM,513)@1
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia <= (others => '0');
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa <= (others => '0');
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab <= reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q;
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq,
address_a => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa,
data_a => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia
);
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0 <= areset;
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q <= rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0(REG,536)@3
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q <= rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid196_rrx_uid34_fpSinCosXTest(BITJOIN,195)@4
os_uid196_rrx_uid34_fpSinCosXTest_q <= reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q & reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q;
--prod_uid198_rrx_uid34_fpSinCosXTest_a_2(BITSELECT,517)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in <= STD_LOGIC_VECTOR("0" & os_uid196_rrx_uid34_fpSinCosXTest_q);
prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in(80 downto 54);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0(REG,542)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0(MULT,521)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1;
END IF;
END IF;
END PROCESS;
--ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a(DELAY,1145)@8
ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a : dspba_delay
GENERIC MAP ( width => 54, depth => 1 )
PORT MAP ( xin => prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q, xout => ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--prod_uid198_rrx_uid34_fpSinCosXTest_align_2(BITSHIFT,524)@9
prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int <= ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int(107 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_a_1(BITSELECT,516)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in <= os_uid196_rrx_uid34_fpSinCosXTest_q(53 downto 0);
prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in(53 downto 27);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0(REG,540)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0(MULT,520)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_align_1(BITSHIFT,523)@8
prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int <= prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q & "000000000000000000000000000";
prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int(80 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_a_0(BITSELECT,515)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in <= os_uid196_rrx_uid34_fpSinCosXTest_q(26 downto 0);
prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in(26 downto 0);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0(REG,538)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0(MULT,519)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_align_0(BITSHIFT,522)@8
prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int <= prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int(53 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0(ADD,525)@8
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a <= STD_LOGIC_VECTOR("0000000000000000000000000000" & prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b <= STD_LOGIC_VECTOR("0" & prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a) + UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b));
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o(81 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0(ADD,526)@9
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a <= STD_LOGIC_VECTOR("000000000000000000000000000" & prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b <= STD_LOGIC_VECTOR("0" & prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a) + UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b));
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o(108 downto 0);
--multFracBits_uid199_rrx_uid34_fpSinCosXTest(BITSELECT,198)@9
multFracBits_uid199_rrx_uid34_fpSinCosXTest_in <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q(77 downto 0);
multFracBits_uid199_rrx_uid34_fpSinCosXTest_b <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_in(77 downto 0);
--multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest(BITSELECT,199)@9
multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b;
multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b <= multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in(77 downto 46);
--reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1(REG,544)@9
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,433)@10
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a(DELAY,1178)@10
ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xout => ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5(REG,555)@12
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q <= ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q;
END IF;
END IF;
END PROCESS;
--zs_uid250_lzcZSin_uid66_fpSinCosXTest(CONSTANT,249)
zs_uid250_lzcZSin_uid66_fpSinCosXTest_q <= "0000000000000000";
--mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest(CONSTANT,434)
mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "11111111111111111111111111111111";
--vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,436)@10
vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q, mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,438)@10
rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in(31 downto 16);
--reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1(REG,546)@10
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,439)@11
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4(REG,554)@11
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q <= vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e(DELAY,1081)@12
ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWE_uid8_fpSinCosXTest(CONSTANT,7)
cstAllZWE_uid8_fpSinCosXTest_q <= "00000000";
--vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,440)@10
vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q(15 downto 0);
vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in(15 downto 0);
--reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,548)@10
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,442)@11
vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q, reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,444)@11
rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in(15 downto 8);
--vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,445)@11
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i <= "1" when vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xin => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d(DELAY,1080)@12
ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xout => ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest(CONSTANT,212)
leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q <= "0000";
--vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,446)@11
vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q(7 downto 0);
vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,550)@11
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,549)@11
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,448)@12
vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q, reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,450)@12
rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in(7 downto 4);
--vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,451)@12
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,553)@12
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest(CONSTANT,226)
leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q <= "00";
--vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,452)@12
vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q(3 downto 0);
vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in(3 downto 0);
--vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,454)@12
vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b, vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
WHEN "1" => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,456)@12
rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in(3 downto 2);
--vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,457)@12
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i <= "1" when vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xin => vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,458)@12
vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q(1 downto 0);
vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in(1 downto 0);
--reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,552)@12
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,551)@12
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,460)@13
vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q, reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,462)@13
rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in(1 downto 1);
--vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,463)@13
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= GND_q;
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest(BITJOIN,464)@13
r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q & ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q & ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q & reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q & vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q & vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
--cstBiasM1_uid23_fpSinCosXTest(CONSTANT,22)
cstBiasM1_uid23_fpSinCosXTest_q <= "01111110";
--expCompOutExt_uid204_rrx_uid34_fpSinCosXTest(SUB,203)@13
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("000" & r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q);
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b));
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q <= expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o(8 downto 0);
--expCompOut_uid205_rrx_uid34_fpSinCosXTest(BITSELECT,204)@13
expCompOut_uid205_rrx_uid34_fpSinCosXTest_in <= expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q(7 downto 0);
expCompOut_uid205_rrx_uid34_fpSinCosXTest_b <= expCompOut_uid205_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2(REG,564)@13
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q <= expCompOut_uid205_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--xBranch_uid191_rrx_uid34_fpSinCosXTest(COMPARE,190)@0
xBranch_uid191_rrx_uid34_fpSinCosXTest_cin <= GND_q;
xBranch_uid191_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid24_fpSinCosXTest_q) & '0';
xBranch_uid191_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & expX_uid186_rrx_uid34_fpSinCosXTest_b) & xBranch_uid191_rrx_uid34_fpSinCosXTest_cin(0);
xBranch_uid191_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xBranch_uid191_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(xBranch_uid191_rrx_uid34_fpSinCosXTest_b));
xBranch_uid191_rrx_uid34_fpSinCosXTest_n(0) <= not xBranch_uid191_rrx_uid34_fpSinCosXTest_o(10);
--reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1(REG,563)@0
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q <= xBranch_uid191_rrx_uid34_fpSinCosXTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b(DELAY,829)@1
ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q, xout => ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalExp_uid209_rrx_uid34_fpSinCosXTest(MUX,208)@14
finalExp_uid209_rrx_uid34_fpSinCosXTest_s <= ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q;
finalExp_uid209_rrx_uid34_fpSinCosXTest: PROCESS (finalExp_uid209_rrx_uid34_fpSinCosXTest_s, en, reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q)
BEGIN
CASE finalExp_uid209_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b(DELAY,833)@14
ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => finalExp_uid209_rrx_uid34_fpSinCosXTest_q, xout => ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1409)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a or ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top(CONSTANT,1279)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q <= "01000";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp(LOGICAL,1280)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q <= "1" when ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a = ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b else "0";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg(REG,1281)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1410)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1411)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1399)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid187_rrx_uid34_fpSinCosXTest_b, xout => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt(COUNTER,1275)
-- every=1, low=0, high=8, step=1, init=1
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i = 7 THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i - 8;
ELSE
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg(REG,1276)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux(MUX,1277)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s, ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q, ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1400)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 4,
numwords_a => 9,
width_b => 23,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(22 downto 0);
--ZerosGB_uid206_rrx_uid34_fpSinCosXTest(CONSTANT,205)
ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q <= "000000000000000000000000000000";
--fracXRExt_uid207_rrx_uid34_fpSinCosXTest(BITJOIN,206)@15
fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q & ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q;
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1499)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1500)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1501)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,474)@9
X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(29 downto 0);
X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in(29 downto 0);
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1491)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 30, depth => 1 )
PORT MAP ( xin => X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1492)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 1,
numwords_a => 2,
width_b => 30,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(29 downto 0);
--leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest(CONSTANT,473)
leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,475)@13
leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1488)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1489)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1490)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,471)@9
X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(45 downto 0);
X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in(45 downto 0);
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1480)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1481)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 1,
numwords_a => 2,
width_b => 46,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(45 downto 0);
--leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,472)@13
leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1477)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1478)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1479)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,468)@9
X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(61 downto 0);
X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in(61 downto 0);
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1469)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1470)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 62,
widthad_a => 1,
numwords_a => 2,
width_b => 62,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(61 downto 0);
--leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,469)@13
leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor(LOGICAL,1510)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q <= not (ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a or ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b);
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena(REG,1511)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q = "1") THEN
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd(LOGICAL,1512)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b <= en;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a and ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg(DELAY,1502)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 78, depth => 1 )
PORT MAP ( xin => multFracBits_uid199_rrx_uid34_fpSinCosXTest_b, xout => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem(DUALMEM,1503)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 78,
widthad_a => 1,
numwords_a => 2,
width_b => 78,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia
);
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq(77 downto 0);
--leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,476)@13
leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in(5 downto 4);
--leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,477)@13
leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b;
leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,485)@13
LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(65 downto 0);
LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in(65 downto 0);
--leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest(CONSTANT,218)
leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q <= "000000000000";
--leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,486)@13
leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b & leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5(REG,560)@13
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,482)@13
LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(69 downto 0);
LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in(69 downto 0);
--leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,483)@13
leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4(REG,559)@13
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,479)@13
LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(73 downto 0);
LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in(73 downto 0);
--leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,480)@13
leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3(REG,558)@13
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2(REG,557)@13
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,487)@13
leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1(REG,556)@13
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,488)@14
leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q;
leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,496)@14
LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(74 downto 0);
LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in(74 downto 0);
--ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1112)@14
ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 75, depth => 1 )
PORT MAP ( xin => LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest(CONSTANT,229)
leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q <= "000";
--leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,497)@15
leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,493)@14
LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(75 downto 0);
LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in(75 downto 0);
--ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1110)@14
ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 76, depth => 1 )
PORT MAP ( xin => LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,494)@15
leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,490)@14
LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(76 downto 0);
LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in(76 downto 0);
--ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1108)@14
ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 77, depth => 1 )
PORT MAP ( xin => LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,491)@15
leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & GND_q;
--reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2(REG,562)@14
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,498)@13
leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a(DELAY,1184)@13
ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1(REG,561)@14
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,499)@15
leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q;
leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracCompOut_uid203_rrx_uid34_fpSinCosXTest(BITSELECT,202)@15
fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in <= leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q(76 downto 0);
fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b <= fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in(76 downto 24);
--ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b(DELAY,826)@0
ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => xBranch_uid191_rrx_uid34_fpSinCosXTest_n, xout => ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalFrac_uid208_rrx_uid34_fpSinCosXTest(MUX,207)@15
finalFrac_uid208_rrx_uid34_fpSinCosXTest_s <= ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q;
finalFrac_uid208_rrx_uid34_fpSinCosXTest: PROCESS (finalFrac_uid208_rrx_uid34_fpSinCosXTest_s, en, fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b, fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE finalFrac_uid208_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b;
WHEN "1" => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RRangeRed_uid210_rrx_uid34_fpSinCosXTest(BITJOIN,209)@15
RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q <= GND_q & ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q & finalFrac_uid208_rrx_uid34_fpSinCosXTest_q;
--expXRR_uid38_fpSinCosXTest(BITSELECT,37)@15
expXRR_uid38_fpSinCosXTest_in <= RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q(60 downto 0);
expXRR_uid38_fpSinCosXTest_b <= expXRR_uid38_fpSinCosXTest_in(60 downto 53);
--reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1(REG,565)@15
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q <= expXRR_uid38_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShiftM2_uid26_fpSinCosXTest(CONSTANT,25)
cstBiasMwShiftM2_uid26_fpSinCosXTest_q <= "01110000";
--cosXIsOneXRR_uid42_fpSinCosXTest(COMPARE,41)@16
cosXIsOneXRR_uid42_fpSinCosXTest_cin <= GND_q;
cosXIsOneXRR_uid42_fpSinCosXTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid26_fpSinCosXTest_q) & '0';
cosXIsOneXRR_uid42_fpSinCosXTest_b <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q) & cosXIsOneXRR_uid42_fpSinCosXTest_cin(0);
cosXIsOneXRR_uid42_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(cosXIsOneXRR_uid42_fpSinCosXTest_a) - SIGNED(cosXIsOneXRR_uid42_fpSinCosXTest_b));
cosXIsOneXRR_uid42_fpSinCosXTest_n(0) <= not cosXIsOneXRR_uid42_fpSinCosXTest_o(11);
--exp_uid9_fpSinCosXTest(BITSELECT,8)@0
exp_uid9_fpSinCosXTest_in <= a(30 downto 0);
exp_uid9_fpSinCosXTest_b <= exp_uid9_fpSinCosXTest_in(30 downto 23);
--sinXIsX_uid40_fpSinCosXTest(COMPARE,39)@0
sinXIsX_uid40_fpSinCosXTest_cin <= GND_q;
sinXIsX_uid40_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid24_fpSinCosXTest_q) & '0';
sinXIsX_uid40_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & exp_uid9_fpSinCosXTest_b) & sinXIsX_uid40_fpSinCosXTest_cin(0);
sinXIsX_uid40_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid40_fpSinCosXTest_a) - UNSIGNED(sinXIsX_uid40_fpSinCosXTest_b));
sinXIsX_uid40_fpSinCosXTest_n(0) <= not sinXIsX_uid40_fpSinCosXTest_o(10);
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a(DELAY,789)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--cosXONe_uid148_fpSinCosXTest(LOGICAL,147)@16
cosXONe_uid148_fpSinCosXTest_a <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q;
cosXONe_uid148_fpSinCosXTest_b <= cosXIsOneXRR_uid42_fpSinCosXTest_n;
cosXONe_uid148_fpSinCosXTest_q <= cosXONe_uid148_fpSinCosXTest_a or cosXONe_uid148_fpSinCosXTest_b;
--ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a(DELAY,791)@16
ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => cosXONe_uid148_fpSinCosXTest_q, xout => ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvCosXONe_uid149_fpSinCosXTest(LOGICAL,148)@20
InvCosXONe_uid149_fpSinCosXTest_a <= ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q;
InvCosXONe_uid149_fpSinCosXTest_q <= not InvCosXONe_uid149_fpSinCosXTest_a;
--cstZwShiftP1_uid27_fpSinCosXTest(CONSTANT,26)
cstZwShiftP1_uid27_fpSinCosXTest_q <= "00000000000000";
--fracXRR_uid39_fpSinCosXTest(BITSELECT,38)@15
fracXRR_uid39_fpSinCosXTest_in <= RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q(52 downto 0);
fracXRR_uid39_fpSinCosXTest_b <= fracXRR_uid39_fpSinCosXTest_in(52 downto 0);
--ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a(DELAY,668)@15
ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => fracXRR_uid39_fpSinCosXTest_b, xout => ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracXRR_uid43_uid43_fpSinCosXTest(BITJOIN,42)@16
oFracXRR_uid43_uid43_fpSinCosXTest_q <= VCC_q & ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q;
--extendedFracX_uid47_fpSinCosXTest(BITJOIN,46)@16
extendedFracX_uid47_fpSinCosXTest_q <= cstZwShiftP1_uid27_fpSinCosXTest_q & oFracXRR_uid43_uid43_fpSinCosXTest_q;
--X55dto0_uid220_fxpX_uid48_fpSinCosXTest(BITSELECT,219)@16
X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(55 downto 0);
X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b <= X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in(55 downto 0);
--leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest(BITJOIN,220)@16
leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q <= X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b & leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5(REG,571)@16
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q <= leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--X59dto0_uid217_fxpX_uid48_fpSinCosXTest(BITSELECT,216)@16
X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(59 downto 0);
X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b <= X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in(59 downto 0);
--leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest(BITJOIN,217)@16
leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q <= X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4(REG,570)@16
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q <= leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--X63dto0_uid214_fxpX_uid48_fpSinCosXTest(BITSELECT,213)@16
X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(63 downto 0);
X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b <= X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in(63 downto 0);
--leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest(BITJOIN,214)@16
leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q <= X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3(REG,569)@16
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q <= leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2(REG,568)@16
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q <= extendedFracX_uid47_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--fxpXShiftValExt_uid45_fpSinCosXTest(SUB,44)@16
fxpXShiftValExt_uid45_fpSinCosXTest_a <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q);
fxpXShiftValExt_uid45_fpSinCosXTest_b <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid26_fpSinCosXTest_q);
fxpXShiftValExt_uid45_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(fxpXShiftValExt_uid45_fpSinCosXTest_a) - SIGNED(fxpXShiftValExt_uid45_fpSinCosXTest_b));
fxpXShiftValExt_uid45_fpSinCosXTest_q <= fxpXShiftValExt_uid45_fpSinCosXTest_o(9 downto 0);
--fxpXShiftVal_uid46_fpSinCosXTest(BITSELECT,45)@16
fxpXShiftVal_uid46_fpSinCosXTest_in <= fxpXShiftValExt_uid45_fpSinCosXTest_q(3 downto 0);
fxpXShiftVal_uid46_fpSinCosXTest_b <= fxpXShiftVal_uid46_fpSinCosXTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest(BITSELECT,221)@16
leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in <= fxpXShiftVal_uid46_fpSinCosXTest_b;
leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b <= leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1(REG,567)@16
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q <= leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest(MUX,222)@17
leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s <= reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q;
leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest: PROCESS (leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s, en, reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q, reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q, reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q, reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest(BITSELECT,230)@17
LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(64 downto 0);
LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in(64 downto 0);
--ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b(DELAY,851)@17
ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest(BITJOIN,231)@18
leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q & leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest(BITSELECT,227)@17
LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(65 downto 0);
LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in(65 downto 0);
--ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b(DELAY,849)@17
ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 66, depth => 1 )
PORT MAP ( xin => LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest(BITJOIN,228)@18
leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest(BITSELECT,224)@17
LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(66 downto 0);
LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in(66 downto 0);
--ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b(DELAY,847)@17
ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 67, depth => 1 )
PORT MAP ( xin => LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest(BITJOIN,225)@18
leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q & GND_q;
--reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2(REG,573)@17
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest(BITSELECT,232)@16
leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in <= fxpXShiftVal_uid46_fpSinCosXTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b <= leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a(DELAY,1195)@16
ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b, xout => ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1(REG,572)@17
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q <= ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest(MUX,233)@18
leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s <= reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q;
leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest: PROCESS (leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s, en, reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q, leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q, leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q, leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q;
WHEN "10" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q;
WHEN "11" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid50_fpSinCosXTest(BITSELECT,49)@18
y_uid50_fpSinCosXTest_in <= leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q(66 downto 0);
y_uid50_fpSinCosXTest_b <= y_uid50_fpSinCosXTest_in(66 downto 1);
--ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b(DELAY,680)@18
ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 66, depth => 2 )
PORT MAP ( xin => y_uid50_fpSinCosXTest_b, xout => ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1(REG,575)@18
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q <= y_uid50_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--pad_one_uid55_fpSinCosXTest(BITJOIN,54)@18
pad_one_uid55_fpSinCosXTest_q <= VCC_q & STD_LOGIC_VECTOR((65 downto 1 => GND_q(0)) & GND_q);
--reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0(REG,574)@18
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q <= pad_one_uid55_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--oneMinusY_uid55_fpSinCosXTest(SUB,55)@19
oneMinusY_uid55_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q);
oneMinusY_uid55_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q);
oneMinusY_uid55_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid55_fpSinCosXTest_a) - UNSIGNED(oneMinusY_uid55_fpSinCosXTest_b));
oneMinusY_uid55_fpSinCosXTest_q <= oneMinusY_uid55_fpSinCosXTest_o(67 downto 0);
--reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0(REG,576)@19
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q <= oneMinusY_uid55_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid57_fpSinCosXTest(COMPARE,56)@20
cmpYToOneMinusY_uid57_fpSinCosXTest_cin <= GND_q;
cmpYToOneMinusY_uid57_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q) & '0';
cmpYToOneMinusY_uid57_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q) & cmpYToOneMinusY_uid57_fpSinCosXTest_cin(0);
cmpYToOneMinusY_uid57_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid57_fpSinCosXTest_a) - UNSIGNED(cmpYToOneMinusY_uid57_fpSinCosXTest_b));
cmpYToOneMinusY_uid57_fpSinCosXTest_c(0) <= cmpYToOneMinusY_uid57_fpSinCosXTest_o(70);
--InvCmpYToOneMinusY_uid61_fpSinCosXTest(LOGICAL,60)@20
InvCmpYToOneMinusY_uid61_fpSinCosXTest_a <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
InvCmpYToOneMinusY_uid61_fpSinCosXTest_q <= not InvCmpYToOneMinusY_uid61_fpSinCosXTest_a;
--intXParity_uid49_fpSinCosXTest(BITSELECT,48)@18
intXParity_uid49_fpSinCosXTest_in <= leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q;
intXParity_uid49_fpSinCosXTest_b <= intXParity_uid49_fpSinCosXTest_in(67 downto 67);
--ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b(DELAY,794)@18
ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => intXParity_uid49_fpSinCosXTest_b, xout => ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--yIsZero_uid51_fpSinCosXTest(LOGICAL,50)@19
yIsZero_uid51_fpSinCosXTest_a <= reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q;
yIsZero_uid51_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000000000000000000000000000000000" & GND_q);
yIsZero_uid51_fpSinCosXTest_q <= "1" when yIsZero_uid51_fpSinCosXTest_a = yIsZero_uid51_fpSinCosXTest_b else "0";
--ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a(DELAY,792)@19
ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => yIsZero_uid51_fpSinCosXTest_q, xout => ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvYIsZero_uid151_fpSinCosXTest(LOGICAL,150)@20
InvYIsZero_uid151_fpSinCosXTest_a <= ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q;
InvYIsZero_uid151_fpSinCosXTest_q <= not InvYIsZero_uid151_fpSinCosXTest_a;
--signRCond2_uid152_fpSinCosXTest(LOGICAL,151)@20
signRCond2_uid152_fpSinCosXTest_a <= InvYIsZero_uid151_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_b <= ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q;
signRCond2_uid152_fpSinCosXTest_c <= InvCmpYToOneMinusY_uid61_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_d <= InvCosXONe_uid149_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_q_i <= signRCond2_uid152_fpSinCosXTest_a and signRCond2_uid152_fpSinCosXTest_b and signRCond2_uid152_fpSinCosXTest_c and signRCond2_uid152_fpSinCosXTest_d;
signRCond2_uid152_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRCond2_uid152_fpSinCosXTest_q, xin => signRCond2_uid152_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--InvIntXParity_uid155_fpSinCosXTest(LOGICAL,154)@20
InvIntXParity_uid155_fpSinCosXTest_a <= ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q;
InvIntXParity_uid155_fpSinCosXTest_q <= not InvIntXParity_uid155_fpSinCosXTest_a;
--signRCond1_uid157_fpSinCosXTest(LOGICAL,156)@20
signRCond1_uid157_fpSinCosXTest_a <= InvYIsZero_uid151_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_b <= InvIntXParity_uid155_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_c <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
signRCond1_uid157_fpSinCosXTest_d <= InvCosXONe_uid149_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_q_i <= signRCond1_uid157_fpSinCosXTest_a and signRCond1_uid157_fpSinCosXTest_b and signRCond1_uid157_fpSinCosXTest_c and signRCond1_uid157_fpSinCosXTest_d;
signRCond1_uid157_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRCond1_uid157_fpSinCosXTest_q, xin => signRCond1_uid157_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--signRCos_uid158_fpSinCosXTest(LOGICAL,157)@21
signRCos_uid158_fpSinCosXTest_a <= signRCond1_uid157_fpSinCosXTest_q;
signRCos_uid158_fpSinCosXTest_b <= signRCond2_uid152_fpSinCosXTest_q;
signRCos_uid158_fpSinCosXTest_q <= signRCos_uid158_fpSinCosXTest_a or signRCos_uid158_fpSinCosXTest_b;
--cstAllZWF_uid7_fpSinCosXTest(CONSTANT,6)
cstAllZWF_uid7_fpSinCosXTest_q <= "00000000000000000000000";
--frac_uid13_fpSinCosXTest(BITSELECT,12)@0
frac_uid13_fpSinCosXTest_in <= a(22 downto 0);
frac_uid13_fpSinCosXTest_b <= frac_uid13_fpSinCosXTest_in(22 downto 0);
--fracXIsZero_uid14_fpSinCosXTest(LOGICAL,13)@0
fracXIsZero_uid14_fpSinCosXTest_a <= frac_uid13_fpSinCosXTest_b;
fracXIsZero_uid14_fpSinCosXTest_b <= cstAllZWF_uid7_fpSinCosXTest_q;
fracXIsZero_uid14_fpSinCosXTest_q <= "1" when fracXIsZero_uid14_fpSinCosXTest_a = fracXIsZero_uid14_fpSinCosXTest_b else "0";
--cstAllOWE_uid6_fpSinCosXTest(CONSTANT,5)
cstAllOWE_uid6_fpSinCosXTest_q <= "11111111";
--expXIsMax_uid12_fpSinCosXTest(LOGICAL,11)@0
expXIsMax_uid12_fpSinCosXTest_a <= exp_uid9_fpSinCosXTest_b;
expXIsMax_uid12_fpSinCosXTest_b <= cstAllOWE_uid6_fpSinCosXTest_q;
expXIsMax_uid12_fpSinCosXTest_q <= "1" when expXIsMax_uid12_fpSinCosXTest_a = expXIsMax_uid12_fpSinCosXTest_b else "0";
--exc_I_uid15_fpSinCosXTest(LOGICAL,14)@0
exc_I_uid15_fpSinCosXTest_a <= expXIsMax_uid12_fpSinCosXTest_q;
exc_I_uid15_fpSinCosXTest_b <= fracXIsZero_uid14_fpSinCosXTest_q;
exc_I_uid15_fpSinCosXTest_q <= exc_I_uid15_fpSinCosXTest_a and exc_I_uid15_fpSinCosXTest_b;
--ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a(DELAY,762)@0
ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 20 )
PORT MAP ( xin => exc_I_uid15_fpSinCosXTest_q, xout => ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_I_uid131_fpSinCosXTest(LOGICAL,130)@20
InvExc_I_uid131_fpSinCosXTest_a <= ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q;
InvExc_I_uid131_fpSinCosXTest_q <= not InvExc_I_uid131_fpSinCosXTest_a;
--reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2(REG,649)@20
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q <= InvExc_I_uid131_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--InvFracXIsZero_uid16_fpSinCosXTest(LOGICAL,15)@0
InvFracXIsZero_uid16_fpSinCosXTest_a <= fracXIsZero_uid14_fpSinCosXTest_q;
InvFracXIsZero_uid16_fpSinCosXTest_q <= not InvFracXIsZero_uid16_fpSinCosXTest_a;
--exc_N_uid17_fpSinCosXTest(LOGICAL,16)@0
exc_N_uid17_fpSinCosXTest_a <= expXIsMax_uid12_fpSinCosXTest_q;
exc_N_uid17_fpSinCosXTest_b <= InvFracXIsZero_uid16_fpSinCosXTest_q;
exc_N_uid17_fpSinCosXTest_q <= exc_N_uid17_fpSinCosXTest_a and exc_N_uid17_fpSinCosXTest_b;
--ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a(DELAY,763)@0
ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 20 )
PORT MAP ( xin => exc_N_uid17_fpSinCosXTest_q, xout => ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid132_fpSinCosXTest(LOGICAL,131)@20
InvExc_N_uid132_fpSinCosXTest_a <= ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q;
InvExc_N_uid132_fpSinCosXTest_q <= not InvExc_N_uid132_fpSinCosXTest_a;
--reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1(REG,648)@20
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q <= InvExc_N_uid132_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--signRCosFull_uid161_fpSinCosXTest(LOGICAL,160)@21
signRCosFull_uid161_fpSinCosXTest_a <= reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q;
signRCosFull_uid161_fpSinCosXTest_b <= reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q;
signRCosFull_uid161_fpSinCosXTest_c <= signRCos_uid158_fpSinCosXTest_q;
signRCosFull_uid161_fpSinCosXTest_q <= signRCosFull_uid161_fpSinCosXTest_a and signRCosFull_uid161_fpSinCosXTest_b and signRCosFull_uid161_fpSinCosXTest_c;
--ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c(DELAY,809)@21
ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signRCosFull_uid161_fpSinCosXTest_q, xout => ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid22_fpSinCosXTest(CONSTANT,21)
cstBias_uid22_fpSinCosXTest_q <= "01111111";
--ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a(DELAY,681)@19
ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 68, depth => 1 )
PORT MAP ( xin => oneMinusY_uid55_fpSinCosXTest_q, xout => ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--zSinOMyBottom_uid58_fpSinCosXTest(BITSELECT,57)@20
zSinOMyBottom_uid58_fpSinCosXTest_in <= ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q(64 downto 0);
zSinOMyBottom_uid58_fpSinCosXTest_b <= zSinOMyBottom_uid58_fpSinCosXTest_in(64 downto 0);
--reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3(REG,579)@20
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q <= zSinOMyBottom_uid58_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--zSinYBottom_uid59_fpSinCosXTest(BITSELECT,58)@20
zSinYBottom_uid59_fpSinCosXTest_in <= ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q(64 downto 0);
zSinYBottom_uid59_fpSinCosXTest_b <= zSinYBottom_uid59_fpSinCosXTest_in(64 downto 0);
--reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2(REG,578)@20
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q <= zSinYBottom_uid59_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1(REG,614)@20
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q <= InvCmpYToOneMinusY_uid61_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--zCos_uid64_fpSinCosXTest(MUX,63)@21
zCos_uid64_fpSinCosXTest_s <= reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q;
zCos_uid64_fpSinCosXTest: PROCESS (zCos_uid64_fpSinCosXTest_s, en, reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q, reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q)
BEGIN
CASE zCos_uid64_fpSinCosXTest_s IS
WHEN "0" => zCos_uid64_fpSinCosXTest_q <= reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q;
WHEN "1" => zCos_uid64_fpSinCosXTest_q <= reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q;
WHEN OTHERS => zCos_uid64_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--addr_uid83_fpSinCosXTest(BITSELECT,82)@21
addr_uid83_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q;
addr_uid83_fpSinCosXTest_b <= addr_uid83_fpSinCosXTest_in(64 downto 57);
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0(REG,630)@21
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q <= addr_uid83_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid404_tableGencosPiZ_lutmem(DUALMEM,532)@22
memoryC2_uid404_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC2_uid404_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC2_uid404_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q;
memoryC2_uid404_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC2_uid404_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid404_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid404_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid404_tableGencosPiZ_lutmem_iq,
address_a => memoryC2_uid404_tableGencosPiZ_lutmem_aa,
data_a => memoryC2_uid404_tableGencosPiZ_lutmem_ia
);
memoryC2_uid404_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC2_uid404_tableGencosPiZ_lutmem_q <= memoryC2_uid404_tableGencosPiZ_lutmem_iq(12 downto 0);
--reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1(REG,632)@24
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q <= memoryC2_uid404_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPcosPiZ_uid87_fpSinCosXTest(BITSELECT,86)@21
zPcosPiZ_uid87_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(56 downto 0);
zPcosPiZ_uid87_fpSinCosXTest_b <= zPcosPiZ_uid87_fpSinCosXTest_in(56 downto 42);
--yT1_uid419_polyEvalcosPiZ(BITSELECT,418)@21
yT1_uid419_polyEvalcosPiZ_in <= zPcosPiZ_uid87_fpSinCosXTest_b;
yT1_uid419_polyEvalcosPiZ_b <= yT1_uid419_polyEvalcosPiZ_in(14 downto 2);
--reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0(REG,631)@21
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q <= yT1_uid419_polyEvalcosPiZ_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg(DELAY,1513)
ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q, xout => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a(DELAY,1125)@22
ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q, xout => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid508_pT1_uid420_polyEvalcosPiZ(MULT,507)@25
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a),14)) * SIGNED(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b);
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a <= (others => '0');
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b <= (others => '0');
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a <= ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b <= reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q <= prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ(BITSELECT,508)@28
prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in <= prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q;
prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in(25 downto 12);
--highBBits_uid422_polyEvalcosPiZ(BITSELECT,421)@28
highBBits_uid422_polyEvalcosPiZ_in <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b;
highBBits_uid422_polyEvalcosPiZ_b <= highBBits_uid422_polyEvalcosPiZ_in(13 downto 1);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a(DELAY,1256)@21
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => addr_uid83_fpSinCosXTest_b, xout => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0(REG,633)@24
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid402_tableGencosPiZ_lutmem(DUALMEM,531)@25
memoryC1_uid402_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC1_uid402_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC1_uid402_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q;
memoryC1_uid402_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC1_uid402_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid402_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid402_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid402_tableGencosPiZ_lutmem_iq,
address_a => memoryC1_uid402_tableGencosPiZ_lutmem_aa,
data_a => memoryC1_uid402_tableGencosPiZ_lutmem_ia
);
memoryC1_uid402_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC1_uid402_tableGencosPiZ_lutmem_q <= memoryC1_uid402_tableGencosPiZ_lutmem_iq(20 downto 0);
--reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0(REG,634)@27
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q <= memoryC1_uid402_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid423_polyEvalcosPiZ(ADD,422)@28
sumAHighB_uid423_polyEvalcosPiZ_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q(20)) & reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q);
sumAHighB_uid423_polyEvalcosPiZ_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid422_polyEvalcosPiZ_b(12)) & highBBits_uid422_polyEvalcosPiZ_b);
sumAHighB_uid423_polyEvalcosPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid423_polyEvalcosPiZ_a) + SIGNED(sumAHighB_uid423_polyEvalcosPiZ_b));
sumAHighB_uid423_polyEvalcosPiZ_q <= sumAHighB_uid423_polyEvalcosPiZ_o(21 downto 0);
--lowRangeB_uid421_polyEvalcosPiZ(BITSELECT,420)@28
lowRangeB_uid421_polyEvalcosPiZ_in <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b(0 downto 0);
lowRangeB_uid421_polyEvalcosPiZ_b <= lowRangeB_uid421_polyEvalcosPiZ_in(0 downto 0);
--s1_uid421_uid424_polyEvalcosPiZ(BITJOIN,423)@28
s1_uid421_uid424_polyEvalcosPiZ_q <= sumAHighB_uid423_polyEvalcosPiZ_q & lowRangeB_uid421_polyEvalcosPiZ_b;
--reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1(REG,636)@28
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q <= s1_uid421_uid424_polyEvalcosPiZ_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor(LOGICAL,1524)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q <= not (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a or ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b);
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top(CONSTANT,1520)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q <= "0100";
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp(LOGICAL,1521)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q <= "1" when ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a = ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b else "0";
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg(REG,1522)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena(REG,1525)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd(LOGICAL,1526)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b <= en;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a and ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b;
--reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0(REG,635)@21
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q <= zPcosPiZ_uid87_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg(DELAY,1514)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q, xout => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt(COUNTER,1516)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i = 3 THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i,3));
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg(REG,1517)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux(MUX,1518)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s <= en;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux: PROCESS (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s, ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q, ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem(DUALMEM,1515)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq,
address_a => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa,
data_a => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia
);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0 <= areset;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq(14 downto 0);
--prodXY_uid511_pT2_uid426_polyEvalcosPiZ(MULT,510)@29
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a),16)) * SIGNED(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b);
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a <= (others => '0');
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b <= (others => '0');
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b <= reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q <= prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ(BITSELECT,511)@32
prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in <= prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q;
prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in(37 downto 14);
--highBBits_uid428_polyEvalcosPiZ(BITSELECT,427)@32
highBBits_uid428_polyEvalcosPiZ_in <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b;
highBBits_uid428_polyEvalcosPiZ_b <= highBBits_uid428_polyEvalcosPiZ_in(23 downto 2);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor(LOGICAL,1577)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q <= not (ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a or ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena(REG,1578)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q = "1") THEN
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd(LOGICAL,1579)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b <= en;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a and ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b;
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg(DELAY,1567)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addr_uid83_fpSinCosXTest_b, xout => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem(DUALMEM,1568)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq,
address_a => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa,
data_a => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia
);
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0(REG,637)@28
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid400_tableGencosPiZ_lutmem(DUALMEM,530)@29
memoryC0_uid400_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC0_uid400_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC0_uid400_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q;
memoryC0_uid400_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC0_uid400_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid400_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid400_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid400_tableGencosPiZ_lutmem_iq,
address_a => memoryC0_uid400_tableGencosPiZ_lutmem_aa,
data_a => memoryC0_uid400_tableGencosPiZ_lutmem_ia
);
memoryC0_uid400_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC0_uid400_tableGencosPiZ_lutmem_q <= memoryC0_uid400_tableGencosPiZ_lutmem_iq(29 downto 0);
--reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0(REG,638)@31
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q <= memoryC0_uid400_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid429_polyEvalcosPiZ(ADD,428)@32
sumAHighB_uid429_polyEvalcosPiZ_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q(29)) & reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q);
sumAHighB_uid429_polyEvalcosPiZ_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid428_polyEvalcosPiZ_b(21)) & highBBits_uid428_polyEvalcosPiZ_b);
sumAHighB_uid429_polyEvalcosPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid429_polyEvalcosPiZ_a) + SIGNED(sumAHighB_uid429_polyEvalcosPiZ_b));
sumAHighB_uid429_polyEvalcosPiZ_q <= sumAHighB_uid429_polyEvalcosPiZ_o(30 downto 0);
--lowRangeB_uid427_polyEvalcosPiZ(BITSELECT,426)@32
lowRangeB_uid427_polyEvalcosPiZ_in <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b(1 downto 0);
lowRangeB_uid427_polyEvalcosPiZ_b <= lowRangeB_uid427_polyEvalcosPiZ_in(1 downto 0);
--s2_uid427_uid430_polyEvalcosPiZ(BITJOIN,429)@32
s2_uid427_uid430_polyEvalcosPiZ_q <= sumAHighB_uid429_polyEvalcosPiZ_q & lowRangeB_uid427_polyEvalcosPiZ_b;
--polyEvalSigcosPiZ_uid89_fpSinCosXTest(BITSELECT,88)@32
polyEvalSigcosPiZ_uid89_fpSinCosXTest_in <= s2_uid427_uid430_polyEvalcosPiZ_q(30 downto 0);
polyEvalSigcosPiZ_uid89_fpSinCosXTest_b <= polyEvalSigcosPiZ_uid89_fpSinCosXTest_in(30 downto 5);
--reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1(REG,640)@32
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q <= polyEvalSigcosPiZ_uid89_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor(LOGICAL,1590)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q <= not (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a or ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b);
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top(CONSTANT,1586)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q <= "010";
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp(LOGICAL,1587)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q <= "1" when ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a = ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b else "0";
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg(REG,1588)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena(REG,1591)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd(LOGICAL,1592)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b <= en;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a and ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b;
--LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest(BITSELECT,388)@27
LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q(63 downto 0);
LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in(63 downto 0);
--leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest(BITJOIN,389)@27
leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b & GND_q;
--cstZmwFRRPwSM1_uid52_fpSinCosXTest(CONSTANT,51)
cstZmwFRRPwSM1_uid52_fpSinCosXTest_q <= "00000000000000000000000000000000000000000000000000000000000000000";
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor(LOGICAL,1455)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q <= not (ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a or ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b);
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena(REG,1456)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q = "1") THEN
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd(LOGICAL,1457)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b <= en;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a and ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b;
--X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest(BITSELECT,359)@21
X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(32 downto 0);
X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b <= X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in(32 downto 0);
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg(DELAY,1447)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem(DUALMEM,1448)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 33,
widthad_a => 1,
numwords_a => 2,
width_b => 33,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia
);
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq(32 downto 0);
--leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest(BITJOIN,360)@25
leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor(LOGICAL,1466)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q <= not (ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a or ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b);
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena(REG,1467)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q = "1") THEN
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd(LOGICAL,1468)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b <= en;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a and ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg(DELAY,1458)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => zCos_uid64_fpSinCosXTest_q, xout => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem(DUALMEM,1459)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 65,
widthad_a => 1,
numwords_a => 2,
width_b => 65,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia
);
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq(64 downto 0);
--zs_uid236_lzcZSin_uid66_fpSinCosXTest(CONSTANT,235)
zs_uid236_lzcZSin_uid66_fpSinCosXTest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--rVStage_uid316_lzcZCos_uid69_fpSinCosXTest(BITSELECT,315)@21
rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q;
rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in(64 downto 1);
--vCount_uid317_lzcZCos_uid69_fpSinCosXTest(LOGICAL,316)@21
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid236_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g(DELAY,985)@22
ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid319_lzcZCos_uid69_fpSinCosXTest(BITSELECT,318)@21
vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(0 downto 0);
vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in(0 downto 0);
--ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b(DELAY,943)@21
ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid239_lzcZSin_uid66_fpSinCosXTest(CONSTANT,238)
mO_uid239_lzcZSin_uid66_fpSinCosXTest_q <= "111111111111111111111111111111111111111111111111111111111111111";
--cStage_uid320_lzcZCos_uid69_fpSinCosXTest(BITJOIN,319)@22
cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q <= ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q & mO_uid239_lzcZSin_uid66_fpSinCosXTest_q;
--ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c(DELAY,945)@21
ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid322_lzcZCos_uid69_fpSinCosXTest(MUX,321)@22
vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid322_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s, en, ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q, cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid324_lzcZCos_uid69_fpSinCosXTest(BITSELECT,323)@22
rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in(63 downto 32);
--vCount_uid325_lzcZCos_uid69_fpSinCosXTest(LOGICAL,324)@22
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f(DELAY,984)@23
ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid326_lzcZCos_uid69_fpSinCosXTest(BITSELECT,325)@22
vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q(31 downto 0);
vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in(31 downto 0);
--ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d(DELAY,952)@22
ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c(DELAY,951)@22
ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid328_lzcZCos_uid69_fpSinCosXTest(MUX,327)@23
vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid328_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s, en, ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q, ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q)
BEGIN
CASE vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q;
WHEN OTHERS => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid330_lzcZCos_uid69_fpSinCosXTest(BITSELECT,329)@23
rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in(31 downto 16);
--vCount_uid331_lzcZCos_uid69_fpSinCosXTest(LOGICAL,330)@23
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b else "0";
--reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4(REG,622)@23
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q <= vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e(DELAY,983)@24
ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid332_lzcZCos_uid69_fpSinCosXTest(BITSELECT,331)@23
vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q(15 downto 0);
vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in(15 downto 0);
--vStagei_uid334_lzcZCos_uid69_fpSinCosXTest(MUX,333)@23
vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid334_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s, en, rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b, vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b;
WHEN "1" => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid336_lzcZCos_uid69_fpSinCosXTest(BITSELECT,335)@23
rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in(15 downto 8);
--reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1(REG,617)@23
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q <= rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid337_lzcZCos_uid69_fpSinCosXTest(LOGICAL,336)@24
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a <= reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q;
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b else "0";
--ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d(DELAY,982)@24
ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid338_lzcZCos_uid69_fpSinCosXTest(BITSELECT,337)@23
vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q(7 downto 0);
vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3(REG,619)@23
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q <= vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid340_lzcZCos_uid69_fpSinCosXTest(MUX,339)@24
vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid340_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s, en, reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q, reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid342_lzcZCos_uid69_fpSinCosXTest(BITSELECT,341)@24
rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in(7 downto 4);
--vCount_uid343_lzcZCos_uid69_fpSinCosXTest(LOGICAL,342)@24
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid344_lzcZCos_uid69_fpSinCosXTest(BITSELECT,343)@24
vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q(3 downto 0);
vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in(3 downto 0);
--reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3(REG,621)@24
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q <= vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2(REG,620)@24
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid346_lzcZCos_uid69_fpSinCosXTest(MUX,345)@25
vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid346_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s, en, reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q, reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid348_lzcZCos_uid69_fpSinCosXTest(BITSELECT,347)@25
rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in(3 downto 2);
--vCount_uid349_lzcZCos_uid69_fpSinCosXTest(LOGICAL,348)@25
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b else "0";
--vStage_uid350_lzcZCos_uid69_fpSinCosXTest(BITSELECT,349)@25
vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q(1 downto 0);
vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in(1 downto 0);
--vStagei_uid352_lzcZCos_uid69_fpSinCosXTest(MUX,351)@25
vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid352_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s, en, rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b, vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b;
WHEN "1" => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid354_lzcZCos_uid69_fpSinCosXTest(BITSELECT,353)@25
rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in(1 downto 1);
--vCount_uid355_lzcZCos_uid69_fpSinCosXTest(LOGICAL,354)@25
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b <= GND_q;
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b else "0";
--r_uid356_lzcZCos_uid69_fpSinCosXTest(BITJOIN,355)@25
r_uid356_lzcZCos_uid69_fpSinCosXTest_q <= ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q & ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q & ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q & ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q & vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q & vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q & vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q;
--leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest(BITSELECT,363)@25
leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q;
leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in(6 downto 5);
--leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest(MUX,364)@25
leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s <= leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b;
leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s, en, ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest(BITSELECT,372)@25
LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(40 downto 0);
LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in(40 downto 0);
--leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest(CONSTANT,292)
leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q <= "000000000000000000000000";
--leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest(BITJOIN,373)@25
leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b & leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5(REG,627)@25
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest(BITSELECT,369)@25
LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(48 downto 0);
LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in(48 downto 0);
--leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest(BITJOIN,370)@25
leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4(REG,626)@25
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest(BITSELECT,366)@25
LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(56 downto 0);
LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in(56 downto 0);
--leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest(BITJOIN,367)@25
leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3(REG,625)@25
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2(REG,624)@25
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest(BITSELECT,374)@25
leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1(REG,623)@25
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q <= leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest(MUX,375)@26
leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s <= reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q;
leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s, en, reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest(BITSELECT,383)@26
LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(58 downto 0);
LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1009)@26
ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest(CONSTANT,303)
leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q <= "000000";
--leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest(BITJOIN,384)@27
leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q;
--LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest(BITSELECT,380)@26
LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(60 downto 0);
LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1007)@26
ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest(BITJOIN,381)@27
leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest(BITSELECT,377)@26
LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(62 downto 0);
LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in(62 downto 0);
--ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1005)@26
ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest(BITJOIN,378)@27
leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2(REG,629)@26
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest(BITSELECT,385)@25
leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1(REG,628)@25
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q <= leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1011)@26
ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest(MUX,386)@27
leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s <= ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q;
leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s, en, reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest(BITSELECT,390)@25
leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1019)@25
ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest(MUX,391)@27
leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s <= ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q;
leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s, en, leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "0" => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "1" => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--pCos_uid77_fpSinCosXTest(BITSELECT,76)@27
pCos_uid77_fpSinCosXTest_in <= leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q;
pCos_uid77_fpSinCosXTest_b <= pCos_uid77_fpSinCosXTest_in(64 downto 39);
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg(DELAY,1580)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => pCos_uid77_fpSinCosXTest_b, xout => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt(COUNTER,1582)
-- every=1, low=0, high=2, step=1, init=1
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i = 1 THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i - 2;
ELSE
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i,2));
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg(REG,1583)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux(MUX,1584)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s <= en;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux: PROCESS (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s, ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q, ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q)
BEGIN
CASE ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s IS
WHEN "0" => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q;
WHEN "1" => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem(DUALMEM,1581)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 2,
numwords_a => 3,
width_b => 26,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq,
address_a => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa,
data_a => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia
);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0 <= areset;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq(25 downto 0);
--reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0(REG,639)@32
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--mulCos_uid105_fpSinCosXTest(MULT,104)@33
mulCos_uid105_fpSinCosXTest_pr <= UNSIGNED(mulCos_uid105_fpSinCosXTest_a) * UNSIGNED(mulCos_uid105_fpSinCosXTest_b);
mulCos_uid105_fpSinCosXTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulCos_uid105_fpSinCosXTest_a <= (others => '0');
mulCos_uid105_fpSinCosXTest_b <= (others => '0');
mulCos_uid105_fpSinCosXTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulCos_uid105_fpSinCosXTest_a <= reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q;
mulCos_uid105_fpSinCosXTest_b <= reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q;
mulCos_uid105_fpSinCosXTest_s1 <= STD_LOGIC_VECTOR(mulCos_uid105_fpSinCosXTest_pr);
END IF;
END IF;
END PROCESS;
mulCos_uid105_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulCos_uid105_fpSinCosXTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulCos_uid105_fpSinCosXTest_q <= mulCos_uid105_fpSinCosXTest_s1;
END IF;
END IF;
END PROCESS;
--normBitCos_uid106_fpSinCosXTest(BITSELECT,105)@36
normBitCos_uid106_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q;
normBitCos_uid106_fpSinCosXTest_b <= normBitCos_uid106_fpSinCosXTest_in(51 downto 51);
--cosRndOp_uid112_uid113_fpSinCosXTest(BITJOIN,112)@36
cosRndOp_uid112_uid113_fpSinCosXTest_q <= normBitCos_uid106_fpSinCosXTest_b & cstAllZWF_uid7_fpSinCosXTest_q & VCC_q;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor(LOGICAL,1296)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q <= not (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a or ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b);
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top(CONSTANT,1292)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q <= "0110";
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp(LOGICAL,1293)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q <= "1" when ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a = ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b else "0";
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg(REG,1294)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena(REG,1297)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd(LOGICAL,1298)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b <= en;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a and ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b;
--reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1(REG,641)@25
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg(DELAY,1286)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q, xout => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt(COUNTER,1288)
-- every=1, low=0, high=6, step=1, init=1
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i = 5 THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i - 6;
ELSE
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i,3));
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg(REG,1289)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux(MUX,1290)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s <= en;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux: PROCESS (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s, ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q, ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem(DUALMEM,1287)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 7,
width_b => 7,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia
);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq(6 downto 0);
--expHardCase_uid78_fpSinCosXTest(SUB,77)@35
expHardCase_uid78_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expHardCase_uid78_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q);
expHardCase_uid78_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid78_fpSinCosXTest_a) - UNSIGNED(expHardCase_uid78_fpSinCosXTest_b));
expHardCase_uid78_fpSinCosXTest_q <= expHardCase_uid78_fpSinCosXTest_o(8 downto 0);
--expPCos_uid79_fpSinCosXTest(BITSELECT,78)@35
expPCos_uid79_fpSinCosXTest_in <= expHardCase_uid78_fpSinCosXTest_q(7 downto 0);
expPCos_uid79_fpSinCosXTest_b <= expPCos_uid79_fpSinCosXTest_in(7 downto 0);
--reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1(REG,642)@35
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q <= expPCos_uid79_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--fracRCosPreRndHigh_uid108_fpSinCosXTest(BITSELECT,107)@36
fracRCosPreRndHigh_uid108_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q(50 downto 0);
fracRCosPreRndHigh_uid108_fpSinCosXTest_b <= fracRCosPreRndHigh_uid108_fpSinCosXTest_in(50 downto 27);
--fracRCosPreRndLow_uid109_fpSinCosXTest(BITSELECT,108)@36
fracRCosPreRndLow_uid109_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q(49 downto 0);
fracRCosPreRndLow_uid109_fpSinCosXTest_b <= fracRCosPreRndLow_uid109_fpSinCosXTest_in(49 downto 26);
--fracRCosPreRnd_uid110_fpSinCosXTest(MUX,109)@36
fracRCosPreRnd_uid110_fpSinCosXTest_s <= normBitCos_uid106_fpSinCosXTest_b;
fracRCosPreRnd_uid110_fpSinCosXTest: PROCESS (fracRCosPreRnd_uid110_fpSinCosXTest_s, en, fracRCosPreRndLow_uid109_fpSinCosXTest_b, fracRCosPreRndHigh_uid108_fpSinCosXTest_b)
BEGIN
CASE fracRCosPreRnd_uid110_fpSinCosXTest_s IS
WHEN "0" => fracRCosPreRnd_uid110_fpSinCosXTest_q <= fracRCosPreRndLow_uid109_fpSinCosXTest_b;
WHEN "1" => fracRCosPreRnd_uid110_fpSinCosXTest_q <= fracRCosPreRndHigh_uid108_fpSinCosXTest_b;
WHEN OTHERS => fracRCosPreRnd_uid110_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracRCosPreRnd_uid111_uid111_fpSinCosXTest(BITJOIN,110)@36
expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q <= reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q & fracRCosPreRnd_uid110_fpSinCosXTest_q;
--expFracRCos_uid114_fpSinCosXTest(ADD,113)@36
expFracRCos_uid114_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q);
expFracRCos_uid114_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00000000" & cosRndOp_uid112_uid113_fpSinCosXTest_q);
expFracRCos_uid114_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRCos_uid114_fpSinCosXTest_a) + UNSIGNED(expFracRCos_uid114_fpSinCosXTest_b));
expFracRCos_uid114_fpSinCosXTest_q <= expFracRCos_uid114_fpSinCosXTest_o(32 downto 0);
--expRCompSin_uid116_fpSinCosXTest(BITSELECT,115)@36
expRCompSin_uid116_fpSinCosXTest_in <= expFracRCos_uid114_fpSinCosXTest_q(31 downto 0);
expRCompSin_uid116_fpSinCosXTest_b <= expRCompSin_uid116_fpSinCosXTest_in(31 downto 24);
--reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2(REG,646)@36
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q <= expRCompSin_uid116_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor(LOGICAL,1385)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q <= not (ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a or ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top(CONSTANT,1305)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q <= "01101";
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp(LOGICAL,1306)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q <= "1" when ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a = ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b else "0";
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg(REG,1307)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena(REG,1386)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q = "1") THEN
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd(LOGICAL,1387)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b <= en;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a and ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b;
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a(DELAY,745)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c(DELAY,783)@16
ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => cosXIsOneXRR_uid42_fpSinCosXTest_n, xout => ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--InvCosXIsOneXRR_uid136_fpSinCosXTest(LOGICAL,135)@16
InvCosXIsOneXRR_uid136_fpSinCosXTest_a <= cosXIsOneXRR_uid42_fpSinCosXTest_n;
InvCosXIsOneXRR_uid136_fpSinCosXTest_q <= not InvCosXIsOneXRR_uid136_fpSinCosXTest_a;
--ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c(DELAY,773)@16
ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => InvCosXIsOneXRR_uid136_fpSinCosXTest_q, xout => ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a(DELAY,755)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsX_uid127_fpSinCosXTest(LOGICAL,126)@18
InvSinXIsX_uid127_fpSinCosXTest_a <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q;
InvSinXIsX_uid127_fpSinCosXTest_q <= not InvSinXIsX_uid127_fpSinCosXTest_a;
--ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b(DELAY,772)@18
ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => InvSinXIsX_uid127_fpSinCosXTest_q, xout => ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--half_uid53_fpSinCosXTest(BITJOIN,52)@19
half_uid53_fpSinCosXTest_q <= VCC_q & cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
--yIsHalf_uid54_fpSinCosXTest(LOGICAL,53)@19
yIsHalf_uid54_fpSinCosXTest_a <= reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q;
yIsHalf_uid54_fpSinCosXTest_b <= half_uid53_fpSinCosXTest_q;
yIsHalf_uid54_fpSinCosXTest_q <= "1" when yIsHalf_uid54_fpSinCosXTest_a = yIsHalf_uid54_fpSinCosXTest_b else "0";
--yHalfCosXNotOne_uid138_fpSinCosXTest(LOGICAL,137)@19
yHalfCosXNotOne_uid138_fpSinCosXTest_a <= yIsHalf_uid54_fpSinCosXTest_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_b <= ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_c <= ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_q <= yHalfCosXNotOne_uid138_fpSinCosXTest_a and yHalfCosXNotOne_uid138_fpSinCosXTest_b and yHalfCosXNotOne_uid138_fpSinCosXTest_c;
--ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b(DELAY,744)@0
ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => exc_I_uid15_fpSinCosXTest_q, xout => ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a(DELAY,743)@0
ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => exc_N_uid17_fpSinCosXTest_q, xout => ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRNaN_uid117_fpSinCosXTest(LOGICAL,116)@19
excRNaN_uid117_fpSinCosXTest_a <= ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q;
excRNaN_uid117_fpSinCosXTest_b <= ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q;
excRNaN_uid117_fpSinCosXTest_q <= excRNaN_uid117_fpSinCosXTest_a or excRNaN_uid117_fpSinCosXTest_b;
--join_uid143_fpSinCosXTest(BITJOIN,142)@19
join_uid143_fpSinCosXTest_q <= ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q & yHalfCosXNotOne_uid138_fpSinCosXTest_q & excRNaN_uid117_fpSinCosXTest_q;
--expSelBitsCos_uid144_fpSinCosXTest(BITJOIN,143)@19
expSelBitsCos_uid144_fpSinCosXTest_q <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q & join_uid143_fpSinCosXTest_q;
--reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0(REG,645)@19
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q <= expSelBitsCos_uid144_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--expSelectorCos_uid145_fpSinCosXTest(LOOKUP,144)@20
expSelectorCos_uid145_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSelectorCos_uid145_fpSinCosXTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q) IS
WHEN "0000" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "0001" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "0010" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "0011" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "0100" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "0101" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "0110" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "0111" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "1000" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "1001" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "1010" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "1011" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "1100" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "1101" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "1110" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "1111" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN OTHERS =>
expSelectorCos_uid145_fpSinCosXTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg(DELAY,1375)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => expSelectorCos_uid145_fpSinCosXTest_q, xout => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt(COUNTER,1301)
-- every=1, low=0, high=13, step=1, init=1
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i = 12 THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i - 13;
ELSE
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg(REG,1302)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux(MUX,1303)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s, ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q, ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem(DUALMEM,1376)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia
);
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq(1 downto 0);
--expRPostExcCos_uid147_fpSinCosXTest(MUX,146)@37
expRPostExcCos_uid147_fpSinCosXTest_s <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q;
expRPostExcCos_uid147_fpSinCosXTest: PROCESS (expRPostExcCos_uid147_fpSinCosXTest_s, en, reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q, cstBias_uid22_fpSinCosXTest_q, cstAllZWE_uid8_fpSinCosXTest_q, cstAllOWE_uid6_fpSinCosXTest_q)
BEGIN
CASE expRPostExcCos_uid147_fpSinCosXTest_s IS
WHEN "00" => expRPostExcCos_uid147_fpSinCosXTest_q <= reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q;
WHEN "01" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstBias_uid22_fpSinCosXTest_q;
WHEN "10" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstAllZWE_uid8_fpSinCosXTest_q;
WHEN "11" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstAllOWE_uid6_fpSinCosXTest_q;
WHEN OTHERS => expRPostExcCos_uid147_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstNaNwF_uid32_fpSinCosXTest(CONSTANT,31)
cstNaNwF_uid32_fpSinCosXTest_q <= "00000000000000000000001";
--fracRCompCos_uid115_fpSinCosXTest(BITSELECT,114)@36
fracRCompCos_uid115_fpSinCosXTest_in <= expFracRCos_uid114_fpSinCosXTest_q(23 downto 0);
fracRCompCos_uid115_fpSinCosXTest_b <= fracRCompCos_uid115_fpSinCosXTest_in(23 downto 1);
--reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2(REG,644)@36
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q <= fracRCompCos_uid115_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor(LOGICAL,1372)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q <= not (ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a or ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b);
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena(REG,1373)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q = "1") THEN
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd(LOGICAL,1374)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b <= en;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a and ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b;
--reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1(REG,613)@19
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q <= excRNaN_uid117_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3(REG,612)@19
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q <= ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q;
END IF;
END IF;
END PROCESS;
--reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2(REG,611)@19
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q;
END IF;
END IF;
END PROCESS;
--reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1(REG,610)@19
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q <= yHalfCosXNotOne_uid138_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--rZOrOne_uid140_fpSinCosXTest(LOGICAL,139)@20
rZOrOne_uid140_fpSinCosXTest_a <= reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q;
rZOrOne_uid140_fpSinCosXTest_b <= reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q;
rZOrOne_uid140_fpSinCosXTest_c <= reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q;
rZOrOne_uid140_fpSinCosXTest_q <= rZOrOne_uid140_fpSinCosXTest_a or rZOrOne_uid140_fpSinCosXTest_b or rZOrOne_uid140_fpSinCosXTest_c;
--join_uid141_fpSinCosXTest(BITJOIN,140)@20
join_uid141_fpSinCosXTest_q <= reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q & rZOrOne_uid140_fpSinCosXTest_q;
--reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1(REG,643)@20
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q <= join_uid141_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg(DELAY,1362)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q, xout => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem(DUALMEM,1363)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia
);
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq(1 downto 0);
--fracRPostExcCos_uid142_fpSinCosXTest(MUX,141)@37
fracRPostExcCos_uid142_fpSinCosXTest_s <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q;
fracRPostExcCos_uid142_fpSinCosXTest: PROCESS (fracRPostExcCos_uid142_fpSinCosXTest_s, en, reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q, cstAllZWF_uid7_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q)
BEGIN
CASE fracRPostExcCos_uid142_fpSinCosXTest_s IS
WHEN "00" => fracRPostExcCos_uid142_fpSinCosXTest_q <= reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q;
WHEN "01" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstAllZWF_uid7_fpSinCosXTest_q;
WHEN "10" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN "11" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN OTHERS => fracRPostExcCos_uid142_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpCos_uid162_fpSinCosXTest(BITJOIN,161)@37
fpCos_uid162_fpSinCosXTest_q <= ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q & expRPostExcCos_uid147_fpSinCosXTest_q & fracRPostExcCos_uid142_fpSinCosXTest_q;
--cstBiasMwShiftM2_uid25_fpSinCosXTest(CONSTANT,24)
cstBiasMwShiftM2_uid25_fpSinCosXTest_q <= "01110001";
--sinXIsXRR_uid41_fpSinCosXTest(COMPARE,40)@16
sinXIsXRR_uid41_fpSinCosXTest_cin <= GND_q;
sinXIsXRR_uid41_fpSinCosXTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid25_fpSinCosXTest_q) & '0';
sinXIsXRR_uid41_fpSinCosXTest_b <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q) & sinXIsXRR_uid41_fpSinCosXTest_cin(0);
sinXIsXRR_uid41_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(sinXIsXRR_uid41_fpSinCosXTest_a) - SIGNED(sinXIsXRR_uid41_fpSinCosXTest_b));
sinXIsXRR_uid41_fpSinCosXTest_n(0) <= not sinXIsXRR_uid41_fpSinCosXTest_o(11);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a(DELAY,756)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsXRR_uid128_fpSinCosXTest(LOGICAL,127)@18
InvSinXIsXRR_uid128_fpSinCosXTest_a <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q;
InvSinXIsXRR_uid128_fpSinCosXTest_q <= not InvSinXIsXRR_uid128_fpSinCosXTest_a;
--signComp_uid129_fpSinCosXTest(LOGICAL,128)@18
signComp_uid129_fpSinCosXTest_a <= InvSinXIsXRR_uid128_fpSinCosXTest_q;
signComp_uid129_fpSinCosXTest_b <= InvSinXIsX_uid127_fpSinCosXTest_q;
signComp_uid129_fpSinCosXTest_c <= intXParity_uid49_fpSinCosXTest_b;
signComp_uid129_fpSinCosXTest_q <= signComp_uid129_fpSinCosXTest_a and signComp_uid129_fpSinCosXTest_b and signComp_uid129_fpSinCosXTest_c;
--signX_uid37_fpSinCosXTest(BITSELECT,36)@0
signX_uid37_fpSinCosXTest_in <= a;
signX_uid37_fpSinCosXTest_b <= signX_uid37_fpSinCosXTest_in(31 downto 31);
--ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a(DELAY,760)@0
ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => signX_uid37_fpSinCosXTest_b, xout => ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid130_fpSinCosXTest(LOGICAL,129)@18
signR_uid130_fpSinCosXTest_a <= ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q;
signR_uid130_fpSinCosXTest_b <= signComp_uid129_fpSinCosXTest_q;
signR_uid130_fpSinCosXTest_q <= signR_uid130_fpSinCosXTest_a xor signR_uid130_fpSinCosXTest_b;
--ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c(DELAY,766)@18
ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => signR_uid130_fpSinCosXTest_q, xout => ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--signRSinFull_uid133_fpSinCosXTest(LOGICAL,132)@20
signRSinFull_uid133_fpSinCosXTest_a <= InvExc_N_uid132_fpSinCosXTest_q;
signRSinFull_uid133_fpSinCosXTest_b <= InvExc_I_uid131_fpSinCosXTest_q;
signRSinFull_uid133_fpSinCosXTest_c <= ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q;
signRSinFull_uid133_fpSinCosXTest_q_i <= signRSinFull_uid133_fpSinCosXTest_a and signRSinFull_uid133_fpSinCosXTest_b and signRSinFull_uid133_fpSinCosXTest_c;
signRSinFull_uid133_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRSinFull_uid133_fpSinCosXTest_q, xin => signRSinFull_uid133_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c(DELAY,769)@21
ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signRSinFull_uid133_fpSinCosXTest_q, xout => ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor(LOGICAL,1359)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q <= not (ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a or ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b);
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top(CONSTANT,1342)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q <= "0100010";
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp(LOGICAL,1343)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q <= "1" when ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a = ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b else "0";
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg(REG,1344)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena(REG,1360)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q = "1") THEN
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd(LOGICAL,1361)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b <= en;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a and ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg(DELAY,1349)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => exp_uid9_fpSinCosXTest_b, xout => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt(COUNTER,1338)
-- every=1, low=0, high=34, step=1, init=1
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i = 33 THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i - 34;
ELSE
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i,6));
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg(REG,1339)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux(MUX,1340)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem(DUALMEM,1350)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 6,
numwords_a => 35,
width_b => 8,
widthad_b => 6,
numwords_b => 35,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia
);
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a(DELAY,1228)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1(REG,605)@35
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor(LOGICAL,1309)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q <= not (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a or ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena(REG,1310)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd(LOGICAL,1311)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b <= en;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a and ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b;
--oFracXRRSmallXRR_uid90_fpSinCosXTest(BITSELECT,89)@16
oFracXRRSmallXRR_uid90_fpSinCosXTest_in <= oFracXRR_uid43_uid43_fpSinCosXTest_q;
oFracXRRSmallXRR_uid90_fpSinCosXTest_b <= oFracXRRSmallXRR_uid90_fpSinCosXTest_in(53 downto 28);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg(DELAY,1299)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => oFracXRRSmallXRR_uid90_fpSinCosXTest_b, xout => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem(DUALMEM,1300)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 4,
numwords_a => 14,
width_b => 26,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia
);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq(25 downto 0);
--reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1(REG,577)@20
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
END IF;
END IF;
END PROCESS;
--zSin_uid60_fpSinCosXTest(MUX,59)@21
zSin_uid60_fpSinCosXTest_s <= reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q;
zSin_uid60_fpSinCosXTest: PROCESS (zSin_uid60_fpSinCosXTest_s, en, reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q, reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q)
BEGIN
CASE zSin_uid60_fpSinCosXTest_s IS
WHEN "0" => zSin_uid60_fpSinCosXTest_q <= reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q;
WHEN "1" => zSin_uid60_fpSinCosXTest_q <= reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q;
WHEN OTHERS => zSin_uid60_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--addr_uid81_fpSinCosXTest(BITSELECT,80)@21
addr_uid81_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q;
addr_uid81_fpSinCosXTest_b <= addr_uid81_fpSinCosXTest_in(64 downto 57);
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0(REG,595)@21
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q <= addr_uid81_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid398_tableGensinPiZ_lutmem(DUALMEM,529)@22
memoryC2_uid398_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC2_uid398_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC2_uid398_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q;
memoryC2_uid398_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC2_uid398_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid398_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid398_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid398_tableGensinPiZ_lutmem_iq,
address_a => memoryC2_uid398_tableGensinPiZ_lutmem_aa,
data_a => memoryC2_uid398_tableGensinPiZ_lutmem_ia
);
memoryC2_uid398_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC2_uid398_tableGensinPiZ_lutmem_q <= memoryC2_uid398_tableGensinPiZ_lutmem_iq(12 downto 0);
--reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1(REG,597)@24
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q <= memoryC2_uid398_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPsinPiZ_uid84_fpSinCosXTest(BITSELECT,83)@21
zPsinPiZ_uid84_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(56 downto 0);
zPsinPiZ_uid84_fpSinCosXTest_b <= zPsinPiZ_uid84_fpSinCosXTest_in(56 downto 42);
--yT1_uid406_polyEvalsinPiZ(BITSELECT,405)@21
yT1_uid406_polyEvalsinPiZ_in <= zPsinPiZ_uid84_fpSinCosXTest_b;
yT1_uid406_polyEvalsinPiZ_b <= yT1_uid406_polyEvalsinPiZ_in(14 downto 2);
--ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg(DELAY,1540)
ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => yT1_uid406_polyEvalsinPiZ_b, xout => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a(DELAY,1219)@21
ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q, xout => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0(REG,596)@24
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q <= ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid502_pT1_uid407_polyEvalsinPiZ(MULT,501)@25
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a),14)) * SIGNED(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b);
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a <= (others => '0');
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b <= (others => '0');
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a <= reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b <= reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q <= prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ(BITSELECT,502)@28
prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in <= prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q;
prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in(25 downto 12);
--highBBits_uid409_polyEvalsinPiZ(BITSELECT,408)@28
highBBits_uid409_polyEvalsinPiZ_in <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b;
highBBits_uid409_polyEvalsinPiZ_b <= highBBits_uid409_polyEvalsinPiZ_in(13 downto 1);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a(DELAY,1221)@21
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => addr_uid81_fpSinCosXTest_b, xout => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0(REG,598)@24
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid396_tableGensinPiZ_lutmem(DUALMEM,528)@25
memoryC1_uid396_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC1_uid396_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC1_uid396_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q;
memoryC1_uid396_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC1_uid396_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid396_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid396_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid396_tableGensinPiZ_lutmem_iq,
address_a => memoryC1_uid396_tableGensinPiZ_lutmem_aa,
data_a => memoryC1_uid396_tableGensinPiZ_lutmem_ia
);
memoryC1_uid396_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC1_uid396_tableGensinPiZ_lutmem_q <= memoryC1_uid396_tableGensinPiZ_lutmem_iq(20 downto 0);
--reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0(REG,599)@27
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q <= memoryC1_uid396_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid410_polyEvalsinPiZ(ADD,409)@28
sumAHighB_uid410_polyEvalsinPiZ_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q(20)) & reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q);
sumAHighB_uid410_polyEvalsinPiZ_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid409_polyEvalsinPiZ_b(12)) & highBBits_uid409_polyEvalsinPiZ_b);
sumAHighB_uid410_polyEvalsinPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid410_polyEvalsinPiZ_a) + SIGNED(sumAHighB_uid410_polyEvalsinPiZ_b));
sumAHighB_uid410_polyEvalsinPiZ_q <= sumAHighB_uid410_polyEvalsinPiZ_o(21 downto 0);
--lowRangeB_uid408_polyEvalsinPiZ(BITSELECT,407)@28
lowRangeB_uid408_polyEvalsinPiZ_in <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b(0 downto 0);
lowRangeB_uid408_polyEvalsinPiZ_b <= lowRangeB_uid408_polyEvalsinPiZ_in(0 downto 0);
--s1_uid408_uid411_polyEvalsinPiZ(BITJOIN,410)@28
s1_uid408_uid411_polyEvalsinPiZ_q <= sumAHighB_uid410_polyEvalsinPiZ_q & lowRangeB_uid408_polyEvalsinPiZ_b;
--reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1(REG,601)@28
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q <= s1_uid408_uid411_polyEvalsinPiZ_q;
END IF;
END IF;
END PROCESS;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor(LOGICAL,1551)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q <= not (ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a or ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b);
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena(REG,1552)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q = "1") THEN
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd(LOGICAL,1553)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b <= en;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a and ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg(DELAY,1541)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => zPsinPiZ_uid84_fpSinCosXTest_b, xout => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem(DUALMEM,1542)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq,
address_a => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa,
data_a => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia
);
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0 <= areset;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq(14 downto 0);
--reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0(REG,600)@28
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid505_pT2_uid413_polyEvalsinPiZ(MULT,504)@29
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a),16)) * SIGNED(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b);
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a <= (others => '0');
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b <= (others => '0');
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a <= reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b <= reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q <= prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ(BITSELECT,505)@32
prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in <= prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q;
prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in(37 downto 14);
--highBBits_uid415_polyEvalsinPiZ(BITSELECT,414)@32
highBBits_uid415_polyEvalsinPiZ_in <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b;
highBBits_uid415_polyEvalsinPiZ_b <= highBBits_uid415_polyEvalsinPiZ_in(23 downto 2);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor(LOGICAL,1564)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q <= not (ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a or ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena(REG,1565)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q = "1") THEN
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd(LOGICAL,1566)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b <= en;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a and ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b;
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg(DELAY,1554)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addr_uid81_fpSinCosXTest_b, xout => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem(DUALMEM,1555)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq,
address_a => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa,
data_a => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia
);
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0(REG,602)@28
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid394_tableGensinPiZ_lutmem(DUALMEM,527)@29
memoryC0_uid394_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC0_uid394_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC0_uid394_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q;
memoryC0_uid394_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC0_uid394_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid394_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid394_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid394_tableGensinPiZ_lutmem_iq,
address_a => memoryC0_uid394_tableGensinPiZ_lutmem_aa,
data_a => memoryC0_uid394_tableGensinPiZ_lutmem_ia
);
memoryC0_uid394_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC0_uid394_tableGensinPiZ_lutmem_q <= memoryC0_uid394_tableGensinPiZ_lutmem_iq(29 downto 0);
--reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0(REG,603)@31
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q <= memoryC0_uid394_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid416_polyEvalsinPiZ(ADD,415)@32
sumAHighB_uid416_polyEvalsinPiZ_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q(29)) & reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q);
sumAHighB_uid416_polyEvalsinPiZ_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid415_polyEvalsinPiZ_b(21)) & highBBits_uid415_polyEvalsinPiZ_b);
sumAHighB_uid416_polyEvalsinPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid416_polyEvalsinPiZ_a) + SIGNED(sumAHighB_uid416_polyEvalsinPiZ_b));
sumAHighB_uid416_polyEvalsinPiZ_q <= sumAHighB_uid416_polyEvalsinPiZ_o(30 downto 0);
--lowRangeB_uid414_polyEvalsinPiZ(BITSELECT,413)@32
lowRangeB_uid414_polyEvalsinPiZ_in <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b(1 downto 0);
lowRangeB_uid414_polyEvalsinPiZ_b <= lowRangeB_uid414_polyEvalsinPiZ_in(1 downto 0);
--s2_uid414_uid417_polyEvalsinPiZ(BITJOIN,416)@32
s2_uid414_uid417_polyEvalsinPiZ_q <= sumAHighB_uid416_polyEvalsinPiZ_q & lowRangeB_uid414_polyEvalsinPiZ_b;
--polyEvalSigsinPiZ_uid86_fpSinCosXTest(BITSELECT,85)@32
polyEvalSigsinPiZ_uid86_fpSinCosXTest_in <= s2_uid414_uid417_polyEvalsinPiZ_q(30 downto 0);
polyEvalSigsinPiZ_uid86_fpSinCosXTest_b <= polyEvalSigsinPiZ_uid86_fpSinCosXTest_in(30 downto 5);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b(DELAY,708)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--multSinOp2_uid91_fpSinCosXTest(MUX,90)@32
multSinOp2_uid91_fpSinCosXTest_s <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q;
multSinOp2_uid91_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSinOp2_uid91_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE multSinOp2_uid91_fpSinCosXTest_s IS
WHEN "0" => multSinOp2_uid91_fpSinCosXTest_q <= polyEvalSigsinPiZ_uid86_fpSinCosXTest_b;
WHEN "1" => multSinOp2_uid91_fpSinCosXTest_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => multSinOp2_uid91_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor(LOGICAL,1320)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q <= not (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a or ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b);
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena(REG,1321)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd(LOGICAL,1322)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b <= en;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a and ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b;
--cPi_uid71_fpSinCosXTest(CONSTANT,70)
cPi_uid71_fpSinCosXTest_q <= "11001001000011111101101011";
--LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest(BITSELECT,309)@27
LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q(63 downto 0);
LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in(63 downto 0);
--leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest(BITJOIN,310)@27
leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b & GND_q;
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor(LOGICAL,1433)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q <= not (ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a or ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b);
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena(REG,1434)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q = "1") THEN
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd(LOGICAL,1435)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b <= en;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a and ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b;
--X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest(BITSELECT,280)@21
X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(32 downto 0);
X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b <= X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in(32 downto 0);
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg(DELAY,1425)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem(DUALMEM,1426)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 33,
widthad_a => 1,
numwords_a => 2,
width_b => 33,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia
);
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq(32 downto 0);
--leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest(BITJOIN,281)@25
leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor(LOGICAL,1444)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q <= not (ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a or ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b);
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena(REG,1445)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q = "1") THEN
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd(LOGICAL,1446)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b <= en;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a and ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg(DELAY,1436)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => zSin_uid60_fpSinCosXTest_q, xout => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem(DUALMEM,1437)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 65,
widthad_a => 1,
numwords_a => 2,
width_b => 65,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia
);
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq(64 downto 0);
--rVStage_uid237_lzcZSin_uid66_fpSinCosXTest(BITSELECT,236)@21
rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q;
rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in(64 downto 1);
--vCount_uid238_lzcZSin_uid66_fpSinCosXTest(LOGICAL,237)@21
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid236_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g(DELAY,903)@22
ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid240_lzcZSin_uid66_fpSinCosXTest(BITSELECT,239)@21
vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(0 downto 0);
vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in(0 downto 0);
--ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b(DELAY,861)@21
ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cStage_uid241_lzcZSin_uid66_fpSinCosXTest(BITJOIN,240)@22
cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q <= ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q & mO_uid239_lzcZSin_uid66_fpSinCosXTest_q;
--ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c(DELAY,863)@21
ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid243_lzcZSin_uid66_fpSinCosXTest(MUX,242)@22
vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid243_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s, en, ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q, cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid245_lzcZSin_uid66_fpSinCosXTest(BITSELECT,244)@22
rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in(63 downto 32);
--vCount_uid246_lzcZSin_uid66_fpSinCosXTest(LOGICAL,245)@22
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f(DELAY,902)@23
ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid247_lzcZSin_uid66_fpSinCosXTest(BITSELECT,246)@22
vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q(31 downto 0);
vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in(31 downto 0);
--ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d(DELAY,870)@22
ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c(DELAY,869)@22
ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid249_lzcZSin_uid66_fpSinCosXTest(MUX,248)@23
vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid249_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s, en, ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q, ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q)
BEGIN
CASE vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q;
WHEN OTHERS => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid251_lzcZSin_uid66_fpSinCosXTest(BITSELECT,250)@23
rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in(31 downto 16);
--vCount_uid252_lzcZSin_uid66_fpSinCosXTest(LOGICAL,251)@23
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b else "0";
--reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4(REG,585)@23
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q <= vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e(DELAY,901)@24
ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid253_lzcZSin_uid66_fpSinCosXTest(BITSELECT,252)@23
vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q(15 downto 0);
vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in(15 downto 0);
--vStagei_uid255_lzcZSin_uid66_fpSinCosXTest(MUX,254)@23
vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid255_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s, en, rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b, vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b;
WHEN "1" => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid257_lzcZSin_uid66_fpSinCosXTest(BITSELECT,256)@23
rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in(15 downto 8);
--reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1(REG,580)@23
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q <= rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid258_lzcZSin_uid66_fpSinCosXTest(LOGICAL,257)@24
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a <= reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q;
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b else "0";
--ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d(DELAY,900)@24
ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid259_lzcZSin_uid66_fpSinCosXTest(BITSELECT,258)@23
vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q(7 downto 0);
vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3(REG,582)@23
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q <= vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid261_lzcZSin_uid66_fpSinCosXTest(MUX,260)@24
vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid261_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s, en, reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q, reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid263_lzcZSin_uid66_fpSinCosXTest(BITSELECT,262)@24
rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in(7 downto 4);
--vCount_uid264_lzcZSin_uid66_fpSinCosXTest(LOGICAL,263)@24
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid265_lzcZSin_uid66_fpSinCosXTest(BITSELECT,264)@24
vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q(3 downto 0);
vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in(3 downto 0);
--reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3(REG,584)@24
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q <= vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2(REG,583)@24
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid267_lzcZSin_uid66_fpSinCosXTest(MUX,266)@25
vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid267_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s, en, reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q, reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid269_lzcZSin_uid66_fpSinCosXTest(BITSELECT,268)@25
rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in(3 downto 2);
--vCount_uid270_lzcZSin_uid66_fpSinCosXTest(LOGICAL,269)@25
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b else "0";
--vStage_uid271_lzcZSin_uid66_fpSinCosXTest(BITSELECT,270)@25
vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q(1 downto 0);
vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in(1 downto 0);
--vStagei_uid273_lzcZSin_uid66_fpSinCosXTest(MUX,272)@25
vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid273_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s, en, rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b, vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b;
WHEN "1" => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid275_lzcZSin_uid66_fpSinCosXTest(BITSELECT,274)@25
rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in(1 downto 1);
--vCount_uid276_lzcZSin_uid66_fpSinCosXTest(LOGICAL,275)@25
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b <= GND_q;
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b else "0";
--r_uid277_lzcZSin_uid66_fpSinCosXTest(BITJOIN,276)@25
r_uid277_lzcZSin_uid66_fpSinCosXTest_q <= ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q & ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q & ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q & ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q & vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q & vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q & vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q;
--leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest(BITSELECT,284)@25
leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q;
leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in(6 downto 5);
--leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest(MUX,285)@25
leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s <= leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b;
leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s, en, ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest(BITSELECT,293)@25
LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(40 downto 0);
LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in(40 downto 0);
--leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest(BITJOIN,294)@25
leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b & leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5(REG,590)@25
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest(BITSELECT,290)@25
LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(48 downto 0);
LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in(48 downto 0);
--leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest(BITJOIN,291)@25
leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4(REG,589)@25
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest(BITSELECT,287)@25
LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(56 downto 0);
LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in(56 downto 0);
--leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest(BITJOIN,288)@25
leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3(REG,588)@25
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2(REG,587)@25
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest(BITSELECT,295)@25
leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1(REG,586)@25
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q <= leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest(MUX,296)@26
leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s <= reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q;
leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s, en, reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest(BITSELECT,304)@26
LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(58 downto 0);
LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b(DELAY,927)@26
ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest(BITJOIN,305)@27
leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q;
--LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest(BITSELECT,301)@26
LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(60 downto 0);
LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b(DELAY,925)@26
ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest(BITJOIN,302)@27
leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest(BITSELECT,298)@26
LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(62 downto 0);
LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in(62 downto 0);
--ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b(DELAY,923)@26
ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest(BITJOIN,299)@27
leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2(REG,592)@26
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest(BITSELECT,306)@25
leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in(2 downto 1);
--ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a(DELAY,1214)@25
ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1(REG,591)@26
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q <= ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest(MUX,307)@27
leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s <= reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q;
leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s, en, reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest(BITSELECT,311)@25
leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b(DELAY,937)@25
ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest(MUX,312)@27
leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s <= ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q;
leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s, en, leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "0" => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "1" => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--pHigh_uid72_fpSinCosXTest(BITSELECT,71)@27
pHigh_uid72_fpSinCosXTest_in <= leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q;
pHigh_uid72_fpSinCosXTest_b <= pHigh_uid72_fpSinCosXTest_in(64 downto 39);
--reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2(REG,594)@27
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q <= pHigh_uid72_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a(DELAY,1216)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1(REG,593)@27
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--p_uid73_fpSinCosXTest(MUX,72)@28
p_uid73_fpSinCosXTest_s <= reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q;
p_uid73_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p_uid73_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE p_uid73_fpSinCosXTest_s IS
WHEN "0" => p_uid73_fpSinCosXTest_q <= reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q;
WHEN "1" => p_uid73_fpSinCosXTest_q <= cPi_uid71_fpSinCosXTest_q;
WHEN OTHERS => p_uid73_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg(DELAY,1312)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => p_uid73_fpSinCosXTest_q, xout => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem(DUALMEM,1313)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 1,
numwords_a => 2,
width_b => 26,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq,
address_a => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa,
data_a => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia
);
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0 <= areset;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq(25 downto 0);
--mulSin_uid92_fpSinCosXTest(MULT,91)@33
mulSin_uid92_fpSinCosXTest_pr <= UNSIGNED(mulSin_uid92_fpSinCosXTest_a) * UNSIGNED(mulSin_uid92_fpSinCosXTest_b);
mulSin_uid92_fpSinCosXTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulSin_uid92_fpSinCosXTest_a <= (others => '0');
mulSin_uid92_fpSinCosXTest_b <= (others => '0');
mulSin_uid92_fpSinCosXTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulSin_uid92_fpSinCosXTest_a <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q;
mulSin_uid92_fpSinCosXTest_b <= multSinOp2_uid91_fpSinCosXTest_q;
mulSin_uid92_fpSinCosXTest_s1 <= STD_LOGIC_VECTOR(mulSin_uid92_fpSinCosXTest_pr);
END IF;
END IF;
END PROCESS;
mulSin_uid92_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulSin_uid92_fpSinCosXTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulSin_uid92_fpSinCosXTest_q <= mulSin_uid92_fpSinCosXTest_s1;
END IF;
END IF;
END PROCESS;
--normBitSin_uid93_fpSinCosXTest(BITSELECT,92)@36
normBitSin_uid93_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q;
normBitSin_uid93_fpSinCosXTest_b <= normBitSin_uid93_fpSinCosXTest_in(51 downto 51);
--join_uid99_fpSinCosXTest(BITJOIN,98)@36
join_uid99_fpSinCosXTest_q <= reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q & normBitSin_uid93_fpSinCosXTest_b;
--sinRndOp_uid100_uid101_fpSinCosXTest(BITJOIN,100)@36
sinRndOp_uid100_uid101_fpSinCosXTest_q <= join_uid99_fpSinCosXTest_q & cstAllZWF_uid7_fpSinCosXTest_q & VCC_q;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor(LOGICAL,1333)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q <= not (ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a or ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b);
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena(REG,1334)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q = "1") THEN
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd(LOGICAL,1335)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b <= en;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a and ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor(LOGICAL,1283)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q <= not (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a or ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b);
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena(REG,1284)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd(LOGICAL,1285)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a and ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg(DELAY,1273)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expXRR_uid38_fpSinCosXTest_b, xout => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem(DUALMEM,1274)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 9,
width_b => 8,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia
);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1(REG,604)@25
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--expSinHC_uid74_fpSinCosXTest(SUB,73)@26
expSinHC_uid74_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expSinHC_uid74_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q);
expSinHC_uid74_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSinHC_uid74_fpSinCosXTest_a) - UNSIGNED(expSinHC_uid74_fpSinCosXTest_b));
expSinHC_uid74_fpSinCosXTest_q <= expSinHC_uid74_fpSinCosXTest_o(8 downto 0);
--expSinHCR_uid75_fpSinCosXTest(BITSELECT,74)@26
expSinHCR_uid75_fpSinCosXTest_in <= expSinHC_uid74_fpSinCosXTest_q(7 downto 0);
expSinHCR_uid75_fpSinCosXTest_b <= expSinHCR_uid75_fpSinCosXTest_in(7 downto 0);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b(DELAY,695)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expPSin_uid76_fpSinCosXTest(MUX,75)@26
expPSin_uid76_fpSinCosXTest_s <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q;
expPSin_uid76_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expPSin_uid76_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expPSin_uid76_fpSinCosXTest_s IS
WHEN "0" => expPSin_uid76_fpSinCosXTest_q <= expSinHCR_uid75_fpSinCosXTest_b;
WHEN "1" => expPSin_uid76_fpSinCosXTest_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => expPSin_uid76_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg(DELAY,1323)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expPSin_uid76_fpSinCosXTest_q, xout => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem(DUALMEM,1324)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 7,
width_b => 8,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia
);
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq(7 downto 0);
--fracRSinPreRndHigh_uid95_fpSinCosXTest(BITSELECT,94)@36
fracRSinPreRndHigh_uid95_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q(50 downto 0);
fracRSinPreRndHigh_uid95_fpSinCosXTest_b <= fracRSinPreRndHigh_uid95_fpSinCosXTest_in(50 downto 27);
--fracRSinPreRndLow_uid96_fpSinCosXTest(BITSELECT,95)@36
fracRSinPreRndLow_uid96_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q(49 downto 0);
fracRSinPreRndLow_uid96_fpSinCosXTest_b <= fracRSinPreRndLow_uid96_fpSinCosXTest_in(49 downto 26);
--fracRSinPreRnd_uid97_fpSinCosXTest(MUX,96)@36
fracRSinPreRnd_uid97_fpSinCosXTest_s <= normBitSin_uid93_fpSinCosXTest_b;
fracRSinPreRnd_uid97_fpSinCosXTest: PROCESS (fracRSinPreRnd_uid97_fpSinCosXTest_s, en, fracRSinPreRndLow_uid96_fpSinCosXTest_b, fracRSinPreRndHigh_uid95_fpSinCosXTest_b)
BEGIN
CASE fracRSinPreRnd_uid97_fpSinCosXTest_s IS
WHEN "0" => fracRSinPreRnd_uid97_fpSinCosXTest_q <= fracRSinPreRndLow_uid96_fpSinCosXTest_b;
WHEN "1" => fracRSinPreRnd_uid97_fpSinCosXTest_q <= fracRSinPreRndHigh_uid95_fpSinCosXTest_b;
WHEN OTHERS => fracRSinPreRnd_uid97_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracRSinPreRnd_uid98_uid98_fpSinCosXTest(BITJOIN,97)@36
expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q & fracRSinPreRnd_uid97_fpSinCosXTest_q;
--expFracRSin_uid102_fpSinCosXTest(ADD,101)@36
expFracRSin_uid102_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q);
expFracRSin_uid102_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0000000" & sinRndOp_uid100_uid101_fpSinCosXTest_q);
expFracRSin_uid102_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRSin_uid102_fpSinCosXTest_a) + UNSIGNED(expFracRSin_uid102_fpSinCosXTest_b));
expFracRSin_uid102_fpSinCosXTest_q <= expFracRSin_uid102_fpSinCosXTest_o(32 downto 0);
--expRCompSin_uid104_fpSinCosXTest(BITSELECT,103)@36
expRCompSin_uid104_fpSinCosXTest_in <= expFracRSin_uid102_fpSinCosXTest_q(31 downto 0);
expRCompSin_uid104_fpSinCosXTest_b <= expRCompSin_uid104_fpSinCosXTest_in(31 downto 24);
--reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2(REG,607)@36
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q <= expRCompSin_uid104_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor(LOGICAL,1537)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q <= not (ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a or ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b);
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena(REG,1538)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q = "1") THEN
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd(LOGICAL,1539)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b <= en;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a and ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b;
--expXIsZero_uid10_fpSinCosXTest(LOGICAL,9)@0
expXIsZero_uid10_fpSinCosXTest_a <= exp_uid9_fpSinCosXTest_b;
expXIsZero_uid10_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
expXIsZero_uid10_fpSinCosXTest_q <= "1" when expXIsZero_uid10_fpSinCosXTest_a = expXIsZero_uid10_fpSinCosXTest_b else "0";
--ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b(DELAY,746)@0
ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => expXIsZero_uid10_fpSinCosXTest_q, xout => ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excSelBitsSin_uid118_fpSinCosXTest(BITJOIN,117)@19
excSelBitsSin_uid118_fpSinCosXTest_q <= excRNaN_uid117_fpSinCosXTest_q & ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q & ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg(DELAY,1527)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => excSelBitsSin_uid118_fpSinCosXTest_q, xout => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem(DUALMEM,1528)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 4,
numwords_a => 14,
width_b => 3,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq,
address_a => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa,
data_a => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia
);
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0 <= areset;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq(2 downto 0);
--reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0(REG,533)@35
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--excSelSin_uid119_fpSinCosXTest(LOOKUP,118)@36
excSelSin_uid119_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excSelSin_uid119_fpSinCosXTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q) IS
WHEN "000" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN "001" => excSelSin_uid119_fpSinCosXTest_q <= "01";
WHEN "010" => excSelSin_uid119_fpSinCosXTest_q <= "10";
WHEN "011" => excSelSin_uid119_fpSinCosXTest_q <= "10";
WHEN "100" => excSelSin_uid119_fpSinCosXTest_q <= "11";
WHEN "101" => excSelSin_uid119_fpSinCosXTest_q <= "11";
WHEN "110" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN "111" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN OTHERS =>
excSelSin_uid119_fpSinCosXTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRPostExcSin_uid126_fpSinCosXTest(MUX,125)@37
expRPostExcSin_uid126_fpSinCosXTest_s <= excSelSin_uid119_fpSinCosXTest_q;
expRPostExcSin_uid126_fpSinCosXTest: PROCESS (expRPostExcSin_uid126_fpSinCosXTest_s, en, reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q, ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q, cstAllZWE_uid8_fpSinCosXTest_q, cstAllOWE_uid6_fpSinCosXTest_q)
BEGIN
CASE expRPostExcSin_uid126_fpSinCosXTest_s IS
WHEN "00" => expRPostExcSin_uid126_fpSinCosXTest_q <= reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q;
WHEN "01" => expRPostExcSin_uid126_fpSinCosXTest_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q;
WHEN "10" => expRPostExcSin_uid126_fpSinCosXTest_q <= cstAllZWE_uid8_fpSinCosXTest_q;
WHEN "11" => expRPostExcSin_uid126_fpSinCosXTest_q <= cstAllOWE_uid6_fpSinCosXTest_q;
WHEN OTHERS => expRPostExcSin_uid126_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor(LOGICAL,1346)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q <= not (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a or ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b);
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena(REG,1347)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd(LOGICAL,1348)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b <= en;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a and ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg(DELAY,1336)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => frac_uid13_fpSinCosXTest_b, xout => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem(DUALMEM,1337)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 6,
numwords_a => 35,
width_b => 23,
widthad_b => 6,
numwords_b => 35,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia
);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq(22 downto 0);
--fracRCompSin_uid103_fpSinCosXTest(BITSELECT,102)@36
fracRCompSin_uid103_fpSinCosXTest_in <= expFracRSin_uid102_fpSinCosXTest_q(23 downto 0);
fracRCompSin_uid103_fpSinCosXTest_b <= fracRCompSin_uid103_fpSinCosXTest_in(23 downto 1);
--reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2(REG,606)@36
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q <= fracRCompSin_uid103_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--fracRPostExcSin_uid122_fpSinCosXTest(MUX,121)@37
fracRPostExcSin_uid122_fpSinCosXTest_s <= excSelSin_uid119_fpSinCosXTest_q;
fracRPostExcSin_uid122_fpSinCosXTest: PROCESS (fracRPostExcSin_uid122_fpSinCosXTest_s, en, reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q, cstAllZWF_uid7_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q)
BEGIN
CASE fracRPostExcSin_uid122_fpSinCosXTest_s IS
WHEN "00" => fracRPostExcSin_uid122_fpSinCosXTest_q <= reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q;
WHEN "01" => fracRPostExcSin_uid122_fpSinCosXTest_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q;
WHEN "10" => fracRPostExcSin_uid122_fpSinCosXTest_q <= cstAllZWF_uid7_fpSinCosXTest_q;
WHEN "11" => fracRPostExcSin_uid122_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN OTHERS => fracRPostExcSin_uid122_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpSin_uid134_fpSinCosXTest(BITJOIN,133)@37
fpSin_uid134_fpSinCosXTest_q <= ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q & expRPostExcSin_uid126_fpSinCosXTest_q & fracRPostExcSin_uid122_fpSinCosXTest_q;
--xOut(GPOUT,4)@37
s <= fpSin_uid134_fpSinCosXTest_q;
c <= fpCos_uid162_fpSinCosXTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_sincos_s5
-- VHDL created on Wed Mar 27 09:55:14 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_sincos_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
s : out std_logic_vector(31 downto 0);
c : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_sincos_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid8_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid22_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid23_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShift_uid24_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid25_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid26_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstZwShiftP1_uid27_fpSinCosXTest_q : std_logic_vector (13 downto 0);
signal cstNaNwF_uid32_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal cstZmwFRRPwSM1_uid52_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal cPi_uid71_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal p_uid73_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal p_uid73_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal expPSin_uid76_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal expPSin_uid76_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal multSinOp2_uid91_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal multSinOp2_uid91_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_a : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_s1 : std_logic_vector (51 downto 0);
signal mulSin_uid92_fpSinCosXTest_pr : UNSIGNED (51 downto 0);
signal mulSin_uid92_fpSinCosXTest_q : std_logic_vector (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_a : std_logic_vector (25 downto 0);
signal mulCos_uid105_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal mulCos_uid105_fpSinCosXTest_s1 : std_logic_vector (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_pr : UNSIGNED (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_q : std_logic_vector (51 downto 0);
signal excSelSin_uid119_fpSinCosXTest_q : std_logic_vector(1 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expSelectorCos_uid145_fpSinCosXTest_q : std_logic_vector(1 downto 0);
signal signRCond2_uid152_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_d : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_d : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q : std_logic_vector (29 downto 0);
signal leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal zs_uid236_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal mO_uid239_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (62 downto 0);
signal zs_uid244_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal zs_uid250_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (5 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(63 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(63 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (47 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a : std_logic_vector (12 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr : SIGNED (26 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q : std_logic_vector (25 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a : std_logic_vector (14 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b : std_logic_vector (22 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr : SIGNED (38 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q : std_logic_vector (37 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a : std_logic_vector (12 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr : SIGNED (26 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q : std_logic_vector (25 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a : std_logic_vector (14 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b : std_logic_vector (22 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr : SIGNED (38 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q : std_logic_vector (37 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0 : std_logic;
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0 : std_logic;
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q : std_logic_vector (39 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a : std_logic_vector(81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b : std_logic_vector(81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o : std_logic_vector (81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q : std_logic_vector (81 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC0_uid394_tableGensinPiZ_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC1_uid396_tableGensinPiZ_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC2_uid398_tableGensinPiZ_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_q : std_logic_vector (12 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC0_uid400_tableGencosPiZ_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC1_uid402_tableGencosPiZ_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC2_uid404_tableGencosPiZ_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_q : std_logic_vector (12 downto 0);
signal reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q : std_logic_vector (2 downto 0);
signal reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q : std_logic_vector (39 downto 0);
signal reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (39 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q : std_logic_vector (26 downto 0);
signal reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (77 downto 0);
signal reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q : std_logic_vector (67 downto 0);
signal reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q : std_logic_vector (66 downto 0);
signal reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q : std_logic_vector (65 downto 0);
signal reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q : std_logic_vector (67 downto 0);
signal reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q : std_logic_vector (25 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q : std_logic_vector (12 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q : std_logic_vector (20 downto 0);
signal reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q : std_logic_vector (22 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q : std_logic_vector (29 downto 0);
signal reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q : std_logic_vector (6 downto 0);
signal reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q : std_logic_vector (22 downto 0);
signal reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q : std_logic_vector (0 downto 0);
signal reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q : std_logic_vector (12 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q : std_logic_vector (20 downto 0);
signal reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q : std_logic_vector (22 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q : std_logic_vector (29 downto 0);
signal reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q : std_logic_vector (25 downto 0);
signal reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q : std_logic_vector (25 downto 0);
signal reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q : std_logic_vector (6 downto 0);
signal reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q : std_logic_vector (22 downto 0);
signal reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q : std_logic_vector (3 downto 0);
signal reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q : std_logic_vector (52 downto 0);
signal ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q : std_logic_vector (65 downto 0);
signal ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q : std_logic_vector (67 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (7 downto 0);
signal ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (66 downto 0);
signal ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (65 downto 0);
signal ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (64 downto 0);
signal ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q : std_logic_vector (63 downto 0);
signal ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q : std_logic_vector (31 downto 0);
signal ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (58 downto 0);
signal ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q : std_logic_vector (63 downto 0);
signal ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q : std_logic_vector (31 downto 0);
signal ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (58 downto 0);
signal ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (76 downto 0);
signal ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (75 downto 0);
signal ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (74 downto 0);
signal ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q : std_logic_vector (12 downto 0);
signal ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q : std_logic_vector (53 downto 0);
signal ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q : std_logic_vector (12 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0 : std_logic;
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q : signal is true;
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q : std_logic_vector (6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0 : std_logic;
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q : signal is true;
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q : signal is true;
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0 : std_logic;
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0 : std_logic;
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0 : std_logic;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq : std_logic;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q : signal is true;
signal sinXIsXRR_uid41_fpSinCosXTest_a : std_logic_vector(11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_b : std_logic_vector(11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_o : std_logic_vector (11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_a : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_b : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_o : std_logic_vector (11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal yIsZero_uid51_fpSinCosXTest_a : std_logic_vector(65 downto 0);
signal yIsZero_uid51_fpSinCosXTest_b : std_logic_vector(65 downto 0);
signal yIsZero_uid51_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal pad_one_uid55_fpSinCosXTest_q : std_logic_vector (66 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_a : std_logic_vector(70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_b : std_logic_vector(70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_o : std_logic_vector (70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_c : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal InvCmpYToOneMinusY_uid61_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCmpYToOneMinusY_uid61_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid127_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid127_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvSinXIsXRR_uid128_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsXRR_uid128_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid131_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid131_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid132_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid132_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid136_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid136_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvCosXONe_uid149_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCosXONe_uid149_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid151_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid151_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvIntXParity_uid155_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvIntXParity_uid155_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal oFracXRR_uid43_uid43_fpSinCosXTest_q : std_logic_vector (53 downto 0);
signal half_uid53_fpSinCosXTest_q : std_logic_vector (65 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal exp_uid9_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal exp_uid9_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal frac_uid13_fpSinCosXTest_in : std_logic_vector (22 downto 0);
signal frac_uid13_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal signX_uid37_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal signX_uid37_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal expFracX_uid166_px_uid33_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal expFracX_uid166_px_uid33_fpSinCosXTest_b : std_logic_vector (30 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_q : std_logic_vector (9 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_a : std_logic_vector(65 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_b : std_logic_vector(65 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_a : std_logic_vector(67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_b : std_logic_vector(67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_o : std_logic_vector (67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal zSin_uid60_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal zSin_uid60_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal zCos_uid64_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal zCos_uid64_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal expSinHC_uid74_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal excRNaN_uid117_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid117_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid117_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracRPostExcSin_uid122_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExcSin_uid122_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal expRPostExcSin_uid126_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExcSin_uid126_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracRPostExcCos_uid142_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExcCos_uid142_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal expRPostExcCos_uid147_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExcCos_uid147_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cosXONe_uid148_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal cosXONe_uid148_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal cosXONe_uid148_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal finalExp_uid209_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal finalExp_uid209_rrx_uid34_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal extendedFracX_uid47_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal normBitSin_uid93_fpSinCosXTest_in : std_logic_vector (51 downto 0);
signal normBitSin_uid93_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal fracRSinPreRndHigh_uid95_fpSinCosXTest_in : std_logic_vector (50 downto 0);
signal fracRSinPreRndHigh_uid95_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracRSinPreRndLow_uid96_fpSinCosXTest_in : std_logic_vector (49 downto 0);
signal fracRSinPreRndLow_uid96_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal normBitCos_uid106_fpSinCosXTest_in : std_logic_vector (51 downto 0);
signal normBitCos_uid106_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal fracRCosPreRndHigh_uid108_fpSinCosXTest_in : std_logic_vector (50 downto 0);
signal fracRCosPreRndHigh_uid108_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracRCosPreRndLow_uid109_fpSinCosXTest_in : std_logic_vector (49 downto 0);
signal fracRCosPreRndLow_uid109_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q : std_logic_vector (52 downto 0);
signal leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b : std_logic_vector (23 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int : std_logic_vector (80 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q : std_logic_vector (80 downto 0);
signal os_uid196_rrx_uid34_fpSinCosXTest_q : std_logic_vector (79 downto 0);
signal leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal join_uid99_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal join_uid141_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal zSinYBottom_uid59_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal zSinYBottom_uid59_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal zSinOMyBottom_uid58_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal zSinOMyBottom_uid58_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal excSelBitsSin_uid118_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal fpSin_uid134_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal join_uid143_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal fpCos_uid162_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int : std_logic_vector (107 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q : std_logic_vector (107 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal fracX_uid187_rrx_uid34_fpSinCosXTest_in : std_logic_vector (22 downto 0);
signal fracX_uid187_rrx_uid34_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal oFracXRRSmallXRR_uid90_fpSinCosXTest_in : std_logic_vector (53 downto 0);
signal oFracXRRSmallXRR_uid90_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal R_uid167_px_uid33_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal InvFracXIsZero_uid16_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid16_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fxpXShiftVal_uid46_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal fxpXShiftVal_uid46_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal addr_uid81_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal addr_uid81_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal zPsinPiZ_uid84_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal zPsinPiZ_uid84_fpSinCosXTest_b : std_logic_vector (14 downto 0);
signal rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (32 downto 0);
signal addr_uid83_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal addr_uid83_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal zPcosPiZ_uid87_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal zPcosPiZ_uid87_fpSinCosXTest_b : std_logic_vector (14 downto 0);
signal rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (32 downto 0);
signal expSinHCR_uid75_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expSinHCR_uid75_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal expPCos_uid79_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expPCos_uid79_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (66 downto 0);
signal LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (66 downto 0);
signal LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (65 downto 0);
signal LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (58 downto 0);
signal rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (58 downto 0);
signal rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (76 downto 0);
signal LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (76 downto 0);
signal LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (75 downto 0);
signal LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (75 downto 0);
signal LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (74 downto 0);
signal LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (74 downto 0);
signal X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (59 downto 0);
signal X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (59 downto 0);
signal X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (55 downto 0);
signal X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (55 downto 0);
signal fracRSinPreRnd_uid97_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal fracRSinPreRnd_uid97_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal fracRCosPreRnd_uid110_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal fracRCosPreRnd_uid110_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal cosRndOp_uid112_uid113_fpSinCosXTest_q : std_logic_vector (24 downto 0);
signal rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal lowRangeB_uid408_polyEvalsinPiZ_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid408_polyEvalsinPiZ_b : std_logic_vector (0 downto 0);
signal highBBits_uid409_polyEvalsinPiZ_in : std_logic_vector (13 downto 0);
signal highBBits_uid409_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid414_polyEvalsinPiZ_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid414_polyEvalsinPiZ_b : std_logic_vector (1 downto 0);
signal highBBits_uid415_polyEvalsinPiZ_in : std_logic_vector (23 downto 0);
signal highBBits_uid415_polyEvalsinPiZ_b : std_logic_vector (21 downto 0);
signal lowRangeB_uid421_polyEvalcosPiZ_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid421_polyEvalcosPiZ_b : std_logic_vector (0 downto 0);
signal highBBits_uid422_polyEvalcosPiZ_in : std_logic_vector (13 downto 0);
signal highBBits_uid422_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid427_polyEvalcosPiZ_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid427_polyEvalcosPiZ_b : std_logic_vector (1 downto 0);
signal highBBits_uid428_polyEvalcosPiZ_in : std_logic_vector (23 downto 0);
signal highBBits_uid428_polyEvalcosPiZ_b : std_logic_vector (21 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in : std_logic_vector (80 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b : std_logic_vector (26 downto 0);
signal fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in : std_logic_vector (76 downto 0);
signal fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b : std_logic_vector (52 downto 0);
signal intXParity_uid49_fpSinCosXTest_in : std_logic_vector (67 downto 0);
signal intXParity_uid49_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal y_uid50_fpSinCosXTest_in : std_logic_vector (66 downto 0);
signal y_uid50_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal sinRndOp_uid100_uid101_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal expSelBitsCos_uid144_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a : std_logic_vector(108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b : std_logic_vector(108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o : std_logic_vector (108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q : std_logic_vector (108 downto 0);
signal oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal expX_uid186_rrx_uid34_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal expX_uid186_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal exc_N_uid17_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal yT1_uid406_polyEvalsinPiZ_in : std_logic_vector (14 downto 0);
signal yT1_uid406_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal yT1_uid419_polyEvalcosPiZ_in : std_logic_vector (14 downto 0);
signal yT1_uid419_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_a : std_logic_vector(32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_b : std_logic_vector(32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_o : std_logic_vector (32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_q : std_logic_vector (30 downto 0);
signal finalFrac_uid208_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal finalFrac_uid208_rrx_uid34_fpSinCosXTest_q : std_logic_vector (52 downto 0);
signal signComp_uid129_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_a : std_logic_vector(32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_b : std_logic_vector(32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_o : std_logic_vector (32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_q : std_logic_vector (32 downto 0);
signal leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal multFracBits_uid199_rrx_uid34_fpSinCosXTest_in : std_logic_vector (77 downto 0);
signal multFracBits_uid199_rrx_uid34_fpSinCosXTest_b : std_logic_vector (77 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b : std_logic_vector (26 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (5 downto 0);
signal fracRCompCos_uid115_fpSinCosXTest_in : std_logic_vector (23 downto 0);
signal fracRCompCos_uid115_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal expRCompSin_uid116_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal expRCompSin_uid116_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal s1_uid408_uid411_polyEvalsinPiZ_q : std_logic_vector (22 downto 0);
signal s2_uid414_uid417_polyEvalsinPiZ_q : std_logic_vector (32 downto 0);
signal s1_uid421_uid424_polyEvalcosPiZ_q : std_logic_vector (22 downto 0);
signal s2_uid427_uid430_polyEvalcosPiZ_q : std_logic_vector (32 downto 0);
signal RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q : std_logic_vector (61 downto 0);
signal signR_uid130_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signR_uid130_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signR_uid130_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal fracRCompSin_uid103_fpSinCosXTest_in : std_logic_vector (23 downto 0);
signal fracRCompSin_uid103_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal expRCompSin_uid104_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal expRCompSin_uid104_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in : std_logic_vector (77 downto 0);
signal multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (61 downto 0);
signal X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (61 downto 0);
signal X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (45 downto 0);
signal X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (45 downto 0);
signal X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (29 downto 0);
signal X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (29 downto 0);
signal expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal polyEvalSigsinPiZ_uid86_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal polyEvalSigsinPiZ_uid86_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal polyEvalSigcosPiZ_uid89_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal polyEvalSigcosPiZ_uid89_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal expXRR_uid38_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal expXRR_uid38_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal fracXRR_uid39_fpSinCosXTest_in : std_logic_vector (52 downto 0);
signal fracXRR_uid39_fpSinCosXTest_b : std_logic_vector (52 downto 0);
signal pHigh_uid72_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal pHigh_uid72_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal pCos_uid77_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal pCos_uid77_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal r_uid277_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (6 downto 0);
signal r_uid356_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (6 downto 0);
signal expCompOut_uid205_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expCompOut_uid205_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (73 downto 0);
signal LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (73 downto 0);
signal LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (69 downto 0);
signal LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (69 downto 0);
signal LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (65 downto 0);
signal LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (56 downto 0);
signal LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (48 downto 0);
signal LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (48 downto 0);
signal LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (40 downto 0);
signal LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (40 downto 0);
signal LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (56 downto 0);
signal LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (48 downto 0);
signal LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (48 downto 0);
signal LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (40 downto 0);
signal LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (40 downto 0);
signal leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
begin
--xIn(GPIN,3)@0
--GND(CONSTANT,0)
GND_q <= "0";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable(LOGICAL,1282)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q <= not ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor(LOGICAL,1422)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q <= not (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a or ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b);
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top(CONSTANT,1418)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q <= "01011";
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp(LOGICAL,1419)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q <= "1" when ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a = ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b else "0";
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg(REG,1420)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena(REG,1423)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd(LOGICAL,1424)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b <= en;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a and ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b;
--expFracX_uid166_px_uid33_fpSinCosXTest(BITSELECT,165)@0
expFracX_uid166_px_uid33_fpSinCosXTest_in <= a(30 downto 0);
expFracX_uid166_px_uid33_fpSinCosXTest_b <= expFracX_uid166_px_uid33_fpSinCosXTest_in(30 downto 0);
--R_uid167_px_uid33_fpSinCosXTest(BITJOIN,166)@0
R_uid167_px_uid33_fpSinCosXTest_q <= GND_q & expFracX_uid166_px_uid33_fpSinCosXTest_b;
--expX_uid186_rrx_uid34_fpSinCosXTest(BITSELECT,185)@0
expX_uid186_rrx_uid34_fpSinCosXTest_in <= R_uid167_px_uid33_fpSinCosXTest_q(30 downto 0);
expX_uid186_rrx_uid34_fpSinCosXTest_b <= expX_uid186_rrx_uid34_fpSinCosXTest_in(30 downto 23);
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg(DELAY,1412)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid186_rrx_uid34_fpSinCosXTest_b, xout => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt(COUNTER,1414)
-- every=1, low=0, high=11, step=1, init=1
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i = 10 THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i - 11;
ELSE
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg(REG,1415)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux(MUX,1416)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem(DUALMEM,1413)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 12,
width_b => 8,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia
);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--zs_uid244_lzcZSin_uid66_fpSinCosXTest(CONSTANT,243)
zs_uid244_lzcZSin_uid66_fpSinCosXTest_q <= "00000000000000000000000000000000";
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor(LOGICAL,1396)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q <= not (ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a or ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b);
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg(REG,1318)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena(REG,1397)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q = "1") THEN
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd(LOGICAL,1398)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b <= en;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a and ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg(DELAY,1388)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid167_px_uid33_fpSinCosXTest_q, xout => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt(COUNTER,1314)
-- every=1, low=0, high=1, step=1, init=1
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i,1));
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg(REG,1315)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux(MUX,1316)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s <= en;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux: PROCESS (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s, ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q, ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q)
BEGIN
CASE ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s IS
WHEN "0" => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
WHEN "1" => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem(DUALMEM,1389)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 1,
numwords_a => 2,
width_b => 32,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq,
address_a => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa,
data_a => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia
);
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0 <= areset;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq(31 downto 0);
--fracX_uid187_rrx_uid34_fpSinCosXTest(BITSELECT,186)@4
fracX_uid187_rrx_uid34_fpSinCosXTest_in <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q(22 downto 0);
fracX_uid187_rrx_uid34_fpSinCosXTest_b <= fracX_uid187_rrx_uid34_fpSinCosXTest_in(22 downto 0);
--oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest(BITJOIN,196)@4
oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q <= VCC_q & fracX_uid187_rrx_uid34_fpSinCosXTest_b;
--prod_uid198_rrx_uid34_fpSinCosXTest_b_0(BITSELECT,518)@4
prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in <= STD_LOGIC_VECTOR("000" & oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q);
prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b <= prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in(26 downto 0);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1(REG,539)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q <= prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShift_uid24_fpSinCosXTest(CONSTANT,23)
cstBiasMwShift_uid24_fpSinCosXTest_q <= "01110011";
--expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest(SUB,191)@0
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expX_uid186_rrx_uid34_fpSinCosXTest_b);
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0" & cstBiasMwShift_uid24_fpSinCosXTest_q);
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b));
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q <= expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o(8 downto 0);
--expXTableAddr_uid193_rrx_uid34_fpSinCosXTest(BITSELECT,192)@0
expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in <= expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q(7 downto 0);
expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b <= expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0(REG,534)@0
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q <= expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem(DUALMEM,514)@1
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia <= (others => '0');
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa <= (others => '0');
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab <= reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q;
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq,
address_a => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa,
data_a => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia
);
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0 <= areset;
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q <= rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1(REG,537)@3
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q <= rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem(DUALMEM,513)@1
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia <= (others => '0');
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa <= (others => '0');
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab <= reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q;
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq,
address_a => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa,
data_a => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia
);
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0 <= areset;
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q <= rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0(REG,536)@3
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q <= rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid196_rrx_uid34_fpSinCosXTest(BITJOIN,195)@4
os_uid196_rrx_uid34_fpSinCosXTest_q <= reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q & reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q;
--prod_uid198_rrx_uid34_fpSinCosXTest_a_2(BITSELECT,517)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in <= STD_LOGIC_VECTOR("0" & os_uid196_rrx_uid34_fpSinCosXTest_q);
prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in(80 downto 54);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0(REG,542)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0(MULT,521)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1;
END IF;
END IF;
END PROCESS;
--ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a(DELAY,1145)@8
ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a : dspba_delay
GENERIC MAP ( width => 54, depth => 1 )
PORT MAP ( xin => prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q, xout => ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--prod_uid198_rrx_uid34_fpSinCosXTest_align_2(BITSHIFT,524)@9
prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int <= ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int(107 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_a_1(BITSELECT,516)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in <= os_uid196_rrx_uid34_fpSinCosXTest_q(53 downto 0);
prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in(53 downto 27);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0(REG,540)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0(MULT,520)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_align_1(BITSHIFT,523)@8
prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int <= prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q & "000000000000000000000000000";
prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int(80 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_a_0(BITSELECT,515)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in <= os_uid196_rrx_uid34_fpSinCosXTest_q(26 downto 0);
prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in(26 downto 0);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0(REG,538)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0(MULT,519)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_align_0(BITSHIFT,522)@8
prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int <= prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int(53 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0(ADD,525)@8
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a <= STD_LOGIC_VECTOR("0000000000000000000000000000" & prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b <= STD_LOGIC_VECTOR("0" & prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a) + UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b));
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o(81 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0(ADD,526)@9
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a <= STD_LOGIC_VECTOR("000000000000000000000000000" & prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b <= STD_LOGIC_VECTOR("0" & prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a) + UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b));
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o(108 downto 0);
--multFracBits_uid199_rrx_uid34_fpSinCosXTest(BITSELECT,198)@9
multFracBits_uid199_rrx_uid34_fpSinCosXTest_in <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q(77 downto 0);
multFracBits_uid199_rrx_uid34_fpSinCosXTest_b <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_in(77 downto 0);
--multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest(BITSELECT,199)@9
multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b;
multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b <= multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in(77 downto 46);
--reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1(REG,544)@9
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,433)@10
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a(DELAY,1178)@10
ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xout => ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5(REG,555)@12
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q <= ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q;
END IF;
END IF;
END PROCESS;
--zs_uid250_lzcZSin_uid66_fpSinCosXTest(CONSTANT,249)
zs_uid250_lzcZSin_uid66_fpSinCosXTest_q <= "0000000000000000";
--mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest(CONSTANT,434)
mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "11111111111111111111111111111111";
--vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,436)@10
vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q, mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,438)@10
rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in(31 downto 16);
--reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1(REG,546)@10
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,439)@11
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4(REG,554)@11
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q <= vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e(DELAY,1081)@12
ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWE_uid8_fpSinCosXTest(CONSTANT,7)
cstAllZWE_uid8_fpSinCosXTest_q <= "00000000";
--vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,440)@10
vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q(15 downto 0);
vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in(15 downto 0);
--reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,548)@10
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,442)@11
vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q, reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,444)@11
rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in(15 downto 8);
--vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,445)@11
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i <= "1" when vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xin => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d(DELAY,1080)@12
ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xout => ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest(CONSTANT,212)
leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q <= "0000";
--vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,446)@11
vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q(7 downto 0);
vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,550)@11
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,549)@11
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,448)@12
vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q, reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,450)@12
rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in(7 downto 4);
--vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,451)@12
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,553)@12
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest(CONSTANT,226)
leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q <= "00";
--vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,452)@12
vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q(3 downto 0);
vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in(3 downto 0);
--vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,454)@12
vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b, vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
WHEN "1" => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,456)@12
rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in(3 downto 2);
--vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,457)@12
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i <= "1" when vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xin => vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,458)@12
vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q(1 downto 0);
vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in(1 downto 0);
--reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,552)@12
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,551)@12
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,460)@13
vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q, reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,462)@13
rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in(1 downto 1);
--vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,463)@13
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= GND_q;
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest(BITJOIN,464)@13
r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q & ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q & ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q & reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q & vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q & vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
--cstBiasM1_uid23_fpSinCosXTest(CONSTANT,22)
cstBiasM1_uid23_fpSinCosXTest_q <= "01111110";
--expCompOutExt_uid204_rrx_uid34_fpSinCosXTest(SUB,203)@13
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("000" & r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q);
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b));
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q <= expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o(8 downto 0);
--expCompOut_uid205_rrx_uid34_fpSinCosXTest(BITSELECT,204)@13
expCompOut_uid205_rrx_uid34_fpSinCosXTest_in <= expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q(7 downto 0);
expCompOut_uid205_rrx_uid34_fpSinCosXTest_b <= expCompOut_uid205_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2(REG,564)@13
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q <= expCompOut_uid205_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--xBranch_uid191_rrx_uid34_fpSinCosXTest(COMPARE,190)@0
xBranch_uid191_rrx_uid34_fpSinCosXTest_cin <= GND_q;
xBranch_uid191_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid24_fpSinCosXTest_q) & '0';
xBranch_uid191_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & expX_uid186_rrx_uid34_fpSinCosXTest_b) & xBranch_uid191_rrx_uid34_fpSinCosXTest_cin(0);
xBranch_uid191_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xBranch_uid191_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(xBranch_uid191_rrx_uid34_fpSinCosXTest_b));
xBranch_uid191_rrx_uid34_fpSinCosXTest_n(0) <= not xBranch_uid191_rrx_uid34_fpSinCosXTest_o(10);
--reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1(REG,563)@0
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q <= xBranch_uid191_rrx_uid34_fpSinCosXTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b(DELAY,829)@1
ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q, xout => ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalExp_uid209_rrx_uid34_fpSinCosXTest(MUX,208)@14
finalExp_uid209_rrx_uid34_fpSinCosXTest_s <= ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q;
finalExp_uid209_rrx_uid34_fpSinCosXTest: PROCESS (finalExp_uid209_rrx_uid34_fpSinCosXTest_s, en, reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q)
BEGIN
CASE finalExp_uid209_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b(DELAY,833)@14
ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => finalExp_uid209_rrx_uid34_fpSinCosXTest_q, xout => ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1409)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a or ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top(CONSTANT,1279)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q <= "01000";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp(LOGICAL,1280)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q <= "1" when ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a = ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b else "0";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg(REG,1281)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1410)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1411)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1399)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid187_rrx_uid34_fpSinCosXTest_b, xout => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt(COUNTER,1275)
-- every=1, low=0, high=8, step=1, init=1
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i = 7 THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i - 8;
ELSE
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg(REG,1276)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux(MUX,1277)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s, ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q, ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1400)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 4,
numwords_a => 9,
width_b => 23,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(22 downto 0);
--ZerosGB_uid206_rrx_uid34_fpSinCosXTest(CONSTANT,205)
ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q <= "000000000000000000000000000000";
--fracXRExt_uid207_rrx_uid34_fpSinCosXTest(BITJOIN,206)@15
fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q & ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q;
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1499)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1500)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1501)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,474)@9
X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(29 downto 0);
X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in(29 downto 0);
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1491)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 30, depth => 1 )
PORT MAP ( xin => X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1492)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 1,
numwords_a => 2,
width_b => 30,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(29 downto 0);
--leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest(CONSTANT,473)
leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,475)@13
leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1488)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1489)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1490)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,471)@9
X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(45 downto 0);
X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in(45 downto 0);
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1480)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1481)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 1,
numwords_a => 2,
width_b => 46,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(45 downto 0);
--leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,472)@13
leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1477)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1478)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1479)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,468)@9
X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(61 downto 0);
X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in(61 downto 0);
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1469)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1470)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 62,
widthad_a => 1,
numwords_a => 2,
width_b => 62,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(61 downto 0);
--leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,469)@13
leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor(LOGICAL,1510)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q <= not (ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a or ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b);
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena(REG,1511)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q = "1") THEN
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd(LOGICAL,1512)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b <= en;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a and ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg(DELAY,1502)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 78, depth => 1 )
PORT MAP ( xin => multFracBits_uid199_rrx_uid34_fpSinCosXTest_b, xout => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem(DUALMEM,1503)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 78,
widthad_a => 1,
numwords_a => 2,
width_b => 78,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia
);
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq(77 downto 0);
--leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,476)@13
leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in(5 downto 4);
--leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,477)@13
leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b;
leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,485)@13
LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(65 downto 0);
LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in(65 downto 0);
--leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest(CONSTANT,218)
leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q <= "000000000000";
--leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,486)@13
leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b & leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5(REG,560)@13
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,482)@13
LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(69 downto 0);
LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in(69 downto 0);
--leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,483)@13
leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4(REG,559)@13
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,479)@13
LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(73 downto 0);
LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in(73 downto 0);
--leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,480)@13
leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3(REG,558)@13
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2(REG,557)@13
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,487)@13
leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1(REG,556)@13
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,488)@14
leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q;
leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,496)@14
LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(74 downto 0);
LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in(74 downto 0);
--ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1112)@14
ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 75, depth => 1 )
PORT MAP ( xin => LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest(CONSTANT,229)
leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q <= "000";
--leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,497)@15
leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,493)@14
LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(75 downto 0);
LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in(75 downto 0);
--ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1110)@14
ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 76, depth => 1 )
PORT MAP ( xin => LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,494)@15
leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,490)@14
LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(76 downto 0);
LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in(76 downto 0);
--ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1108)@14
ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 77, depth => 1 )
PORT MAP ( xin => LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,491)@15
leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & GND_q;
--reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2(REG,562)@14
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,498)@13
leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a(DELAY,1184)@13
ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1(REG,561)@14
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,499)@15
leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q;
leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracCompOut_uid203_rrx_uid34_fpSinCosXTest(BITSELECT,202)@15
fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in <= leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q(76 downto 0);
fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b <= fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in(76 downto 24);
--ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b(DELAY,826)@0
ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => xBranch_uid191_rrx_uid34_fpSinCosXTest_n, xout => ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalFrac_uid208_rrx_uid34_fpSinCosXTest(MUX,207)@15
finalFrac_uid208_rrx_uid34_fpSinCosXTest_s <= ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q;
finalFrac_uid208_rrx_uid34_fpSinCosXTest: PROCESS (finalFrac_uid208_rrx_uid34_fpSinCosXTest_s, en, fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b, fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE finalFrac_uid208_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b;
WHEN "1" => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RRangeRed_uid210_rrx_uid34_fpSinCosXTest(BITJOIN,209)@15
RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q <= GND_q & ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q & finalFrac_uid208_rrx_uid34_fpSinCosXTest_q;
--expXRR_uid38_fpSinCosXTest(BITSELECT,37)@15
expXRR_uid38_fpSinCosXTest_in <= RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q(60 downto 0);
expXRR_uid38_fpSinCosXTest_b <= expXRR_uid38_fpSinCosXTest_in(60 downto 53);
--reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1(REG,565)@15
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q <= expXRR_uid38_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShiftM2_uid26_fpSinCosXTest(CONSTANT,25)
cstBiasMwShiftM2_uid26_fpSinCosXTest_q <= "01110000";
--cosXIsOneXRR_uid42_fpSinCosXTest(COMPARE,41)@16
cosXIsOneXRR_uid42_fpSinCosXTest_cin <= GND_q;
cosXIsOneXRR_uid42_fpSinCosXTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid26_fpSinCosXTest_q) & '0';
cosXIsOneXRR_uid42_fpSinCosXTest_b <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q) & cosXIsOneXRR_uid42_fpSinCosXTest_cin(0);
cosXIsOneXRR_uid42_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(cosXIsOneXRR_uid42_fpSinCosXTest_a) - SIGNED(cosXIsOneXRR_uid42_fpSinCosXTest_b));
cosXIsOneXRR_uid42_fpSinCosXTest_n(0) <= not cosXIsOneXRR_uid42_fpSinCosXTest_o(11);
--exp_uid9_fpSinCosXTest(BITSELECT,8)@0
exp_uid9_fpSinCosXTest_in <= a(30 downto 0);
exp_uid9_fpSinCosXTest_b <= exp_uid9_fpSinCosXTest_in(30 downto 23);
--sinXIsX_uid40_fpSinCosXTest(COMPARE,39)@0
sinXIsX_uid40_fpSinCosXTest_cin <= GND_q;
sinXIsX_uid40_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid24_fpSinCosXTest_q) & '0';
sinXIsX_uid40_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & exp_uid9_fpSinCosXTest_b) & sinXIsX_uid40_fpSinCosXTest_cin(0);
sinXIsX_uid40_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid40_fpSinCosXTest_a) - UNSIGNED(sinXIsX_uid40_fpSinCosXTest_b));
sinXIsX_uid40_fpSinCosXTest_n(0) <= not sinXIsX_uid40_fpSinCosXTest_o(10);
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a(DELAY,789)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--cosXONe_uid148_fpSinCosXTest(LOGICAL,147)@16
cosXONe_uid148_fpSinCosXTest_a <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q;
cosXONe_uid148_fpSinCosXTest_b <= cosXIsOneXRR_uid42_fpSinCosXTest_n;
cosXONe_uid148_fpSinCosXTest_q <= cosXONe_uid148_fpSinCosXTest_a or cosXONe_uid148_fpSinCosXTest_b;
--ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a(DELAY,791)@16
ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => cosXONe_uid148_fpSinCosXTest_q, xout => ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvCosXONe_uid149_fpSinCosXTest(LOGICAL,148)@20
InvCosXONe_uid149_fpSinCosXTest_a <= ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q;
InvCosXONe_uid149_fpSinCosXTest_q <= not InvCosXONe_uid149_fpSinCosXTest_a;
--cstZwShiftP1_uid27_fpSinCosXTest(CONSTANT,26)
cstZwShiftP1_uid27_fpSinCosXTest_q <= "00000000000000";
--fracXRR_uid39_fpSinCosXTest(BITSELECT,38)@15
fracXRR_uid39_fpSinCosXTest_in <= RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q(52 downto 0);
fracXRR_uid39_fpSinCosXTest_b <= fracXRR_uid39_fpSinCosXTest_in(52 downto 0);
--ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a(DELAY,668)@15
ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => fracXRR_uid39_fpSinCosXTest_b, xout => ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracXRR_uid43_uid43_fpSinCosXTest(BITJOIN,42)@16
oFracXRR_uid43_uid43_fpSinCosXTest_q <= VCC_q & ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q;
--extendedFracX_uid47_fpSinCosXTest(BITJOIN,46)@16
extendedFracX_uid47_fpSinCosXTest_q <= cstZwShiftP1_uid27_fpSinCosXTest_q & oFracXRR_uid43_uid43_fpSinCosXTest_q;
--X55dto0_uid220_fxpX_uid48_fpSinCosXTest(BITSELECT,219)@16
X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(55 downto 0);
X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b <= X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in(55 downto 0);
--leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest(BITJOIN,220)@16
leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q <= X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b & leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5(REG,571)@16
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q <= leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--X59dto0_uid217_fxpX_uid48_fpSinCosXTest(BITSELECT,216)@16
X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(59 downto 0);
X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b <= X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in(59 downto 0);
--leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest(BITJOIN,217)@16
leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q <= X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4(REG,570)@16
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q <= leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--X63dto0_uid214_fxpX_uid48_fpSinCosXTest(BITSELECT,213)@16
X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(63 downto 0);
X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b <= X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in(63 downto 0);
--leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest(BITJOIN,214)@16
leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q <= X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3(REG,569)@16
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q <= leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2(REG,568)@16
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q <= extendedFracX_uid47_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--fxpXShiftValExt_uid45_fpSinCosXTest(SUB,44)@16
fxpXShiftValExt_uid45_fpSinCosXTest_a <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q);
fxpXShiftValExt_uid45_fpSinCosXTest_b <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid26_fpSinCosXTest_q);
fxpXShiftValExt_uid45_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(fxpXShiftValExt_uid45_fpSinCosXTest_a) - SIGNED(fxpXShiftValExt_uid45_fpSinCosXTest_b));
fxpXShiftValExt_uid45_fpSinCosXTest_q <= fxpXShiftValExt_uid45_fpSinCosXTest_o(9 downto 0);
--fxpXShiftVal_uid46_fpSinCosXTest(BITSELECT,45)@16
fxpXShiftVal_uid46_fpSinCosXTest_in <= fxpXShiftValExt_uid45_fpSinCosXTest_q(3 downto 0);
fxpXShiftVal_uid46_fpSinCosXTest_b <= fxpXShiftVal_uid46_fpSinCosXTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest(BITSELECT,221)@16
leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in <= fxpXShiftVal_uid46_fpSinCosXTest_b;
leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b <= leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1(REG,567)@16
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q <= leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest(MUX,222)@17
leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s <= reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q;
leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest: PROCESS (leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s, en, reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q, reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q, reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q, reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest(BITSELECT,230)@17
LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(64 downto 0);
LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in(64 downto 0);
--ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b(DELAY,851)@17
ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest(BITJOIN,231)@18
leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q & leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest(BITSELECT,227)@17
LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(65 downto 0);
LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in(65 downto 0);
--ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b(DELAY,849)@17
ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 66, depth => 1 )
PORT MAP ( xin => LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest(BITJOIN,228)@18
leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest(BITSELECT,224)@17
LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(66 downto 0);
LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in(66 downto 0);
--ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b(DELAY,847)@17
ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 67, depth => 1 )
PORT MAP ( xin => LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest(BITJOIN,225)@18
leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q & GND_q;
--reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2(REG,573)@17
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest(BITSELECT,232)@16
leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in <= fxpXShiftVal_uid46_fpSinCosXTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b <= leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a(DELAY,1195)@16
ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b, xout => ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1(REG,572)@17
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q <= ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest(MUX,233)@18
leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s <= reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q;
leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest: PROCESS (leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s, en, reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q, leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q, leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q, leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q;
WHEN "10" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q;
WHEN "11" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid50_fpSinCosXTest(BITSELECT,49)@18
y_uid50_fpSinCosXTest_in <= leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q(66 downto 0);
y_uid50_fpSinCosXTest_b <= y_uid50_fpSinCosXTest_in(66 downto 1);
--ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b(DELAY,680)@18
ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 66, depth => 2 )
PORT MAP ( xin => y_uid50_fpSinCosXTest_b, xout => ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1(REG,575)@18
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q <= y_uid50_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--pad_one_uid55_fpSinCosXTest(BITJOIN,54)@18
pad_one_uid55_fpSinCosXTest_q <= VCC_q & STD_LOGIC_VECTOR((65 downto 1 => GND_q(0)) & GND_q);
--reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0(REG,574)@18
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q <= pad_one_uid55_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--oneMinusY_uid55_fpSinCosXTest(SUB,55)@19
oneMinusY_uid55_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q);
oneMinusY_uid55_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q);
oneMinusY_uid55_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid55_fpSinCosXTest_a) - UNSIGNED(oneMinusY_uid55_fpSinCosXTest_b));
oneMinusY_uid55_fpSinCosXTest_q <= oneMinusY_uid55_fpSinCosXTest_o(67 downto 0);
--reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0(REG,576)@19
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q <= oneMinusY_uid55_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid57_fpSinCosXTest(COMPARE,56)@20
cmpYToOneMinusY_uid57_fpSinCosXTest_cin <= GND_q;
cmpYToOneMinusY_uid57_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q) & '0';
cmpYToOneMinusY_uid57_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q) & cmpYToOneMinusY_uid57_fpSinCosXTest_cin(0);
cmpYToOneMinusY_uid57_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid57_fpSinCosXTest_a) - UNSIGNED(cmpYToOneMinusY_uid57_fpSinCosXTest_b));
cmpYToOneMinusY_uid57_fpSinCosXTest_c(0) <= cmpYToOneMinusY_uid57_fpSinCosXTest_o(70);
--InvCmpYToOneMinusY_uid61_fpSinCosXTest(LOGICAL,60)@20
InvCmpYToOneMinusY_uid61_fpSinCosXTest_a <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
InvCmpYToOneMinusY_uid61_fpSinCosXTest_q <= not InvCmpYToOneMinusY_uid61_fpSinCosXTest_a;
--intXParity_uid49_fpSinCosXTest(BITSELECT,48)@18
intXParity_uid49_fpSinCosXTest_in <= leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q;
intXParity_uid49_fpSinCosXTest_b <= intXParity_uid49_fpSinCosXTest_in(67 downto 67);
--ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b(DELAY,794)@18
ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => intXParity_uid49_fpSinCosXTest_b, xout => ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--yIsZero_uid51_fpSinCosXTest(LOGICAL,50)@19
yIsZero_uid51_fpSinCosXTest_a <= reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q;
yIsZero_uid51_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000000000000000000000000000000000" & GND_q);
yIsZero_uid51_fpSinCosXTest_q <= "1" when yIsZero_uid51_fpSinCosXTest_a = yIsZero_uid51_fpSinCosXTest_b else "0";
--ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a(DELAY,792)@19
ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => yIsZero_uid51_fpSinCosXTest_q, xout => ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvYIsZero_uid151_fpSinCosXTest(LOGICAL,150)@20
InvYIsZero_uid151_fpSinCosXTest_a <= ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q;
InvYIsZero_uid151_fpSinCosXTest_q <= not InvYIsZero_uid151_fpSinCosXTest_a;
--signRCond2_uid152_fpSinCosXTest(LOGICAL,151)@20
signRCond2_uid152_fpSinCosXTest_a <= InvYIsZero_uid151_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_b <= ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q;
signRCond2_uid152_fpSinCosXTest_c <= InvCmpYToOneMinusY_uid61_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_d <= InvCosXONe_uid149_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_q_i <= signRCond2_uid152_fpSinCosXTest_a and signRCond2_uid152_fpSinCosXTest_b and signRCond2_uid152_fpSinCosXTest_c and signRCond2_uid152_fpSinCosXTest_d;
signRCond2_uid152_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRCond2_uid152_fpSinCosXTest_q, xin => signRCond2_uid152_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--InvIntXParity_uid155_fpSinCosXTest(LOGICAL,154)@20
InvIntXParity_uid155_fpSinCosXTest_a <= ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q;
InvIntXParity_uid155_fpSinCosXTest_q <= not InvIntXParity_uid155_fpSinCosXTest_a;
--signRCond1_uid157_fpSinCosXTest(LOGICAL,156)@20
signRCond1_uid157_fpSinCosXTest_a <= InvYIsZero_uid151_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_b <= InvIntXParity_uid155_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_c <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
signRCond1_uid157_fpSinCosXTest_d <= InvCosXONe_uid149_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_q_i <= signRCond1_uid157_fpSinCosXTest_a and signRCond1_uid157_fpSinCosXTest_b and signRCond1_uid157_fpSinCosXTest_c and signRCond1_uid157_fpSinCosXTest_d;
signRCond1_uid157_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRCond1_uid157_fpSinCosXTest_q, xin => signRCond1_uid157_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--signRCos_uid158_fpSinCosXTest(LOGICAL,157)@21
signRCos_uid158_fpSinCosXTest_a <= signRCond1_uid157_fpSinCosXTest_q;
signRCos_uid158_fpSinCosXTest_b <= signRCond2_uid152_fpSinCosXTest_q;
signRCos_uid158_fpSinCosXTest_q <= signRCos_uid158_fpSinCosXTest_a or signRCos_uid158_fpSinCosXTest_b;
--cstAllZWF_uid7_fpSinCosXTest(CONSTANT,6)
cstAllZWF_uid7_fpSinCosXTest_q <= "00000000000000000000000";
--frac_uid13_fpSinCosXTest(BITSELECT,12)@0
frac_uid13_fpSinCosXTest_in <= a(22 downto 0);
frac_uid13_fpSinCosXTest_b <= frac_uid13_fpSinCosXTest_in(22 downto 0);
--fracXIsZero_uid14_fpSinCosXTest(LOGICAL,13)@0
fracXIsZero_uid14_fpSinCosXTest_a <= frac_uid13_fpSinCosXTest_b;
fracXIsZero_uid14_fpSinCosXTest_b <= cstAllZWF_uid7_fpSinCosXTest_q;
fracXIsZero_uid14_fpSinCosXTest_q <= "1" when fracXIsZero_uid14_fpSinCosXTest_a = fracXIsZero_uid14_fpSinCosXTest_b else "0";
--cstAllOWE_uid6_fpSinCosXTest(CONSTANT,5)
cstAllOWE_uid6_fpSinCosXTest_q <= "11111111";
--expXIsMax_uid12_fpSinCosXTest(LOGICAL,11)@0
expXIsMax_uid12_fpSinCosXTest_a <= exp_uid9_fpSinCosXTest_b;
expXIsMax_uid12_fpSinCosXTest_b <= cstAllOWE_uid6_fpSinCosXTest_q;
expXIsMax_uid12_fpSinCosXTest_q <= "1" when expXIsMax_uid12_fpSinCosXTest_a = expXIsMax_uid12_fpSinCosXTest_b else "0";
--exc_I_uid15_fpSinCosXTest(LOGICAL,14)@0
exc_I_uid15_fpSinCosXTest_a <= expXIsMax_uid12_fpSinCosXTest_q;
exc_I_uid15_fpSinCosXTest_b <= fracXIsZero_uid14_fpSinCosXTest_q;
exc_I_uid15_fpSinCosXTest_q <= exc_I_uid15_fpSinCosXTest_a and exc_I_uid15_fpSinCosXTest_b;
--ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a(DELAY,762)@0
ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 20 )
PORT MAP ( xin => exc_I_uid15_fpSinCosXTest_q, xout => ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_I_uid131_fpSinCosXTest(LOGICAL,130)@20
InvExc_I_uid131_fpSinCosXTest_a <= ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q;
InvExc_I_uid131_fpSinCosXTest_q <= not InvExc_I_uid131_fpSinCosXTest_a;
--reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2(REG,649)@20
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q <= InvExc_I_uid131_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--InvFracXIsZero_uid16_fpSinCosXTest(LOGICAL,15)@0
InvFracXIsZero_uid16_fpSinCosXTest_a <= fracXIsZero_uid14_fpSinCosXTest_q;
InvFracXIsZero_uid16_fpSinCosXTest_q <= not InvFracXIsZero_uid16_fpSinCosXTest_a;
--exc_N_uid17_fpSinCosXTest(LOGICAL,16)@0
exc_N_uid17_fpSinCosXTest_a <= expXIsMax_uid12_fpSinCosXTest_q;
exc_N_uid17_fpSinCosXTest_b <= InvFracXIsZero_uid16_fpSinCosXTest_q;
exc_N_uid17_fpSinCosXTest_q <= exc_N_uid17_fpSinCosXTest_a and exc_N_uid17_fpSinCosXTest_b;
--ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a(DELAY,763)@0
ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 20 )
PORT MAP ( xin => exc_N_uid17_fpSinCosXTest_q, xout => ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid132_fpSinCosXTest(LOGICAL,131)@20
InvExc_N_uid132_fpSinCosXTest_a <= ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q;
InvExc_N_uid132_fpSinCosXTest_q <= not InvExc_N_uid132_fpSinCosXTest_a;
--reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1(REG,648)@20
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q <= InvExc_N_uid132_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--signRCosFull_uid161_fpSinCosXTest(LOGICAL,160)@21
signRCosFull_uid161_fpSinCosXTest_a <= reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q;
signRCosFull_uid161_fpSinCosXTest_b <= reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q;
signRCosFull_uid161_fpSinCosXTest_c <= signRCos_uid158_fpSinCosXTest_q;
signRCosFull_uid161_fpSinCosXTest_q <= signRCosFull_uid161_fpSinCosXTest_a and signRCosFull_uid161_fpSinCosXTest_b and signRCosFull_uid161_fpSinCosXTest_c;
--ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c(DELAY,809)@21
ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signRCosFull_uid161_fpSinCosXTest_q, xout => ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid22_fpSinCosXTest(CONSTANT,21)
cstBias_uid22_fpSinCosXTest_q <= "01111111";
--ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a(DELAY,681)@19
ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 68, depth => 1 )
PORT MAP ( xin => oneMinusY_uid55_fpSinCosXTest_q, xout => ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--zSinOMyBottom_uid58_fpSinCosXTest(BITSELECT,57)@20
zSinOMyBottom_uid58_fpSinCosXTest_in <= ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q(64 downto 0);
zSinOMyBottom_uid58_fpSinCosXTest_b <= zSinOMyBottom_uid58_fpSinCosXTest_in(64 downto 0);
--reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3(REG,579)@20
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q <= zSinOMyBottom_uid58_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--zSinYBottom_uid59_fpSinCosXTest(BITSELECT,58)@20
zSinYBottom_uid59_fpSinCosXTest_in <= ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q(64 downto 0);
zSinYBottom_uid59_fpSinCosXTest_b <= zSinYBottom_uid59_fpSinCosXTest_in(64 downto 0);
--reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2(REG,578)@20
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q <= zSinYBottom_uid59_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1(REG,614)@20
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q <= InvCmpYToOneMinusY_uid61_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--zCos_uid64_fpSinCosXTest(MUX,63)@21
zCos_uid64_fpSinCosXTest_s <= reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q;
zCos_uid64_fpSinCosXTest: PROCESS (zCos_uid64_fpSinCosXTest_s, en, reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q, reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q)
BEGIN
CASE zCos_uid64_fpSinCosXTest_s IS
WHEN "0" => zCos_uid64_fpSinCosXTest_q <= reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q;
WHEN "1" => zCos_uid64_fpSinCosXTest_q <= reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q;
WHEN OTHERS => zCos_uid64_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--addr_uid83_fpSinCosXTest(BITSELECT,82)@21
addr_uid83_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q;
addr_uid83_fpSinCosXTest_b <= addr_uid83_fpSinCosXTest_in(64 downto 57);
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0(REG,630)@21
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q <= addr_uid83_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid404_tableGencosPiZ_lutmem(DUALMEM,532)@22
memoryC2_uid404_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC2_uid404_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC2_uid404_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q;
memoryC2_uid404_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC2_uid404_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid404_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid404_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid404_tableGencosPiZ_lutmem_iq,
address_a => memoryC2_uid404_tableGencosPiZ_lutmem_aa,
data_a => memoryC2_uid404_tableGencosPiZ_lutmem_ia
);
memoryC2_uid404_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC2_uid404_tableGencosPiZ_lutmem_q <= memoryC2_uid404_tableGencosPiZ_lutmem_iq(12 downto 0);
--reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1(REG,632)@24
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q <= memoryC2_uid404_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPcosPiZ_uid87_fpSinCosXTest(BITSELECT,86)@21
zPcosPiZ_uid87_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(56 downto 0);
zPcosPiZ_uid87_fpSinCosXTest_b <= zPcosPiZ_uid87_fpSinCosXTest_in(56 downto 42);
--yT1_uid419_polyEvalcosPiZ(BITSELECT,418)@21
yT1_uid419_polyEvalcosPiZ_in <= zPcosPiZ_uid87_fpSinCosXTest_b;
yT1_uid419_polyEvalcosPiZ_b <= yT1_uid419_polyEvalcosPiZ_in(14 downto 2);
--reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0(REG,631)@21
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q <= yT1_uid419_polyEvalcosPiZ_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg(DELAY,1513)
ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q, xout => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a(DELAY,1125)@22
ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q, xout => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid508_pT1_uid420_polyEvalcosPiZ(MULT,507)@25
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a),14)) * SIGNED(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b);
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a <= (others => '0');
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b <= (others => '0');
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a <= ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b <= reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q <= prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ(BITSELECT,508)@28
prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in <= prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q;
prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in(25 downto 12);
--highBBits_uid422_polyEvalcosPiZ(BITSELECT,421)@28
highBBits_uid422_polyEvalcosPiZ_in <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b;
highBBits_uid422_polyEvalcosPiZ_b <= highBBits_uid422_polyEvalcosPiZ_in(13 downto 1);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a(DELAY,1256)@21
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => addr_uid83_fpSinCosXTest_b, xout => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0(REG,633)@24
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid402_tableGencosPiZ_lutmem(DUALMEM,531)@25
memoryC1_uid402_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC1_uid402_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC1_uid402_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q;
memoryC1_uid402_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC1_uid402_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid402_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid402_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid402_tableGencosPiZ_lutmem_iq,
address_a => memoryC1_uid402_tableGencosPiZ_lutmem_aa,
data_a => memoryC1_uid402_tableGencosPiZ_lutmem_ia
);
memoryC1_uid402_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC1_uid402_tableGencosPiZ_lutmem_q <= memoryC1_uid402_tableGencosPiZ_lutmem_iq(20 downto 0);
--reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0(REG,634)@27
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q <= memoryC1_uid402_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid423_polyEvalcosPiZ(ADD,422)@28
sumAHighB_uid423_polyEvalcosPiZ_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q(20)) & reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q);
sumAHighB_uid423_polyEvalcosPiZ_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid422_polyEvalcosPiZ_b(12)) & highBBits_uid422_polyEvalcosPiZ_b);
sumAHighB_uid423_polyEvalcosPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid423_polyEvalcosPiZ_a) + SIGNED(sumAHighB_uid423_polyEvalcosPiZ_b));
sumAHighB_uid423_polyEvalcosPiZ_q <= sumAHighB_uid423_polyEvalcosPiZ_o(21 downto 0);
--lowRangeB_uid421_polyEvalcosPiZ(BITSELECT,420)@28
lowRangeB_uid421_polyEvalcosPiZ_in <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b(0 downto 0);
lowRangeB_uid421_polyEvalcosPiZ_b <= lowRangeB_uid421_polyEvalcosPiZ_in(0 downto 0);
--s1_uid421_uid424_polyEvalcosPiZ(BITJOIN,423)@28
s1_uid421_uid424_polyEvalcosPiZ_q <= sumAHighB_uid423_polyEvalcosPiZ_q & lowRangeB_uid421_polyEvalcosPiZ_b;
--reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1(REG,636)@28
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q <= s1_uid421_uid424_polyEvalcosPiZ_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor(LOGICAL,1524)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q <= not (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a or ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b);
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top(CONSTANT,1520)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q <= "0100";
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp(LOGICAL,1521)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q <= "1" when ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a = ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b else "0";
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg(REG,1522)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena(REG,1525)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd(LOGICAL,1526)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b <= en;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a and ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b;
--reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0(REG,635)@21
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q <= zPcosPiZ_uid87_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg(DELAY,1514)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q, xout => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt(COUNTER,1516)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i = 3 THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i,3));
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg(REG,1517)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux(MUX,1518)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s <= en;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux: PROCESS (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s, ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q, ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem(DUALMEM,1515)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq,
address_a => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa,
data_a => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia
);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0 <= areset;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq(14 downto 0);
--prodXY_uid511_pT2_uid426_polyEvalcosPiZ(MULT,510)@29
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a),16)) * SIGNED(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b);
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a <= (others => '0');
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b <= (others => '0');
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b <= reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q <= prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ(BITSELECT,511)@32
prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in <= prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q;
prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in(37 downto 14);
--highBBits_uid428_polyEvalcosPiZ(BITSELECT,427)@32
highBBits_uid428_polyEvalcosPiZ_in <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b;
highBBits_uid428_polyEvalcosPiZ_b <= highBBits_uid428_polyEvalcosPiZ_in(23 downto 2);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor(LOGICAL,1577)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q <= not (ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a or ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena(REG,1578)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q = "1") THEN
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd(LOGICAL,1579)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b <= en;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a and ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b;
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg(DELAY,1567)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addr_uid83_fpSinCosXTest_b, xout => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem(DUALMEM,1568)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq,
address_a => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa,
data_a => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia
);
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0(REG,637)@28
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid400_tableGencosPiZ_lutmem(DUALMEM,530)@29
memoryC0_uid400_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC0_uid400_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC0_uid400_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q;
memoryC0_uid400_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC0_uid400_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid400_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid400_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid400_tableGencosPiZ_lutmem_iq,
address_a => memoryC0_uid400_tableGencosPiZ_lutmem_aa,
data_a => memoryC0_uid400_tableGencosPiZ_lutmem_ia
);
memoryC0_uid400_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC0_uid400_tableGencosPiZ_lutmem_q <= memoryC0_uid400_tableGencosPiZ_lutmem_iq(29 downto 0);
--reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0(REG,638)@31
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q <= memoryC0_uid400_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid429_polyEvalcosPiZ(ADD,428)@32
sumAHighB_uid429_polyEvalcosPiZ_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q(29)) & reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q);
sumAHighB_uid429_polyEvalcosPiZ_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid428_polyEvalcosPiZ_b(21)) & highBBits_uid428_polyEvalcosPiZ_b);
sumAHighB_uid429_polyEvalcosPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid429_polyEvalcosPiZ_a) + SIGNED(sumAHighB_uid429_polyEvalcosPiZ_b));
sumAHighB_uid429_polyEvalcosPiZ_q <= sumAHighB_uid429_polyEvalcosPiZ_o(30 downto 0);
--lowRangeB_uid427_polyEvalcosPiZ(BITSELECT,426)@32
lowRangeB_uid427_polyEvalcosPiZ_in <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b(1 downto 0);
lowRangeB_uid427_polyEvalcosPiZ_b <= lowRangeB_uid427_polyEvalcosPiZ_in(1 downto 0);
--s2_uid427_uid430_polyEvalcosPiZ(BITJOIN,429)@32
s2_uid427_uid430_polyEvalcosPiZ_q <= sumAHighB_uid429_polyEvalcosPiZ_q & lowRangeB_uid427_polyEvalcosPiZ_b;
--polyEvalSigcosPiZ_uid89_fpSinCosXTest(BITSELECT,88)@32
polyEvalSigcosPiZ_uid89_fpSinCosXTest_in <= s2_uid427_uid430_polyEvalcosPiZ_q(30 downto 0);
polyEvalSigcosPiZ_uid89_fpSinCosXTest_b <= polyEvalSigcosPiZ_uid89_fpSinCosXTest_in(30 downto 5);
--reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1(REG,640)@32
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q <= polyEvalSigcosPiZ_uid89_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor(LOGICAL,1590)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q <= not (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a or ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b);
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top(CONSTANT,1586)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q <= "010";
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp(LOGICAL,1587)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q <= "1" when ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a = ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b else "0";
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg(REG,1588)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena(REG,1591)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd(LOGICAL,1592)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b <= en;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a and ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b;
--LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest(BITSELECT,388)@27
LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q(63 downto 0);
LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in(63 downto 0);
--leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest(BITJOIN,389)@27
leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b & GND_q;
--cstZmwFRRPwSM1_uid52_fpSinCosXTest(CONSTANT,51)
cstZmwFRRPwSM1_uid52_fpSinCosXTest_q <= "00000000000000000000000000000000000000000000000000000000000000000";
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor(LOGICAL,1455)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q <= not (ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a or ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b);
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena(REG,1456)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q = "1") THEN
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd(LOGICAL,1457)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b <= en;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a and ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b;
--X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest(BITSELECT,359)@21
X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(32 downto 0);
X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b <= X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in(32 downto 0);
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg(DELAY,1447)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem(DUALMEM,1448)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 33,
widthad_a => 1,
numwords_a => 2,
width_b => 33,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia
);
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq(32 downto 0);
--leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest(BITJOIN,360)@25
leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor(LOGICAL,1466)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q <= not (ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a or ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b);
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena(REG,1467)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q = "1") THEN
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd(LOGICAL,1468)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b <= en;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a and ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg(DELAY,1458)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => zCos_uid64_fpSinCosXTest_q, xout => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem(DUALMEM,1459)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 65,
widthad_a => 1,
numwords_a => 2,
width_b => 65,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia
);
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq(64 downto 0);
--zs_uid236_lzcZSin_uid66_fpSinCosXTest(CONSTANT,235)
zs_uid236_lzcZSin_uid66_fpSinCosXTest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--rVStage_uid316_lzcZCos_uid69_fpSinCosXTest(BITSELECT,315)@21
rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q;
rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in(64 downto 1);
--vCount_uid317_lzcZCos_uid69_fpSinCosXTest(LOGICAL,316)@21
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid236_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g(DELAY,985)@22
ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid319_lzcZCos_uid69_fpSinCosXTest(BITSELECT,318)@21
vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(0 downto 0);
vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in(0 downto 0);
--ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b(DELAY,943)@21
ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid239_lzcZSin_uid66_fpSinCosXTest(CONSTANT,238)
mO_uid239_lzcZSin_uid66_fpSinCosXTest_q <= "111111111111111111111111111111111111111111111111111111111111111";
--cStage_uid320_lzcZCos_uid69_fpSinCosXTest(BITJOIN,319)@22
cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q <= ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q & mO_uid239_lzcZSin_uid66_fpSinCosXTest_q;
--ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c(DELAY,945)@21
ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid322_lzcZCos_uid69_fpSinCosXTest(MUX,321)@22
vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid322_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s, en, ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q, cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid324_lzcZCos_uid69_fpSinCosXTest(BITSELECT,323)@22
rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in(63 downto 32);
--vCount_uid325_lzcZCos_uid69_fpSinCosXTest(LOGICAL,324)@22
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f(DELAY,984)@23
ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid326_lzcZCos_uid69_fpSinCosXTest(BITSELECT,325)@22
vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q(31 downto 0);
vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in(31 downto 0);
--ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d(DELAY,952)@22
ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c(DELAY,951)@22
ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid328_lzcZCos_uid69_fpSinCosXTest(MUX,327)@23
vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid328_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s, en, ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q, ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q)
BEGIN
CASE vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q;
WHEN OTHERS => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid330_lzcZCos_uid69_fpSinCosXTest(BITSELECT,329)@23
rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in(31 downto 16);
--vCount_uid331_lzcZCos_uid69_fpSinCosXTest(LOGICAL,330)@23
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b else "0";
--reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4(REG,622)@23
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q <= vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e(DELAY,983)@24
ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid332_lzcZCos_uid69_fpSinCosXTest(BITSELECT,331)@23
vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q(15 downto 0);
vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in(15 downto 0);
--vStagei_uid334_lzcZCos_uid69_fpSinCosXTest(MUX,333)@23
vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid334_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s, en, rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b, vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b;
WHEN "1" => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid336_lzcZCos_uid69_fpSinCosXTest(BITSELECT,335)@23
rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in(15 downto 8);
--reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1(REG,617)@23
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q <= rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid337_lzcZCos_uid69_fpSinCosXTest(LOGICAL,336)@24
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a <= reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q;
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b else "0";
--ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d(DELAY,982)@24
ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid338_lzcZCos_uid69_fpSinCosXTest(BITSELECT,337)@23
vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q(7 downto 0);
vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3(REG,619)@23
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q <= vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid340_lzcZCos_uid69_fpSinCosXTest(MUX,339)@24
vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid340_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s, en, reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q, reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid342_lzcZCos_uid69_fpSinCosXTest(BITSELECT,341)@24
rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in(7 downto 4);
--vCount_uid343_lzcZCos_uid69_fpSinCosXTest(LOGICAL,342)@24
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid344_lzcZCos_uid69_fpSinCosXTest(BITSELECT,343)@24
vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q(3 downto 0);
vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in(3 downto 0);
--reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3(REG,621)@24
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q <= vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2(REG,620)@24
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid346_lzcZCos_uid69_fpSinCosXTest(MUX,345)@25
vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid346_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s, en, reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q, reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid348_lzcZCos_uid69_fpSinCosXTest(BITSELECT,347)@25
rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in(3 downto 2);
--vCount_uid349_lzcZCos_uid69_fpSinCosXTest(LOGICAL,348)@25
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b else "0";
--vStage_uid350_lzcZCos_uid69_fpSinCosXTest(BITSELECT,349)@25
vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q(1 downto 0);
vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in(1 downto 0);
--vStagei_uid352_lzcZCos_uid69_fpSinCosXTest(MUX,351)@25
vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid352_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s, en, rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b, vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b;
WHEN "1" => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid354_lzcZCos_uid69_fpSinCosXTest(BITSELECT,353)@25
rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in(1 downto 1);
--vCount_uid355_lzcZCos_uid69_fpSinCosXTest(LOGICAL,354)@25
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b <= GND_q;
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b else "0";
--r_uid356_lzcZCos_uid69_fpSinCosXTest(BITJOIN,355)@25
r_uid356_lzcZCos_uid69_fpSinCosXTest_q <= ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q & ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q & ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q & ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q & vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q & vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q & vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q;
--leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest(BITSELECT,363)@25
leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q;
leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in(6 downto 5);
--leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest(MUX,364)@25
leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s <= leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b;
leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s, en, ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest(BITSELECT,372)@25
LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(40 downto 0);
LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in(40 downto 0);
--leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest(CONSTANT,292)
leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q <= "000000000000000000000000";
--leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest(BITJOIN,373)@25
leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b & leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5(REG,627)@25
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest(BITSELECT,369)@25
LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(48 downto 0);
LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in(48 downto 0);
--leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest(BITJOIN,370)@25
leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4(REG,626)@25
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest(BITSELECT,366)@25
LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(56 downto 0);
LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in(56 downto 0);
--leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest(BITJOIN,367)@25
leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3(REG,625)@25
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2(REG,624)@25
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest(BITSELECT,374)@25
leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1(REG,623)@25
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q <= leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest(MUX,375)@26
leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s <= reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q;
leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s, en, reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest(BITSELECT,383)@26
LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(58 downto 0);
LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1009)@26
ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest(CONSTANT,303)
leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q <= "000000";
--leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest(BITJOIN,384)@27
leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q;
--LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest(BITSELECT,380)@26
LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(60 downto 0);
LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1007)@26
ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest(BITJOIN,381)@27
leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest(BITSELECT,377)@26
LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(62 downto 0);
LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in(62 downto 0);
--ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1005)@26
ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest(BITJOIN,378)@27
leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2(REG,629)@26
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest(BITSELECT,385)@25
leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1(REG,628)@25
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q <= leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1011)@26
ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest(MUX,386)@27
leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s <= ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q;
leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s, en, reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest(BITSELECT,390)@25
leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1019)@25
ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest(MUX,391)@27
leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s <= ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q;
leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s, en, leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "0" => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "1" => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--pCos_uid77_fpSinCosXTest(BITSELECT,76)@27
pCos_uid77_fpSinCosXTest_in <= leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q;
pCos_uid77_fpSinCosXTest_b <= pCos_uid77_fpSinCosXTest_in(64 downto 39);
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg(DELAY,1580)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => pCos_uid77_fpSinCosXTest_b, xout => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt(COUNTER,1582)
-- every=1, low=0, high=2, step=1, init=1
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i = 1 THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i - 2;
ELSE
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i,2));
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg(REG,1583)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux(MUX,1584)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s <= en;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux: PROCESS (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s, ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q, ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q)
BEGIN
CASE ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s IS
WHEN "0" => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q;
WHEN "1" => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem(DUALMEM,1581)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 2,
numwords_a => 3,
width_b => 26,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq,
address_a => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa,
data_a => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia
);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0 <= areset;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq(25 downto 0);
--reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0(REG,639)@32
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--mulCos_uid105_fpSinCosXTest(MULT,104)@33
mulCos_uid105_fpSinCosXTest_pr <= UNSIGNED(mulCos_uid105_fpSinCosXTest_a) * UNSIGNED(mulCos_uid105_fpSinCosXTest_b);
mulCos_uid105_fpSinCosXTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulCos_uid105_fpSinCosXTest_a <= (others => '0');
mulCos_uid105_fpSinCosXTest_b <= (others => '0');
mulCos_uid105_fpSinCosXTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulCos_uid105_fpSinCosXTest_a <= reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q;
mulCos_uid105_fpSinCosXTest_b <= reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q;
mulCos_uid105_fpSinCosXTest_s1 <= STD_LOGIC_VECTOR(mulCos_uid105_fpSinCosXTest_pr);
END IF;
END IF;
END PROCESS;
mulCos_uid105_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulCos_uid105_fpSinCosXTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulCos_uid105_fpSinCosXTest_q <= mulCos_uid105_fpSinCosXTest_s1;
END IF;
END IF;
END PROCESS;
--normBitCos_uid106_fpSinCosXTest(BITSELECT,105)@36
normBitCos_uid106_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q;
normBitCos_uid106_fpSinCosXTest_b <= normBitCos_uid106_fpSinCosXTest_in(51 downto 51);
--cosRndOp_uid112_uid113_fpSinCosXTest(BITJOIN,112)@36
cosRndOp_uid112_uid113_fpSinCosXTest_q <= normBitCos_uid106_fpSinCosXTest_b & cstAllZWF_uid7_fpSinCosXTest_q & VCC_q;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor(LOGICAL,1296)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q <= not (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a or ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b);
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top(CONSTANT,1292)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q <= "0110";
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp(LOGICAL,1293)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q <= "1" when ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a = ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b else "0";
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg(REG,1294)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena(REG,1297)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd(LOGICAL,1298)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b <= en;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a and ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b;
--reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1(REG,641)@25
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg(DELAY,1286)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q, xout => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt(COUNTER,1288)
-- every=1, low=0, high=6, step=1, init=1
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i = 5 THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i - 6;
ELSE
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i,3));
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg(REG,1289)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux(MUX,1290)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s <= en;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux: PROCESS (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s, ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q, ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem(DUALMEM,1287)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 7,
width_b => 7,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia
);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq(6 downto 0);
--expHardCase_uid78_fpSinCosXTest(SUB,77)@35
expHardCase_uid78_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expHardCase_uid78_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q);
expHardCase_uid78_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid78_fpSinCosXTest_a) - UNSIGNED(expHardCase_uid78_fpSinCosXTest_b));
expHardCase_uid78_fpSinCosXTest_q <= expHardCase_uid78_fpSinCosXTest_o(8 downto 0);
--expPCos_uid79_fpSinCosXTest(BITSELECT,78)@35
expPCos_uid79_fpSinCosXTest_in <= expHardCase_uid78_fpSinCosXTest_q(7 downto 0);
expPCos_uid79_fpSinCosXTest_b <= expPCos_uid79_fpSinCosXTest_in(7 downto 0);
--reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1(REG,642)@35
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q <= expPCos_uid79_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--fracRCosPreRndHigh_uid108_fpSinCosXTest(BITSELECT,107)@36
fracRCosPreRndHigh_uid108_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q(50 downto 0);
fracRCosPreRndHigh_uid108_fpSinCosXTest_b <= fracRCosPreRndHigh_uid108_fpSinCosXTest_in(50 downto 27);
--fracRCosPreRndLow_uid109_fpSinCosXTest(BITSELECT,108)@36
fracRCosPreRndLow_uid109_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q(49 downto 0);
fracRCosPreRndLow_uid109_fpSinCosXTest_b <= fracRCosPreRndLow_uid109_fpSinCosXTest_in(49 downto 26);
--fracRCosPreRnd_uid110_fpSinCosXTest(MUX,109)@36
fracRCosPreRnd_uid110_fpSinCosXTest_s <= normBitCos_uid106_fpSinCosXTest_b;
fracRCosPreRnd_uid110_fpSinCosXTest: PROCESS (fracRCosPreRnd_uid110_fpSinCosXTest_s, en, fracRCosPreRndLow_uid109_fpSinCosXTest_b, fracRCosPreRndHigh_uid108_fpSinCosXTest_b)
BEGIN
CASE fracRCosPreRnd_uid110_fpSinCosXTest_s IS
WHEN "0" => fracRCosPreRnd_uid110_fpSinCosXTest_q <= fracRCosPreRndLow_uid109_fpSinCosXTest_b;
WHEN "1" => fracRCosPreRnd_uid110_fpSinCosXTest_q <= fracRCosPreRndHigh_uid108_fpSinCosXTest_b;
WHEN OTHERS => fracRCosPreRnd_uid110_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracRCosPreRnd_uid111_uid111_fpSinCosXTest(BITJOIN,110)@36
expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q <= reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q & fracRCosPreRnd_uid110_fpSinCosXTest_q;
--expFracRCos_uid114_fpSinCosXTest(ADD,113)@36
expFracRCos_uid114_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q);
expFracRCos_uid114_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00000000" & cosRndOp_uid112_uid113_fpSinCosXTest_q);
expFracRCos_uid114_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRCos_uid114_fpSinCosXTest_a) + UNSIGNED(expFracRCos_uid114_fpSinCosXTest_b));
expFracRCos_uid114_fpSinCosXTest_q <= expFracRCos_uid114_fpSinCosXTest_o(32 downto 0);
--expRCompSin_uid116_fpSinCosXTest(BITSELECT,115)@36
expRCompSin_uid116_fpSinCosXTest_in <= expFracRCos_uid114_fpSinCosXTest_q(31 downto 0);
expRCompSin_uid116_fpSinCosXTest_b <= expRCompSin_uid116_fpSinCosXTest_in(31 downto 24);
--reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2(REG,646)@36
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q <= expRCompSin_uid116_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor(LOGICAL,1385)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q <= not (ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a or ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top(CONSTANT,1305)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q <= "01101";
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp(LOGICAL,1306)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q <= "1" when ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a = ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b else "0";
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg(REG,1307)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena(REG,1386)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q = "1") THEN
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd(LOGICAL,1387)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b <= en;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a and ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b;
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a(DELAY,745)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c(DELAY,783)@16
ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => cosXIsOneXRR_uid42_fpSinCosXTest_n, xout => ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--InvCosXIsOneXRR_uid136_fpSinCosXTest(LOGICAL,135)@16
InvCosXIsOneXRR_uid136_fpSinCosXTest_a <= cosXIsOneXRR_uid42_fpSinCosXTest_n;
InvCosXIsOneXRR_uid136_fpSinCosXTest_q <= not InvCosXIsOneXRR_uid136_fpSinCosXTest_a;
--ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c(DELAY,773)@16
ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => InvCosXIsOneXRR_uid136_fpSinCosXTest_q, xout => ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a(DELAY,755)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsX_uid127_fpSinCosXTest(LOGICAL,126)@18
InvSinXIsX_uid127_fpSinCosXTest_a <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q;
InvSinXIsX_uid127_fpSinCosXTest_q <= not InvSinXIsX_uid127_fpSinCosXTest_a;
--ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b(DELAY,772)@18
ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => InvSinXIsX_uid127_fpSinCosXTest_q, xout => ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--half_uid53_fpSinCosXTest(BITJOIN,52)@19
half_uid53_fpSinCosXTest_q <= VCC_q & cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
--yIsHalf_uid54_fpSinCosXTest(LOGICAL,53)@19
yIsHalf_uid54_fpSinCosXTest_a <= reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q;
yIsHalf_uid54_fpSinCosXTest_b <= half_uid53_fpSinCosXTest_q;
yIsHalf_uid54_fpSinCosXTest_q <= "1" when yIsHalf_uid54_fpSinCosXTest_a = yIsHalf_uid54_fpSinCosXTest_b else "0";
--yHalfCosXNotOne_uid138_fpSinCosXTest(LOGICAL,137)@19
yHalfCosXNotOne_uid138_fpSinCosXTest_a <= yIsHalf_uid54_fpSinCosXTest_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_b <= ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_c <= ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_q <= yHalfCosXNotOne_uid138_fpSinCosXTest_a and yHalfCosXNotOne_uid138_fpSinCosXTest_b and yHalfCosXNotOne_uid138_fpSinCosXTest_c;
--ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b(DELAY,744)@0
ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => exc_I_uid15_fpSinCosXTest_q, xout => ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a(DELAY,743)@0
ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => exc_N_uid17_fpSinCosXTest_q, xout => ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRNaN_uid117_fpSinCosXTest(LOGICAL,116)@19
excRNaN_uid117_fpSinCosXTest_a <= ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q;
excRNaN_uid117_fpSinCosXTest_b <= ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q;
excRNaN_uid117_fpSinCosXTest_q <= excRNaN_uid117_fpSinCosXTest_a or excRNaN_uid117_fpSinCosXTest_b;
--join_uid143_fpSinCosXTest(BITJOIN,142)@19
join_uid143_fpSinCosXTest_q <= ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q & yHalfCosXNotOne_uid138_fpSinCosXTest_q & excRNaN_uid117_fpSinCosXTest_q;
--expSelBitsCos_uid144_fpSinCosXTest(BITJOIN,143)@19
expSelBitsCos_uid144_fpSinCosXTest_q <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q & join_uid143_fpSinCosXTest_q;
--reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0(REG,645)@19
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q <= expSelBitsCos_uid144_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--expSelectorCos_uid145_fpSinCosXTest(LOOKUP,144)@20
expSelectorCos_uid145_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSelectorCos_uid145_fpSinCosXTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q) IS
WHEN "0000" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "0001" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "0010" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "0011" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "0100" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "0101" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "0110" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "0111" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "1000" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "1001" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "1010" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "1011" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "1100" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "1101" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "1110" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "1111" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN OTHERS =>
expSelectorCos_uid145_fpSinCosXTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg(DELAY,1375)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => expSelectorCos_uid145_fpSinCosXTest_q, xout => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt(COUNTER,1301)
-- every=1, low=0, high=13, step=1, init=1
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i = 12 THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i - 13;
ELSE
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg(REG,1302)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux(MUX,1303)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s, ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q, ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem(DUALMEM,1376)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia
);
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq(1 downto 0);
--expRPostExcCos_uid147_fpSinCosXTest(MUX,146)@37
expRPostExcCos_uid147_fpSinCosXTest_s <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q;
expRPostExcCos_uid147_fpSinCosXTest: PROCESS (expRPostExcCos_uid147_fpSinCosXTest_s, en, reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q, cstBias_uid22_fpSinCosXTest_q, cstAllZWE_uid8_fpSinCosXTest_q, cstAllOWE_uid6_fpSinCosXTest_q)
BEGIN
CASE expRPostExcCos_uid147_fpSinCosXTest_s IS
WHEN "00" => expRPostExcCos_uid147_fpSinCosXTest_q <= reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q;
WHEN "01" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstBias_uid22_fpSinCosXTest_q;
WHEN "10" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstAllZWE_uid8_fpSinCosXTest_q;
WHEN "11" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstAllOWE_uid6_fpSinCosXTest_q;
WHEN OTHERS => expRPostExcCos_uid147_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstNaNwF_uid32_fpSinCosXTest(CONSTANT,31)
cstNaNwF_uid32_fpSinCosXTest_q <= "00000000000000000000001";
--fracRCompCos_uid115_fpSinCosXTest(BITSELECT,114)@36
fracRCompCos_uid115_fpSinCosXTest_in <= expFracRCos_uid114_fpSinCosXTest_q(23 downto 0);
fracRCompCos_uid115_fpSinCosXTest_b <= fracRCompCos_uid115_fpSinCosXTest_in(23 downto 1);
--reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2(REG,644)@36
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q <= fracRCompCos_uid115_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor(LOGICAL,1372)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q <= not (ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a or ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b);
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena(REG,1373)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q = "1") THEN
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd(LOGICAL,1374)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b <= en;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a and ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b;
--reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1(REG,613)@19
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q <= excRNaN_uid117_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3(REG,612)@19
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q <= ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q;
END IF;
END IF;
END PROCESS;
--reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2(REG,611)@19
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q;
END IF;
END IF;
END PROCESS;
--reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1(REG,610)@19
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q <= yHalfCosXNotOne_uid138_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--rZOrOne_uid140_fpSinCosXTest(LOGICAL,139)@20
rZOrOne_uid140_fpSinCosXTest_a <= reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q;
rZOrOne_uid140_fpSinCosXTest_b <= reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q;
rZOrOne_uid140_fpSinCosXTest_c <= reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q;
rZOrOne_uid140_fpSinCosXTest_q <= rZOrOne_uid140_fpSinCosXTest_a or rZOrOne_uid140_fpSinCosXTest_b or rZOrOne_uid140_fpSinCosXTest_c;
--join_uid141_fpSinCosXTest(BITJOIN,140)@20
join_uid141_fpSinCosXTest_q <= reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q & rZOrOne_uid140_fpSinCosXTest_q;
--reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1(REG,643)@20
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q <= join_uid141_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg(DELAY,1362)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q, xout => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem(DUALMEM,1363)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia
);
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq(1 downto 0);
--fracRPostExcCos_uid142_fpSinCosXTest(MUX,141)@37
fracRPostExcCos_uid142_fpSinCosXTest_s <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q;
fracRPostExcCos_uid142_fpSinCosXTest: PROCESS (fracRPostExcCos_uid142_fpSinCosXTest_s, en, reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q, cstAllZWF_uid7_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q)
BEGIN
CASE fracRPostExcCos_uid142_fpSinCosXTest_s IS
WHEN "00" => fracRPostExcCos_uid142_fpSinCosXTest_q <= reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q;
WHEN "01" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstAllZWF_uid7_fpSinCosXTest_q;
WHEN "10" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN "11" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN OTHERS => fracRPostExcCos_uid142_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpCos_uid162_fpSinCosXTest(BITJOIN,161)@37
fpCos_uid162_fpSinCosXTest_q <= ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q & expRPostExcCos_uid147_fpSinCosXTest_q & fracRPostExcCos_uid142_fpSinCosXTest_q;
--cstBiasMwShiftM2_uid25_fpSinCosXTest(CONSTANT,24)
cstBiasMwShiftM2_uid25_fpSinCosXTest_q <= "01110001";
--sinXIsXRR_uid41_fpSinCosXTest(COMPARE,40)@16
sinXIsXRR_uid41_fpSinCosXTest_cin <= GND_q;
sinXIsXRR_uid41_fpSinCosXTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid25_fpSinCosXTest_q) & '0';
sinXIsXRR_uid41_fpSinCosXTest_b <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q) & sinXIsXRR_uid41_fpSinCosXTest_cin(0);
sinXIsXRR_uid41_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(sinXIsXRR_uid41_fpSinCosXTest_a) - SIGNED(sinXIsXRR_uid41_fpSinCosXTest_b));
sinXIsXRR_uid41_fpSinCosXTest_n(0) <= not sinXIsXRR_uid41_fpSinCosXTest_o(11);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a(DELAY,756)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsXRR_uid128_fpSinCosXTest(LOGICAL,127)@18
InvSinXIsXRR_uid128_fpSinCosXTest_a <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q;
InvSinXIsXRR_uid128_fpSinCosXTest_q <= not InvSinXIsXRR_uid128_fpSinCosXTest_a;
--signComp_uid129_fpSinCosXTest(LOGICAL,128)@18
signComp_uid129_fpSinCosXTest_a <= InvSinXIsXRR_uid128_fpSinCosXTest_q;
signComp_uid129_fpSinCosXTest_b <= InvSinXIsX_uid127_fpSinCosXTest_q;
signComp_uid129_fpSinCosXTest_c <= intXParity_uid49_fpSinCosXTest_b;
signComp_uid129_fpSinCosXTest_q <= signComp_uid129_fpSinCosXTest_a and signComp_uid129_fpSinCosXTest_b and signComp_uid129_fpSinCosXTest_c;
--signX_uid37_fpSinCosXTest(BITSELECT,36)@0
signX_uid37_fpSinCosXTest_in <= a;
signX_uid37_fpSinCosXTest_b <= signX_uid37_fpSinCosXTest_in(31 downto 31);
--ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a(DELAY,760)@0
ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => signX_uid37_fpSinCosXTest_b, xout => ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid130_fpSinCosXTest(LOGICAL,129)@18
signR_uid130_fpSinCosXTest_a <= ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q;
signR_uid130_fpSinCosXTest_b <= signComp_uid129_fpSinCosXTest_q;
signR_uid130_fpSinCosXTest_q <= signR_uid130_fpSinCosXTest_a xor signR_uid130_fpSinCosXTest_b;
--ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c(DELAY,766)@18
ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => signR_uid130_fpSinCosXTest_q, xout => ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--signRSinFull_uid133_fpSinCosXTest(LOGICAL,132)@20
signRSinFull_uid133_fpSinCosXTest_a <= InvExc_N_uid132_fpSinCosXTest_q;
signRSinFull_uid133_fpSinCosXTest_b <= InvExc_I_uid131_fpSinCosXTest_q;
signRSinFull_uid133_fpSinCosXTest_c <= ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q;
signRSinFull_uid133_fpSinCosXTest_q_i <= signRSinFull_uid133_fpSinCosXTest_a and signRSinFull_uid133_fpSinCosXTest_b and signRSinFull_uid133_fpSinCosXTest_c;
signRSinFull_uid133_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRSinFull_uid133_fpSinCosXTest_q, xin => signRSinFull_uid133_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c(DELAY,769)@21
ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signRSinFull_uid133_fpSinCosXTest_q, xout => ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor(LOGICAL,1359)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q <= not (ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a or ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b);
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top(CONSTANT,1342)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q <= "0100010";
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp(LOGICAL,1343)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q <= "1" when ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a = ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b else "0";
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg(REG,1344)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena(REG,1360)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q = "1") THEN
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd(LOGICAL,1361)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b <= en;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a and ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg(DELAY,1349)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => exp_uid9_fpSinCosXTest_b, xout => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt(COUNTER,1338)
-- every=1, low=0, high=34, step=1, init=1
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i = 33 THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i - 34;
ELSE
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i,6));
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg(REG,1339)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux(MUX,1340)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem(DUALMEM,1350)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 6,
numwords_a => 35,
width_b => 8,
widthad_b => 6,
numwords_b => 35,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia
);
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a(DELAY,1228)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1(REG,605)@35
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor(LOGICAL,1309)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q <= not (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a or ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena(REG,1310)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd(LOGICAL,1311)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b <= en;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a and ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b;
--oFracXRRSmallXRR_uid90_fpSinCosXTest(BITSELECT,89)@16
oFracXRRSmallXRR_uid90_fpSinCosXTest_in <= oFracXRR_uid43_uid43_fpSinCosXTest_q;
oFracXRRSmallXRR_uid90_fpSinCosXTest_b <= oFracXRRSmallXRR_uid90_fpSinCosXTest_in(53 downto 28);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg(DELAY,1299)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => oFracXRRSmallXRR_uid90_fpSinCosXTest_b, xout => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem(DUALMEM,1300)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 4,
numwords_a => 14,
width_b => 26,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia
);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq(25 downto 0);
--reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1(REG,577)@20
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
END IF;
END IF;
END PROCESS;
--zSin_uid60_fpSinCosXTest(MUX,59)@21
zSin_uid60_fpSinCosXTest_s <= reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q;
zSin_uid60_fpSinCosXTest: PROCESS (zSin_uid60_fpSinCosXTest_s, en, reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q, reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q)
BEGIN
CASE zSin_uid60_fpSinCosXTest_s IS
WHEN "0" => zSin_uid60_fpSinCosXTest_q <= reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q;
WHEN "1" => zSin_uid60_fpSinCosXTest_q <= reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q;
WHEN OTHERS => zSin_uid60_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--addr_uid81_fpSinCosXTest(BITSELECT,80)@21
addr_uid81_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q;
addr_uid81_fpSinCosXTest_b <= addr_uid81_fpSinCosXTest_in(64 downto 57);
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0(REG,595)@21
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q <= addr_uid81_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid398_tableGensinPiZ_lutmem(DUALMEM,529)@22
memoryC2_uid398_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC2_uid398_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC2_uid398_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q;
memoryC2_uid398_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC2_uid398_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid398_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid398_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid398_tableGensinPiZ_lutmem_iq,
address_a => memoryC2_uid398_tableGensinPiZ_lutmem_aa,
data_a => memoryC2_uid398_tableGensinPiZ_lutmem_ia
);
memoryC2_uid398_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC2_uid398_tableGensinPiZ_lutmem_q <= memoryC2_uid398_tableGensinPiZ_lutmem_iq(12 downto 0);
--reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1(REG,597)@24
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q <= memoryC2_uid398_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPsinPiZ_uid84_fpSinCosXTest(BITSELECT,83)@21
zPsinPiZ_uid84_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(56 downto 0);
zPsinPiZ_uid84_fpSinCosXTest_b <= zPsinPiZ_uid84_fpSinCosXTest_in(56 downto 42);
--yT1_uid406_polyEvalsinPiZ(BITSELECT,405)@21
yT1_uid406_polyEvalsinPiZ_in <= zPsinPiZ_uid84_fpSinCosXTest_b;
yT1_uid406_polyEvalsinPiZ_b <= yT1_uid406_polyEvalsinPiZ_in(14 downto 2);
--ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg(DELAY,1540)
ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => yT1_uid406_polyEvalsinPiZ_b, xout => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a(DELAY,1219)@21
ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q, xout => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0(REG,596)@24
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q <= ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid502_pT1_uid407_polyEvalsinPiZ(MULT,501)@25
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a),14)) * SIGNED(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b);
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a <= (others => '0');
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b <= (others => '0');
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a <= reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b <= reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q <= prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ(BITSELECT,502)@28
prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in <= prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q;
prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in(25 downto 12);
--highBBits_uid409_polyEvalsinPiZ(BITSELECT,408)@28
highBBits_uid409_polyEvalsinPiZ_in <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b;
highBBits_uid409_polyEvalsinPiZ_b <= highBBits_uid409_polyEvalsinPiZ_in(13 downto 1);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a(DELAY,1221)@21
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => addr_uid81_fpSinCosXTest_b, xout => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0(REG,598)@24
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid396_tableGensinPiZ_lutmem(DUALMEM,528)@25
memoryC1_uid396_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC1_uid396_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC1_uid396_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q;
memoryC1_uid396_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC1_uid396_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid396_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid396_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid396_tableGensinPiZ_lutmem_iq,
address_a => memoryC1_uid396_tableGensinPiZ_lutmem_aa,
data_a => memoryC1_uid396_tableGensinPiZ_lutmem_ia
);
memoryC1_uid396_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC1_uid396_tableGensinPiZ_lutmem_q <= memoryC1_uid396_tableGensinPiZ_lutmem_iq(20 downto 0);
--reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0(REG,599)@27
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q <= memoryC1_uid396_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid410_polyEvalsinPiZ(ADD,409)@28
sumAHighB_uid410_polyEvalsinPiZ_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q(20)) & reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q);
sumAHighB_uid410_polyEvalsinPiZ_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid409_polyEvalsinPiZ_b(12)) & highBBits_uid409_polyEvalsinPiZ_b);
sumAHighB_uid410_polyEvalsinPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid410_polyEvalsinPiZ_a) + SIGNED(sumAHighB_uid410_polyEvalsinPiZ_b));
sumAHighB_uid410_polyEvalsinPiZ_q <= sumAHighB_uid410_polyEvalsinPiZ_o(21 downto 0);
--lowRangeB_uid408_polyEvalsinPiZ(BITSELECT,407)@28
lowRangeB_uid408_polyEvalsinPiZ_in <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b(0 downto 0);
lowRangeB_uid408_polyEvalsinPiZ_b <= lowRangeB_uid408_polyEvalsinPiZ_in(0 downto 0);
--s1_uid408_uid411_polyEvalsinPiZ(BITJOIN,410)@28
s1_uid408_uid411_polyEvalsinPiZ_q <= sumAHighB_uid410_polyEvalsinPiZ_q & lowRangeB_uid408_polyEvalsinPiZ_b;
--reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1(REG,601)@28
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q <= s1_uid408_uid411_polyEvalsinPiZ_q;
END IF;
END IF;
END PROCESS;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor(LOGICAL,1551)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q <= not (ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a or ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b);
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena(REG,1552)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q = "1") THEN
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd(LOGICAL,1553)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b <= en;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a and ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg(DELAY,1541)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => zPsinPiZ_uid84_fpSinCosXTest_b, xout => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem(DUALMEM,1542)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq,
address_a => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa,
data_a => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia
);
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0 <= areset;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq(14 downto 0);
--reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0(REG,600)@28
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid505_pT2_uid413_polyEvalsinPiZ(MULT,504)@29
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a),16)) * SIGNED(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b);
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a <= (others => '0');
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b <= (others => '0');
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a <= reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b <= reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q <= prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ(BITSELECT,505)@32
prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in <= prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q;
prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in(37 downto 14);
--highBBits_uid415_polyEvalsinPiZ(BITSELECT,414)@32
highBBits_uid415_polyEvalsinPiZ_in <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b;
highBBits_uid415_polyEvalsinPiZ_b <= highBBits_uid415_polyEvalsinPiZ_in(23 downto 2);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor(LOGICAL,1564)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q <= not (ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a or ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena(REG,1565)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q = "1") THEN
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd(LOGICAL,1566)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b <= en;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a and ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b;
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg(DELAY,1554)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addr_uid81_fpSinCosXTest_b, xout => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem(DUALMEM,1555)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq,
address_a => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa,
data_a => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia
);
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0(REG,602)@28
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid394_tableGensinPiZ_lutmem(DUALMEM,527)@29
memoryC0_uid394_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC0_uid394_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC0_uid394_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q;
memoryC0_uid394_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC0_uid394_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid394_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid394_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid394_tableGensinPiZ_lutmem_iq,
address_a => memoryC0_uid394_tableGensinPiZ_lutmem_aa,
data_a => memoryC0_uid394_tableGensinPiZ_lutmem_ia
);
memoryC0_uid394_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC0_uid394_tableGensinPiZ_lutmem_q <= memoryC0_uid394_tableGensinPiZ_lutmem_iq(29 downto 0);
--reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0(REG,603)@31
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q <= memoryC0_uid394_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid416_polyEvalsinPiZ(ADD,415)@32
sumAHighB_uid416_polyEvalsinPiZ_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q(29)) & reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q);
sumAHighB_uid416_polyEvalsinPiZ_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid415_polyEvalsinPiZ_b(21)) & highBBits_uid415_polyEvalsinPiZ_b);
sumAHighB_uid416_polyEvalsinPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid416_polyEvalsinPiZ_a) + SIGNED(sumAHighB_uid416_polyEvalsinPiZ_b));
sumAHighB_uid416_polyEvalsinPiZ_q <= sumAHighB_uid416_polyEvalsinPiZ_o(30 downto 0);
--lowRangeB_uid414_polyEvalsinPiZ(BITSELECT,413)@32
lowRangeB_uid414_polyEvalsinPiZ_in <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b(1 downto 0);
lowRangeB_uid414_polyEvalsinPiZ_b <= lowRangeB_uid414_polyEvalsinPiZ_in(1 downto 0);
--s2_uid414_uid417_polyEvalsinPiZ(BITJOIN,416)@32
s2_uid414_uid417_polyEvalsinPiZ_q <= sumAHighB_uid416_polyEvalsinPiZ_q & lowRangeB_uid414_polyEvalsinPiZ_b;
--polyEvalSigsinPiZ_uid86_fpSinCosXTest(BITSELECT,85)@32
polyEvalSigsinPiZ_uid86_fpSinCosXTest_in <= s2_uid414_uid417_polyEvalsinPiZ_q(30 downto 0);
polyEvalSigsinPiZ_uid86_fpSinCosXTest_b <= polyEvalSigsinPiZ_uid86_fpSinCosXTest_in(30 downto 5);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b(DELAY,708)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--multSinOp2_uid91_fpSinCosXTest(MUX,90)@32
multSinOp2_uid91_fpSinCosXTest_s <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q;
multSinOp2_uid91_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSinOp2_uid91_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE multSinOp2_uid91_fpSinCosXTest_s IS
WHEN "0" => multSinOp2_uid91_fpSinCosXTest_q <= polyEvalSigsinPiZ_uid86_fpSinCosXTest_b;
WHEN "1" => multSinOp2_uid91_fpSinCosXTest_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => multSinOp2_uid91_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor(LOGICAL,1320)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q <= not (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a or ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b);
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena(REG,1321)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd(LOGICAL,1322)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b <= en;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a and ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b;
--cPi_uid71_fpSinCosXTest(CONSTANT,70)
cPi_uid71_fpSinCosXTest_q <= "11001001000011111101101011";
--LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest(BITSELECT,309)@27
LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q(63 downto 0);
LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in(63 downto 0);
--leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest(BITJOIN,310)@27
leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b & GND_q;
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor(LOGICAL,1433)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q <= not (ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a or ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b);
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena(REG,1434)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q = "1") THEN
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd(LOGICAL,1435)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b <= en;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a and ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b;
--X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest(BITSELECT,280)@21
X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(32 downto 0);
X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b <= X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in(32 downto 0);
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg(DELAY,1425)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem(DUALMEM,1426)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 33,
widthad_a => 1,
numwords_a => 2,
width_b => 33,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia
);
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq(32 downto 0);
--leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest(BITJOIN,281)@25
leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor(LOGICAL,1444)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q <= not (ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a or ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b);
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena(REG,1445)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q = "1") THEN
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd(LOGICAL,1446)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b <= en;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a and ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg(DELAY,1436)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => zSin_uid60_fpSinCosXTest_q, xout => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem(DUALMEM,1437)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 65,
widthad_a => 1,
numwords_a => 2,
width_b => 65,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia
);
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq(64 downto 0);
--rVStage_uid237_lzcZSin_uid66_fpSinCosXTest(BITSELECT,236)@21
rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q;
rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in(64 downto 1);
--vCount_uid238_lzcZSin_uid66_fpSinCosXTest(LOGICAL,237)@21
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid236_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g(DELAY,903)@22
ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid240_lzcZSin_uid66_fpSinCosXTest(BITSELECT,239)@21
vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(0 downto 0);
vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in(0 downto 0);
--ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b(DELAY,861)@21
ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cStage_uid241_lzcZSin_uid66_fpSinCosXTest(BITJOIN,240)@22
cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q <= ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q & mO_uid239_lzcZSin_uid66_fpSinCosXTest_q;
--ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c(DELAY,863)@21
ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid243_lzcZSin_uid66_fpSinCosXTest(MUX,242)@22
vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid243_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s, en, ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q, cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid245_lzcZSin_uid66_fpSinCosXTest(BITSELECT,244)@22
rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in(63 downto 32);
--vCount_uid246_lzcZSin_uid66_fpSinCosXTest(LOGICAL,245)@22
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f(DELAY,902)@23
ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid247_lzcZSin_uid66_fpSinCosXTest(BITSELECT,246)@22
vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q(31 downto 0);
vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in(31 downto 0);
--ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d(DELAY,870)@22
ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c(DELAY,869)@22
ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid249_lzcZSin_uid66_fpSinCosXTest(MUX,248)@23
vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid249_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s, en, ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q, ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q)
BEGIN
CASE vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q;
WHEN OTHERS => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid251_lzcZSin_uid66_fpSinCosXTest(BITSELECT,250)@23
rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in(31 downto 16);
--vCount_uid252_lzcZSin_uid66_fpSinCosXTest(LOGICAL,251)@23
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b else "0";
--reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4(REG,585)@23
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q <= vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e(DELAY,901)@24
ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid253_lzcZSin_uid66_fpSinCosXTest(BITSELECT,252)@23
vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q(15 downto 0);
vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in(15 downto 0);
--vStagei_uid255_lzcZSin_uid66_fpSinCosXTest(MUX,254)@23
vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid255_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s, en, rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b, vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b;
WHEN "1" => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid257_lzcZSin_uid66_fpSinCosXTest(BITSELECT,256)@23
rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in(15 downto 8);
--reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1(REG,580)@23
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q <= rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid258_lzcZSin_uid66_fpSinCosXTest(LOGICAL,257)@24
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a <= reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q;
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b else "0";
--ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d(DELAY,900)@24
ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid259_lzcZSin_uid66_fpSinCosXTest(BITSELECT,258)@23
vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q(7 downto 0);
vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3(REG,582)@23
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q <= vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid261_lzcZSin_uid66_fpSinCosXTest(MUX,260)@24
vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid261_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s, en, reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q, reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid263_lzcZSin_uid66_fpSinCosXTest(BITSELECT,262)@24
rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in(7 downto 4);
--vCount_uid264_lzcZSin_uid66_fpSinCosXTest(LOGICAL,263)@24
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid265_lzcZSin_uid66_fpSinCosXTest(BITSELECT,264)@24
vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q(3 downto 0);
vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in(3 downto 0);
--reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3(REG,584)@24
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q <= vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2(REG,583)@24
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid267_lzcZSin_uid66_fpSinCosXTest(MUX,266)@25
vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid267_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s, en, reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q, reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid269_lzcZSin_uid66_fpSinCosXTest(BITSELECT,268)@25
rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in(3 downto 2);
--vCount_uid270_lzcZSin_uid66_fpSinCosXTest(LOGICAL,269)@25
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b else "0";
--vStage_uid271_lzcZSin_uid66_fpSinCosXTest(BITSELECT,270)@25
vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q(1 downto 0);
vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in(1 downto 0);
--vStagei_uid273_lzcZSin_uid66_fpSinCosXTest(MUX,272)@25
vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid273_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s, en, rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b, vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b;
WHEN "1" => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid275_lzcZSin_uid66_fpSinCosXTest(BITSELECT,274)@25
rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in(1 downto 1);
--vCount_uid276_lzcZSin_uid66_fpSinCosXTest(LOGICAL,275)@25
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b <= GND_q;
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b else "0";
--r_uid277_lzcZSin_uid66_fpSinCosXTest(BITJOIN,276)@25
r_uid277_lzcZSin_uid66_fpSinCosXTest_q <= ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q & ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q & ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q & ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q & vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q & vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q & vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q;
--leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest(BITSELECT,284)@25
leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q;
leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in(6 downto 5);
--leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest(MUX,285)@25
leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s <= leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b;
leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s, en, ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest(BITSELECT,293)@25
LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(40 downto 0);
LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in(40 downto 0);
--leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest(BITJOIN,294)@25
leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b & leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5(REG,590)@25
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest(BITSELECT,290)@25
LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(48 downto 0);
LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in(48 downto 0);
--leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest(BITJOIN,291)@25
leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4(REG,589)@25
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest(BITSELECT,287)@25
LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(56 downto 0);
LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in(56 downto 0);
--leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest(BITJOIN,288)@25
leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3(REG,588)@25
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2(REG,587)@25
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest(BITSELECT,295)@25
leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1(REG,586)@25
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q <= leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest(MUX,296)@26
leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s <= reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q;
leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s, en, reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest(BITSELECT,304)@26
LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(58 downto 0);
LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b(DELAY,927)@26
ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest(BITJOIN,305)@27
leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q;
--LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest(BITSELECT,301)@26
LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(60 downto 0);
LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b(DELAY,925)@26
ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest(BITJOIN,302)@27
leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest(BITSELECT,298)@26
LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(62 downto 0);
LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in(62 downto 0);
--ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b(DELAY,923)@26
ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest(BITJOIN,299)@27
leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2(REG,592)@26
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest(BITSELECT,306)@25
leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in(2 downto 1);
--ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a(DELAY,1214)@25
ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1(REG,591)@26
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q <= ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest(MUX,307)@27
leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s <= reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q;
leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s, en, reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest(BITSELECT,311)@25
leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b(DELAY,937)@25
ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest(MUX,312)@27
leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s <= ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q;
leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s, en, leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "0" => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "1" => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--pHigh_uid72_fpSinCosXTest(BITSELECT,71)@27
pHigh_uid72_fpSinCosXTest_in <= leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q;
pHigh_uid72_fpSinCosXTest_b <= pHigh_uid72_fpSinCosXTest_in(64 downto 39);
--reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2(REG,594)@27
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q <= pHigh_uid72_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a(DELAY,1216)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1(REG,593)@27
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--p_uid73_fpSinCosXTest(MUX,72)@28
p_uid73_fpSinCosXTest_s <= reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q;
p_uid73_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p_uid73_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE p_uid73_fpSinCosXTest_s IS
WHEN "0" => p_uid73_fpSinCosXTest_q <= reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q;
WHEN "1" => p_uid73_fpSinCosXTest_q <= cPi_uid71_fpSinCosXTest_q;
WHEN OTHERS => p_uid73_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg(DELAY,1312)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => p_uid73_fpSinCosXTest_q, xout => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem(DUALMEM,1313)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 1,
numwords_a => 2,
width_b => 26,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq,
address_a => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa,
data_a => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia
);
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0 <= areset;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq(25 downto 0);
--mulSin_uid92_fpSinCosXTest(MULT,91)@33
mulSin_uid92_fpSinCosXTest_pr <= UNSIGNED(mulSin_uid92_fpSinCosXTest_a) * UNSIGNED(mulSin_uid92_fpSinCosXTest_b);
mulSin_uid92_fpSinCosXTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulSin_uid92_fpSinCosXTest_a <= (others => '0');
mulSin_uid92_fpSinCosXTest_b <= (others => '0');
mulSin_uid92_fpSinCosXTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulSin_uid92_fpSinCosXTest_a <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q;
mulSin_uid92_fpSinCosXTest_b <= multSinOp2_uid91_fpSinCosXTest_q;
mulSin_uid92_fpSinCosXTest_s1 <= STD_LOGIC_VECTOR(mulSin_uid92_fpSinCosXTest_pr);
END IF;
END IF;
END PROCESS;
mulSin_uid92_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulSin_uid92_fpSinCosXTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulSin_uid92_fpSinCosXTest_q <= mulSin_uid92_fpSinCosXTest_s1;
END IF;
END IF;
END PROCESS;
--normBitSin_uid93_fpSinCosXTest(BITSELECT,92)@36
normBitSin_uid93_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q;
normBitSin_uid93_fpSinCosXTest_b <= normBitSin_uid93_fpSinCosXTest_in(51 downto 51);
--join_uid99_fpSinCosXTest(BITJOIN,98)@36
join_uid99_fpSinCosXTest_q <= reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q & normBitSin_uid93_fpSinCosXTest_b;
--sinRndOp_uid100_uid101_fpSinCosXTest(BITJOIN,100)@36
sinRndOp_uid100_uid101_fpSinCosXTest_q <= join_uid99_fpSinCosXTest_q & cstAllZWF_uid7_fpSinCosXTest_q & VCC_q;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor(LOGICAL,1333)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q <= not (ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a or ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b);
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena(REG,1334)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q = "1") THEN
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd(LOGICAL,1335)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b <= en;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a and ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor(LOGICAL,1283)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q <= not (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a or ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b);
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena(REG,1284)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd(LOGICAL,1285)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a and ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg(DELAY,1273)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expXRR_uid38_fpSinCosXTest_b, xout => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem(DUALMEM,1274)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 9,
width_b => 8,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia
);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1(REG,604)@25
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--expSinHC_uid74_fpSinCosXTest(SUB,73)@26
expSinHC_uid74_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expSinHC_uid74_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q);
expSinHC_uid74_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSinHC_uid74_fpSinCosXTest_a) - UNSIGNED(expSinHC_uid74_fpSinCosXTest_b));
expSinHC_uid74_fpSinCosXTest_q <= expSinHC_uid74_fpSinCosXTest_o(8 downto 0);
--expSinHCR_uid75_fpSinCosXTest(BITSELECT,74)@26
expSinHCR_uid75_fpSinCosXTest_in <= expSinHC_uid74_fpSinCosXTest_q(7 downto 0);
expSinHCR_uid75_fpSinCosXTest_b <= expSinHCR_uid75_fpSinCosXTest_in(7 downto 0);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b(DELAY,695)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expPSin_uid76_fpSinCosXTest(MUX,75)@26
expPSin_uid76_fpSinCosXTest_s <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q;
expPSin_uid76_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expPSin_uid76_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expPSin_uid76_fpSinCosXTest_s IS
WHEN "0" => expPSin_uid76_fpSinCosXTest_q <= expSinHCR_uid75_fpSinCosXTest_b;
WHEN "1" => expPSin_uid76_fpSinCosXTest_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => expPSin_uid76_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg(DELAY,1323)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expPSin_uid76_fpSinCosXTest_q, xout => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem(DUALMEM,1324)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 7,
width_b => 8,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia
);
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq(7 downto 0);
--fracRSinPreRndHigh_uid95_fpSinCosXTest(BITSELECT,94)@36
fracRSinPreRndHigh_uid95_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q(50 downto 0);
fracRSinPreRndHigh_uid95_fpSinCosXTest_b <= fracRSinPreRndHigh_uid95_fpSinCosXTest_in(50 downto 27);
--fracRSinPreRndLow_uid96_fpSinCosXTest(BITSELECT,95)@36
fracRSinPreRndLow_uid96_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q(49 downto 0);
fracRSinPreRndLow_uid96_fpSinCosXTest_b <= fracRSinPreRndLow_uid96_fpSinCosXTest_in(49 downto 26);
--fracRSinPreRnd_uid97_fpSinCosXTest(MUX,96)@36
fracRSinPreRnd_uid97_fpSinCosXTest_s <= normBitSin_uid93_fpSinCosXTest_b;
fracRSinPreRnd_uid97_fpSinCosXTest: PROCESS (fracRSinPreRnd_uid97_fpSinCosXTest_s, en, fracRSinPreRndLow_uid96_fpSinCosXTest_b, fracRSinPreRndHigh_uid95_fpSinCosXTest_b)
BEGIN
CASE fracRSinPreRnd_uid97_fpSinCosXTest_s IS
WHEN "0" => fracRSinPreRnd_uid97_fpSinCosXTest_q <= fracRSinPreRndLow_uid96_fpSinCosXTest_b;
WHEN "1" => fracRSinPreRnd_uid97_fpSinCosXTest_q <= fracRSinPreRndHigh_uid95_fpSinCosXTest_b;
WHEN OTHERS => fracRSinPreRnd_uid97_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracRSinPreRnd_uid98_uid98_fpSinCosXTest(BITJOIN,97)@36
expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q & fracRSinPreRnd_uid97_fpSinCosXTest_q;
--expFracRSin_uid102_fpSinCosXTest(ADD,101)@36
expFracRSin_uid102_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q);
expFracRSin_uid102_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0000000" & sinRndOp_uid100_uid101_fpSinCosXTest_q);
expFracRSin_uid102_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRSin_uid102_fpSinCosXTest_a) + UNSIGNED(expFracRSin_uid102_fpSinCosXTest_b));
expFracRSin_uid102_fpSinCosXTest_q <= expFracRSin_uid102_fpSinCosXTest_o(32 downto 0);
--expRCompSin_uid104_fpSinCosXTest(BITSELECT,103)@36
expRCompSin_uid104_fpSinCosXTest_in <= expFracRSin_uid102_fpSinCosXTest_q(31 downto 0);
expRCompSin_uid104_fpSinCosXTest_b <= expRCompSin_uid104_fpSinCosXTest_in(31 downto 24);
--reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2(REG,607)@36
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q <= expRCompSin_uid104_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor(LOGICAL,1537)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q <= not (ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a or ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b);
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena(REG,1538)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q = "1") THEN
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd(LOGICAL,1539)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b <= en;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a and ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b;
--expXIsZero_uid10_fpSinCosXTest(LOGICAL,9)@0
expXIsZero_uid10_fpSinCosXTest_a <= exp_uid9_fpSinCosXTest_b;
expXIsZero_uid10_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
expXIsZero_uid10_fpSinCosXTest_q <= "1" when expXIsZero_uid10_fpSinCosXTest_a = expXIsZero_uid10_fpSinCosXTest_b else "0";
--ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b(DELAY,746)@0
ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => expXIsZero_uid10_fpSinCosXTest_q, xout => ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excSelBitsSin_uid118_fpSinCosXTest(BITJOIN,117)@19
excSelBitsSin_uid118_fpSinCosXTest_q <= excRNaN_uid117_fpSinCosXTest_q & ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q & ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg(DELAY,1527)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => excSelBitsSin_uid118_fpSinCosXTest_q, xout => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem(DUALMEM,1528)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 4,
numwords_a => 14,
width_b => 3,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq,
address_a => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa,
data_a => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia
);
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0 <= areset;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq(2 downto 0);
--reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0(REG,533)@35
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--excSelSin_uid119_fpSinCosXTest(LOOKUP,118)@36
excSelSin_uid119_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excSelSin_uid119_fpSinCosXTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q) IS
WHEN "000" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN "001" => excSelSin_uid119_fpSinCosXTest_q <= "01";
WHEN "010" => excSelSin_uid119_fpSinCosXTest_q <= "10";
WHEN "011" => excSelSin_uid119_fpSinCosXTest_q <= "10";
WHEN "100" => excSelSin_uid119_fpSinCosXTest_q <= "11";
WHEN "101" => excSelSin_uid119_fpSinCosXTest_q <= "11";
WHEN "110" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN "111" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN OTHERS =>
excSelSin_uid119_fpSinCosXTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRPostExcSin_uid126_fpSinCosXTest(MUX,125)@37
expRPostExcSin_uid126_fpSinCosXTest_s <= excSelSin_uid119_fpSinCosXTest_q;
expRPostExcSin_uid126_fpSinCosXTest: PROCESS (expRPostExcSin_uid126_fpSinCosXTest_s, en, reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q, ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q, cstAllZWE_uid8_fpSinCosXTest_q, cstAllOWE_uid6_fpSinCosXTest_q)
BEGIN
CASE expRPostExcSin_uid126_fpSinCosXTest_s IS
WHEN "00" => expRPostExcSin_uid126_fpSinCosXTest_q <= reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q;
WHEN "01" => expRPostExcSin_uid126_fpSinCosXTest_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q;
WHEN "10" => expRPostExcSin_uid126_fpSinCosXTest_q <= cstAllZWE_uid8_fpSinCosXTest_q;
WHEN "11" => expRPostExcSin_uid126_fpSinCosXTest_q <= cstAllOWE_uid6_fpSinCosXTest_q;
WHEN OTHERS => expRPostExcSin_uid126_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor(LOGICAL,1346)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q <= not (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a or ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b);
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena(REG,1347)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd(LOGICAL,1348)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b <= en;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a and ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg(DELAY,1336)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => frac_uid13_fpSinCosXTest_b, xout => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem(DUALMEM,1337)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 6,
numwords_a => 35,
width_b => 23,
widthad_b => 6,
numwords_b => 35,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia
);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq(22 downto 0);
--fracRCompSin_uid103_fpSinCosXTest(BITSELECT,102)@36
fracRCompSin_uid103_fpSinCosXTest_in <= expFracRSin_uid102_fpSinCosXTest_q(23 downto 0);
fracRCompSin_uid103_fpSinCosXTest_b <= fracRCompSin_uid103_fpSinCosXTest_in(23 downto 1);
--reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2(REG,606)@36
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q <= fracRCompSin_uid103_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--fracRPostExcSin_uid122_fpSinCosXTest(MUX,121)@37
fracRPostExcSin_uid122_fpSinCosXTest_s <= excSelSin_uid119_fpSinCosXTest_q;
fracRPostExcSin_uid122_fpSinCosXTest: PROCESS (fracRPostExcSin_uid122_fpSinCosXTest_s, en, reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q, cstAllZWF_uid7_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q)
BEGIN
CASE fracRPostExcSin_uid122_fpSinCosXTest_s IS
WHEN "00" => fracRPostExcSin_uid122_fpSinCosXTest_q <= reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q;
WHEN "01" => fracRPostExcSin_uid122_fpSinCosXTest_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q;
WHEN "10" => fracRPostExcSin_uid122_fpSinCosXTest_q <= cstAllZWF_uid7_fpSinCosXTest_q;
WHEN "11" => fracRPostExcSin_uid122_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN OTHERS => fracRPostExcSin_uid122_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpSin_uid134_fpSinCosXTest(BITJOIN,133)@37
fpSin_uid134_fpSinCosXTest_q <= ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q & expRPostExcSin_uid126_fpSinCosXTest_q & fracRPostExcSin_uid122_fpSinCosXTest_q;
--xOut(GPOUT,4)@37
s <= fpSin_uid134_fpSinCosXTest_q;
c <= fpCos_uid162_fpSinCosXTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_sincos_s5
-- VHDL created on Wed Mar 27 09:55:14 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_sincos_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
s : out std_logic_vector(31 downto 0);
c : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_sincos_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid8_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid22_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid23_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShift_uid24_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid25_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid26_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstZwShiftP1_uid27_fpSinCosXTest_q : std_logic_vector (13 downto 0);
signal cstNaNwF_uid32_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal cstZmwFRRPwSM1_uid52_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal cPi_uid71_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal p_uid73_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal p_uid73_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal expPSin_uid76_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal expPSin_uid76_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal multSinOp2_uid91_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal multSinOp2_uid91_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_a : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_s1 : std_logic_vector (51 downto 0);
signal mulSin_uid92_fpSinCosXTest_pr : UNSIGNED (51 downto 0);
signal mulSin_uid92_fpSinCosXTest_q : std_logic_vector (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_a : std_logic_vector (25 downto 0);
signal mulCos_uid105_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal mulCos_uid105_fpSinCosXTest_s1 : std_logic_vector (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_pr : UNSIGNED (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_q : std_logic_vector (51 downto 0);
signal excSelSin_uid119_fpSinCosXTest_q : std_logic_vector(1 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expSelectorCos_uid145_fpSinCosXTest_q : std_logic_vector(1 downto 0);
signal signRCond2_uid152_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_d : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_d : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q : std_logic_vector (29 downto 0);
signal leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal zs_uid236_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal mO_uid239_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (62 downto 0);
signal zs_uid244_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal zs_uid250_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (5 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(63 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(63 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (47 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a : std_logic_vector (12 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr : SIGNED (26 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q : std_logic_vector (25 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a : std_logic_vector (14 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b : std_logic_vector (22 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr : SIGNED (38 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q : std_logic_vector (37 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a : std_logic_vector (12 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr : SIGNED (26 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q : std_logic_vector (25 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a : std_logic_vector (14 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b : std_logic_vector (22 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr : SIGNED (38 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q : std_logic_vector (37 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0 : std_logic;
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0 : std_logic;
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q : std_logic_vector (39 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a : std_logic_vector(81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b : std_logic_vector(81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o : std_logic_vector (81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q : std_logic_vector (81 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC0_uid394_tableGensinPiZ_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC1_uid396_tableGensinPiZ_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC2_uid398_tableGensinPiZ_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_q : std_logic_vector (12 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC0_uid400_tableGencosPiZ_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC1_uid402_tableGencosPiZ_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC2_uid404_tableGencosPiZ_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_q : std_logic_vector (12 downto 0);
signal reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q : std_logic_vector (2 downto 0);
signal reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q : std_logic_vector (39 downto 0);
signal reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (39 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q : std_logic_vector (26 downto 0);
signal reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (77 downto 0);
signal reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q : std_logic_vector (67 downto 0);
signal reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q : std_logic_vector (66 downto 0);
signal reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q : std_logic_vector (65 downto 0);
signal reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q : std_logic_vector (67 downto 0);
signal reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q : std_logic_vector (25 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q : std_logic_vector (12 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q : std_logic_vector (20 downto 0);
signal reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q : std_logic_vector (22 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q : std_logic_vector (29 downto 0);
signal reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q : std_logic_vector (6 downto 0);
signal reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q : std_logic_vector (22 downto 0);
signal reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q : std_logic_vector (0 downto 0);
signal reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q : std_logic_vector (12 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q : std_logic_vector (20 downto 0);
signal reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q : std_logic_vector (22 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q : std_logic_vector (29 downto 0);
signal reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q : std_logic_vector (25 downto 0);
signal reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q : std_logic_vector (25 downto 0);
signal reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q : std_logic_vector (6 downto 0);
signal reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q : std_logic_vector (22 downto 0);
signal reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q : std_logic_vector (3 downto 0);
signal reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q : std_logic_vector (52 downto 0);
signal ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q : std_logic_vector (65 downto 0);
signal ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q : std_logic_vector (67 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (7 downto 0);
signal ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (66 downto 0);
signal ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (65 downto 0);
signal ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (64 downto 0);
signal ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q : std_logic_vector (63 downto 0);
signal ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q : std_logic_vector (31 downto 0);
signal ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (58 downto 0);
signal ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q : std_logic_vector (63 downto 0);
signal ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q : std_logic_vector (31 downto 0);
signal ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (58 downto 0);
signal ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (76 downto 0);
signal ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (75 downto 0);
signal ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (74 downto 0);
signal ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q : std_logic_vector (12 downto 0);
signal ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q : std_logic_vector (53 downto 0);
signal ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q : std_logic_vector (12 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0 : std_logic;
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q : signal is true;
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q : std_logic_vector (6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0 : std_logic;
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q : signal is true;
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q : signal is true;
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0 : std_logic;
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0 : std_logic;
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0 : std_logic;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq : std_logic;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q : signal is true;
signal sinXIsXRR_uid41_fpSinCosXTest_a : std_logic_vector(11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_b : std_logic_vector(11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_o : std_logic_vector (11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_a : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_b : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_o : std_logic_vector (11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal yIsZero_uid51_fpSinCosXTest_a : std_logic_vector(65 downto 0);
signal yIsZero_uid51_fpSinCosXTest_b : std_logic_vector(65 downto 0);
signal yIsZero_uid51_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal pad_one_uid55_fpSinCosXTest_q : std_logic_vector (66 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_a : std_logic_vector(70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_b : std_logic_vector(70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_o : std_logic_vector (70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_c : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal InvCmpYToOneMinusY_uid61_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCmpYToOneMinusY_uid61_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid127_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid127_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvSinXIsXRR_uid128_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsXRR_uid128_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid131_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid131_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid132_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid132_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid136_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid136_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvCosXONe_uid149_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCosXONe_uid149_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid151_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid151_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvIntXParity_uid155_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvIntXParity_uid155_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal oFracXRR_uid43_uid43_fpSinCosXTest_q : std_logic_vector (53 downto 0);
signal half_uid53_fpSinCosXTest_q : std_logic_vector (65 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal exp_uid9_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal exp_uid9_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal frac_uid13_fpSinCosXTest_in : std_logic_vector (22 downto 0);
signal frac_uid13_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal signX_uid37_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal signX_uid37_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal expFracX_uid166_px_uid33_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal expFracX_uid166_px_uid33_fpSinCosXTest_b : std_logic_vector (30 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_q : std_logic_vector (9 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_a : std_logic_vector(65 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_b : std_logic_vector(65 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_a : std_logic_vector(67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_b : std_logic_vector(67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_o : std_logic_vector (67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal zSin_uid60_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal zSin_uid60_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal zCos_uid64_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal zCos_uid64_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal expSinHC_uid74_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal excRNaN_uid117_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid117_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid117_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracRPostExcSin_uid122_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExcSin_uid122_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal expRPostExcSin_uid126_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExcSin_uid126_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracRPostExcCos_uid142_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExcCos_uid142_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal expRPostExcCos_uid147_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExcCos_uid147_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cosXONe_uid148_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal cosXONe_uid148_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal cosXONe_uid148_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal finalExp_uid209_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal finalExp_uid209_rrx_uid34_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal extendedFracX_uid47_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal normBitSin_uid93_fpSinCosXTest_in : std_logic_vector (51 downto 0);
signal normBitSin_uid93_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal fracRSinPreRndHigh_uid95_fpSinCosXTest_in : std_logic_vector (50 downto 0);
signal fracRSinPreRndHigh_uid95_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracRSinPreRndLow_uid96_fpSinCosXTest_in : std_logic_vector (49 downto 0);
signal fracRSinPreRndLow_uid96_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal normBitCos_uid106_fpSinCosXTest_in : std_logic_vector (51 downto 0);
signal normBitCos_uid106_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal fracRCosPreRndHigh_uid108_fpSinCosXTest_in : std_logic_vector (50 downto 0);
signal fracRCosPreRndHigh_uid108_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracRCosPreRndLow_uid109_fpSinCosXTest_in : std_logic_vector (49 downto 0);
signal fracRCosPreRndLow_uid109_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q : std_logic_vector (52 downto 0);
signal leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b : std_logic_vector (23 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int : std_logic_vector (80 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q : std_logic_vector (80 downto 0);
signal os_uid196_rrx_uid34_fpSinCosXTest_q : std_logic_vector (79 downto 0);
signal leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal join_uid99_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal join_uid141_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal zSinYBottom_uid59_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal zSinYBottom_uid59_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal zSinOMyBottom_uid58_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal zSinOMyBottom_uid58_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal excSelBitsSin_uid118_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal fpSin_uid134_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal join_uid143_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal fpCos_uid162_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int : std_logic_vector (107 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q : std_logic_vector (107 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal fracX_uid187_rrx_uid34_fpSinCosXTest_in : std_logic_vector (22 downto 0);
signal fracX_uid187_rrx_uid34_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal oFracXRRSmallXRR_uid90_fpSinCosXTest_in : std_logic_vector (53 downto 0);
signal oFracXRRSmallXRR_uid90_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal R_uid167_px_uid33_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal InvFracXIsZero_uid16_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid16_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fxpXShiftVal_uid46_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal fxpXShiftVal_uid46_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal addr_uid81_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal addr_uid81_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal zPsinPiZ_uid84_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal zPsinPiZ_uid84_fpSinCosXTest_b : std_logic_vector (14 downto 0);
signal rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (32 downto 0);
signal addr_uid83_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal addr_uid83_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal zPcosPiZ_uid87_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal zPcosPiZ_uid87_fpSinCosXTest_b : std_logic_vector (14 downto 0);
signal rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (32 downto 0);
signal expSinHCR_uid75_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expSinHCR_uid75_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal expPCos_uid79_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expPCos_uid79_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (66 downto 0);
signal LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (66 downto 0);
signal LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (65 downto 0);
signal LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (58 downto 0);
signal rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (58 downto 0);
signal rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (76 downto 0);
signal LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (76 downto 0);
signal LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (75 downto 0);
signal LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (75 downto 0);
signal LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (74 downto 0);
signal LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (74 downto 0);
signal X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (59 downto 0);
signal X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (59 downto 0);
signal X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (55 downto 0);
signal X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (55 downto 0);
signal fracRSinPreRnd_uid97_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal fracRSinPreRnd_uid97_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal fracRCosPreRnd_uid110_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal fracRCosPreRnd_uid110_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal cosRndOp_uid112_uid113_fpSinCosXTest_q : std_logic_vector (24 downto 0);
signal rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal lowRangeB_uid408_polyEvalsinPiZ_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid408_polyEvalsinPiZ_b : std_logic_vector (0 downto 0);
signal highBBits_uid409_polyEvalsinPiZ_in : std_logic_vector (13 downto 0);
signal highBBits_uid409_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid414_polyEvalsinPiZ_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid414_polyEvalsinPiZ_b : std_logic_vector (1 downto 0);
signal highBBits_uid415_polyEvalsinPiZ_in : std_logic_vector (23 downto 0);
signal highBBits_uid415_polyEvalsinPiZ_b : std_logic_vector (21 downto 0);
signal lowRangeB_uid421_polyEvalcosPiZ_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid421_polyEvalcosPiZ_b : std_logic_vector (0 downto 0);
signal highBBits_uid422_polyEvalcosPiZ_in : std_logic_vector (13 downto 0);
signal highBBits_uid422_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid427_polyEvalcosPiZ_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid427_polyEvalcosPiZ_b : std_logic_vector (1 downto 0);
signal highBBits_uid428_polyEvalcosPiZ_in : std_logic_vector (23 downto 0);
signal highBBits_uid428_polyEvalcosPiZ_b : std_logic_vector (21 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in : std_logic_vector (80 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b : std_logic_vector (26 downto 0);
signal fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in : std_logic_vector (76 downto 0);
signal fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b : std_logic_vector (52 downto 0);
signal intXParity_uid49_fpSinCosXTest_in : std_logic_vector (67 downto 0);
signal intXParity_uid49_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal y_uid50_fpSinCosXTest_in : std_logic_vector (66 downto 0);
signal y_uid50_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal sinRndOp_uid100_uid101_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal expSelBitsCos_uid144_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a : std_logic_vector(108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b : std_logic_vector(108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o : std_logic_vector (108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q : std_logic_vector (108 downto 0);
signal oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal expX_uid186_rrx_uid34_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal expX_uid186_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal exc_N_uid17_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal yT1_uid406_polyEvalsinPiZ_in : std_logic_vector (14 downto 0);
signal yT1_uid406_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal yT1_uid419_polyEvalcosPiZ_in : std_logic_vector (14 downto 0);
signal yT1_uid419_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_a : std_logic_vector(32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_b : std_logic_vector(32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_o : std_logic_vector (32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_q : std_logic_vector (30 downto 0);
signal finalFrac_uid208_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal finalFrac_uid208_rrx_uid34_fpSinCosXTest_q : std_logic_vector (52 downto 0);
signal signComp_uid129_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_a : std_logic_vector(32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_b : std_logic_vector(32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_o : std_logic_vector (32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_q : std_logic_vector (32 downto 0);
signal leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal multFracBits_uid199_rrx_uid34_fpSinCosXTest_in : std_logic_vector (77 downto 0);
signal multFracBits_uid199_rrx_uid34_fpSinCosXTest_b : std_logic_vector (77 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b : std_logic_vector (26 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (5 downto 0);
signal fracRCompCos_uid115_fpSinCosXTest_in : std_logic_vector (23 downto 0);
signal fracRCompCos_uid115_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal expRCompSin_uid116_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal expRCompSin_uid116_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal s1_uid408_uid411_polyEvalsinPiZ_q : std_logic_vector (22 downto 0);
signal s2_uid414_uid417_polyEvalsinPiZ_q : std_logic_vector (32 downto 0);
signal s1_uid421_uid424_polyEvalcosPiZ_q : std_logic_vector (22 downto 0);
signal s2_uid427_uid430_polyEvalcosPiZ_q : std_logic_vector (32 downto 0);
signal RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q : std_logic_vector (61 downto 0);
signal signR_uid130_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signR_uid130_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signR_uid130_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal fracRCompSin_uid103_fpSinCosXTest_in : std_logic_vector (23 downto 0);
signal fracRCompSin_uid103_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal expRCompSin_uid104_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal expRCompSin_uid104_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in : std_logic_vector (77 downto 0);
signal multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (61 downto 0);
signal X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (61 downto 0);
signal X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (45 downto 0);
signal X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (45 downto 0);
signal X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (29 downto 0);
signal X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (29 downto 0);
signal expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal polyEvalSigsinPiZ_uid86_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal polyEvalSigsinPiZ_uid86_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal polyEvalSigcosPiZ_uid89_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal polyEvalSigcosPiZ_uid89_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal expXRR_uid38_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal expXRR_uid38_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal fracXRR_uid39_fpSinCosXTest_in : std_logic_vector (52 downto 0);
signal fracXRR_uid39_fpSinCosXTest_b : std_logic_vector (52 downto 0);
signal pHigh_uid72_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal pHigh_uid72_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal pCos_uid77_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal pCos_uid77_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal r_uid277_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (6 downto 0);
signal r_uid356_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (6 downto 0);
signal expCompOut_uid205_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expCompOut_uid205_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (73 downto 0);
signal LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (73 downto 0);
signal LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (69 downto 0);
signal LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (69 downto 0);
signal LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (65 downto 0);
signal LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (56 downto 0);
signal LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (48 downto 0);
signal LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (48 downto 0);
signal LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (40 downto 0);
signal LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (40 downto 0);
signal LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (56 downto 0);
signal LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (48 downto 0);
signal LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (48 downto 0);
signal LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (40 downto 0);
signal LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (40 downto 0);
signal leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
begin
--xIn(GPIN,3)@0
--GND(CONSTANT,0)
GND_q <= "0";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable(LOGICAL,1282)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q <= not ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor(LOGICAL,1422)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q <= not (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a or ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b);
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top(CONSTANT,1418)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q <= "01011";
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp(LOGICAL,1419)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q <= "1" when ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a = ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b else "0";
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg(REG,1420)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena(REG,1423)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd(LOGICAL,1424)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b <= en;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a and ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b;
--expFracX_uid166_px_uid33_fpSinCosXTest(BITSELECT,165)@0
expFracX_uid166_px_uid33_fpSinCosXTest_in <= a(30 downto 0);
expFracX_uid166_px_uid33_fpSinCosXTest_b <= expFracX_uid166_px_uid33_fpSinCosXTest_in(30 downto 0);
--R_uid167_px_uid33_fpSinCosXTest(BITJOIN,166)@0
R_uid167_px_uid33_fpSinCosXTest_q <= GND_q & expFracX_uid166_px_uid33_fpSinCosXTest_b;
--expX_uid186_rrx_uid34_fpSinCosXTest(BITSELECT,185)@0
expX_uid186_rrx_uid34_fpSinCosXTest_in <= R_uid167_px_uid33_fpSinCosXTest_q(30 downto 0);
expX_uid186_rrx_uid34_fpSinCosXTest_b <= expX_uid186_rrx_uid34_fpSinCosXTest_in(30 downto 23);
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg(DELAY,1412)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid186_rrx_uid34_fpSinCosXTest_b, xout => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt(COUNTER,1414)
-- every=1, low=0, high=11, step=1, init=1
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i = 10 THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i - 11;
ELSE
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg(REG,1415)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux(MUX,1416)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem(DUALMEM,1413)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 12,
width_b => 8,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia
);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--zs_uid244_lzcZSin_uid66_fpSinCosXTest(CONSTANT,243)
zs_uid244_lzcZSin_uid66_fpSinCosXTest_q <= "00000000000000000000000000000000";
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor(LOGICAL,1396)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q <= not (ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a or ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b);
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg(REG,1318)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena(REG,1397)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q = "1") THEN
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd(LOGICAL,1398)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b <= en;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a and ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg(DELAY,1388)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid167_px_uid33_fpSinCosXTest_q, xout => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt(COUNTER,1314)
-- every=1, low=0, high=1, step=1, init=1
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i,1));
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg(REG,1315)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux(MUX,1316)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s <= en;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux: PROCESS (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s, ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q, ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q)
BEGIN
CASE ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s IS
WHEN "0" => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
WHEN "1" => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem(DUALMEM,1389)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 1,
numwords_a => 2,
width_b => 32,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq,
address_a => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa,
data_a => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia
);
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0 <= areset;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq(31 downto 0);
--fracX_uid187_rrx_uid34_fpSinCosXTest(BITSELECT,186)@4
fracX_uid187_rrx_uid34_fpSinCosXTest_in <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q(22 downto 0);
fracX_uid187_rrx_uid34_fpSinCosXTest_b <= fracX_uid187_rrx_uid34_fpSinCosXTest_in(22 downto 0);
--oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest(BITJOIN,196)@4
oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q <= VCC_q & fracX_uid187_rrx_uid34_fpSinCosXTest_b;
--prod_uid198_rrx_uid34_fpSinCosXTest_b_0(BITSELECT,518)@4
prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in <= STD_LOGIC_VECTOR("000" & oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q);
prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b <= prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in(26 downto 0);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1(REG,539)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q <= prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShift_uid24_fpSinCosXTest(CONSTANT,23)
cstBiasMwShift_uid24_fpSinCosXTest_q <= "01110011";
--expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest(SUB,191)@0
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expX_uid186_rrx_uid34_fpSinCosXTest_b);
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0" & cstBiasMwShift_uid24_fpSinCosXTest_q);
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b));
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q <= expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o(8 downto 0);
--expXTableAddr_uid193_rrx_uid34_fpSinCosXTest(BITSELECT,192)@0
expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in <= expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q(7 downto 0);
expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b <= expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0(REG,534)@0
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q <= expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem(DUALMEM,514)@1
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia <= (others => '0');
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa <= (others => '0');
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab <= reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q;
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq,
address_a => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa,
data_a => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia
);
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0 <= areset;
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q <= rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1(REG,537)@3
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q <= rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem(DUALMEM,513)@1
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia <= (others => '0');
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa <= (others => '0');
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab <= reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q;
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq,
address_a => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa,
data_a => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia
);
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0 <= areset;
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q <= rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0(REG,536)@3
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q <= rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid196_rrx_uid34_fpSinCosXTest(BITJOIN,195)@4
os_uid196_rrx_uid34_fpSinCosXTest_q <= reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q & reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q;
--prod_uid198_rrx_uid34_fpSinCosXTest_a_2(BITSELECT,517)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in <= STD_LOGIC_VECTOR("0" & os_uid196_rrx_uid34_fpSinCosXTest_q);
prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in(80 downto 54);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0(REG,542)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0(MULT,521)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1;
END IF;
END IF;
END PROCESS;
--ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a(DELAY,1145)@8
ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a : dspba_delay
GENERIC MAP ( width => 54, depth => 1 )
PORT MAP ( xin => prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q, xout => ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--prod_uid198_rrx_uid34_fpSinCosXTest_align_2(BITSHIFT,524)@9
prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int <= ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int(107 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_a_1(BITSELECT,516)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in <= os_uid196_rrx_uid34_fpSinCosXTest_q(53 downto 0);
prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in(53 downto 27);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0(REG,540)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0(MULT,520)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_align_1(BITSHIFT,523)@8
prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int <= prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q & "000000000000000000000000000";
prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int(80 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_a_0(BITSELECT,515)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in <= os_uid196_rrx_uid34_fpSinCosXTest_q(26 downto 0);
prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in(26 downto 0);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0(REG,538)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0(MULT,519)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_align_0(BITSHIFT,522)@8
prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int <= prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int(53 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0(ADD,525)@8
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a <= STD_LOGIC_VECTOR("0000000000000000000000000000" & prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b <= STD_LOGIC_VECTOR("0" & prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a) + UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b));
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o(81 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0(ADD,526)@9
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a <= STD_LOGIC_VECTOR("000000000000000000000000000" & prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b <= STD_LOGIC_VECTOR("0" & prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a) + UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b));
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o(108 downto 0);
--multFracBits_uid199_rrx_uid34_fpSinCosXTest(BITSELECT,198)@9
multFracBits_uid199_rrx_uid34_fpSinCosXTest_in <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q(77 downto 0);
multFracBits_uid199_rrx_uid34_fpSinCosXTest_b <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_in(77 downto 0);
--multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest(BITSELECT,199)@9
multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b;
multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b <= multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in(77 downto 46);
--reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1(REG,544)@9
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,433)@10
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a(DELAY,1178)@10
ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xout => ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5(REG,555)@12
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q <= ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q;
END IF;
END IF;
END PROCESS;
--zs_uid250_lzcZSin_uid66_fpSinCosXTest(CONSTANT,249)
zs_uid250_lzcZSin_uid66_fpSinCosXTest_q <= "0000000000000000";
--mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest(CONSTANT,434)
mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "11111111111111111111111111111111";
--vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,436)@10
vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q, mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,438)@10
rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in(31 downto 16);
--reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1(REG,546)@10
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,439)@11
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4(REG,554)@11
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q <= vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e(DELAY,1081)@12
ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWE_uid8_fpSinCosXTest(CONSTANT,7)
cstAllZWE_uid8_fpSinCosXTest_q <= "00000000";
--vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,440)@10
vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q(15 downto 0);
vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in(15 downto 0);
--reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,548)@10
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,442)@11
vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q, reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,444)@11
rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in(15 downto 8);
--vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,445)@11
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i <= "1" when vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xin => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d(DELAY,1080)@12
ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xout => ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest(CONSTANT,212)
leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q <= "0000";
--vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,446)@11
vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q(7 downto 0);
vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,550)@11
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,549)@11
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,448)@12
vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q, reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,450)@12
rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in(7 downto 4);
--vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,451)@12
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,553)@12
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest(CONSTANT,226)
leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q <= "00";
--vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,452)@12
vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q(3 downto 0);
vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in(3 downto 0);
--vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,454)@12
vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b, vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
WHEN "1" => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,456)@12
rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in(3 downto 2);
--vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,457)@12
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i <= "1" when vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xin => vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,458)@12
vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q(1 downto 0);
vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in(1 downto 0);
--reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,552)@12
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,551)@12
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,460)@13
vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q, reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,462)@13
rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in(1 downto 1);
--vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,463)@13
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= GND_q;
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest(BITJOIN,464)@13
r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q & ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q & ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q & reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q & vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q & vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
--cstBiasM1_uid23_fpSinCosXTest(CONSTANT,22)
cstBiasM1_uid23_fpSinCosXTest_q <= "01111110";
--expCompOutExt_uid204_rrx_uid34_fpSinCosXTest(SUB,203)@13
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("000" & r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q);
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b));
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q <= expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o(8 downto 0);
--expCompOut_uid205_rrx_uid34_fpSinCosXTest(BITSELECT,204)@13
expCompOut_uid205_rrx_uid34_fpSinCosXTest_in <= expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q(7 downto 0);
expCompOut_uid205_rrx_uid34_fpSinCosXTest_b <= expCompOut_uid205_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2(REG,564)@13
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q <= expCompOut_uid205_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--xBranch_uid191_rrx_uid34_fpSinCosXTest(COMPARE,190)@0
xBranch_uid191_rrx_uid34_fpSinCosXTest_cin <= GND_q;
xBranch_uid191_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid24_fpSinCosXTest_q) & '0';
xBranch_uid191_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & expX_uid186_rrx_uid34_fpSinCosXTest_b) & xBranch_uid191_rrx_uid34_fpSinCosXTest_cin(0);
xBranch_uid191_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xBranch_uid191_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(xBranch_uid191_rrx_uid34_fpSinCosXTest_b));
xBranch_uid191_rrx_uid34_fpSinCosXTest_n(0) <= not xBranch_uid191_rrx_uid34_fpSinCosXTest_o(10);
--reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1(REG,563)@0
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q <= xBranch_uid191_rrx_uid34_fpSinCosXTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b(DELAY,829)@1
ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q, xout => ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalExp_uid209_rrx_uid34_fpSinCosXTest(MUX,208)@14
finalExp_uid209_rrx_uid34_fpSinCosXTest_s <= ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q;
finalExp_uid209_rrx_uid34_fpSinCosXTest: PROCESS (finalExp_uid209_rrx_uid34_fpSinCosXTest_s, en, reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q)
BEGIN
CASE finalExp_uid209_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b(DELAY,833)@14
ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => finalExp_uid209_rrx_uid34_fpSinCosXTest_q, xout => ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1409)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a or ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top(CONSTANT,1279)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q <= "01000";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp(LOGICAL,1280)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q <= "1" when ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a = ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b else "0";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg(REG,1281)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1410)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1411)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1399)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid187_rrx_uid34_fpSinCosXTest_b, xout => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt(COUNTER,1275)
-- every=1, low=0, high=8, step=1, init=1
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i = 7 THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i - 8;
ELSE
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg(REG,1276)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux(MUX,1277)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s, ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q, ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1400)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 4,
numwords_a => 9,
width_b => 23,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(22 downto 0);
--ZerosGB_uid206_rrx_uid34_fpSinCosXTest(CONSTANT,205)
ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q <= "000000000000000000000000000000";
--fracXRExt_uid207_rrx_uid34_fpSinCosXTest(BITJOIN,206)@15
fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q & ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q;
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1499)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1500)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1501)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,474)@9
X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(29 downto 0);
X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in(29 downto 0);
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1491)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 30, depth => 1 )
PORT MAP ( xin => X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1492)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 1,
numwords_a => 2,
width_b => 30,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(29 downto 0);
--leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest(CONSTANT,473)
leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,475)@13
leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1488)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1489)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1490)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,471)@9
X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(45 downto 0);
X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in(45 downto 0);
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1480)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1481)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 1,
numwords_a => 2,
width_b => 46,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(45 downto 0);
--leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,472)@13
leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1477)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1478)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1479)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,468)@9
X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(61 downto 0);
X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in(61 downto 0);
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1469)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1470)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 62,
widthad_a => 1,
numwords_a => 2,
width_b => 62,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(61 downto 0);
--leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,469)@13
leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor(LOGICAL,1510)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q <= not (ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a or ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b);
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena(REG,1511)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q = "1") THEN
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd(LOGICAL,1512)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b <= en;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a and ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg(DELAY,1502)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 78, depth => 1 )
PORT MAP ( xin => multFracBits_uid199_rrx_uid34_fpSinCosXTest_b, xout => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem(DUALMEM,1503)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 78,
widthad_a => 1,
numwords_a => 2,
width_b => 78,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia
);
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq(77 downto 0);
--leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,476)@13
leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in(5 downto 4);
--leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,477)@13
leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b;
leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,485)@13
LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(65 downto 0);
LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in(65 downto 0);
--leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest(CONSTANT,218)
leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q <= "000000000000";
--leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,486)@13
leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b & leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5(REG,560)@13
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,482)@13
LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(69 downto 0);
LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in(69 downto 0);
--leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,483)@13
leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4(REG,559)@13
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,479)@13
LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(73 downto 0);
LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in(73 downto 0);
--leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,480)@13
leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3(REG,558)@13
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2(REG,557)@13
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,487)@13
leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1(REG,556)@13
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,488)@14
leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q;
leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,496)@14
LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(74 downto 0);
LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in(74 downto 0);
--ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1112)@14
ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 75, depth => 1 )
PORT MAP ( xin => LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest(CONSTANT,229)
leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q <= "000";
--leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,497)@15
leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,493)@14
LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(75 downto 0);
LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in(75 downto 0);
--ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1110)@14
ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 76, depth => 1 )
PORT MAP ( xin => LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,494)@15
leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,490)@14
LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(76 downto 0);
LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in(76 downto 0);
--ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1108)@14
ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 77, depth => 1 )
PORT MAP ( xin => LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,491)@15
leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & GND_q;
--reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2(REG,562)@14
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,498)@13
leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a(DELAY,1184)@13
ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1(REG,561)@14
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,499)@15
leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q;
leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracCompOut_uid203_rrx_uid34_fpSinCosXTest(BITSELECT,202)@15
fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in <= leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q(76 downto 0);
fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b <= fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in(76 downto 24);
--ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b(DELAY,826)@0
ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => xBranch_uid191_rrx_uid34_fpSinCosXTest_n, xout => ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalFrac_uid208_rrx_uid34_fpSinCosXTest(MUX,207)@15
finalFrac_uid208_rrx_uid34_fpSinCosXTest_s <= ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q;
finalFrac_uid208_rrx_uid34_fpSinCosXTest: PROCESS (finalFrac_uid208_rrx_uid34_fpSinCosXTest_s, en, fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b, fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE finalFrac_uid208_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b;
WHEN "1" => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RRangeRed_uid210_rrx_uid34_fpSinCosXTest(BITJOIN,209)@15
RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q <= GND_q & ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q & finalFrac_uid208_rrx_uid34_fpSinCosXTest_q;
--expXRR_uid38_fpSinCosXTest(BITSELECT,37)@15
expXRR_uid38_fpSinCosXTest_in <= RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q(60 downto 0);
expXRR_uid38_fpSinCosXTest_b <= expXRR_uid38_fpSinCosXTest_in(60 downto 53);
--reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1(REG,565)@15
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q <= expXRR_uid38_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShiftM2_uid26_fpSinCosXTest(CONSTANT,25)
cstBiasMwShiftM2_uid26_fpSinCosXTest_q <= "01110000";
--cosXIsOneXRR_uid42_fpSinCosXTest(COMPARE,41)@16
cosXIsOneXRR_uid42_fpSinCosXTest_cin <= GND_q;
cosXIsOneXRR_uid42_fpSinCosXTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid26_fpSinCosXTest_q) & '0';
cosXIsOneXRR_uid42_fpSinCosXTest_b <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q) & cosXIsOneXRR_uid42_fpSinCosXTest_cin(0);
cosXIsOneXRR_uid42_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(cosXIsOneXRR_uid42_fpSinCosXTest_a) - SIGNED(cosXIsOneXRR_uid42_fpSinCosXTest_b));
cosXIsOneXRR_uid42_fpSinCosXTest_n(0) <= not cosXIsOneXRR_uid42_fpSinCosXTest_o(11);
--exp_uid9_fpSinCosXTest(BITSELECT,8)@0
exp_uid9_fpSinCosXTest_in <= a(30 downto 0);
exp_uid9_fpSinCosXTest_b <= exp_uid9_fpSinCosXTest_in(30 downto 23);
--sinXIsX_uid40_fpSinCosXTest(COMPARE,39)@0
sinXIsX_uid40_fpSinCosXTest_cin <= GND_q;
sinXIsX_uid40_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid24_fpSinCosXTest_q) & '0';
sinXIsX_uid40_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & exp_uid9_fpSinCosXTest_b) & sinXIsX_uid40_fpSinCosXTest_cin(0);
sinXIsX_uid40_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid40_fpSinCosXTest_a) - UNSIGNED(sinXIsX_uid40_fpSinCosXTest_b));
sinXIsX_uid40_fpSinCosXTest_n(0) <= not sinXIsX_uid40_fpSinCosXTest_o(10);
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a(DELAY,789)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--cosXONe_uid148_fpSinCosXTest(LOGICAL,147)@16
cosXONe_uid148_fpSinCosXTest_a <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q;
cosXONe_uid148_fpSinCosXTest_b <= cosXIsOneXRR_uid42_fpSinCosXTest_n;
cosXONe_uid148_fpSinCosXTest_q <= cosXONe_uid148_fpSinCosXTest_a or cosXONe_uid148_fpSinCosXTest_b;
--ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a(DELAY,791)@16
ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => cosXONe_uid148_fpSinCosXTest_q, xout => ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvCosXONe_uid149_fpSinCosXTest(LOGICAL,148)@20
InvCosXONe_uid149_fpSinCosXTest_a <= ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q;
InvCosXONe_uid149_fpSinCosXTest_q <= not InvCosXONe_uid149_fpSinCosXTest_a;
--cstZwShiftP1_uid27_fpSinCosXTest(CONSTANT,26)
cstZwShiftP1_uid27_fpSinCosXTest_q <= "00000000000000";
--fracXRR_uid39_fpSinCosXTest(BITSELECT,38)@15
fracXRR_uid39_fpSinCosXTest_in <= RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q(52 downto 0);
fracXRR_uid39_fpSinCosXTest_b <= fracXRR_uid39_fpSinCosXTest_in(52 downto 0);
--ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a(DELAY,668)@15
ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => fracXRR_uid39_fpSinCosXTest_b, xout => ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracXRR_uid43_uid43_fpSinCosXTest(BITJOIN,42)@16
oFracXRR_uid43_uid43_fpSinCosXTest_q <= VCC_q & ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q;
--extendedFracX_uid47_fpSinCosXTest(BITJOIN,46)@16
extendedFracX_uid47_fpSinCosXTest_q <= cstZwShiftP1_uid27_fpSinCosXTest_q & oFracXRR_uid43_uid43_fpSinCosXTest_q;
--X55dto0_uid220_fxpX_uid48_fpSinCosXTest(BITSELECT,219)@16
X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(55 downto 0);
X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b <= X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in(55 downto 0);
--leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest(BITJOIN,220)@16
leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q <= X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b & leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5(REG,571)@16
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q <= leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--X59dto0_uid217_fxpX_uid48_fpSinCosXTest(BITSELECT,216)@16
X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(59 downto 0);
X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b <= X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in(59 downto 0);
--leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest(BITJOIN,217)@16
leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q <= X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4(REG,570)@16
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q <= leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--X63dto0_uid214_fxpX_uid48_fpSinCosXTest(BITSELECT,213)@16
X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(63 downto 0);
X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b <= X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in(63 downto 0);
--leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest(BITJOIN,214)@16
leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q <= X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3(REG,569)@16
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q <= leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2(REG,568)@16
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q <= extendedFracX_uid47_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--fxpXShiftValExt_uid45_fpSinCosXTest(SUB,44)@16
fxpXShiftValExt_uid45_fpSinCosXTest_a <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q);
fxpXShiftValExt_uid45_fpSinCosXTest_b <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid26_fpSinCosXTest_q);
fxpXShiftValExt_uid45_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(fxpXShiftValExt_uid45_fpSinCosXTest_a) - SIGNED(fxpXShiftValExt_uid45_fpSinCosXTest_b));
fxpXShiftValExt_uid45_fpSinCosXTest_q <= fxpXShiftValExt_uid45_fpSinCosXTest_o(9 downto 0);
--fxpXShiftVal_uid46_fpSinCosXTest(BITSELECT,45)@16
fxpXShiftVal_uid46_fpSinCosXTest_in <= fxpXShiftValExt_uid45_fpSinCosXTest_q(3 downto 0);
fxpXShiftVal_uid46_fpSinCosXTest_b <= fxpXShiftVal_uid46_fpSinCosXTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest(BITSELECT,221)@16
leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in <= fxpXShiftVal_uid46_fpSinCosXTest_b;
leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b <= leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1(REG,567)@16
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q <= leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest(MUX,222)@17
leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s <= reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q;
leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest: PROCESS (leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s, en, reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q, reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q, reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q, reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest(BITSELECT,230)@17
LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(64 downto 0);
LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in(64 downto 0);
--ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b(DELAY,851)@17
ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest(BITJOIN,231)@18
leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q & leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest(BITSELECT,227)@17
LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(65 downto 0);
LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in(65 downto 0);
--ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b(DELAY,849)@17
ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 66, depth => 1 )
PORT MAP ( xin => LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest(BITJOIN,228)@18
leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest(BITSELECT,224)@17
LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(66 downto 0);
LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in(66 downto 0);
--ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b(DELAY,847)@17
ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 67, depth => 1 )
PORT MAP ( xin => LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest(BITJOIN,225)@18
leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q & GND_q;
--reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2(REG,573)@17
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest(BITSELECT,232)@16
leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in <= fxpXShiftVal_uid46_fpSinCosXTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b <= leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a(DELAY,1195)@16
ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b, xout => ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1(REG,572)@17
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q <= ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest(MUX,233)@18
leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s <= reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q;
leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest: PROCESS (leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s, en, reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q, leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q, leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q, leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q;
WHEN "10" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q;
WHEN "11" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid50_fpSinCosXTest(BITSELECT,49)@18
y_uid50_fpSinCosXTest_in <= leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q(66 downto 0);
y_uid50_fpSinCosXTest_b <= y_uid50_fpSinCosXTest_in(66 downto 1);
--ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b(DELAY,680)@18
ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 66, depth => 2 )
PORT MAP ( xin => y_uid50_fpSinCosXTest_b, xout => ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1(REG,575)@18
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q <= y_uid50_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--pad_one_uid55_fpSinCosXTest(BITJOIN,54)@18
pad_one_uid55_fpSinCosXTest_q <= VCC_q & STD_LOGIC_VECTOR((65 downto 1 => GND_q(0)) & GND_q);
--reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0(REG,574)@18
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q <= pad_one_uid55_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--oneMinusY_uid55_fpSinCosXTest(SUB,55)@19
oneMinusY_uid55_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q);
oneMinusY_uid55_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q);
oneMinusY_uid55_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid55_fpSinCosXTest_a) - UNSIGNED(oneMinusY_uid55_fpSinCosXTest_b));
oneMinusY_uid55_fpSinCosXTest_q <= oneMinusY_uid55_fpSinCosXTest_o(67 downto 0);
--reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0(REG,576)@19
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q <= oneMinusY_uid55_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid57_fpSinCosXTest(COMPARE,56)@20
cmpYToOneMinusY_uid57_fpSinCosXTest_cin <= GND_q;
cmpYToOneMinusY_uid57_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q) & '0';
cmpYToOneMinusY_uid57_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q) & cmpYToOneMinusY_uid57_fpSinCosXTest_cin(0);
cmpYToOneMinusY_uid57_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid57_fpSinCosXTest_a) - UNSIGNED(cmpYToOneMinusY_uid57_fpSinCosXTest_b));
cmpYToOneMinusY_uid57_fpSinCosXTest_c(0) <= cmpYToOneMinusY_uid57_fpSinCosXTest_o(70);
--InvCmpYToOneMinusY_uid61_fpSinCosXTest(LOGICAL,60)@20
InvCmpYToOneMinusY_uid61_fpSinCosXTest_a <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
InvCmpYToOneMinusY_uid61_fpSinCosXTest_q <= not InvCmpYToOneMinusY_uid61_fpSinCosXTest_a;
--intXParity_uid49_fpSinCosXTest(BITSELECT,48)@18
intXParity_uid49_fpSinCosXTest_in <= leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q;
intXParity_uid49_fpSinCosXTest_b <= intXParity_uid49_fpSinCosXTest_in(67 downto 67);
--ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b(DELAY,794)@18
ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => intXParity_uid49_fpSinCosXTest_b, xout => ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--yIsZero_uid51_fpSinCosXTest(LOGICAL,50)@19
yIsZero_uid51_fpSinCosXTest_a <= reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q;
yIsZero_uid51_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000000000000000000000000000000000" & GND_q);
yIsZero_uid51_fpSinCosXTest_q <= "1" when yIsZero_uid51_fpSinCosXTest_a = yIsZero_uid51_fpSinCosXTest_b else "0";
--ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a(DELAY,792)@19
ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => yIsZero_uid51_fpSinCosXTest_q, xout => ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvYIsZero_uid151_fpSinCosXTest(LOGICAL,150)@20
InvYIsZero_uid151_fpSinCosXTest_a <= ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q;
InvYIsZero_uid151_fpSinCosXTest_q <= not InvYIsZero_uid151_fpSinCosXTest_a;
--signRCond2_uid152_fpSinCosXTest(LOGICAL,151)@20
signRCond2_uid152_fpSinCosXTest_a <= InvYIsZero_uid151_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_b <= ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q;
signRCond2_uid152_fpSinCosXTest_c <= InvCmpYToOneMinusY_uid61_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_d <= InvCosXONe_uid149_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_q_i <= signRCond2_uid152_fpSinCosXTest_a and signRCond2_uid152_fpSinCosXTest_b and signRCond2_uid152_fpSinCosXTest_c and signRCond2_uid152_fpSinCosXTest_d;
signRCond2_uid152_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRCond2_uid152_fpSinCosXTest_q, xin => signRCond2_uid152_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--InvIntXParity_uid155_fpSinCosXTest(LOGICAL,154)@20
InvIntXParity_uid155_fpSinCosXTest_a <= ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q;
InvIntXParity_uid155_fpSinCosXTest_q <= not InvIntXParity_uid155_fpSinCosXTest_a;
--signRCond1_uid157_fpSinCosXTest(LOGICAL,156)@20
signRCond1_uid157_fpSinCosXTest_a <= InvYIsZero_uid151_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_b <= InvIntXParity_uid155_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_c <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
signRCond1_uid157_fpSinCosXTest_d <= InvCosXONe_uid149_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_q_i <= signRCond1_uid157_fpSinCosXTest_a and signRCond1_uid157_fpSinCosXTest_b and signRCond1_uid157_fpSinCosXTest_c and signRCond1_uid157_fpSinCosXTest_d;
signRCond1_uid157_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRCond1_uid157_fpSinCosXTest_q, xin => signRCond1_uid157_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--signRCos_uid158_fpSinCosXTest(LOGICAL,157)@21
signRCos_uid158_fpSinCosXTest_a <= signRCond1_uid157_fpSinCosXTest_q;
signRCos_uid158_fpSinCosXTest_b <= signRCond2_uid152_fpSinCosXTest_q;
signRCos_uid158_fpSinCosXTest_q <= signRCos_uid158_fpSinCosXTest_a or signRCos_uid158_fpSinCosXTest_b;
--cstAllZWF_uid7_fpSinCosXTest(CONSTANT,6)
cstAllZWF_uid7_fpSinCosXTest_q <= "00000000000000000000000";
--frac_uid13_fpSinCosXTest(BITSELECT,12)@0
frac_uid13_fpSinCosXTest_in <= a(22 downto 0);
frac_uid13_fpSinCosXTest_b <= frac_uid13_fpSinCosXTest_in(22 downto 0);
--fracXIsZero_uid14_fpSinCosXTest(LOGICAL,13)@0
fracXIsZero_uid14_fpSinCosXTest_a <= frac_uid13_fpSinCosXTest_b;
fracXIsZero_uid14_fpSinCosXTest_b <= cstAllZWF_uid7_fpSinCosXTest_q;
fracXIsZero_uid14_fpSinCosXTest_q <= "1" when fracXIsZero_uid14_fpSinCosXTest_a = fracXIsZero_uid14_fpSinCosXTest_b else "0";
--cstAllOWE_uid6_fpSinCosXTest(CONSTANT,5)
cstAllOWE_uid6_fpSinCosXTest_q <= "11111111";
--expXIsMax_uid12_fpSinCosXTest(LOGICAL,11)@0
expXIsMax_uid12_fpSinCosXTest_a <= exp_uid9_fpSinCosXTest_b;
expXIsMax_uid12_fpSinCosXTest_b <= cstAllOWE_uid6_fpSinCosXTest_q;
expXIsMax_uid12_fpSinCosXTest_q <= "1" when expXIsMax_uid12_fpSinCosXTest_a = expXIsMax_uid12_fpSinCosXTest_b else "0";
--exc_I_uid15_fpSinCosXTest(LOGICAL,14)@0
exc_I_uid15_fpSinCosXTest_a <= expXIsMax_uid12_fpSinCosXTest_q;
exc_I_uid15_fpSinCosXTest_b <= fracXIsZero_uid14_fpSinCosXTest_q;
exc_I_uid15_fpSinCosXTest_q <= exc_I_uid15_fpSinCosXTest_a and exc_I_uid15_fpSinCosXTest_b;
--ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a(DELAY,762)@0
ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 20 )
PORT MAP ( xin => exc_I_uid15_fpSinCosXTest_q, xout => ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_I_uid131_fpSinCosXTest(LOGICAL,130)@20
InvExc_I_uid131_fpSinCosXTest_a <= ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q;
InvExc_I_uid131_fpSinCosXTest_q <= not InvExc_I_uid131_fpSinCosXTest_a;
--reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2(REG,649)@20
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q <= InvExc_I_uid131_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--InvFracXIsZero_uid16_fpSinCosXTest(LOGICAL,15)@0
InvFracXIsZero_uid16_fpSinCosXTest_a <= fracXIsZero_uid14_fpSinCosXTest_q;
InvFracXIsZero_uid16_fpSinCosXTest_q <= not InvFracXIsZero_uid16_fpSinCosXTest_a;
--exc_N_uid17_fpSinCosXTest(LOGICAL,16)@0
exc_N_uid17_fpSinCosXTest_a <= expXIsMax_uid12_fpSinCosXTest_q;
exc_N_uid17_fpSinCosXTest_b <= InvFracXIsZero_uid16_fpSinCosXTest_q;
exc_N_uid17_fpSinCosXTest_q <= exc_N_uid17_fpSinCosXTest_a and exc_N_uid17_fpSinCosXTest_b;
--ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a(DELAY,763)@0
ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 20 )
PORT MAP ( xin => exc_N_uid17_fpSinCosXTest_q, xout => ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid132_fpSinCosXTest(LOGICAL,131)@20
InvExc_N_uid132_fpSinCosXTest_a <= ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q;
InvExc_N_uid132_fpSinCosXTest_q <= not InvExc_N_uid132_fpSinCosXTest_a;
--reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1(REG,648)@20
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q <= InvExc_N_uid132_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--signRCosFull_uid161_fpSinCosXTest(LOGICAL,160)@21
signRCosFull_uid161_fpSinCosXTest_a <= reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q;
signRCosFull_uid161_fpSinCosXTest_b <= reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q;
signRCosFull_uid161_fpSinCosXTest_c <= signRCos_uid158_fpSinCosXTest_q;
signRCosFull_uid161_fpSinCosXTest_q <= signRCosFull_uid161_fpSinCosXTest_a and signRCosFull_uid161_fpSinCosXTest_b and signRCosFull_uid161_fpSinCosXTest_c;
--ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c(DELAY,809)@21
ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signRCosFull_uid161_fpSinCosXTest_q, xout => ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid22_fpSinCosXTest(CONSTANT,21)
cstBias_uid22_fpSinCosXTest_q <= "01111111";
--ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a(DELAY,681)@19
ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 68, depth => 1 )
PORT MAP ( xin => oneMinusY_uid55_fpSinCosXTest_q, xout => ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--zSinOMyBottom_uid58_fpSinCosXTest(BITSELECT,57)@20
zSinOMyBottom_uid58_fpSinCosXTest_in <= ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q(64 downto 0);
zSinOMyBottom_uid58_fpSinCosXTest_b <= zSinOMyBottom_uid58_fpSinCosXTest_in(64 downto 0);
--reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3(REG,579)@20
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q <= zSinOMyBottom_uid58_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--zSinYBottom_uid59_fpSinCosXTest(BITSELECT,58)@20
zSinYBottom_uid59_fpSinCosXTest_in <= ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q(64 downto 0);
zSinYBottom_uid59_fpSinCosXTest_b <= zSinYBottom_uid59_fpSinCosXTest_in(64 downto 0);
--reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2(REG,578)@20
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q <= zSinYBottom_uid59_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1(REG,614)@20
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q <= InvCmpYToOneMinusY_uid61_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--zCos_uid64_fpSinCosXTest(MUX,63)@21
zCos_uid64_fpSinCosXTest_s <= reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q;
zCos_uid64_fpSinCosXTest: PROCESS (zCos_uid64_fpSinCosXTest_s, en, reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q, reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q)
BEGIN
CASE zCos_uid64_fpSinCosXTest_s IS
WHEN "0" => zCos_uid64_fpSinCosXTest_q <= reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q;
WHEN "1" => zCos_uid64_fpSinCosXTest_q <= reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q;
WHEN OTHERS => zCos_uid64_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--addr_uid83_fpSinCosXTest(BITSELECT,82)@21
addr_uid83_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q;
addr_uid83_fpSinCosXTest_b <= addr_uid83_fpSinCosXTest_in(64 downto 57);
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0(REG,630)@21
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q <= addr_uid83_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid404_tableGencosPiZ_lutmem(DUALMEM,532)@22
memoryC2_uid404_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC2_uid404_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC2_uid404_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q;
memoryC2_uid404_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC2_uid404_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid404_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid404_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid404_tableGencosPiZ_lutmem_iq,
address_a => memoryC2_uid404_tableGencosPiZ_lutmem_aa,
data_a => memoryC2_uid404_tableGencosPiZ_lutmem_ia
);
memoryC2_uid404_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC2_uid404_tableGencosPiZ_lutmem_q <= memoryC2_uid404_tableGencosPiZ_lutmem_iq(12 downto 0);
--reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1(REG,632)@24
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q <= memoryC2_uid404_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPcosPiZ_uid87_fpSinCosXTest(BITSELECT,86)@21
zPcosPiZ_uid87_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(56 downto 0);
zPcosPiZ_uid87_fpSinCosXTest_b <= zPcosPiZ_uid87_fpSinCosXTest_in(56 downto 42);
--yT1_uid419_polyEvalcosPiZ(BITSELECT,418)@21
yT1_uid419_polyEvalcosPiZ_in <= zPcosPiZ_uid87_fpSinCosXTest_b;
yT1_uid419_polyEvalcosPiZ_b <= yT1_uid419_polyEvalcosPiZ_in(14 downto 2);
--reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0(REG,631)@21
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q <= yT1_uid419_polyEvalcosPiZ_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg(DELAY,1513)
ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q, xout => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a(DELAY,1125)@22
ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q, xout => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid508_pT1_uid420_polyEvalcosPiZ(MULT,507)@25
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a),14)) * SIGNED(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b);
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a <= (others => '0');
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b <= (others => '0');
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a <= ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b <= reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q <= prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ(BITSELECT,508)@28
prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in <= prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q;
prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in(25 downto 12);
--highBBits_uid422_polyEvalcosPiZ(BITSELECT,421)@28
highBBits_uid422_polyEvalcosPiZ_in <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b;
highBBits_uid422_polyEvalcosPiZ_b <= highBBits_uid422_polyEvalcosPiZ_in(13 downto 1);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a(DELAY,1256)@21
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => addr_uid83_fpSinCosXTest_b, xout => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0(REG,633)@24
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid402_tableGencosPiZ_lutmem(DUALMEM,531)@25
memoryC1_uid402_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC1_uid402_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC1_uid402_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q;
memoryC1_uid402_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC1_uid402_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid402_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid402_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid402_tableGencosPiZ_lutmem_iq,
address_a => memoryC1_uid402_tableGencosPiZ_lutmem_aa,
data_a => memoryC1_uid402_tableGencosPiZ_lutmem_ia
);
memoryC1_uid402_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC1_uid402_tableGencosPiZ_lutmem_q <= memoryC1_uid402_tableGencosPiZ_lutmem_iq(20 downto 0);
--reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0(REG,634)@27
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q <= memoryC1_uid402_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid423_polyEvalcosPiZ(ADD,422)@28
sumAHighB_uid423_polyEvalcosPiZ_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q(20)) & reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q);
sumAHighB_uid423_polyEvalcosPiZ_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid422_polyEvalcosPiZ_b(12)) & highBBits_uid422_polyEvalcosPiZ_b);
sumAHighB_uid423_polyEvalcosPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid423_polyEvalcosPiZ_a) + SIGNED(sumAHighB_uid423_polyEvalcosPiZ_b));
sumAHighB_uid423_polyEvalcosPiZ_q <= sumAHighB_uid423_polyEvalcosPiZ_o(21 downto 0);
--lowRangeB_uid421_polyEvalcosPiZ(BITSELECT,420)@28
lowRangeB_uid421_polyEvalcosPiZ_in <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b(0 downto 0);
lowRangeB_uid421_polyEvalcosPiZ_b <= lowRangeB_uid421_polyEvalcosPiZ_in(0 downto 0);
--s1_uid421_uid424_polyEvalcosPiZ(BITJOIN,423)@28
s1_uid421_uid424_polyEvalcosPiZ_q <= sumAHighB_uid423_polyEvalcosPiZ_q & lowRangeB_uid421_polyEvalcosPiZ_b;
--reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1(REG,636)@28
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q <= s1_uid421_uid424_polyEvalcosPiZ_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor(LOGICAL,1524)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q <= not (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a or ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b);
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top(CONSTANT,1520)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q <= "0100";
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp(LOGICAL,1521)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q <= "1" when ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a = ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b else "0";
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg(REG,1522)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena(REG,1525)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd(LOGICAL,1526)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b <= en;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a and ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b;
--reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0(REG,635)@21
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q <= zPcosPiZ_uid87_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg(DELAY,1514)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q, xout => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt(COUNTER,1516)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i = 3 THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i,3));
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg(REG,1517)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux(MUX,1518)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s <= en;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux: PROCESS (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s, ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q, ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem(DUALMEM,1515)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq,
address_a => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa,
data_a => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia
);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0 <= areset;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq(14 downto 0);
--prodXY_uid511_pT2_uid426_polyEvalcosPiZ(MULT,510)@29
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a),16)) * SIGNED(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b);
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a <= (others => '0');
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b <= (others => '0');
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b <= reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q <= prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ(BITSELECT,511)@32
prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in <= prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q;
prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in(37 downto 14);
--highBBits_uid428_polyEvalcosPiZ(BITSELECT,427)@32
highBBits_uid428_polyEvalcosPiZ_in <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b;
highBBits_uid428_polyEvalcosPiZ_b <= highBBits_uid428_polyEvalcosPiZ_in(23 downto 2);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor(LOGICAL,1577)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q <= not (ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a or ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena(REG,1578)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q = "1") THEN
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd(LOGICAL,1579)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b <= en;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a and ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b;
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg(DELAY,1567)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addr_uid83_fpSinCosXTest_b, xout => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem(DUALMEM,1568)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq,
address_a => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa,
data_a => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia
);
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0(REG,637)@28
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid400_tableGencosPiZ_lutmem(DUALMEM,530)@29
memoryC0_uid400_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC0_uid400_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC0_uid400_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q;
memoryC0_uid400_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC0_uid400_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid400_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid400_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid400_tableGencosPiZ_lutmem_iq,
address_a => memoryC0_uid400_tableGencosPiZ_lutmem_aa,
data_a => memoryC0_uid400_tableGencosPiZ_lutmem_ia
);
memoryC0_uid400_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC0_uid400_tableGencosPiZ_lutmem_q <= memoryC0_uid400_tableGencosPiZ_lutmem_iq(29 downto 0);
--reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0(REG,638)@31
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q <= memoryC0_uid400_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid429_polyEvalcosPiZ(ADD,428)@32
sumAHighB_uid429_polyEvalcosPiZ_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q(29)) & reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q);
sumAHighB_uid429_polyEvalcosPiZ_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid428_polyEvalcosPiZ_b(21)) & highBBits_uid428_polyEvalcosPiZ_b);
sumAHighB_uid429_polyEvalcosPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid429_polyEvalcosPiZ_a) + SIGNED(sumAHighB_uid429_polyEvalcosPiZ_b));
sumAHighB_uid429_polyEvalcosPiZ_q <= sumAHighB_uid429_polyEvalcosPiZ_o(30 downto 0);
--lowRangeB_uid427_polyEvalcosPiZ(BITSELECT,426)@32
lowRangeB_uid427_polyEvalcosPiZ_in <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b(1 downto 0);
lowRangeB_uid427_polyEvalcosPiZ_b <= lowRangeB_uid427_polyEvalcosPiZ_in(1 downto 0);
--s2_uid427_uid430_polyEvalcosPiZ(BITJOIN,429)@32
s2_uid427_uid430_polyEvalcosPiZ_q <= sumAHighB_uid429_polyEvalcosPiZ_q & lowRangeB_uid427_polyEvalcosPiZ_b;
--polyEvalSigcosPiZ_uid89_fpSinCosXTest(BITSELECT,88)@32
polyEvalSigcosPiZ_uid89_fpSinCosXTest_in <= s2_uid427_uid430_polyEvalcosPiZ_q(30 downto 0);
polyEvalSigcosPiZ_uid89_fpSinCosXTest_b <= polyEvalSigcosPiZ_uid89_fpSinCosXTest_in(30 downto 5);
--reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1(REG,640)@32
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q <= polyEvalSigcosPiZ_uid89_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor(LOGICAL,1590)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q <= not (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a or ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b);
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top(CONSTANT,1586)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q <= "010";
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp(LOGICAL,1587)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q <= "1" when ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a = ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b else "0";
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg(REG,1588)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena(REG,1591)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd(LOGICAL,1592)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b <= en;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a and ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b;
--LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest(BITSELECT,388)@27
LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q(63 downto 0);
LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in(63 downto 0);
--leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest(BITJOIN,389)@27
leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b & GND_q;
--cstZmwFRRPwSM1_uid52_fpSinCosXTest(CONSTANT,51)
cstZmwFRRPwSM1_uid52_fpSinCosXTest_q <= "00000000000000000000000000000000000000000000000000000000000000000";
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor(LOGICAL,1455)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q <= not (ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a or ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b);
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena(REG,1456)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q = "1") THEN
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd(LOGICAL,1457)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b <= en;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a and ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b;
--X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest(BITSELECT,359)@21
X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(32 downto 0);
X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b <= X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in(32 downto 0);
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg(DELAY,1447)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem(DUALMEM,1448)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 33,
widthad_a => 1,
numwords_a => 2,
width_b => 33,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia
);
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq(32 downto 0);
--leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest(BITJOIN,360)@25
leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor(LOGICAL,1466)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q <= not (ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a or ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b);
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena(REG,1467)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q = "1") THEN
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd(LOGICAL,1468)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b <= en;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a and ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg(DELAY,1458)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => zCos_uid64_fpSinCosXTest_q, xout => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem(DUALMEM,1459)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 65,
widthad_a => 1,
numwords_a => 2,
width_b => 65,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia
);
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq(64 downto 0);
--zs_uid236_lzcZSin_uid66_fpSinCosXTest(CONSTANT,235)
zs_uid236_lzcZSin_uid66_fpSinCosXTest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--rVStage_uid316_lzcZCos_uid69_fpSinCosXTest(BITSELECT,315)@21
rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q;
rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in(64 downto 1);
--vCount_uid317_lzcZCos_uid69_fpSinCosXTest(LOGICAL,316)@21
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid236_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g(DELAY,985)@22
ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid319_lzcZCos_uid69_fpSinCosXTest(BITSELECT,318)@21
vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(0 downto 0);
vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in(0 downto 0);
--ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b(DELAY,943)@21
ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid239_lzcZSin_uid66_fpSinCosXTest(CONSTANT,238)
mO_uid239_lzcZSin_uid66_fpSinCosXTest_q <= "111111111111111111111111111111111111111111111111111111111111111";
--cStage_uid320_lzcZCos_uid69_fpSinCosXTest(BITJOIN,319)@22
cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q <= ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q & mO_uid239_lzcZSin_uid66_fpSinCosXTest_q;
--ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c(DELAY,945)@21
ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid322_lzcZCos_uid69_fpSinCosXTest(MUX,321)@22
vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid322_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s, en, ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q, cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid324_lzcZCos_uid69_fpSinCosXTest(BITSELECT,323)@22
rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in(63 downto 32);
--vCount_uid325_lzcZCos_uid69_fpSinCosXTest(LOGICAL,324)@22
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f(DELAY,984)@23
ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid326_lzcZCos_uid69_fpSinCosXTest(BITSELECT,325)@22
vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q(31 downto 0);
vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in(31 downto 0);
--ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d(DELAY,952)@22
ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c(DELAY,951)@22
ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid328_lzcZCos_uid69_fpSinCosXTest(MUX,327)@23
vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid328_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s, en, ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q, ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q)
BEGIN
CASE vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q;
WHEN OTHERS => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid330_lzcZCos_uid69_fpSinCosXTest(BITSELECT,329)@23
rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in(31 downto 16);
--vCount_uid331_lzcZCos_uid69_fpSinCosXTest(LOGICAL,330)@23
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b else "0";
--reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4(REG,622)@23
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q <= vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e(DELAY,983)@24
ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid332_lzcZCos_uid69_fpSinCosXTest(BITSELECT,331)@23
vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q(15 downto 0);
vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in(15 downto 0);
--vStagei_uid334_lzcZCos_uid69_fpSinCosXTest(MUX,333)@23
vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid334_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s, en, rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b, vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b;
WHEN "1" => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid336_lzcZCos_uid69_fpSinCosXTest(BITSELECT,335)@23
rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in(15 downto 8);
--reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1(REG,617)@23
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q <= rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid337_lzcZCos_uid69_fpSinCosXTest(LOGICAL,336)@24
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a <= reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q;
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b else "0";
--ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d(DELAY,982)@24
ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid338_lzcZCos_uid69_fpSinCosXTest(BITSELECT,337)@23
vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q(7 downto 0);
vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3(REG,619)@23
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q <= vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid340_lzcZCos_uid69_fpSinCosXTest(MUX,339)@24
vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid340_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s, en, reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q, reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid342_lzcZCos_uid69_fpSinCosXTest(BITSELECT,341)@24
rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in(7 downto 4);
--vCount_uid343_lzcZCos_uid69_fpSinCosXTest(LOGICAL,342)@24
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid344_lzcZCos_uid69_fpSinCosXTest(BITSELECT,343)@24
vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q(3 downto 0);
vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in(3 downto 0);
--reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3(REG,621)@24
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q <= vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2(REG,620)@24
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid346_lzcZCos_uid69_fpSinCosXTest(MUX,345)@25
vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid346_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s, en, reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q, reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid348_lzcZCos_uid69_fpSinCosXTest(BITSELECT,347)@25
rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in(3 downto 2);
--vCount_uid349_lzcZCos_uid69_fpSinCosXTest(LOGICAL,348)@25
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b else "0";
--vStage_uid350_lzcZCos_uid69_fpSinCosXTest(BITSELECT,349)@25
vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q(1 downto 0);
vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in(1 downto 0);
--vStagei_uid352_lzcZCos_uid69_fpSinCosXTest(MUX,351)@25
vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid352_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s, en, rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b, vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b;
WHEN "1" => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid354_lzcZCos_uid69_fpSinCosXTest(BITSELECT,353)@25
rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in(1 downto 1);
--vCount_uid355_lzcZCos_uid69_fpSinCosXTest(LOGICAL,354)@25
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b <= GND_q;
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b else "0";
--r_uid356_lzcZCos_uid69_fpSinCosXTest(BITJOIN,355)@25
r_uid356_lzcZCos_uid69_fpSinCosXTest_q <= ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q & ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q & ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q & ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q & vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q & vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q & vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q;
--leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest(BITSELECT,363)@25
leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q;
leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in(6 downto 5);
--leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest(MUX,364)@25
leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s <= leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b;
leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s, en, ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest(BITSELECT,372)@25
LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(40 downto 0);
LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in(40 downto 0);
--leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest(CONSTANT,292)
leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q <= "000000000000000000000000";
--leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest(BITJOIN,373)@25
leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b & leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5(REG,627)@25
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest(BITSELECT,369)@25
LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(48 downto 0);
LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in(48 downto 0);
--leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest(BITJOIN,370)@25
leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4(REG,626)@25
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest(BITSELECT,366)@25
LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(56 downto 0);
LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in(56 downto 0);
--leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest(BITJOIN,367)@25
leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3(REG,625)@25
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2(REG,624)@25
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest(BITSELECT,374)@25
leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1(REG,623)@25
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q <= leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest(MUX,375)@26
leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s <= reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q;
leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s, en, reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest(BITSELECT,383)@26
LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(58 downto 0);
LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1009)@26
ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest(CONSTANT,303)
leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q <= "000000";
--leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest(BITJOIN,384)@27
leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q;
--LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest(BITSELECT,380)@26
LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(60 downto 0);
LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1007)@26
ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest(BITJOIN,381)@27
leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest(BITSELECT,377)@26
LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(62 downto 0);
LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in(62 downto 0);
--ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1005)@26
ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest(BITJOIN,378)@27
leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2(REG,629)@26
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest(BITSELECT,385)@25
leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1(REG,628)@25
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q <= leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1011)@26
ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest(MUX,386)@27
leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s <= ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q;
leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s, en, reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest(BITSELECT,390)@25
leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1019)@25
ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest(MUX,391)@27
leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s <= ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q;
leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s, en, leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "0" => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "1" => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--pCos_uid77_fpSinCosXTest(BITSELECT,76)@27
pCos_uid77_fpSinCosXTest_in <= leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q;
pCos_uid77_fpSinCosXTest_b <= pCos_uid77_fpSinCosXTest_in(64 downto 39);
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg(DELAY,1580)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => pCos_uid77_fpSinCosXTest_b, xout => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt(COUNTER,1582)
-- every=1, low=0, high=2, step=1, init=1
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i = 1 THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i - 2;
ELSE
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i,2));
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg(REG,1583)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux(MUX,1584)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s <= en;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux: PROCESS (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s, ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q, ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q)
BEGIN
CASE ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s IS
WHEN "0" => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q;
WHEN "1" => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem(DUALMEM,1581)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 2,
numwords_a => 3,
width_b => 26,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq,
address_a => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa,
data_a => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia
);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0 <= areset;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq(25 downto 0);
--reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0(REG,639)@32
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--mulCos_uid105_fpSinCosXTest(MULT,104)@33
mulCos_uid105_fpSinCosXTest_pr <= UNSIGNED(mulCos_uid105_fpSinCosXTest_a) * UNSIGNED(mulCos_uid105_fpSinCosXTest_b);
mulCos_uid105_fpSinCosXTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulCos_uid105_fpSinCosXTest_a <= (others => '0');
mulCos_uid105_fpSinCosXTest_b <= (others => '0');
mulCos_uid105_fpSinCosXTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulCos_uid105_fpSinCosXTest_a <= reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q;
mulCos_uid105_fpSinCosXTest_b <= reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q;
mulCos_uid105_fpSinCosXTest_s1 <= STD_LOGIC_VECTOR(mulCos_uid105_fpSinCosXTest_pr);
END IF;
END IF;
END PROCESS;
mulCos_uid105_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulCos_uid105_fpSinCosXTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulCos_uid105_fpSinCosXTest_q <= mulCos_uid105_fpSinCosXTest_s1;
END IF;
END IF;
END PROCESS;
--normBitCos_uid106_fpSinCosXTest(BITSELECT,105)@36
normBitCos_uid106_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q;
normBitCos_uid106_fpSinCosXTest_b <= normBitCos_uid106_fpSinCosXTest_in(51 downto 51);
--cosRndOp_uid112_uid113_fpSinCosXTest(BITJOIN,112)@36
cosRndOp_uid112_uid113_fpSinCosXTest_q <= normBitCos_uid106_fpSinCosXTest_b & cstAllZWF_uid7_fpSinCosXTest_q & VCC_q;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor(LOGICAL,1296)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q <= not (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a or ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b);
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top(CONSTANT,1292)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q <= "0110";
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp(LOGICAL,1293)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q <= "1" when ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a = ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b else "0";
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg(REG,1294)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena(REG,1297)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd(LOGICAL,1298)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b <= en;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a and ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b;
--reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1(REG,641)@25
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg(DELAY,1286)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q, xout => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt(COUNTER,1288)
-- every=1, low=0, high=6, step=1, init=1
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i = 5 THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i - 6;
ELSE
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i,3));
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg(REG,1289)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux(MUX,1290)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s <= en;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux: PROCESS (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s, ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q, ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem(DUALMEM,1287)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 7,
width_b => 7,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia
);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq(6 downto 0);
--expHardCase_uid78_fpSinCosXTest(SUB,77)@35
expHardCase_uid78_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expHardCase_uid78_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q);
expHardCase_uid78_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid78_fpSinCosXTest_a) - UNSIGNED(expHardCase_uid78_fpSinCosXTest_b));
expHardCase_uid78_fpSinCosXTest_q <= expHardCase_uid78_fpSinCosXTest_o(8 downto 0);
--expPCos_uid79_fpSinCosXTest(BITSELECT,78)@35
expPCos_uid79_fpSinCosXTest_in <= expHardCase_uid78_fpSinCosXTest_q(7 downto 0);
expPCos_uid79_fpSinCosXTest_b <= expPCos_uid79_fpSinCosXTest_in(7 downto 0);
--reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1(REG,642)@35
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q <= expPCos_uid79_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--fracRCosPreRndHigh_uid108_fpSinCosXTest(BITSELECT,107)@36
fracRCosPreRndHigh_uid108_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q(50 downto 0);
fracRCosPreRndHigh_uid108_fpSinCosXTest_b <= fracRCosPreRndHigh_uid108_fpSinCosXTest_in(50 downto 27);
--fracRCosPreRndLow_uid109_fpSinCosXTest(BITSELECT,108)@36
fracRCosPreRndLow_uid109_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q(49 downto 0);
fracRCosPreRndLow_uid109_fpSinCosXTest_b <= fracRCosPreRndLow_uid109_fpSinCosXTest_in(49 downto 26);
--fracRCosPreRnd_uid110_fpSinCosXTest(MUX,109)@36
fracRCosPreRnd_uid110_fpSinCosXTest_s <= normBitCos_uid106_fpSinCosXTest_b;
fracRCosPreRnd_uid110_fpSinCosXTest: PROCESS (fracRCosPreRnd_uid110_fpSinCosXTest_s, en, fracRCosPreRndLow_uid109_fpSinCosXTest_b, fracRCosPreRndHigh_uid108_fpSinCosXTest_b)
BEGIN
CASE fracRCosPreRnd_uid110_fpSinCosXTest_s IS
WHEN "0" => fracRCosPreRnd_uid110_fpSinCosXTest_q <= fracRCosPreRndLow_uid109_fpSinCosXTest_b;
WHEN "1" => fracRCosPreRnd_uid110_fpSinCosXTest_q <= fracRCosPreRndHigh_uid108_fpSinCosXTest_b;
WHEN OTHERS => fracRCosPreRnd_uid110_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracRCosPreRnd_uid111_uid111_fpSinCosXTest(BITJOIN,110)@36
expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q <= reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q & fracRCosPreRnd_uid110_fpSinCosXTest_q;
--expFracRCos_uid114_fpSinCosXTest(ADD,113)@36
expFracRCos_uid114_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q);
expFracRCos_uid114_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00000000" & cosRndOp_uid112_uid113_fpSinCosXTest_q);
expFracRCos_uid114_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRCos_uid114_fpSinCosXTest_a) + UNSIGNED(expFracRCos_uid114_fpSinCosXTest_b));
expFracRCos_uid114_fpSinCosXTest_q <= expFracRCos_uid114_fpSinCosXTest_o(32 downto 0);
--expRCompSin_uid116_fpSinCosXTest(BITSELECT,115)@36
expRCompSin_uid116_fpSinCosXTest_in <= expFracRCos_uid114_fpSinCosXTest_q(31 downto 0);
expRCompSin_uid116_fpSinCosXTest_b <= expRCompSin_uid116_fpSinCosXTest_in(31 downto 24);
--reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2(REG,646)@36
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q <= expRCompSin_uid116_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor(LOGICAL,1385)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q <= not (ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a or ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top(CONSTANT,1305)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q <= "01101";
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp(LOGICAL,1306)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q <= "1" when ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a = ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b else "0";
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg(REG,1307)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena(REG,1386)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q = "1") THEN
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd(LOGICAL,1387)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b <= en;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a and ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b;
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a(DELAY,745)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c(DELAY,783)@16
ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => cosXIsOneXRR_uid42_fpSinCosXTest_n, xout => ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--InvCosXIsOneXRR_uid136_fpSinCosXTest(LOGICAL,135)@16
InvCosXIsOneXRR_uid136_fpSinCosXTest_a <= cosXIsOneXRR_uid42_fpSinCosXTest_n;
InvCosXIsOneXRR_uid136_fpSinCosXTest_q <= not InvCosXIsOneXRR_uid136_fpSinCosXTest_a;
--ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c(DELAY,773)@16
ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => InvCosXIsOneXRR_uid136_fpSinCosXTest_q, xout => ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a(DELAY,755)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsX_uid127_fpSinCosXTest(LOGICAL,126)@18
InvSinXIsX_uid127_fpSinCosXTest_a <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q;
InvSinXIsX_uid127_fpSinCosXTest_q <= not InvSinXIsX_uid127_fpSinCosXTest_a;
--ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b(DELAY,772)@18
ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => InvSinXIsX_uid127_fpSinCosXTest_q, xout => ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--half_uid53_fpSinCosXTest(BITJOIN,52)@19
half_uid53_fpSinCosXTest_q <= VCC_q & cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
--yIsHalf_uid54_fpSinCosXTest(LOGICAL,53)@19
yIsHalf_uid54_fpSinCosXTest_a <= reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q;
yIsHalf_uid54_fpSinCosXTest_b <= half_uid53_fpSinCosXTest_q;
yIsHalf_uid54_fpSinCosXTest_q <= "1" when yIsHalf_uid54_fpSinCosXTest_a = yIsHalf_uid54_fpSinCosXTest_b else "0";
--yHalfCosXNotOne_uid138_fpSinCosXTest(LOGICAL,137)@19
yHalfCosXNotOne_uid138_fpSinCosXTest_a <= yIsHalf_uid54_fpSinCosXTest_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_b <= ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_c <= ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_q <= yHalfCosXNotOne_uid138_fpSinCosXTest_a and yHalfCosXNotOne_uid138_fpSinCosXTest_b and yHalfCosXNotOne_uid138_fpSinCosXTest_c;
--ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b(DELAY,744)@0
ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => exc_I_uid15_fpSinCosXTest_q, xout => ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a(DELAY,743)@0
ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => exc_N_uid17_fpSinCosXTest_q, xout => ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRNaN_uid117_fpSinCosXTest(LOGICAL,116)@19
excRNaN_uid117_fpSinCosXTest_a <= ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q;
excRNaN_uid117_fpSinCosXTest_b <= ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q;
excRNaN_uid117_fpSinCosXTest_q <= excRNaN_uid117_fpSinCosXTest_a or excRNaN_uid117_fpSinCosXTest_b;
--join_uid143_fpSinCosXTest(BITJOIN,142)@19
join_uid143_fpSinCosXTest_q <= ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q & yHalfCosXNotOne_uid138_fpSinCosXTest_q & excRNaN_uid117_fpSinCosXTest_q;
--expSelBitsCos_uid144_fpSinCosXTest(BITJOIN,143)@19
expSelBitsCos_uid144_fpSinCosXTest_q <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q & join_uid143_fpSinCosXTest_q;
--reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0(REG,645)@19
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q <= expSelBitsCos_uid144_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--expSelectorCos_uid145_fpSinCosXTest(LOOKUP,144)@20
expSelectorCos_uid145_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSelectorCos_uid145_fpSinCosXTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q) IS
WHEN "0000" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "0001" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "0010" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "0011" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "0100" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "0101" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "0110" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "0111" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "1000" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "1001" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "1010" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "1011" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "1100" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "1101" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "1110" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "1111" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN OTHERS =>
expSelectorCos_uid145_fpSinCosXTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg(DELAY,1375)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => expSelectorCos_uid145_fpSinCosXTest_q, xout => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt(COUNTER,1301)
-- every=1, low=0, high=13, step=1, init=1
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i = 12 THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i - 13;
ELSE
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg(REG,1302)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux(MUX,1303)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s, ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q, ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem(DUALMEM,1376)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia
);
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq(1 downto 0);
--expRPostExcCos_uid147_fpSinCosXTest(MUX,146)@37
expRPostExcCos_uid147_fpSinCosXTest_s <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q;
expRPostExcCos_uid147_fpSinCosXTest: PROCESS (expRPostExcCos_uid147_fpSinCosXTest_s, en, reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q, cstBias_uid22_fpSinCosXTest_q, cstAllZWE_uid8_fpSinCosXTest_q, cstAllOWE_uid6_fpSinCosXTest_q)
BEGIN
CASE expRPostExcCos_uid147_fpSinCosXTest_s IS
WHEN "00" => expRPostExcCos_uid147_fpSinCosXTest_q <= reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q;
WHEN "01" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstBias_uid22_fpSinCosXTest_q;
WHEN "10" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstAllZWE_uid8_fpSinCosXTest_q;
WHEN "11" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstAllOWE_uid6_fpSinCosXTest_q;
WHEN OTHERS => expRPostExcCos_uid147_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstNaNwF_uid32_fpSinCosXTest(CONSTANT,31)
cstNaNwF_uid32_fpSinCosXTest_q <= "00000000000000000000001";
--fracRCompCos_uid115_fpSinCosXTest(BITSELECT,114)@36
fracRCompCos_uid115_fpSinCosXTest_in <= expFracRCos_uid114_fpSinCosXTest_q(23 downto 0);
fracRCompCos_uid115_fpSinCosXTest_b <= fracRCompCos_uid115_fpSinCosXTest_in(23 downto 1);
--reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2(REG,644)@36
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q <= fracRCompCos_uid115_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor(LOGICAL,1372)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q <= not (ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a or ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b);
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena(REG,1373)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q = "1") THEN
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd(LOGICAL,1374)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b <= en;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a and ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b;
--reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1(REG,613)@19
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q <= excRNaN_uid117_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3(REG,612)@19
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q <= ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q;
END IF;
END IF;
END PROCESS;
--reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2(REG,611)@19
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q;
END IF;
END IF;
END PROCESS;
--reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1(REG,610)@19
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q <= yHalfCosXNotOne_uid138_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--rZOrOne_uid140_fpSinCosXTest(LOGICAL,139)@20
rZOrOne_uid140_fpSinCosXTest_a <= reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q;
rZOrOne_uid140_fpSinCosXTest_b <= reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q;
rZOrOne_uid140_fpSinCosXTest_c <= reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q;
rZOrOne_uid140_fpSinCosXTest_q <= rZOrOne_uid140_fpSinCosXTest_a or rZOrOne_uid140_fpSinCosXTest_b or rZOrOne_uid140_fpSinCosXTest_c;
--join_uid141_fpSinCosXTest(BITJOIN,140)@20
join_uid141_fpSinCosXTest_q <= reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q & rZOrOne_uid140_fpSinCosXTest_q;
--reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1(REG,643)@20
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q <= join_uid141_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg(DELAY,1362)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q, xout => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem(DUALMEM,1363)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia
);
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq(1 downto 0);
--fracRPostExcCos_uid142_fpSinCosXTest(MUX,141)@37
fracRPostExcCos_uid142_fpSinCosXTest_s <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q;
fracRPostExcCos_uid142_fpSinCosXTest: PROCESS (fracRPostExcCos_uid142_fpSinCosXTest_s, en, reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q, cstAllZWF_uid7_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q)
BEGIN
CASE fracRPostExcCos_uid142_fpSinCosXTest_s IS
WHEN "00" => fracRPostExcCos_uid142_fpSinCosXTest_q <= reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q;
WHEN "01" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstAllZWF_uid7_fpSinCosXTest_q;
WHEN "10" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN "11" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN OTHERS => fracRPostExcCos_uid142_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpCos_uid162_fpSinCosXTest(BITJOIN,161)@37
fpCos_uid162_fpSinCosXTest_q <= ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q & expRPostExcCos_uid147_fpSinCosXTest_q & fracRPostExcCos_uid142_fpSinCosXTest_q;
--cstBiasMwShiftM2_uid25_fpSinCosXTest(CONSTANT,24)
cstBiasMwShiftM2_uid25_fpSinCosXTest_q <= "01110001";
--sinXIsXRR_uid41_fpSinCosXTest(COMPARE,40)@16
sinXIsXRR_uid41_fpSinCosXTest_cin <= GND_q;
sinXIsXRR_uid41_fpSinCosXTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid25_fpSinCosXTest_q) & '0';
sinXIsXRR_uid41_fpSinCosXTest_b <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q) & sinXIsXRR_uid41_fpSinCosXTest_cin(0);
sinXIsXRR_uid41_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(sinXIsXRR_uid41_fpSinCosXTest_a) - SIGNED(sinXIsXRR_uid41_fpSinCosXTest_b));
sinXIsXRR_uid41_fpSinCosXTest_n(0) <= not sinXIsXRR_uid41_fpSinCosXTest_o(11);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a(DELAY,756)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsXRR_uid128_fpSinCosXTest(LOGICAL,127)@18
InvSinXIsXRR_uid128_fpSinCosXTest_a <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q;
InvSinXIsXRR_uid128_fpSinCosXTest_q <= not InvSinXIsXRR_uid128_fpSinCosXTest_a;
--signComp_uid129_fpSinCosXTest(LOGICAL,128)@18
signComp_uid129_fpSinCosXTest_a <= InvSinXIsXRR_uid128_fpSinCosXTest_q;
signComp_uid129_fpSinCosXTest_b <= InvSinXIsX_uid127_fpSinCosXTest_q;
signComp_uid129_fpSinCosXTest_c <= intXParity_uid49_fpSinCosXTest_b;
signComp_uid129_fpSinCosXTest_q <= signComp_uid129_fpSinCosXTest_a and signComp_uid129_fpSinCosXTest_b and signComp_uid129_fpSinCosXTest_c;
--signX_uid37_fpSinCosXTest(BITSELECT,36)@0
signX_uid37_fpSinCosXTest_in <= a;
signX_uid37_fpSinCosXTest_b <= signX_uid37_fpSinCosXTest_in(31 downto 31);
--ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a(DELAY,760)@0
ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => signX_uid37_fpSinCosXTest_b, xout => ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid130_fpSinCosXTest(LOGICAL,129)@18
signR_uid130_fpSinCosXTest_a <= ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q;
signR_uid130_fpSinCosXTest_b <= signComp_uid129_fpSinCosXTest_q;
signR_uid130_fpSinCosXTest_q <= signR_uid130_fpSinCosXTest_a xor signR_uid130_fpSinCosXTest_b;
--ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c(DELAY,766)@18
ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => signR_uid130_fpSinCosXTest_q, xout => ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--signRSinFull_uid133_fpSinCosXTest(LOGICAL,132)@20
signRSinFull_uid133_fpSinCosXTest_a <= InvExc_N_uid132_fpSinCosXTest_q;
signRSinFull_uid133_fpSinCosXTest_b <= InvExc_I_uid131_fpSinCosXTest_q;
signRSinFull_uid133_fpSinCosXTest_c <= ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q;
signRSinFull_uid133_fpSinCosXTest_q_i <= signRSinFull_uid133_fpSinCosXTest_a and signRSinFull_uid133_fpSinCosXTest_b and signRSinFull_uid133_fpSinCosXTest_c;
signRSinFull_uid133_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRSinFull_uid133_fpSinCosXTest_q, xin => signRSinFull_uid133_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c(DELAY,769)@21
ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signRSinFull_uid133_fpSinCosXTest_q, xout => ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor(LOGICAL,1359)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q <= not (ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a or ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b);
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top(CONSTANT,1342)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q <= "0100010";
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp(LOGICAL,1343)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q <= "1" when ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a = ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b else "0";
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg(REG,1344)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena(REG,1360)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q = "1") THEN
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd(LOGICAL,1361)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b <= en;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a and ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg(DELAY,1349)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => exp_uid9_fpSinCosXTest_b, xout => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt(COUNTER,1338)
-- every=1, low=0, high=34, step=1, init=1
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i = 33 THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i - 34;
ELSE
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i,6));
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg(REG,1339)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux(MUX,1340)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem(DUALMEM,1350)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 6,
numwords_a => 35,
width_b => 8,
widthad_b => 6,
numwords_b => 35,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia
);
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a(DELAY,1228)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1(REG,605)@35
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor(LOGICAL,1309)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q <= not (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a or ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena(REG,1310)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd(LOGICAL,1311)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b <= en;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a and ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b;
--oFracXRRSmallXRR_uid90_fpSinCosXTest(BITSELECT,89)@16
oFracXRRSmallXRR_uid90_fpSinCosXTest_in <= oFracXRR_uid43_uid43_fpSinCosXTest_q;
oFracXRRSmallXRR_uid90_fpSinCosXTest_b <= oFracXRRSmallXRR_uid90_fpSinCosXTest_in(53 downto 28);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg(DELAY,1299)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => oFracXRRSmallXRR_uid90_fpSinCosXTest_b, xout => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem(DUALMEM,1300)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 4,
numwords_a => 14,
width_b => 26,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia
);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq(25 downto 0);
--reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1(REG,577)@20
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
END IF;
END IF;
END PROCESS;
--zSin_uid60_fpSinCosXTest(MUX,59)@21
zSin_uid60_fpSinCosXTest_s <= reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q;
zSin_uid60_fpSinCosXTest: PROCESS (zSin_uid60_fpSinCosXTest_s, en, reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q, reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q)
BEGIN
CASE zSin_uid60_fpSinCosXTest_s IS
WHEN "0" => zSin_uid60_fpSinCosXTest_q <= reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q;
WHEN "1" => zSin_uid60_fpSinCosXTest_q <= reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q;
WHEN OTHERS => zSin_uid60_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--addr_uid81_fpSinCosXTest(BITSELECT,80)@21
addr_uid81_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q;
addr_uid81_fpSinCosXTest_b <= addr_uid81_fpSinCosXTest_in(64 downto 57);
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0(REG,595)@21
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q <= addr_uid81_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid398_tableGensinPiZ_lutmem(DUALMEM,529)@22
memoryC2_uid398_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC2_uid398_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC2_uid398_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q;
memoryC2_uid398_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC2_uid398_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid398_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid398_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid398_tableGensinPiZ_lutmem_iq,
address_a => memoryC2_uid398_tableGensinPiZ_lutmem_aa,
data_a => memoryC2_uid398_tableGensinPiZ_lutmem_ia
);
memoryC2_uid398_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC2_uid398_tableGensinPiZ_lutmem_q <= memoryC2_uid398_tableGensinPiZ_lutmem_iq(12 downto 0);
--reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1(REG,597)@24
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q <= memoryC2_uid398_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPsinPiZ_uid84_fpSinCosXTest(BITSELECT,83)@21
zPsinPiZ_uid84_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(56 downto 0);
zPsinPiZ_uid84_fpSinCosXTest_b <= zPsinPiZ_uid84_fpSinCosXTest_in(56 downto 42);
--yT1_uid406_polyEvalsinPiZ(BITSELECT,405)@21
yT1_uid406_polyEvalsinPiZ_in <= zPsinPiZ_uid84_fpSinCosXTest_b;
yT1_uid406_polyEvalsinPiZ_b <= yT1_uid406_polyEvalsinPiZ_in(14 downto 2);
--ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg(DELAY,1540)
ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => yT1_uid406_polyEvalsinPiZ_b, xout => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a(DELAY,1219)@21
ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q, xout => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0(REG,596)@24
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q <= ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid502_pT1_uid407_polyEvalsinPiZ(MULT,501)@25
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a),14)) * SIGNED(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b);
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a <= (others => '0');
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b <= (others => '0');
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a <= reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b <= reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q <= prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ(BITSELECT,502)@28
prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in <= prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q;
prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in(25 downto 12);
--highBBits_uid409_polyEvalsinPiZ(BITSELECT,408)@28
highBBits_uid409_polyEvalsinPiZ_in <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b;
highBBits_uid409_polyEvalsinPiZ_b <= highBBits_uid409_polyEvalsinPiZ_in(13 downto 1);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a(DELAY,1221)@21
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => addr_uid81_fpSinCosXTest_b, xout => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0(REG,598)@24
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid396_tableGensinPiZ_lutmem(DUALMEM,528)@25
memoryC1_uid396_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC1_uid396_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC1_uid396_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q;
memoryC1_uid396_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC1_uid396_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid396_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid396_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid396_tableGensinPiZ_lutmem_iq,
address_a => memoryC1_uid396_tableGensinPiZ_lutmem_aa,
data_a => memoryC1_uid396_tableGensinPiZ_lutmem_ia
);
memoryC1_uid396_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC1_uid396_tableGensinPiZ_lutmem_q <= memoryC1_uid396_tableGensinPiZ_lutmem_iq(20 downto 0);
--reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0(REG,599)@27
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q <= memoryC1_uid396_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid410_polyEvalsinPiZ(ADD,409)@28
sumAHighB_uid410_polyEvalsinPiZ_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q(20)) & reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q);
sumAHighB_uid410_polyEvalsinPiZ_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid409_polyEvalsinPiZ_b(12)) & highBBits_uid409_polyEvalsinPiZ_b);
sumAHighB_uid410_polyEvalsinPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid410_polyEvalsinPiZ_a) + SIGNED(sumAHighB_uid410_polyEvalsinPiZ_b));
sumAHighB_uid410_polyEvalsinPiZ_q <= sumAHighB_uid410_polyEvalsinPiZ_o(21 downto 0);
--lowRangeB_uid408_polyEvalsinPiZ(BITSELECT,407)@28
lowRangeB_uid408_polyEvalsinPiZ_in <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b(0 downto 0);
lowRangeB_uid408_polyEvalsinPiZ_b <= lowRangeB_uid408_polyEvalsinPiZ_in(0 downto 0);
--s1_uid408_uid411_polyEvalsinPiZ(BITJOIN,410)@28
s1_uid408_uid411_polyEvalsinPiZ_q <= sumAHighB_uid410_polyEvalsinPiZ_q & lowRangeB_uid408_polyEvalsinPiZ_b;
--reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1(REG,601)@28
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q <= s1_uid408_uid411_polyEvalsinPiZ_q;
END IF;
END IF;
END PROCESS;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor(LOGICAL,1551)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q <= not (ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a or ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b);
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena(REG,1552)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q = "1") THEN
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd(LOGICAL,1553)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b <= en;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a and ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg(DELAY,1541)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => zPsinPiZ_uid84_fpSinCosXTest_b, xout => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem(DUALMEM,1542)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq,
address_a => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa,
data_a => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia
);
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0 <= areset;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq(14 downto 0);
--reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0(REG,600)@28
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid505_pT2_uid413_polyEvalsinPiZ(MULT,504)@29
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a),16)) * SIGNED(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b);
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a <= (others => '0');
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b <= (others => '0');
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a <= reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b <= reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q <= prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ(BITSELECT,505)@32
prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in <= prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q;
prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in(37 downto 14);
--highBBits_uid415_polyEvalsinPiZ(BITSELECT,414)@32
highBBits_uid415_polyEvalsinPiZ_in <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b;
highBBits_uid415_polyEvalsinPiZ_b <= highBBits_uid415_polyEvalsinPiZ_in(23 downto 2);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor(LOGICAL,1564)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q <= not (ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a or ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena(REG,1565)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q = "1") THEN
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd(LOGICAL,1566)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b <= en;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a and ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b;
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg(DELAY,1554)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addr_uid81_fpSinCosXTest_b, xout => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem(DUALMEM,1555)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq,
address_a => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa,
data_a => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia
);
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0(REG,602)@28
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid394_tableGensinPiZ_lutmem(DUALMEM,527)@29
memoryC0_uid394_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC0_uid394_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC0_uid394_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q;
memoryC0_uid394_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC0_uid394_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid394_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid394_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid394_tableGensinPiZ_lutmem_iq,
address_a => memoryC0_uid394_tableGensinPiZ_lutmem_aa,
data_a => memoryC0_uid394_tableGensinPiZ_lutmem_ia
);
memoryC0_uid394_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC0_uid394_tableGensinPiZ_lutmem_q <= memoryC0_uid394_tableGensinPiZ_lutmem_iq(29 downto 0);
--reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0(REG,603)@31
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q <= memoryC0_uid394_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid416_polyEvalsinPiZ(ADD,415)@32
sumAHighB_uid416_polyEvalsinPiZ_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q(29)) & reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q);
sumAHighB_uid416_polyEvalsinPiZ_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid415_polyEvalsinPiZ_b(21)) & highBBits_uid415_polyEvalsinPiZ_b);
sumAHighB_uid416_polyEvalsinPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid416_polyEvalsinPiZ_a) + SIGNED(sumAHighB_uid416_polyEvalsinPiZ_b));
sumAHighB_uid416_polyEvalsinPiZ_q <= sumAHighB_uid416_polyEvalsinPiZ_o(30 downto 0);
--lowRangeB_uid414_polyEvalsinPiZ(BITSELECT,413)@32
lowRangeB_uid414_polyEvalsinPiZ_in <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b(1 downto 0);
lowRangeB_uid414_polyEvalsinPiZ_b <= lowRangeB_uid414_polyEvalsinPiZ_in(1 downto 0);
--s2_uid414_uid417_polyEvalsinPiZ(BITJOIN,416)@32
s2_uid414_uid417_polyEvalsinPiZ_q <= sumAHighB_uid416_polyEvalsinPiZ_q & lowRangeB_uid414_polyEvalsinPiZ_b;
--polyEvalSigsinPiZ_uid86_fpSinCosXTest(BITSELECT,85)@32
polyEvalSigsinPiZ_uid86_fpSinCosXTest_in <= s2_uid414_uid417_polyEvalsinPiZ_q(30 downto 0);
polyEvalSigsinPiZ_uid86_fpSinCosXTest_b <= polyEvalSigsinPiZ_uid86_fpSinCosXTest_in(30 downto 5);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b(DELAY,708)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--multSinOp2_uid91_fpSinCosXTest(MUX,90)@32
multSinOp2_uid91_fpSinCosXTest_s <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q;
multSinOp2_uid91_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSinOp2_uid91_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE multSinOp2_uid91_fpSinCosXTest_s IS
WHEN "0" => multSinOp2_uid91_fpSinCosXTest_q <= polyEvalSigsinPiZ_uid86_fpSinCosXTest_b;
WHEN "1" => multSinOp2_uid91_fpSinCosXTest_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => multSinOp2_uid91_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor(LOGICAL,1320)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q <= not (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a or ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b);
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena(REG,1321)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd(LOGICAL,1322)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b <= en;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a and ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b;
--cPi_uid71_fpSinCosXTest(CONSTANT,70)
cPi_uid71_fpSinCosXTest_q <= "11001001000011111101101011";
--LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest(BITSELECT,309)@27
LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q(63 downto 0);
LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in(63 downto 0);
--leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest(BITJOIN,310)@27
leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b & GND_q;
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor(LOGICAL,1433)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q <= not (ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a or ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b);
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena(REG,1434)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q = "1") THEN
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd(LOGICAL,1435)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b <= en;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a and ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b;
--X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest(BITSELECT,280)@21
X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(32 downto 0);
X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b <= X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in(32 downto 0);
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg(DELAY,1425)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem(DUALMEM,1426)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 33,
widthad_a => 1,
numwords_a => 2,
width_b => 33,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia
);
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq(32 downto 0);
--leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest(BITJOIN,281)@25
leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor(LOGICAL,1444)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q <= not (ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a or ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b);
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena(REG,1445)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q = "1") THEN
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd(LOGICAL,1446)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b <= en;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a and ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg(DELAY,1436)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => zSin_uid60_fpSinCosXTest_q, xout => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem(DUALMEM,1437)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 65,
widthad_a => 1,
numwords_a => 2,
width_b => 65,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia
);
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq(64 downto 0);
--rVStage_uid237_lzcZSin_uid66_fpSinCosXTest(BITSELECT,236)@21
rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q;
rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in(64 downto 1);
--vCount_uid238_lzcZSin_uid66_fpSinCosXTest(LOGICAL,237)@21
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid236_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g(DELAY,903)@22
ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid240_lzcZSin_uid66_fpSinCosXTest(BITSELECT,239)@21
vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(0 downto 0);
vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in(0 downto 0);
--ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b(DELAY,861)@21
ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cStage_uid241_lzcZSin_uid66_fpSinCosXTest(BITJOIN,240)@22
cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q <= ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q & mO_uid239_lzcZSin_uid66_fpSinCosXTest_q;
--ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c(DELAY,863)@21
ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid243_lzcZSin_uid66_fpSinCosXTest(MUX,242)@22
vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid243_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s, en, ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q, cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid245_lzcZSin_uid66_fpSinCosXTest(BITSELECT,244)@22
rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in(63 downto 32);
--vCount_uid246_lzcZSin_uid66_fpSinCosXTest(LOGICAL,245)@22
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f(DELAY,902)@23
ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid247_lzcZSin_uid66_fpSinCosXTest(BITSELECT,246)@22
vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q(31 downto 0);
vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in(31 downto 0);
--ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d(DELAY,870)@22
ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c(DELAY,869)@22
ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid249_lzcZSin_uid66_fpSinCosXTest(MUX,248)@23
vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid249_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s, en, ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q, ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q)
BEGIN
CASE vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q;
WHEN OTHERS => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid251_lzcZSin_uid66_fpSinCosXTest(BITSELECT,250)@23
rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in(31 downto 16);
--vCount_uid252_lzcZSin_uid66_fpSinCosXTest(LOGICAL,251)@23
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b else "0";
--reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4(REG,585)@23
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q <= vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e(DELAY,901)@24
ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid253_lzcZSin_uid66_fpSinCosXTest(BITSELECT,252)@23
vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q(15 downto 0);
vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in(15 downto 0);
--vStagei_uid255_lzcZSin_uid66_fpSinCosXTest(MUX,254)@23
vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid255_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s, en, rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b, vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b;
WHEN "1" => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid257_lzcZSin_uid66_fpSinCosXTest(BITSELECT,256)@23
rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in(15 downto 8);
--reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1(REG,580)@23
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q <= rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid258_lzcZSin_uid66_fpSinCosXTest(LOGICAL,257)@24
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a <= reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q;
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b else "0";
--ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d(DELAY,900)@24
ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid259_lzcZSin_uid66_fpSinCosXTest(BITSELECT,258)@23
vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q(7 downto 0);
vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3(REG,582)@23
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q <= vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid261_lzcZSin_uid66_fpSinCosXTest(MUX,260)@24
vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid261_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s, en, reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q, reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid263_lzcZSin_uid66_fpSinCosXTest(BITSELECT,262)@24
rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in(7 downto 4);
--vCount_uid264_lzcZSin_uid66_fpSinCosXTest(LOGICAL,263)@24
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid265_lzcZSin_uid66_fpSinCosXTest(BITSELECT,264)@24
vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q(3 downto 0);
vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in(3 downto 0);
--reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3(REG,584)@24
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q <= vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2(REG,583)@24
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid267_lzcZSin_uid66_fpSinCosXTest(MUX,266)@25
vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid267_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s, en, reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q, reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid269_lzcZSin_uid66_fpSinCosXTest(BITSELECT,268)@25
rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in(3 downto 2);
--vCount_uid270_lzcZSin_uid66_fpSinCosXTest(LOGICAL,269)@25
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b else "0";
--vStage_uid271_lzcZSin_uid66_fpSinCosXTest(BITSELECT,270)@25
vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q(1 downto 0);
vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in(1 downto 0);
--vStagei_uid273_lzcZSin_uid66_fpSinCosXTest(MUX,272)@25
vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid273_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s, en, rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b, vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b;
WHEN "1" => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid275_lzcZSin_uid66_fpSinCosXTest(BITSELECT,274)@25
rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in(1 downto 1);
--vCount_uid276_lzcZSin_uid66_fpSinCosXTest(LOGICAL,275)@25
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b <= GND_q;
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b else "0";
--r_uid277_lzcZSin_uid66_fpSinCosXTest(BITJOIN,276)@25
r_uid277_lzcZSin_uid66_fpSinCosXTest_q <= ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q & ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q & ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q & ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q & vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q & vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q & vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q;
--leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest(BITSELECT,284)@25
leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q;
leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in(6 downto 5);
--leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest(MUX,285)@25
leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s <= leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b;
leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s, en, ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest(BITSELECT,293)@25
LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(40 downto 0);
LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in(40 downto 0);
--leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest(BITJOIN,294)@25
leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b & leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5(REG,590)@25
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest(BITSELECT,290)@25
LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(48 downto 0);
LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in(48 downto 0);
--leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest(BITJOIN,291)@25
leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4(REG,589)@25
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest(BITSELECT,287)@25
LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(56 downto 0);
LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in(56 downto 0);
--leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest(BITJOIN,288)@25
leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3(REG,588)@25
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2(REG,587)@25
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest(BITSELECT,295)@25
leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1(REG,586)@25
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q <= leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest(MUX,296)@26
leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s <= reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q;
leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s, en, reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest(BITSELECT,304)@26
LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(58 downto 0);
LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b(DELAY,927)@26
ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest(BITJOIN,305)@27
leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q;
--LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest(BITSELECT,301)@26
LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(60 downto 0);
LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b(DELAY,925)@26
ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest(BITJOIN,302)@27
leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest(BITSELECT,298)@26
LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(62 downto 0);
LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in(62 downto 0);
--ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b(DELAY,923)@26
ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest(BITJOIN,299)@27
leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2(REG,592)@26
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest(BITSELECT,306)@25
leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in(2 downto 1);
--ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a(DELAY,1214)@25
ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1(REG,591)@26
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q <= ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest(MUX,307)@27
leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s <= reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q;
leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s, en, reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest(BITSELECT,311)@25
leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b(DELAY,937)@25
ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest(MUX,312)@27
leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s <= ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q;
leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s, en, leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "0" => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "1" => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--pHigh_uid72_fpSinCosXTest(BITSELECT,71)@27
pHigh_uid72_fpSinCosXTest_in <= leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q;
pHigh_uid72_fpSinCosXTest_b <= pHigh_uid72_fpSinCosXTest_in(64 downto 39);
--reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2(REG,594)@27
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q <= pHigh_uid72_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a(DELAY,1216)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1(REG,593)@27
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--p_uid73_fpSinCosXTest(MUX,72)@28
p_uid73_fpSinCosXTest_s <= reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q;
p_uid73_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p_uid73_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE p_uid73_fpSinCosXTest_s IS
WHEN "0" => p_uid73_fpSinCosXTest_q <= reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q;
WHEN "1" => p_uid73_fpSinCosXTest_q <= cPi_uid71_fpSinCosXTest_q;
WHEN OTHERS => p_uid73_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg(DELAY,1312)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => p_uid73_fpSinCosXTest_q, xout => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem(DUALMEM,1313)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 1,
numwords_a => 2,
width_b => 26,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq,
address_a => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa,
data_a => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia
);
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0 <= areset;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq(25 downto 0);
--mulSin_uid92_fpSinCosXTest(MULT,91)@33
mulSin_uid92_fpSinCosXTest_pr <= UNSIGNED(mulSin_uid92_fpSinCosXTest_a) * UNSIGNED(mulSin_uid92_fpSinCosXTest_b);
mulSin_uid92_fpSinCosXTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulSin_uid92_fpSinCosXTest_a <= (others => '0');
mulSin_uid92_fpSinCosXTest_b <= (others => '0');
mulSin_uid92_fpSinCosXTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulSin_uid92_fpSinCosXTest_a <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q;
mulSin_uid92_fpSinCosXTest_b <= multSinOp2_uid91_fpSinCosXTest_q;
mulSin_uid92_fpSinCosXTest_s1 <= STD_LOGIC_VECTOR(mulSin_uid92_fpSinCosXTest_pr);
END IF;
END IF;
END PROCESS;
mulSin_uid92_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulSin_uid92_fpSinCosXTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulSin_uid92_fpSinCosXTest_q <= mulSin_uid92_fpSinCosXTest_s1;
END IF;
END IF;
END PROCESS;
--normBitSin_uid93_fpSinCosXTest(BITSELECT,92)@36
normBitSin_uid93_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q;
normBitSin_uid93_fpSinCosXTest_b <= normBitSin_uid93_fpSinCosXTest_in(51 downto 51);
--join_uid99_fpSinCosXTest(BITJOIN,98)@36
join_uid99_fpSinCosXTest_q <= reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q & normBitSin_uid93_fpSinCosXTest_b;
--sinRndOp_uid100_uid101_fpSinCosXTest(BITJOIN,100)@36
sinRndOp_uid100_uid101_fpSinCosXTest_q <= join_uid99_fpSinCosXTest_q & cstAllZWF_uid7_fpSinCosXTest_q & VCC_q;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor(LOGICAL,1333)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q <= not (ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a or ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b);
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena(REG,1334)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q = "1") THEN
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd(LOGICAL,1335)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b <= en;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a and ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor(LOGICAL,1283)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q <= not (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a or ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b);
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena(REG,1284)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd(LOGICAL,1285)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a and ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg(DELAY,1273)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expXRR_uid38_fpSinCosXTest_b, xout => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem(DUALMEM,1274)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 9,
width_b => 8,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia
);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1(REG,604)@25
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--expSinHC_uid74_fpSinCosXTest(SUB,73)@26
expSinHC_uid74_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expSinHC_uid74_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q);
expSinHC_uid74_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSinHC_uid74_fpSinCosXTest_a) - UNSIGNED(expSinHC_uid74_fpSinCosXTest_b));
expSinHC_uid74_fpSinCosXTest_q <= expSinHC_uid74_fpSinCosXTest_o(8 downto 0);
--expSinHCR_uid75_fpSinCosXTest(BITSELECT,74)@26
expSinHCR_uid75_fpSinCosXTest_in <= expSinHC_uid74_fpSinCosXTest_q(7 downto 0);
expSinHCR_uid75_fpSinCosXTest_b <= expSinHCR_uid75_fpSinCosXTest_in(7 downto 0);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b(DELAY,695)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expPSin_uid76_fpSinCosXTest(MUX,75)@26
expPSin_uid76_fpSinCosXTest_s <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q;
expPSin_uid76_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expPSin_uid76_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expPSin_uid76_fpSinCosXTest_s IS
WHEN "0" => expPSin_uid76_fpSinCosXTest_q <= expSinHCR_uid75_fpSinCosXTest_b;
WHEN "1" => expPSin_uid76_fpSinCosXTest_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => expPSin_uid76_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg(DELAY,1323)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expPSin_uid76_fpSinCosXTest_q, xout => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem(DUALMEM,1324)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 7,
width_b => 8,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia
);
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq(7 downto 0);
--fracRSinPreRndHigh_uid95_fpSinCosXTest(BITSELECT,94)@36
fracRSinPreRndHigh_uid95_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q(50 downto 0);
fracRSinPreRndHigh_uid95_fpSinCosXTest_b <= fracRSinPreRndHigh_uid95_fpSinCosXTest_in(50 downto 27);
--fracRSinPreRndLow_uid96_fpSinCosXTest(BITSELECT,95)@36
fracRSinPreRndLow_uid96_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q(49 downto 0);
fracRSinPreRndLow_uid96_fpSinCosXTest_b <= fracRSinPreRndLow_uid96_fpSinCosXTest_in(49 downto 26);
--fracRSinPreRnd_uid97_fpSinCosXTest(MUX,96)@36
fracRSinPreRnd_uid97_fpSinCosXTest_s <= normBitSin_uid93_fpSinCosXTest_b;
fracRSinPreRnd_uid97_fpSinCosXTest: PROCESS (fracRSinPreRnd_uid97_fpSinCosXTest_s, en, fracRSinPreRndLow_uid96_fpSinCosXTest_b, fracRSinPreRndHigh_uid95_fpSinCosXTest_b)
BEGIN
CASE fracRSinPreRnd_uid97_fpSinCosXTest_s IS
WHEN "0" => fracRSinPreRnd_uid97_fpSinCosXTest_q <= fracRSinPreRndLow_uid96_fpSinCosXTest_b;
WHEN "1" => fracRSinPreRnd_uid97_fpSinCosXTest_q <= fracRSinPreRndHigh_uid95_fpSinCosXTest_b;
WHEN OTHERS => fracRSinPreRnd_uid97_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracRSinPreRnd_uid98_uid98_fpSinCosXTest(BITJOIN,97)@36
expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q & fracRSinPreRnd_uid97_fpSinCosXTest_q;
--expFracRSin_uid102_fpSinCosXTest(ADD,101)@36
expFracRSin_uid102_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q);
expFracRSin_uid102_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0000000" & sinRndOp_uid100_uid101_fpSinCosXTest_q);
expFracRSin_uid102_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRSin_uid102_fpSinCosXTest_a) + UNSIGNED(expFracRSin_uid102_fpSinCosXTest_b));
expFracRSin_uid102_fpSinCosXTest_q <= expFracRSin_uid102_fpSinCosXTest_o(32 downto 0);
--expRCompSin_uid104_fpSinCosXTest(BITSELECT,103)@36
expRCompSin_uid104_fpSinCosXTest_in <= expFracRSin_uid102_fpSinCosXTest_q(31 downto 0);
expRCompSin_uid104_fpSinCosXTest_b <= expRCompSin_uid104_fpSinCosXTest_in(31 downto 24);
--reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2(REG,607)@36
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q <= expRCompSin_uid104_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor(LOGICAL,1537)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q <= not (ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a or ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b);
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena(REG,1538)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q = "1") THEN
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd(LOGICAL,1539)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b <= en;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a and ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b;
--expXIsZero_uid10_fpSinCosXTest(LOGICAL,9)@0
expXIsZero_uid10_fpSinCosXTest_a <= exp_uid9_fpSinCosXTest_b;
expXIsZero_uid10_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
expXIsZero_uid10_fpSinCosXTest_q <= "1" when expXIsZero_uid10_fpSinCosXTest_a = expXIsZero_uid10_fpSinCosXTest_b else "0";
--ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b(DELAY,746)@0
ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => expXIsZero_uid10_fpSinCosXTest_q, xout => ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excSelBitsSin_uid118_fpSinCosXTest(BITJOIN,117)@19
excSelBitsSin_uid118_fpSinCosXTest_q <= excRNaN_uid117_fpSinCosXTest_q & ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q & ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg(DELAY,1527)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => excSelBitsSin_uid118_fpSinCosXTest_q, xout => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem(DUALMEM,1528)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 4,
numwords_a => 14,
width_b => 3,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq,
address_a => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa,
data_a => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia
);
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0 <= areset;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq(2 downto 0);
--reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0(REG,533)@35
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--excSelSin_uid119_fpSinCosXTest(LOOKUP,118)@36
excSelSin_uid119_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excSelSin_uid119_fpSinCosXTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q) IS
WHEN "000" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN "001" => excSelSin_uid119_fpSinCosXTest_q <= "01";
WHEN "010" => excSelSin_uid119_fpSinCosXTest_q <= "10";
WHEN "011" => excSelSin_uid119_fpSinCosXTest_q <= "10";
WHEN "100" => excSelSin_uid119_fpSinCosXTest_q <= "11";
WHEN "101" => excSelSin_uid119_fpSinCosXTest_q <= "11";
WHEN "110" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN "111" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN OTHERS =>
excSelSin_uid119_fpSinCosXTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRPostExcSin_uid126_fpSinCosXTest(MUX,125)@37
expRPostExcSin_uid126_fpSinCosXTest_s <= excSelSin_uid119_fpSinCosXTest_q;
expRPostExcSin_uid126_fpSinCosXTest: PROCESS (expRPostExcSin_uid126_fpSinCosXTest_s, en, reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q, ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q, cstAllZWE_uid8_fpSinCosXTest_q, cstAllOWE_uid6_fpSinCosXTest_q)
BEGIN
CASE expRPostExcSin_uid126_fpSinCosXTest_s IS
WHEN "00" => expRPostExcSin_uid126_fpSinCosXTest_q <= reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q;
WHEN "01" => expRPostExcSin_uid126_fpSinCosXTest_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q;
WHEN "10" => expRPostExcSin_uid126_fpSinCosXTest_q <= cstAllZWE_uid8_fpSinCosXTest_q;
WHEN "11" => expRPostExcSin_uid126_fpSinCosXTest_q <= cstAllOWE_uid6_fpSinCosXTest_q;
WHEN OTHERS => expRPostExcSin_uid126_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor(LOGICAL,1346)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q <= not (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a or ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b);
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena(REG,1347)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd(LOGICAL,1348)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b <= en;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a and ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg(DELAY,1336)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => frac_uid13_fpSinCosXTest_b, xout => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem(DUALMEM,1337)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 6,
numwords_a => 35,
width_b => 23,
widthad_b => 6,
numwords_b => 35,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia
);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq(22 downto 0);
--fracRCompSin_uid103_fpSinCosXTest(BITSELECT,102)@36
fracRCompSin_uid103_fpSinCosXTest_in <= expFracRSin_uid102_fpSinCosXTest_q(23 downto 0);
fracRCompSin_uid103_fpSinCosXTest_b <= fracRCompSin_uid103_fpSinCosXTest_in(23 downto 1);
--reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2(REG,606)@36
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q <= fracRCompSin_uid103_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--fracRPostExcSin_uid122_fpSinCosXTest(MUX,121)@37
fracRPostExcSin_uid122_fpSinCosXTest_s <= excSelSin_uid119_fpSinCosXTest_q;
fracRPostExcSin_uid122_fpSinCosXTest: PROCESS (fracRPostExcSin_uid122_fpSinCosXTest_s, en, reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q, cstAllZWF_uid7_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q)
BEGIN
CASE fracRPostExcSin_uid122_fpSinCosXTest_s IS
WHEN "00" => fracRPostExcSin_uid122_fpSinCosXTest_q <= reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q;
WHEN "01" => fracRPostExcSin_uid122_fpSinCosXTest_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q;
WHEN "10" => fracRPostExcSin_uid122_fpSinCosXTest_q <= cstAllZWF_uid7_fpSinCosXTest_q;
WHEN "11" => fracRPostExcSin_uid122_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN OTHERS => fracRPostExcSin_uid122_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpSin_uid134_fpSinCosXTest(BITJOIN,133)@37
fpSin_uid134_fpSinCosXTest_q <= ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q & expRPostExcSin_uid126_fpSinCosXTest_q & fracRPostExcSin_uid122_fpSinCosXTest_q;
--xOut(GPOUT,4)@37
s <= fpSin_uid134_fpSinCosXTest_q;
c <= fpCos_uid162_fpSinCosXTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
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-- software and tools, and its AMPP partner logic functions, and any output
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-- terms and conditions of the Altera Program License Subscription Agreement,
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-- agreement, including, without limitation, that your use is for the sole
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-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_sincos_s5
-- VHDL created on Wed Mar 27 09:55:14 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_sincos_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
s : out std_logic_vector(31 downto 0);
c : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_sincos_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid8_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid22_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid23_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShift_uid24_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid25_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid26_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstZwShiftP1_uid27_fpSinCosXTest_q : std_logic_vector (13 downto 0);
signal cstNaNwF_uid32_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal cstZmwFRRPwSM1_uid52_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal cPi_uid71_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal p_uid73_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal p_uid73_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal expPSin_uid76_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal expPSin_uid76_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal multSinOp2_uid91_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal multSinOp2_uid91_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_a : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_s1 : std_logic_vector (51 downto 0);
signal mulSin_uid92_fpSinCosXTest_pr : UNSIGNED (51 downto 0);
signal mulSin_uid92_fpSinCosXTest_q : std_logic_vector (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_a : std_logic_vector (25 downto 0);
signal mulCos_uid105_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal mulCos_uid105_fpSinCosXTest_s1 : std_logic_vector (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_pr : UNSIGNED (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_q : std_logic_vector (51 downto 0);
signal excSelSin_uid119_fpSinCosXTest_q : std_logic_vector(1 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expSelectorCos_uid145_fpSinCosXTest_q : std_logic_vector(1 downto 0);
signal signRCond2_uid152_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_d : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_d : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q : std_logic_vector (29 downto 0);
signal leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal zs_uid236_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal mO_uid239_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (62 downto 0);
signal zs_uid244_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal zs_uid250_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (5 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(63 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(63 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (47 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a : std_logic_vector (12 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr : SIGNED (26 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q : std_logic_vector (25 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a : std_logic_vector (14 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b : std_logic_vector (22 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr : SIGNED (38 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q : std_logic_vector (37 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a : std_logic_vector (12 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr : SIGNED (26 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q : std_logic_vector (25 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a : std_logic_vector (14 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b : std_logic_vector (22 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr : SIGNED (38 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q : std_logic_vector (37 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0 : std_logic;
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0 : std_logic;
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q : std_logic_vector (39 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a : std_logic_vector(81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b : std_logic_vector(81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o : std_logic_vector (81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q : std_logic_vector (81 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC0_uid394_tableGensinPiZ_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC1_uid396_tableGensinPiZ_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC2_uid398_tableGensinPiZ_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_q : std_logic_vector (12 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC0_uid400_tableGencosPiZ_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC1_uid402_tableGencosPiZ_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC2_uid404_tableGencosPiZ_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_q : std_logic_vector (12 downto 0);
signal reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q : std_logic_vector (2 downto 0);
signal reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q : std_logic_vector (39 downto 0);
signal reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (39 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q : std_logic_vector (26 downto 0);
signal reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (77 downto 0);
signal reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q : std_logic_vector (67 downto 0);
signal reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q : std_logic_vector (66 downto 0);
signal reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q : std_logic_vector (65 downto 0);
signal reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q : std_logic_vector (67 downto 0);
signal reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q : std_logic_vector (25 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q : std_logic_vector (12 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q : std_logic_vector (20 downto 0);
signal reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q : std_logic_vector (22 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q : std_logic_vector (29 downto 0);
signal reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q : std_logic_vector (6 downto 0);
signal reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q : std_logic_vector (22 downto 0);
signal reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q : std_logic_vector (0 downto 0);
signal reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q : std_logic_vector (12 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q : std_logic_vector (20 downto 0);
signal reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q : std_logic_vector (22 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q : std_logic_vector (29 downto 0);
signal reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q : std_logic_vector (25 downto 0);
signal reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q : std_logic_vector (25 downto 0);
signal reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q : std_logic_vector (6 downto 0);
signal reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q : std_logic_vector (22 downto 0);
signal reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q : std_logic_vector (3 downto 0);
signal reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q : std_logic_vector (52 downto 0);
signal ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q : std_logic_vector (65 downto 0);
signal ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q : std_logic_vector (67 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (7 downto 0);
signal ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (66 downto 0);
signal ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (65 downto 0);
signal ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (64 downto 0);
signal ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q : std_logic_vector (63 downto 0);
signal ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q : std_logic_vector (31 downto 0);
signal ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (58 downto 0);
signal ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q : std_logic_vector (63 downto 0);
signal ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q : std_logic_vector (31 downto 0);
signal ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (58 downto 0);
signal ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (76 downto 0);
signal ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (75 downto 0);
signal ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (74 downto 0);
signal ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q : std_logic_vector (12 downto 0);
signal ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q : std_logic_vector (53 downto 0);
signal ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q : std_logic_vector (12 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0 : std_logic;
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q : signal is true;
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q : std_logic_vector (6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0 : std_logic;
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q : signal is true;
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q : signal is true;
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0 : std_logic;
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0 : std_logic;
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0 : std_logic;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq : std_logic;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q : signal is true;
signal sinXIsXRR_uid41_fpSinCosXTest_a : std_logic_vector(11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_b : std_logic_vector(11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_o : std_logic_vector (11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_a : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_b : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_o : std_logic_vector (11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal yIsZero_uid51_fpSinCosXTest_a : std_logic_vector(65 downto 0);
signal yIsZero_uid51_fpSinCosXTest_b : std_logic_vector(65 downto 0);
signal yIsZero_uid51_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal pad_one_uid55_fpSinCosXTest_q : std_logic_vector (66 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_a : std_logic_vector(70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_b : std_logic_vector(70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_o : std_logic_vector (70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_c : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal InvCmpYToOneMinusY_uid61_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCmpYToOneMinusY_uid61_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid127_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid127_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvSinXIsXRR_uid128_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsXRR_uid128_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid131_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid131_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid132_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid132_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid136_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid136_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvCosXONe_uid149_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCosXONe_uid149_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid151_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid151_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvIntXParity_uid155_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvIntXParity_uid155_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal oFracXRR_uid43_uid43_fpSinCosXTest_q : std_logic_vector (53 downto 0);
signal half_uid53_fpSinCosXTest_q : std_logic_vector (65 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal exp_uid9_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal exp_uid9_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal frac_uid13_fpSinCosXTest_in : std_logic_vector (22 downto 0);
signal frac_uid13_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal signX_uid37_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal signX_uid37_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal expFracX_uid166_px_uid33_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal expFracX_uid166_px_uid33_fpSinCosXTest_b : std_logic_vector (30 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_q : std_logic_vector (9 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_a : std_logic_vector(65 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_b : std_logic_vector(65 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_a : std_logic_vector(67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_b : std_logic_vector(67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_o : std_logic_vector (67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal zSin_uid60_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal zSin_uid60_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal zCos_uid64_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal zCos_uid64_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal expSinHC_uid74_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal excRNaN_uid117_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid117_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid117_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracRPostExcSin_uid122_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExcSin_uid122_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal expRPostExcSin_uid126_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExcSin_uid126_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracRPostExcCos_uid142_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExcCos_uid142_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal expRPostExcCos_uid147_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExcCos_uid147_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cosXONe_uid148_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal cosXONe_uid148_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal cosXONe_uid148_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal finalExp_uid209_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal finalExp_uid209_rrx_uid34_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal extendedFracX_uid47_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal normBitSin_uid93_fpSinCosXTest_in : std_logic_vector (51 downto 0);
signal normBitSin_uid93_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal fracRSinPreRndHigh_uid95_fpSinCosXTest_in : std_logic_vector (50 downto 0);
signal fracRSinPreRndHigh_uid95_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracRSinPreRndLow_uid96_fpSinCosXTest_in : std_logic_vector (49 downto 0);
signal fracRSinPreRndLow_uid96_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal normBitCos_uid106_fpSinCosXTest_in : std_logic_vector (51 downto 0);
signal normBitCos_uid106_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal fracRCosPreRndHigh_uid108_fpSinCosXTest_in : std_logic_vector (50 downto 0);
signal fracRCosPreRndHigh_uid108_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracRCosPreRndLow_uid109_fpSinCosXTest_in : std_logic_vector (49 downto 0);
signal fracRCosPreRndLow_uid109_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q : std_logic_vector (52 downto 0);
signal leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b : std_logic_vector (23 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int : std_logic_vector (80 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q : std_logic_vector (80 downto 0);
signal os_uid196_rrx_uid34_fpSinCosXTest_q : std_logic_vector (79 downto 0);
signal leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal join_uid99_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal join_uid141_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal zSinYBottom_uid59_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal zSinYBottom_uid59_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal zSinOMyBottom_uid58_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal zSinOMyBottom_uid58_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal excSelBitsSin_uid118_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal fpSin_uid134_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal join_uid143_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal fpCos_uid162_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int : std_logic_vector (107 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q : std_logic_vector (107 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal fracX_uid187_rrx_uid34_fpSinCosXTest_in : std_logic_vector (22 downto 0);
signal fracX_uid187_rrx_uid34_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal oFracXRRSmallXRR_uid90_fpSinCosXTest_in : std_logic_vector (53 downto 0);
signal oFracXRRSmallXRR_uid90_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal R_uid167_px_uid33_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal InvFracXIsZero_uid16_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid16_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fxpXShiftVal_uid46_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal fxpXShiftVal_uid46_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal addr_uid81_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal addr_uid81_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal zPsinPiZ_uid84_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal zPsinPiZ_uid84_fpSinCosXTest_b : std_logic_vector (14 downto 0);
signal rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (32 downto 0);
signal addr_uid83_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal addr_uid83_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal zPcosPiZ_uid87_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal zPcosPiZ_uid87_fpSinCosXTest_b : std_logic_vector (14 downto 0);
signal rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (32 downto 0);
signal expSinHCR_uid75_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expSinHCR_uid75_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal expPCos_uid79_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expPCos_uid79_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (66 downto 0);
signal LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (66 downto 0);
signal LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (65 downto 0);
signal LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (58 downto 0);
signal rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (58 downto 0);
signal rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (76 downto 0);
signal LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (76 downto 0);
signal LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (75 downto 0);
signal LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (75 downto 0);
signal LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (74 downto 0);
signal LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (74 downto 0);
signal X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (59 downto 0);
signal X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (59 downto 0);
signal X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (55 downto 0);
signal X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (55 downto 0);
signal fracRSinPreRnd_uid97_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal fracRSinPreRnd_uid97_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal fracRCosPreRnd_uid110_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal fracRCosPreRnd_uid110_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal cosRndOp_uid112_uid113_fpSinCosXTest_q : std_logic_vector (24 downto 0);
signal rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal lowRangeB_uid408_polyEvalsinPiZ_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid408_polyEvalsinPiZ_b : std_logic_vector (0 downto 0);
signal highBBits_uid409_polyEvalsinPiZ_in : std_logic_vector (13 downto 0);
signal highBBits_uid409_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid414_polyEvalsinPiZ_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid414_polyEvalsinPiZ_b : std_logic_vector (1 downto 0);
signal highBBits_uid415_polyEvalsinPiZ_in : std_logic_vector (23 downto 0);
signal highBBits_uid415_polyEvalsinPiZ_b : std_logic_vector (21 downto 0);
signal lowRangeB_uid421_polyEvalcosPiZ_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid421_polyEvalcosPiZ_b : std_logic_vector (0 downto 0);
signal highBBits_uid422_polyEvalcosPiZ_in : std_logic_vector (13 downto 0);
signal highBBits_uid422_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid427_polyEvalcosPiZ_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid427_polyEvalcosPiZ_b : std_logic_vector (1 downto 0);
signal highBBits_uid428_polyEvalcosPiZ_in : std_logic_vector (23 downto 0);
signal highBBits_uid428_polyEvalcosPiZ_b : std_logic_vector (21 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in : std_logic_vector (80 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b : std_logic_vector (26 downto 0);
signal fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in : std_logic_vector (76 downto 0);
signal fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b : std_logic_vector (52 downto 0);
signal intXParity_uid49_fpSinCosXTest_in : std_logic_vector (67 downto 0);
signal intXParity_uid49_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal y_uid50_fpSinCosXTest_in : std_logic_vector (66 downto 0);
signal y_uid50_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal sinRndOp_uid100_uid101_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal expSelBitsCos_uid144_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a : std_logic_vector(108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b : std_logic_vector(108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o : std_logic_vector (108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q : std_logic_vector (108 downto 0);
signal oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal expX_uid186_rrx_uid34_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal expX_uid186_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal exc_N_uid17_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal yT1_uid406_polyEvalsinPiZ_in : std_logic_vector (14 downto 0);
signal yT1_uid406_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal yT1_uid419_polyEvalcosPiZ_in : std_logic_vector (14 downto 0);
signal yT1_uid419_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_a : std_logic_vector(32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_b : std_logic_vector(32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_o : std_logic_vector (32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_q : std_logic_vector (30 downto 0);
signal finalFrac_uid208_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal finalFrac_uid208_rrx_uid34_fpSinCosXTest_q : std_logic_vector (52 downto 0);
signal signComp_uid129_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_a : std_logic_vector(32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_b : std_logic_vector(32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_o : std_logic_vector (32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_q : std_logic_vector (32 downto 0);
signal leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal multFracBits_uid199_rrx_uid34_fpSinCosXTest_in : std_logic_vector (77 downto 0);
signal multFracBits_uid199_rrx_uid34_fpSinCosXTest_b : std_logic_vector (77 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b : std_logic_vector (26 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (5 downto 0);
signal fracRCompCos_uid115_fpSinCosXTest_in : std_logic_vector (23 downto 0);
signal fracRCompCos_uid115_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal expRCompSin_uid116_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal expRCompSin_uid116_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal s1_uid408_uid411_polyEvalsinPiZ_q : std_logic_vector (22 downto 0);
signal s2_uid414_uid417_polyEvalsinPiZ_q : std_logic_vector (32 downto 0);
signal s1_uid421_uid424_polyEvalcosPiZ_q : std_logic_vector (22 downto 0);
signal s2_uid427_uid430_polyEvalcosPiZ_q : std_logic_vector (32 downto 0);
signal RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q : std_logic_vector (61 downto 0);
signal signR_uid130_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signR_uid130_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signR_uid130_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal fracRCompSin_uid103_fpSinCosXTest_in : std_logic_vector (23 downto 0);
signal fracRCompSin_uid103_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal expRCompSin_uid104_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal expRCompSin_uid104_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in : std_logic_vector (77 downto 0);
signal multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (61 downto 0);
signal X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (61 downto 0);
signal X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (45 downto 0);
signal X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (45 downto 0);
signal X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (29 downto 0);
signal X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (29 downto 0);
signal expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal polyEvalSigsinPiZ_uid86_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal polyEvalSigsinPiZ_uid86_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal polyEvalSigcosPiZ_uid89_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal polyEvalSigcosPiZ_uid89_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal expXRR_uid38_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal expXRR_uid38_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal fracXRR_uid39_fpSinCosXTest_in : std_logic_vector (52 downto 0);
signal fracXRR_uid39_fpSinCosXTest_b : std_logic_vector (52 downto 0);
signal pHigh_uid72_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal pHigh_uid72_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal pCos_uid77_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal pCos_uid77_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal r_uid277_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (6 downto 0);
signal r_uid356_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (6 downto 0);
signal expCompOut_uid205_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expCompOut_uid205_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (73 downto 0);
signal LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (73 downto 0);
signal LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (69 downto 0);
signal LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (69 downto 0);
signal LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (65 downto 0);
signal LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (56 downto 0);
signal LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (48 downto 0);
signal LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (48 downto 0);
signal LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (40 downto 0);
signal LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (40 downto 0);
signal LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (56 downto 0);
signal LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (48 downto 0);
signal LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (48 downto 0);
signal LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (40 downto 0);
signal LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (40 downto 0);
signal leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
begin
--xIn(GPIN,3)@0
--GND(CONSTANT,0)
GND_q <= "0";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable(LOGICAL,1282)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q <= not ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor(LOGICAL,1422)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q <= not (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a or ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b);
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top(CONSTANT,1418)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q <= "01011";
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp(LOGICAL,1419)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q <= "1" when ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a = ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b else "0";
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg(REG,1420)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena(REG,1423)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd(LOGICAL,1424)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b <= en;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a and ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b;
--expFracX_uid166_px_uid33_fpSinCosXTest(BITSELECT,165)@0
expFracX_uid166_px_uid33_fpSinCosXTest_in <= a(30 downto 0);
expFracX_uid166_px_uid33_fpSinCosXTest_b <= expFracX_uid166_px_uid33_fpSinCosXTest_in(30 downto 0);
--R_uid167_px_uid33_fpSinCosXTest(BITJOIN,166)@0
R_uid167_px_uid33_fpSinCosXTest_q <= GND_q & expFracX_uid166_px_uid33_fpSinCosXTest_b;
--expX_uid186_rrx_uid34_fpSinCosXTest(BITSELECT,185)@0
expX_uid186_rrx_uid34_fpSinCosXTest_in <= R_uid167_px_uid33_fpSinCosXTest_q(30 downto 0);
expX_uid186_rrx_uid34_fpSinCosXTest_b <= expX_uid186_rrx_uid34_fpSinCosXTest_in(30 downto 23);
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg(DELAY,1412)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid186_rrx_uid34_fpSinCosXTest_b, xout => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt(COUNTER,1414)
-- every=1, low=0, high=11, step=1, init=1
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i = 10 THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i - 11;
ELSE
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg(REG,1415)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux(MUX,1416)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem(DUALMEM,1413)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 12,
width_b => 8,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia
);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--zs_uid244_lzcZSin_uid66_fpSinCosXTest(CONSTANT,243)
zs_uid244_lzcZSin_uid66_fpSinCosXTest_q <= "00000000000000000000000000000000";
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor(LOGICAL,1396)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q <= not (ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a or ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b);
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg(REG,1318)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena(REG,1397)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q = "1") THEN
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd(LOGICAL,1398)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b <= en;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a and ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg(DELAY,1388)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid167_px_uid33_fpSinCosXTest_q, xout => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt(COUNTER,1314)
-- every=1, low=0, high=1, step=1, init=1
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i,1));
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg(REG,1315)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux(MUX,1316)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s <= en;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux: PROCESS (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s, ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q, ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q)
BEGIN
CASE ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s IS
WHEN "0" => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
WHEN "1" => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem(DUALMEM,1389)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 1,
numwords_a => 2,
width_b => 32,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq,
address_a => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa,
data_a => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia
);
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0 <= areset;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq(31 downto 0);
--fracX_uid187_rrx_uid34_fpSinCosXTest(BITSELECT,186)@4
fracX_uid187_rrx_uid34_fpSinCosXTest_in <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q(22 downto 0);
fracX_uid187_rrx_uid34_fpSinCosXTest_b <= fracX_uid187_rrx_uid34_fpSinCosXTest_in(22 downto 0);
--oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest(BITJOIN,196)@4
oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q <= VCC_q & fracX_uid187_rrx_uid34_fpSinCosXTest_b;
--prod_uid198_rrx_uid34_fpSinCosXTest_b_0(BITSELECT,518)@4
prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in <= STD_LOGIC_VECTOR("000" & oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q);
prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b <= prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in(26 downto 0);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1(REG,539)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q <= prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShift_uid24_fpSinCosXTest(CONSTANT,23)
cstBiasMwShift_uid24_fpSinCosXTest_q <= "01110011";
--expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest(SUB,191)@0
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expX_uid186_rrx_uid34_fpSinCosXTest_b);
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0" & cstBiasMwShift_uid24_fpSinCosXTest_q);
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b));
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q <= expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o(8 downto 0);
--expXTableAddr_uid193_rrx_uid34_fpSinCosXTest(BITSELECT,192)@0
expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in <= expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q(7 downto 0);
expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b <= expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0(REG,534)@0
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q <= expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem(DUALMEM,514)@1
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia <= (others => '0');
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa <= (others => '0');
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab <= reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q;
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq,
address_a => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa,
data_a => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia
);
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0 <= areset;
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q <= rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1(REG,537)@3
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q <= rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem(DUALMEM,513)@1
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia <= (others => '0');
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa <= (others => '0');
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab <= reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q;
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq,
address_a => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa,
data_a => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia
);
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0 <= areset;
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q <= rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0(REG,536)@3
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q <= rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid196_rrx_uid34_fpSinCosXTest(BITJOIN,195)@4
os_uid196_rrx_uid34_fpSinCosXTest_q <= reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q & reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q;
--prod_uid198_rrx_uid34_fpSinCosXTest_a_2(BITSELECT,517)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in <= STD_LOGIC_VECTOR("0" & os_uid196_rrx_uid34_fpSinCosXTest_q);
prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in(80 downto 54);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0(REG,542)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0(MULT,521)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1;
END IF;
END IF;
END PROCESS;
--ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a(DELAY,1145)@8
ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a : dspba_delay
GENERIC MAP ( width => 54, depth => 1 )
PORT MAP ( xin => prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q, xout => ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--prod_uid198_rrx_uid34_fpSinCosXTest_align_2(BITSHIFT,524)@9
prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int <= ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int(107 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_a_1(BITSELECT,516)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in <= os_uid196_rrx_uid34_fpSinCosXTest_q(53 downto 0);
prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in(53 downto 27);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0(REG,540)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0(MULT,520)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_align_1(BITSHIFT,523)@8
prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int <= prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q & "000000000000000000000000000";
prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int(80 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_a_0(BITSELECT,515)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in <= os_uid196_rrx_uid34_fpSinCosXTest_q(26 downto 0);
prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in(26 downto 0);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0(REG,538)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0(MULT,519)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_align_0(BITSHIFT,522)@8
prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int <= prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int(53 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0(ADD,525)@8
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a <= STD_LOGIC_VECTOR("0000000000000000000000000000" & prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b <= STD_LOGIC_VECTOR("0" & prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a) + UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b));
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o(81 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0(ADD,526)@9
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a <= STD_LOGIC_VECTOR("000000000000000000000000000" & prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b <= STD_LOGIC_VECTOR("0" & prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a) + UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b));
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o(108 downto 0);
--multFracBits_uid199_rrx_uid34_fpSinCosXTest(BITSELECT,198)@9
multFracBits_uid199_rrx_uid34_fpSinCosXTest_in <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q(77 downto 0);
multFracBits_uid199_rrx_uid34_fpSinCosXTest_b <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_in(77 downto 0);
--multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest(BITSELECT,199)@9
multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b;
multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b <= multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in(77 downto 46);
--reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1(REG,544)@9
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,433)@10
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a(DELAY,1178)@10
ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xout => ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5(REG,555)@12
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q <= ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q;
END IF;
END IF;
END PROCESS;
--zs_uid250_lzcZSin_uid66_fpSinCosXTest(CONSTANT,249)
zs_uid250_lzcZSin_uid66_fpSinCosXTest_q <= "0000000000000000";
--mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest(CONSTANT,434)
mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "11111111111111111111111111111111";
--vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,436)@10
vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q, mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,438)@10
rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in(31 downto 16);
--reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1(REG,546)@10
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,439)@11
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4(REG,554)@11
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q <= vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e(DELAY,1081)@12
ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWE_uid8_fpSinCosXTest(CONSTANT,7)
cstAllZWE_uid8_fpSinCosXTest_q <= "00000000";
--vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,440)@10
vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q(15 downto 0);
vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in(15 downto 0);
--reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,548)@10
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,442)@11
vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q, reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,444)@11
rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in(15 downto 8);
--vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,445)@11
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i <= "1" when vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xin => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d(DELAY,1080)@12
ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xout => ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest(CONSTANT,212)
leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q <= "0000";
--vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,446)@11
vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q(7 downto 0);
vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,550)@11
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,549)@11
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,448)@12
vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q, reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,450)@12
rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in(7 downto 4);
--vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,451)@12
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,553)@12
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest(CONSTANT,226)
leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q <= "00";
--vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,452)@12
vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q(3 downto 0);
vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in(3 downto 0);
--vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,454)@12
vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b, vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
WHEN "1" => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,456)@12
rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in(3 downto 2);
--vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,457)@12
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i <= "1" when vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xin => vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,458)@12
vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q(1 downto 0);
vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in(1 downto 0);
--reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,552)@12
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,551)@12
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,460)@13
vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q, reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,462)@13
rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in(1 downto 1);
--vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,463)@13
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= GND_q;
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest(BITJOIN,464)@13
r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q & ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q & ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q & reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q & vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q & vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
--cstBiasM1_uid23_fpSinCosXTest(CONSTANT,22)
cstBiasM1_uid23_fpSinCosXTest_q <= "01111110";
--expCompOutExt_uid204_rrx_uid34_fpSinCosXTest(SUB,203)@13
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("000" & r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q);
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b));
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q <= expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o(8 downto 0);
--expCompOut_uid205_rrx_uid34_fpSinCosXTest(BITSELECT,204)@13
expCompOut_uid205_rrx_uid34_fpSinCosXTest_in <= expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q(7 downto 0);
expCompOut_uid205_rrx_uid34_fpSinCosXTest_b <= expCompOut_uid205_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2(REG,564)@13
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q <= expCompOut_uid205_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--xBranch_uid191_rrx_uid34_fpSinCosXTest(COMPARE,190)@0
xBranch_uid191_rrx_uid34_fpSinCosXTest_cin <= GND_q;
xBranch_uid191_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid24_fpSinCosXTest_q) & '0';
xBranch_uid191_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & expX_uid186_rrx_uid34_fpSinCosXTest_b) & xBranch_uid191_rrx_uid34_fpSinCosXTest_cin(0);
xBranch_uid191_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xBranch_uid191_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(xBranch_uid191_rrx_uid34_fpSinCosXTest_b));
xBranch_uid191_rrx_uid34_fpSinCosXTest_n(0) <= not xBranch_uid191_rrx_uid34_fpSinCosXTest_o(10);
--reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1(REG,563)@0
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q <= xBranch_uid191_rrx_uid34_fpSinCosXTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b(DELAY,829)@1
ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q, xout => ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalExp_uid209_rrx_uid34_fpSinCosXTest(MUX,208)@14
finalExp_uid209_rrx_uid34_fpSinCosXTest_s <= ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q;
finalExp_uid209_rrx_uid34_fpSinCosXTest: PROCESS (finalExp_uid209_rrx_uid34_fpSinCosXTest_s, en, reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q)
BEGIN
CASE finalExp_uid209_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b(DELAY,833)@14
ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => finalExp_uid209_rrx_uid34_fpSinCosXTest_q, xout => ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1409)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a or ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top(CONSTANT,1279)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q <= "01000";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp(LOGICAL,1280)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q <= "1" when ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a = ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b else "0";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg(REG,1281)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1410)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1411)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1399)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid187_rrx_uid34_fpSinCosXTest_b, xout => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt(COUNTER,1275)
-- every=1, low=0, high=8, step=1, init=1
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i = 7 THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i - 8;
ELSE
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg(REG,1276)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux(MUX,1277)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s, ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q, ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1400)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 4,
numwords_a => 9,
width_b => 23,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(22 downto 0);
--ZerosGB_uid206_rrx_uid34_fpSinCosXTest(CONSTANT,205)
ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q <= "000000000000000000000000000000";
--fracXRExt_uid207_rrx_uid34_fpSinCosXTest(BITJOIN,206)@15
fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q & ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q;
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1499)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1500)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1501)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,474)@9
X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(29 downto 0);
X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in(29 downto 0);
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1491)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 30, depth => 1 )
PORT MAP ( xin => X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1492)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 1,
numwords_a => 2,
width_b => 30,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(29 downto 0);
--leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest(CONSTANT,473)
leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,475)@13
leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1488)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1489)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1490)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,471)@9
X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(45 downto 0);
X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in(45 downto 0);
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1480)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1481)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 1,
numwords_a => 2,
width_b => 46,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(45 downto 0);
--leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,472)@13
leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1477)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1478)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1479)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,468)@9
X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(61 downto 0);
X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in(61 downto 0);
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1469)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1470)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 62,
widthad_a => 1,
numwords_a => 2,
width_b => 62,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(61 downto 0);
--leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,469)@13
leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor(LOGICAL,1510)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q <= not (ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a or ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b);
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena(REG,1511)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q = "1") THEN
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd(LOGICAL,1512)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b <= en;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a and ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg(DELAY,1502)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 78, depth => 1 )
PORT MAP ( xin => multFracBits_uid199_rrx_uid34_fpSinCosXTest_b, xout => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem(DUALMEM,1503)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 78,
widthad_a => 1,
numwords_a => 2,
width_b => 78,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia
);
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq(77 downto 0);
--leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,476)@13
leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in(5 downto 4);
--leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,477)@13
leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b;
leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,485)@13
LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(65 downto 0);
LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in(65 downto 0);
--leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest(CONSTANT,218)
leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q <= "000000000000";
--leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,486)@13
leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b & leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5(REG,560)@13
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,482)@13
LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(69 downto 0);
LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in(69 downto 0);
--leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,483)@13
leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4(REG,559)@13
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,479)@13
LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(73 downto 0);
LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in(73 downto 0);
--leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,480)@13
leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3(REG,558)@13
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2(REG,557)@13
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,487)@13
leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1(REG,556)@13
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,488)@14
leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q;
leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,496)@14
LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(74 downto 0);
LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in(74 downto 0);
--ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1112)@14
ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 75, depth => 1 )
PORT MAP ( xin => LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest(CONSTANT,229)
leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q <= "000";
--leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,497)@15
leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,493)@14
LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(75 downto 0);
LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in(75 downto 0);
--ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1110)@14
ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 76, depth => 1 )
PORT MAP ( xin => LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,494)@15
leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,490)@14
LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(76 downto 0);
LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in(76 downto 0);
--ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1108)@14
ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 77, depth => 1 )
PORT MAP ( xin => LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,491)@15
leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & GND_q;
--reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2(REG,562)@14
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,498)@13
leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a(DELAY,1184)@13
ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1(REG,561)@14
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,499)@15
leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q;
leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracCompOut_uid203_rrx_uid34_fpSinCosXTest(BITSELECT,202)@15
fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in <= leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q(76 downto 0);
fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b <= fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in(76 downto 24);
--ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b(DELAY,826)@0
ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => xBranch_uid191_rrx_uid34_fpSinCosXTest_n, xout => ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalFrac_uid208_rrx_uid34_fpSinCosXTest(MUX,207)@15
finalFrac_uid208_rrx_uid34_fpSinCosXTest_s <= ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q;
finalFrac_uid208_rrx_uid34_fpSinCosXTest: PROCESS (finalFrac_uid208_rrx_uid34_fpSinCosXTest_s, en, fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b, fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE finalFrac_uid208_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b;
WHEN "1" => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RRangeRed_uid210_rrx_uid34_fpSinCosXTest(BITJOIN,209)@15
RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q <= GND_q & ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q & finalFrac_uid208_rrx_uid34_fpSinCosXTest_q;
--expXRR_uid38_fpSinCosXTest(BITSELECT,37)@15
expXRR_uid38_fpSinCosXTest_in <= RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q(60 downto 0);
expXRR_uid38_fpSinCosXTest_b <= expXRR_uid38_fpSinCosXTest_in(60 downto 53);
--reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1(REG,565)@15
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q <= expXRR_uid38_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShiftM2_uid26_fpSinCosXTest(CONSTANT,25)
cstBiasMwShiftM2_uid26_fpSinCosXTest_q <= "01110000";
--cosXIsOneXRR_uid42_fpSinCosXTest(COMPARE,41)@16
cosXIsOneXRR_uid42_fpSinCosXTest_cin <= GND_q;
cosXIsOneXRR_uid42_fpSinCosXTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid26_fpSinCosXTest_q) & '0';
cosXIsOneXRR_uid42_fpSinCosXTest_b <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q) & cosXIsOneXRR_uid42_fpSinCosXTest_cin(0);
cosXIsOneXRR_uid42_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(cosXIsOneXRR_uid42_fpSinCosXTest_a) - SIGNED(cosXIsOneXRR_uid42_fpSinCosXTest_b));
cosXIsOneXRR_uid42_fpSinCosXTest_n(0) <= not cosXIsOneXRR_uid42_fpSinCosXTest_o(11);
--exp_uid9_fpSinCosXTest(BITSELECT,8)@0
exp_uid9_fpSinCosXTest_in <= a(30 downto 0);
exp_uid9_fpSinCosXTest_b <= exp_uid9_fpSinCosXTest_in(30 downto 23);
--sinXIsX_uid40_fpSinCosXTest(COMPARE,39)@0
sinXIsX_uid40_fpSinCosXTest_cin <= GND_q;
sinXIsX_uid40_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid24_fpSinCosXTest_q) & '0';
sinXIsX_uid40_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & exp_uid9_fpSinCosXTest_b) & sinXIsX_uid40_fpSinCosXTest_cin(0);
sinXIsX_uid40_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid40_fpSinCosXTest_a) - UNSIGNED(sinXIsX_uid40_fpSinCosXTest_b));
sinXIsX_uid40_fpSinCosXTest_n(0) <= not sinXIsX_uid40_fpSinCosXTest_o(10);
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a(DELAY,789)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--cosXONe_uid148_fpSinCosXTest(LOGICAL,147)@16
cosXONe_uid148_fpSinCosXTest_a <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q;
cosXONe_uid148_fpSinCosXTest_b <= cosXIsOneXRR_uid42_fpSinCosXTest_n;
cosXONe_uid148_fpSinCosXTest_q <= cosXONe_uid148_fpSinCosXTest_a or cosXONe_uid148_fpSinCosXTest_b;
--ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a(DELAY,791)@16
ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => cosXONe_uid148_fpSinCosXTest_q, xout => ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvCosXONe_uid149_fpSinCosXTest(LOGICAL,148)@20
InvCosXONe_uid149_fpSinCosXTest_a <= ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q;
InvCosXONe_uid149_fpSinCosXTest_q <= not InvCosXONe_uid149_fpSinCosXTest_a;
--cstZwShiftP1_uid27_fpSinCosXTest(CONSTANT,26)
cstZwShiftP1_uid27_fpSinCosXTest_q <= "00000000000000";
--fracXRR_uid39_fpSinCosXTest(BITSELECT,38)@15
fracXRR_uid39_fpSinCosXTest_in <= RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q(52 downto 0);
fracXRR_uid39_fpSinCosXTest_b <= fracXRR_uid39_fpSinCosXTest_in(52 downto 0);
--ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a(DELAY,668)@15
ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => fracXRR_uid39_fpSinCosXTest_b, xout => ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracXRR_uid43_uid43_fpSinCosXTest(BITJOIN,42)@16
oFracXRR_uid43_uid43_fpSinCosXTest_q <= VCC_q & ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q;
--extendedFracX_uid47_fpSinCosXTest(BITJOIN,46)@16
extendedFracX_uid47_fpSinCosXTest_q <= cstZwShiftP1_uid27_fpSinCosXTest_q & oFracXRR_uid43_uid43_fpSinCosXTest_q;
--X55dto0_uid220_fxpX_uid48_fpSinCosXTest(BITSELECT,219)@16
X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(55 downto 0);
X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b <= X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in(55 downto 0);
--leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest(BITJOIN,220)@16
leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q <= X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b & leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5(REG,571)@16
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q <= leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--X59dto0_uid217_fxpX_uid48_fpSinCosXTest(BITSELECT,216)@16
X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(59 downto 0);
X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b <= X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in(59 downto 0);
--leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest(BITJOIN,217)@16
leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q <= X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4(REG,570)@16
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q <= leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--X63dto0_uid214_fxpX_uid48_fpSinCosXTest(BITSELECT,213)@16
X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(63 downto 0);
X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b <= X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in(63 downto 0);
--leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest(BITJOIN,214)@16
leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q <= X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3(REG,569)@16
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q <= leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2(REG,568)@16
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q <= extendedFracX_uid47_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--fxpXShiftValExt_uid45_fpSinCosXTest(SUB,44)@16
fxpXShiftValExt_uid45_fpSinCosXTest_a <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q);
fxpXShiftValExt_uid45_fpSinCosXTest_b <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid26_fpSinCosXTest_q);
fxpXShiftValExt_uid45_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(fxpXShiftValExt_uid45_fpSinCosXTest_a) - SIGNED(fxpXShiftValExt_uid45_fpSinCosXTest_b));
fxpXShiftValExt_uid45_fpSinCosXTest_q <= fxpXShiftValExt_uid45_fpSinCosXTest_o(9 downto 0);
--fxpXShiftVal_uid46_fpSinCosXTest(BITSELECT,45)@16
fxpXShiftVal_uid46_fpSinCosXTest_in <= fxpXShiftValExt_uid45_fpSinCosXTest_q(3 downto 0);
fxpXShiftVal_uid46_fpSinCosXTest_b <= fxpXShiftVal_uid46_fpSinCosXTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest(BITSELECT,221)@16
leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in <= fxpXShiftVal_uid46_fpSinCosXTest_b;
leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b <= leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1(REG,567)@16
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q <= leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest(MUX,222)@17
leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s <= reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q;
leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest: PROCESS (leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s, en, reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q, reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q, reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q, reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest(BITSELECT,230)@17
LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(64 downto 0);
LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in(64 downto 0);
--ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b(DELAY,851)@17
ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest(BITJOIN,231)@18
leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q & leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest(BITSELECT,227)@17
LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(65 downto 0);
LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in(65 downto 0);
--ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b(DELAY,849)@17
ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 66, depth => 1 )
PORT MAP ( xin => LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest(BITJOIN,228)@18
leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest(BITSELECT,224)@17
LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(66 downto 0);
LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in(66 downto 0);
--ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b(DELAY,847)@17
ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 67, depth => 1 )
PORT MAP ( xin => LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest(BITJOIN,225)@18
leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q & GND_q;
--reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2(REG,573)@17
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest(BITSELECT,232)@16
leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in <= fxpXShiftVal_uid46_fpSinCosXTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b <= leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a(DELAY,1195)@16
ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b, xout => ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1(REG,572)@17
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q <= ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest(MUX,233)@18
leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s <= reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q;
leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest: PROCESS (leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s, en, reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q, leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q, leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q, leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q;
WHEN "10" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q;
WHEN "11" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid50_fpSinCosXTest(BITSELECT,49)@18
y_uid50_fpSinCosXTest_in <= leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q(66 downto 0);
y_uid50_fpSinCosXTest_b <= y_uid50_fpSinCosXTest_in(66 downto 1);
--ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b(DELAY,680)@18
ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 66, depth => 2 )
PORT MAP ( xin => y_uid50_fpSinCosXTest_b, xout => ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1(REG,575)@18
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q <= y_uid50_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--pad_one_uid55_fpSinCosXTest(BITJOIN,54)@18
pad_one_uid55_fpSinCosXTest_q <= VCC_q & STD_LOGIC_VECTOR((65 downto 1 => GND_q(0)) & GND_q);
--reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0(REG,574)@18
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q <= pad_one_uid55_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--oneMinusY_uid55_fpSinCosXTest(SUB,55)@19
oneMinusY_uid55_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q);
oneMinusY_uid55_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q);
oneMinusY_uid55_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid55_fpSinCosXTest_a) - UNSIGNED(oneMinusY_uid55_fpSinCosXTest_b));
oneMinusY_uid55_fpSinCosXTest_q <= oneMinusY_uid55_fpSinCosXTest_o(67 downto 0);
--reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0(REG,576)@19
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q <= oneMinusY_uid55_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid57_fpSinCosXTest(COMPARE,56)@20
cmpYToOneMinusY_uid57_fpSinCosXTest_cin <= GND_q;
cmpYToOneMinusY_uid57_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q) & '0';
cmpYToOneMinusY_uid57_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q) & cmpYToOneMinusY_uid57_fpSinCosXTest_cin(0);
cmpYToOneMinusY_uid57_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid57_fpSinCosXTest_a) - UNSIGNED(cmpYToOneMinusY_uid57_fpSinCosXTest_b));
cmpYToOneMinusY_uid57_fpSinCosXTest_c(0) <= cmpYToOneMinusY_uid57_fpSinCosXTest_o(70);
--InvCmpYToOneMinusY_uid61_fpSinCosXTest(LOGICAL,60)@20
InvCmpYToOneMinusY_uid61_fpSinCosXTest_a <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
InvCmpYToOneMinusY_uid61_fpSinCosXTest_q <= not InvCmpYToOneMinusY_uid61_fpSinCosXTest_a;
--intXParity_uid49_fpSinCosXTest(BITSELECT,48)@18
intXParity_uid49_fpSinCosXTest_in <= leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q;
intXParity_uid49_fpSinCosXTest_b <= intXParity_uid49_fpSinCosXTest_in(67 downto 67);
--ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b(DELAY,794)@18
ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => intXParity_uid49_fpSinCosXTest_b, xout => ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--yIsZero_uid51_fpSinCosXTest(LOGICAL,50)@19
yIsZero_uid51_fpSinCosXTest_a <= reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q;
yIsZero_uid51_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000000000000000000000000000000000" & GND_q);
yIsZero_uid51_fpSinCosXTest_q <= "1" when yIsZero_uid51_fpSinCosXTest_a = yIsZero_uid51_fpSinCosXTest_b else "0";
--ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a(DELAY,792)@19
ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => yIsZero_uid51_fpSinCosXTest_q, xout => ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvYIsZero_uid151_fpSinCosXTest(LOGICAL,150)@20
InvYIsZero_uid151_fpSinCosXTest_a <= ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q;
InvYIsZero_uid151_fpSinCosXTest_q <= not InvYIsZero_uid151_fpSinCosXTest_a;
--signRCond2_uid152_fpSinCosXTest(LOGICAL,151)@20
signRCond2_uid152_fpSinCosXTest_a <= InvYIsZero_uid151_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_b <= ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q;
signRCond2_uid152_fpSinCosXTest_c <= InvCmpYToOneMinusY_uid61_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_d <= InvCosXONe_uid149_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_q_i <= signRCond2_uid152_fpSinCosXTest_a and signRCond2_uid152_fpSinCosXTest_b and signRCond2_uid152_fpSinCosXTest_c and signRCond2_uid152_fpSinCosXTest_d;
signRCond2_uid152_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRCond2_uid152_fpSinCosXTest_q, xin => signRCond2_uid152_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--InvIntXParity_uid155_fpSinCosXTest(LOGICAL,154)@20
InvIntXParity_uid155_fpSinCosXTest_a <= ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q;
InvIntXParity_uid155_fpSinCosXTest_q <= not InvIntXParity_uid155_fpSinCosXTest_a;
--signRCond1_uid157_fpSinCosXTest(LOGICAL,156)@20
signRCond1_uid157_fpSinCosXTest_a <= InvYIsZero_uid151_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_b <= InvIntXParity_uid155_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_c <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
signRCond1_uid157_fpSinCosXTest_d <= InvCosXONe_uid149_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_q_i <= signRCond1_uid157_fpSinCosXTest_a and signRCond1_uid157_fpSinCosXTest_b and signRCond1_uid157_fpSinCosXTest_c and signRCond1_uid157_fpSinCosXTest_d;
signRCond1_uid157_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRCond1_uid157_fpSinCosXTest_q, xin => signRCond1_uid157_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--signRCos_uid158_fpSinCosXTest(LOGICAL,157)@21
signRCos_uid158_fpSinCosXTest_a <= signRCond1_uid157_fpSinCosXTest_q;
signRCos_uid158_fpSinCosXTest_b <= signRCond2_uid152_fpSinCosXTest_q;
signRCos_uid158_fpSinCosXTest_q <= signRCos_uid158_fpSinCosXTest_a or signRCos_uid158_fpSinCosXTest_b;
--cstAllZWF_uid7_fpSinCosXTest(CONSTANT,6)
cstAllZWF_uid7_fpSinCosXTest_q <= "00000000000000000000000";
--frac_uid13_fpSinCosXTest(BITSELECT,12)@0
frac_uid13_fpSinCosXTest_in <= a(22 downto 0);
frac_uid13_fpSinCosXTest_b <= frac_uid13_fpSinCosXTest_in(22 downto 0);
--fracXIsZero_uid14_fpSinCosXTest(LOGICAL,13)@0
fracXIsZero_uid14_fpSinCosXTest_a <= frac_uid13_fpSinCosXTest_b;
fracXIsZero_uid14_fpSinCosXTest_b <= cstAllZWF_uid7_fpSinCosXTest_q;
fracXIsZero_uid14_fpSinCosXTest_q <= "1" when fracXIsZero_uid14_fpSinCosXTest_a = fracXIsZero_uid14_fpSinCosXTest_b else "0";
--cstAllOWE_uid6_fpSinCosXTest(CONSTANT,5)
cstAllOWE_uid6_fpSinCosXTest_q <= "11111111";
--expXIsMax_uid12_fpSinCosXTest(LOGICAL,11)@0
expXIsMax_uid12_fpSinCosXTest_a <= exp_uid9_fpSinCosXTest_b;
expXIsMax_uid12_fpSinCosXTest_b <= cstAllOWE_uid6_fpSinCosXTest_q;
expXIsMax_uid12_fpSinCosXTest_q <= "1" when expXIsMax_uid12_fpSinCosXTest_a = expXIsMax_uid12_fpSinCosXTest_b else "0";
--exc_I_uid15_fpSinCosXTest(LOGICAL,14)@0
exc_I_uid15_fpSinCosXTest_a <= expXIsMax_uid12_fpSinCosXTest_q;
exc_I_uid15_fpSinCosXTest_b <= fracXIsZero_uid14_fpSinCosXTest_q;
exc_I_uid15_fpSinCosXTest_q <= exc_I_uid15_fpSinCosXTest_a and exc_I_uid15_fpSinCosXTest_b;
--ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a(DELAY,762)@0
ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 20 )
PORT MAP ( xin => exc_I_uid15_fpSinCosXTest_q, xout => ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_I_uid131_fpSinCosXTest(LOGICAL,130)@20
InvExc_I_uid131_fpSinCosXTest_a <= ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q;
InvExc_I_uid131_fpSinCosXTest_q <= not InvExc_I_uid131_fpSinCosXTest_a;
--reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2(REG,649)@20
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q <= InvExc_I_uid131_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--InvFracXIsZero_uid16_fpSinCosXTest(LOGICAL,15)@0
InvFracXIsZero_uid16_fpSinCosXTest_a <= fracXIsZero_uid14_fpSinCosXTest_q;
InvFracXIsZero_uid16_fpSinCosXTest_q <= not InvFracXIsZero_uid16_fpSinCosXTest_a;
--exc_N_uid17_fpSinCosXTest(LOGICAL,16)@0
exc_N_uid17_fpSinCosXTest_a <= expXIsMax_uid12_fpSinCosXTest_q;
exc_N_uid17_fpSinCosXTest_b <= InvFracXIsZero_uid16_fpSinCosXTest_q;
exc_N_uid17_fpSinCosXTest_q <= exc_N_uid17_fpSinCosXTest_a and exc_N_uid17_fpSinCosXTest_b;
--ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a(DELAY,763)@0
ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 20 )
PORT MAP ( xin => exc_N_uid17_fpSinCosXTest_q, xout => ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid132_fpSinCosXTest(LOGICAL,131)@20
InvExc_N_uid132_fpSinCosXTest_a <= ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q;
InvExc_N_uid132_fpSinCosXTest_q <= not InvExc_N_uid132_fpSinCosXTest_a;
--reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1(REG,648)@20
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q <= InvExc_N_uid132_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--signRCosFull_uid161_fpSinCosXTest(LOGICAL,160)@21
signRCosFull_uid161_fpSinCosXTest_a <= reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q;
signRCosFull_uid161_fpSinCosXTest_b <= reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q;
signRCosFull_uid161_fpSinCosXTest_c <= signRCos_uid158_fpSinCosXTest_q;
signRCosFull_uid161_fpSinCosXTest_q <= signRCosFull_uid161_fpSinCosXTest_a and signRCosFull_uid161_fpSinCosXTest_b and signRCosFull_uid161_fpSinCosXTest_c;
--ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c(DELAY,809)@21
ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signRCosFull_uid161_fpSinCosXTest_q, xout => ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid22_fpSinCosXTest(CONSTANT,21)
cstBias_uid22_fpSinCosXTest_q <= "01111111";
--ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a(DELAY,681)@19
ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 68, depth => 1 )
PORT MAP ( xin => oneMinusY_uid55_fpSinCosXTest_q, xout => ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--zSinOMyBottom_uid58_fpSinCosXTest(BITSELECT,57)@20
zSinOMyBottom_uid58_fpSinCosXTest_in <= ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q(64 downto 0);
zSinOMyBottom_uid58_fpSinCosXTest_b <= zSinOMyBottom_uid58_fpSinCosXTest_in(64 downto 0);
--reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3(REG,579)@20
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q <= zSinOMyBottom_uid58_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--zSinYBottom_uid59_fpSinCosXTest(BITSELECT,58)@20
zSinYBottom_uid59_fpSinCosXTest_in <= ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q(64 downto 0);
zSinYBottom_uid59_fpSinCosXTest_b <= zSinYBottom_uid59_fpSinCosXTest_in(64 downto 0);
--reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2(REG,578)@20
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q <= zSinYBottom_uid59_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1(REG,614)@20
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q <= InvCmpYToOneMinusY_uid61_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--zCos_uid64_fpSinCosXTest(MUX,63)@21
zCos_uid64_fpSinCosXTest_s <= reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q;
zCos_uid64_fpSinCosXTest: PROCESS (zCos_uid64_fpSinCosXTest_s, en, reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q, reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q)
BEGIN
CASE zCos_uid64_fpSinCosXTest_s IS
WHEN "0" => zCos_uid64_fpSinCosXTest_q <= reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q;
WHEN "1" => zCos_uid64_fpSinCosXTest_q <= reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q;
WHEN OTHERS => zCos_uid64_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--addr_uid83_fpSinCosXTest(BITSELECT,82)@21
addr_uid83_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q;
addr_uid83_fpSinCosXTest_b <= addr_uid83_fpSinCosXTest_in(64 downto 57);
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0(REG,630)@21
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q <= addr_uid83_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid404_tableGencosPiZ_lutmem(DUALMEM,532)@22
memoryC2_uid404_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC2_uid404_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC2_uid404_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q;
memoryC2_uid404_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC2_uid404_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid404_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid404_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid404_tableGencosPiZ_lutmem_iq,
address_a => memoryC2_uid404_tableGencosPiZ_lutmem_aa,
data_a => memoryC2_uid404_tableGencosPiZ_lutmem_ia
);
memoryC2_uid404_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC2_uid404_tableGencosPiZ_lutmem_q <= memoryC2_uid404_tableGencosPiZ_lutmem_iq(12 downto 0);
--reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1(REG,632)@24
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q <= memoryC2_uid404_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPcosPiZ_uid87_fpSinCosXTest(BITSELECT,86)@21
zPcosPiZ_uid87_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(56 downto 0);
zPcosPiZ_uid87_fpSinCosXTest_b <= zPcosPiZ_uid87_fpSinCosXTest_in(56 downto 42);
--yT1_uid419_polyEvalcosPiZ(BITSELECT,418)@21
yT1_uid419_polyEvalcosPiZ_in <= zPcosPiZ_uid87_fpSinCosXTest_b;
yT1_uid419_polyEvalcosPiZ_b <= yT1_uid419_polyEvalcosPiZ_in(14 downto 2);
--reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0(REG,631)@21
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q <= yT1_uid419_polyEvalcosPiZ_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg(DELAY,1513)
ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q, xout => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a(DELAY,1125)@22
ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q, xout => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid508_pT1_uid420_polyEvalcosPiZ(MULT,507)@25
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a),14)) * SIGNED(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b);
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a <= (others => '0');
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b <= (others => '0');
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a <= ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b <= reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q <= prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ(BITSELECT,508)@28
prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in <= prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q;
prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in(25 downto 12);
--highBBits_uid422_polyEvalcosPiZ(BITSELECT,421)@28
highBBits_uid422_polyEvalcosPiZ_in <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b;
highBBits_uid422_polyEvalcosPiZ_b <= highBBits_uid422_polyEvalcosPiZ_in(13 downto 1);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a(DELAY,1256)@21
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => addr_uid83_fpSinCosXTest_b, xout => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0(REG,633)@24
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid402_tableGencosPiZ_lutmem(DUALMEM,531)@25
memoryC1_uid402_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC1_uid402_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC1_uid402_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q;
memoryC1_uid402_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC1_uid402_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid402_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid402_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid402_tableGencosPiZ_lutmem_iq,
address_a => memoryC1_uid402_tableGencosPiZ_lutmem_aa,
data_a => memoryC1_uid402_tableGencosPiZ_lutmem_ia
);
memoryC1_uid402_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC1_uid402_tableGencosPiZ_lutmem_q <= memoryC1_uid402_tableGencosPiZ_lutmem_iq(20 downto 0);
--reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0(REG,634)@27
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q <= memoryC1_uid402_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid423_polyEvalcosPiZ(ADD,422)@28
sumAHighB_uid423_polyEvalcosPiZ_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q(20)) & reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q);
sumAHighB_uid423_polyEvalcosPiZ_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid422_polyEvalcosPiZ_b(12)) & highBBits_uid422_polyEvalcosPiZ_b);
sumAHighB_uid423_polyEvalcosPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid423_polyEvalcosPiZ_a) + SIGNED(sumAHighB_uid423_polyEvalcosPiZ_b));
sumAHighB_uid423_polyEvalcosPiZ_q <= sumAHighB_uid423_polyEvalcosPiZ_o(21 downto 0);
--lowRangeB_uid421_polyEvalcosPiZ(BITSELECT,420)@28
lowRangeB_uid421_polyEvalcosPiZ_in <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b(0 downto 0);
lowRangeB_uid421_polyEvalcosPiZ_b <= lowRangeB_uid421_polyEvalcosPiZ_in(0 downto 0);
--s1_uid421_uid424_polyEvalcosPiZ(BITJOIN,423)@28
s1_uid421_uid424_polyEvalcosPiZ_q <= sumAHighB_uid423_polyEvalcosPiZ_q & lowRangeB_uid421_polyEvalcosPiZ_b;
--reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1(REG,636)@28
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q <= s1_uid421_uid424_polyEvalcosPiZ_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor(LOGICAL,1524)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q <= not (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a or ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b);
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top(CONSTANT,1520)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q <= "0100";
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp(LOGICAL,1521)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q <= "1" when ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a = ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b else "0";
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg(REG,1522)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena(REG,1525)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd(LOGICAL,1526)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b <= en;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a and ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b;
--reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0(REG,635)@21
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q <= zPcosPiZ_uid87_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg(DELAY,1514)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q, xout => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt(COUNTER,1516)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i = 3 THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i,3));
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg(REG,1517)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux(MUX,1518)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s <= en;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux: PROCESS (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s, ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q, ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem(DUALMEM,1515)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq,
address_a => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa,
data_a => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia
);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0 <= areset;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq(14 downto 0);
--prodXY_uid511_pT2_uid426_polyEvalcosPiZ(MULT,510)@29
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a),16)) * SIGNED(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b);
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a <= (others => '0');
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b <= (others => '0');
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b <= reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q <= prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ(BITSELECT,511)@32
prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in <= prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q;
prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in(37 downto 14);
--highBBits_uid428_polyEvalcosPiZ(BITSELECT,427)@32
highBBits_uid428_polyEvalcosPiZ_in <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b;
highBBits_uid428_polyEvalcosPiZ_b <= highBBits_uid428_polyEvalcosPiZ_in(23 downto 2);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor(LOGICAL,1577)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q <= not (ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a or ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena(REG,1578)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q = "1") THEN
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd(LOGICAL,1579)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b <= en;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a and ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b;
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg(DELAY,1567)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addr_uid83_fpSinCosXTest_b, xout => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem(DUALMEM,1568)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq,
address_a => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa,
data_a => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia
);
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0(REG,637)@28
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid400_tableGencosPiZ_lutmem(DUALMEM,530)@29
memoryC0_uid400_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC0_uid400_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC0_uid400_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q;
memoryC0_uid400_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC0_uid400_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid400_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid400_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid400_tableGencosPiZ_lutmem_iq,
address_a => memoryC0_uid400_tableGencosPiZ_lutmem_aa,
data_a => memoryC0_uid400_tableGencosPiZ_lutmem_ia
);
memoryC0_uid400_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC0_uid400_tableGencosPiZ_lutmem_q <= memoryC0_uid400_tableGencosPiZ_lutmem_iq(29 downto 0);
--reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0(REG,638)@31
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q <= memoryC0_uid400_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid429_polyEvalcosPiZ(ADD,428)@32
sumAHighB_uid429_polyEvalcosPiZ_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q(29)) & reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q);
sumAHighB_uid429_polyEvalcosPiZ_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid428_polyEvalcosPiZ_b(21)) & highBBits_uid428_polyEvalcosPiZ_b);
sumAHighB_uid429_polyEvalcosPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid429_polyEvalcosPiZ_a) + SIGNED(sumAHighB_uid429_polyEvalcosPiZ_b));
sumAHighB_uid429_polyEvalcosPiZ_q <= sumAHighB_uid429_polyEvalcosPiZ_o(30 downto 0);
--lowRangeB_uid427_polyEvalcosPiZ(BITSELECT,426)@32
lowRangeB_uid427_polyEvalcosPiZ_in <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b(1 downto 0);
lowRangeB_uid427_polyEvalcosPiZ_b <= lowRangeB_uid427_polyEvalcosPiZ_in(1 downto 0);
--s2_uid427_uid430_polyEvalcosPiZ(BITJOIN,429)@32
s2_uid427_uid430_polyEvalcosPiZ_q <= sumAHighB_uid429_polyEvalcosPiZ_q & lowRangeB_uid427_polyEvalcosPiZ_b;
--polyEvalSigcosPiZ_uid89_fpSinCosXTest(BITSELECT,88)@32
polyEvalSigcosPiZ_uid89_fpSinCosXTest_in <= s2_uid427_uid430_polyEvalcosPiZ_q(30 downto 0);
polyEvalSigcosPiZ_uid89_fpSinCosXTest_b <= polyEvalSigcosPiZ_uid89_fpSinCosXTest_in(30 downto 5);
--reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1(REG,640)@32
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q <= polyEvalSigcosPiZ_uid89_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor(LOGICAL,1590)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q <= not (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a or ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b);
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top(CONSTANT,1586)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q <= "010";
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp(LOGICAL,1587)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q <= "1" when ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a = ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b else "0";
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg(REG,1588)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena(REG,1591)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd(LOGICAL,1592)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b <= en;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a and ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b;
--LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest(BITSELECT,388)@27
LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q(63 downto 0);
LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in(63 downto 0);
--leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest(BITJOIN,389)@27
leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b & GND_q;
--cstZmwFRRPwSM1_uid52_fpSinCosXTest(CONSTANT,51)
cstZmwFRRPwSM1_uid52_fpSinCosXTest_q <= "00000000000000000000000000000000000000000000000000000000000000000";
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor(LOGICAL,1455)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q <= not (ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a or ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b);
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena(REG,1456)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q = "1") THEN
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd(LOGICAL,1457)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b <= en;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a and ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b;
--X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest(BITSELECT,359)@21
X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(32 downto 0);
X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b <= X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in(32 downto 0);
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg(DELAY,1447)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem(DUALMEM,1448)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 33,
widthad_a => 1,
numwords_a => 2,
width_b => 33,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia
);
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq(32 downto 0);
--leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest(BITJOIN,360)@25
leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor(LOGICAL,1466)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q <= not (ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a or ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b);
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena(REG,1467)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q = "1") THEN
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd(LOGICAL,1468)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b <= en;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a and ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg(DELAY,1458)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => zCos_uid64_fpSinCosXTest_q, xout => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem(DUALMEM,1459)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 65,
widthad_a => 1,
numwords_a => 2,
width_b => 65,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia
);
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq(64 downto 0);
--zs_uid236_lzcZSin_uid66_fpSinCosXTest(CONSTANT,235)
zs_uid236_lzcZSin_uid66_fpSinCosXTest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--rVStage_uid316_lzcZCos_uid69_fpSinCosXTest(BITSELECT,315)@21
rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q;
rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in(64 downto 1);
--vCount_uid317_lzcZCos_uid69_fpSinCosXTest(LOGICAL,316)@21
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid236_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g(DELAY,985)@22
ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid319_lzcZCos_uid69_fpSinCosXTest(BITSELECT,318)@21
vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(0 downto 0);
vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in(0 downto 0);
--ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b(DELAY,943)@21
ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid239_lzcZSin_uid66_fpSinCosXTest(CONSTANT,238)
mO_uid239_lzcZSin_uid66_fpSinCosXTest_q <= "111111111111111111111111111111111111111111111111111111111111111";
--cStage_uid320_lzcZCos_uid69_fpSinCosXTest(BITJOIN,319)@22
cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q <= ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q & mO_uid239_lzcZSin_uid66_fpSinCosXTest_q;
--ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c(DELAY,945)@21
ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid322_lzcZCos_uid69_fpSinCosXTest(MUX,321)@22
vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid322_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s, en, ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q, cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid324_lzcZCos_uid69_fpSinCosXTest(BITSELECT,323)@22
rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in(63 downto 32);
--vCount_uid325_lzcZCos_uid69_fpSinCosXTest(LOGICAL,324)@22
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f(DELAY,984)@23
ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid326_lzcZCos_uid69_fpSinCosXTest(BITSELECT,325)@22
vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q(31 downto 0);
vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in(31 downto 0);
--ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d(DELAY,952)@22
ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c(DELAY,951)@22
ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid328_lzcZCos_uid69_fpSinCosXTest(MUX,327)@23
vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid328_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s, en, ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q, ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q)
BEGIN
CASE vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q;
WHEN OTHERS => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid330_lzcZCos_uid69_fpSinCosXTest(BITSELECT,329)@23
rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in(31 downto 16);
--vCount_uid331_lzcZCos_uid69_fpSinCosXTest(LOGICAL,330)@23
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b else "0";
--reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4(REG,622)@23
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q <= vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e(DELAY,983)@24
ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid332_lzcZCos_uid69_fpSinCosXTest(BITSELECT,331)@23
vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q(15 downto 0);
vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in(15 downto 0);
--vStagei_uid334_lzcZCos_uid69_fpSinCosXTest(MUX,333)@23
vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid334_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s, en, rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b, vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b;
WHEN "1" => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid336_lzcZCos_uid69_fpSinCosXTest(BITSELECT,335)@23
rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in(15 downto 8);
--reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1(REG,617)@23
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q <= rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid337_lzcZCos_uid69_fpSinCosXTest(LOGICAL,336)@24
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a <= reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q;
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b else "0";
--ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d(DELAY,982)@24
ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid338_lzcZCos_uid69_fpSinCosXTest(BITSELECT,337)@23
vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q(7 downto 0);
vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3(REG,619)@23
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q <= vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid340_lzcZCos_uid69_fpSinCosXTest(MUX,339)@24
vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid340_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s, en, reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q, reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid342_lzcZCos_uid69_fpSinCosXTest(BITSELECT,341)@24
rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in(7 downto 4);
--vCount_uid343_lzcZCos_uid69_fpSinCosXTest(LOGICAL,342)@24
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid344_lzcZCos_uid69_fpSinCosXTest(BITSELECT,343)@24
vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q(3 downto 0);
vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in(3 downto 0);
--reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3(REG,621)@24
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q <= vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2(REG,620)@24
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid346_lzcZCos_uid69_fpSinCosXTest(MUX,345)@25
vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid346_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s, en, reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q, reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid348_lzcZCos_uid69_fpSinCosXTest(BITSELECT,347)@25
rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in(3 downto 2);
--vCount_uid349_lzcZCos_uid69_fpSinCosXTest(LOGICAL,348)@25
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b else "0";
--vStage_uid350_lzcZCos_uid69_fpSinCosXTest(BITSELECT,349)@25
vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q(1 downto 0);
vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in(1 downto 0);
--vStagei_uid352_lzcZCos_uid69_fpSinCosXTest(MUX,351)@25
vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid352_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s, en, rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b, vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b;
WHEN "1" => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid354_lzcZCos_uid69_fpSinCosXTest(BITSELECT,353)@25
rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in(1 downto 1);
--vCount_uid355_lzcZCos_uid69_fpSinCosXTest(LOGICAL,354)@25
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b <= GND_q;
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b else "0";
--r_uid356_lzcZCos_uid69_fpSinCosXTest(BITJOIN,355)@25
r_uid356_lzcZCos_uid69_fpSinCosXTest_q <= ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q & ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q & ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q & ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q & vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q & vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q & vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q;
--leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest(BITSELECT,363)@25
leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q;
leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in(6 downto 5);
--leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest(MUX,364)@25
leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s <= leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b;
leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s, en, ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest(BITSELECT,372)@25
LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(40 downto 0);
LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in(40 downto 0);
--leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest(CONSTANT,292)
leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q <= "000000000000000000000000";
--leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest(BITJOIN,373)@25
leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b & leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5(REG,627)@25
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest(BITSELECT,369)@25
LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(48 downto 0);
LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in(48 downto 0);
--leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest(BITJOIN,370)@25
leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4(REG,626)@25
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest(BITSELECT,366)@25
LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(56 downto 0);
LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in(56 downto 0);
--leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest(BITJOIN,367)@25
leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3(REG,625)@25
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2(REG,624)@25
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest(BITSELECT,374)@25
leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1(REG,623)@25
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q <= leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest(MUX,375)@26
leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s <= reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q;
leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s, en, reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest(BITSELECT,383)@26
LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(58 downto 0);
LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1009)@26
ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest(CONSTANT,303)
leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q <= "000000";
--leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest(BITJOIN,384)@27
leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q;
--LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest(BITSELECT,380)@26
LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(60 downto 0);
LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1007)@26
ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest(BITJOIN,381)@27
leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest(BITSELECT,377)@26
LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(62 downto 0);
LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in(62 downto 0);
--ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1005)@26
ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest(BITJOIN,378)@27
leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2(REG,629)@26
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest(BITSELECT,385)@25
leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1(REG,628)@25
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q <= leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1011)@26
ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest(MUX,386)@27
leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s <= ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q;
leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s, en, reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest(BITSELECT,390)@25
leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1019)@25
ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest(MUX,391)@27
leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s <= ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q;
leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s, en, leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "0" => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "1" => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--pCos_uid77_fpSinCosXTest(BITSELECT,76)@27
pCos_uid77_fpSinCosXTest_in <= leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q;
pCos_uid77_fpSinCosXTest_b <= pCos_uid77_fpSinCosXTest_in(64 downto 39);
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg(DELAY,1580)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => pCos_uid77_fpSinCosXTest_b, xout => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt(COUNTER,1582)
-- every=1, low=0, high=2, step=1, init=1
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i = 1 THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i - 2;
ELSE
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i,2));
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg(REG,1583)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux(MUX,1584)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s <= en;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux: PROCESS (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s, ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q, ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q)
BEGIN
CASE ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s IS
WHEN "0" => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q;
WHEN "1" => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem(DUALMEM,1581)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 2,
numwords_a => 3,
width_b => 26,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq,
address_a => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa,
data_a => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia
);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0 <= areset;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq(25 downto 0);
--reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0(REG,639)@32
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--mulCos_uid105_fpSinCosXTest(MULT,104)@33
mulCos_uid105_fpSinCosXTest_pr <= UNSIGNED(mulCos_uid105_fpSinCosXTest_a) * UNSIGNED(mulCos_uid105_fpSinCosXTest_b);
mulCos_uid105_fpSinCosXTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulCos_uid105_fpSinCosXTest_a <= (others => '0');
mulCos_uid105_fpSinCosXTest_b <= (others => '0');
mulCos_uid105_fpSinCosXTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulCos_uid105_fpSinCosXTest_a <= reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q;
mulCos_uid105_fpSinCosXTest_b <= reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q;
mulCos_uid105_fpSinCosXTest_s1 <= STD_LOGIC_VECTOR(mulCos_uid105_fpSinCosXTest_pr);
END IF;
END IF;
END PROCESS;
mulCos_uid105_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulCos_uid105_fpSinCosXTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulCos_uid105_fpSinCosXTest_q <= mulCos_uid105_fpSinCosXTest_s1;
END IF;
END IF;
END PROCESS;
--normBitCos_uid106_fpSinCosXTest(BITSELECT,105)@36
normBitCos_uid106_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q;
normBitCos_uid106_fpSinCosXTest_b <= normBitCos_uid106_fpSinCosXTest_in(51 downto 51);
--cosRndOp_uid112_uid113_fpSinCosXTest(BITJOIN,112)@36
cosRndOp_uid112_uid113_fpSinCosXTest_q <= normBitCos_uid106_fpSinCosXTest_b & cstAllZWF_uid7_fpSinCosXTest_q & VCC_q;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor(LOGICAL,1296)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q <= not (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a or ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b);
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top(CONSTANT,1292)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q <= "0110";
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp(LOGICAL,1293)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q <= "1" when ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a = ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b else "0";
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg(REG,1294)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena(REG,1297)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd(LOGICAL,1298)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b <= en;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a and ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b;
--reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1(REG,641)@25
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg(DELAY,1286)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q, xout => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt(COUNTER,1288)
-- every=1, low=0, high=6, step=1, init=1
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i = 5 THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i - 6;
ELSE
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i,3));
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg(REG,1289)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux(MUX,1290)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s <= en;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux: PROCESS (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s, ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q, ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem(DUALMEM,1287)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 7,
width_b => 7,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia
);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq(6 downto 0);
--expHardCase_uid78_fpSinCosXTest(SUB,77)@35
expHardCase_uid78_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expHardCase_uid78_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q);
expHardCase_uid78_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid78_fpSinCosXTest_a) - UNSIGNED(expHardCase_uid78_fpSinCosXTest_b));
expHardCase_uid78_fpSinCosXTest_q <= expHardCase_uid78_fpSinCosXTest_o(8 downto 0);
--expPCos_uid79_fpSinCosXTest(BITSELECT,78)@35
expPCos_uid79_fpSinCosXTest_in <= expHardCase_uid78_fpSinCosXTest_q(7 downto 0);
expPCos_uid79_fpSinCosXTest_b <= expPCos_uid79_fpSinCosXTest_in(7 downto 0);
--reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1(REG,642)@35
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q <= expPCos_uid79_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--fracRCosPreRndHigh_uid108_fpSinCosXTest(BITSELECT,107)@36
fracRCosPreRndHigh_uid108_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q(50 downto 0);
fracRCosPreRndHigh_uid108_fpSinCosXTest_b <= fracRCosPreRndHigh_uid108_fpSinCosXTest_in(50 downto 27);
--fracRCosPreRndLow_uid109_fpSinCosXTest(BITSELECT,108)@36
fracRCosPreRndLow_uid109_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q(49 downto 0);
fracRCosPreRndLow_uid109_fpSinCosXTest_b <= fracRCosPreRndLow_uid109_fpSinCosXTest_in(49 downto 26);
--fracRCosPreRnd_uid110_fpSinCosXTest(MUX,109)@36
fracRCosPreRnd_uid110_fpSinCosXTest_s <= normBitCos_uid106_fpSinCosXTest_b;
fracRCosPreRnd_uid110_fpSinCosXTest: PROCESS (fracRCosPreRnd_uid110_fpSinCosXTest_s, en, fracRCosPreRndLow_uid109_fpSinCosXTest_b, fracRCosPreRndHigh_uid108_fpSinCosXTest_b)
BEGIN
CASE fracRCosPreRnd_uid110_fpSinCosXTest_s IS
WHEN "0" => fracRCosPreRnd_uid110_fpSinCosXTest_q <= fracRCosPreRndLow_uid109_fpSinCosXTest_b;
WHEN "1" => fracRCosPreRnd_uid110_fpSinCosXTest_q <= fracRCosPreRndHigh_uid108_fpSinCosXTest_b;
WHEN OTHERS => fracRCosPreRnd_uid110_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracRCosPreRnd_uid111_uid111_fpSinCosXTest(BITJOIN,110)@36
expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q <= reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q & fracRCosPreRnd_uid110_fpSinCosXTest_q;
--expFracRCos_uid114_fpSinCosXTest(ADD,113)@36
expFracRCos_uid114_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q);
expFracRCos_uid114_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00000000" & cosRndOp_uid112_uid113_fpSinCosXTest_q);
expFracRCos_uid114_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRCos_uid114_fpSinCosXTest_a) + UNSIGNED(expFracRCos_uid114_fpSinCosXTest_b));
expFracRCos_uid114_fpSinCosXTest_q <= expFracRCos_uid114_fpSinCosXTest_o(32 downto 0);
--expRCompSin_uid116_fpSinCosXTest(BITSELECT,115)@36
expRCompSin_uid116_fpSinCosXTest_in <= expFracRCos_uid114_fpSinCosXTest_q(31 downto 0);
expRCompSin_uid116_fpSinCosXTest_b <= expRCompSin_uid116_fpSinCosXTest_in(31 downto 24);
--reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2(REG,646)@36
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q <= expRCompSin_uid116_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor(LOGICAL,1385)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q <= not (ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a or ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top(CONSTANT,1305)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q <= "01101";
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp(LOGICAL,1306)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q <= "1" when ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a = ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b else "0";
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg(REG,1307)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena(REG,1386)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q = "1") THEN
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd(LOGICAL,1387)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b <= en;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a and ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b;
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a(DELAY,745)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c(DELAY,783)@16
ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => cosXIsOneXRR_uid42_fpSinCosXTest_n, xout => ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--InvCosXIsOneXRR_uid136_fpSinCosXTest(LOGICAL,135)@16
InvCosXIsOneXRR_uid136_fpSinCosXTest_a <= cosXIsOneXRR_uid42_fpSinCosXTest_n;
InvCosXIsOneXRR_uid136_fpSinCosXTest_q <= not InvCosXIsOneXRR_uid136_fpSinCosXTest_a;
--ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c(DELAY,773)@16
ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => InvCosXIsOneXRR_uid136_fpSinCosXTest_q, xout => ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a(DELAY,755)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsX_uid127_fpSinCosXTest(LOGICAL,126)@18
InvSinXIsX_uid127_fpSinCosXTest_a <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q;
InvSinXIsX_uid127_fpSinCosXTest_q <= not InvSinXIsX_uid127_fpSinCosXTest_a;
--ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b(DELAY,772)@18
ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => InvSinXIsX_uid127_fpSinCosXTest_q, xout => ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--half_uid53_fpSinCosXTest(BITJOIN,52)@19
half_uid53_fpSinCosXTest_q <= VCC_q & cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
--yIsHalf_uid54_fpSinCosXTest(LOGICAL,53)@19
yIsHalf_uid54_fpSinCosXTest_a <= reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q;
yIsHalf_uid54_fpSinCosXTest_b <= half_uid53_fpSinCosXTest_q;
yIsHalf_uid54_fpSinCosXTest_q <= "1" when yIsHalf_uid54_fpSinCosXTest_a = yIsHalf_uid54_fpSinCosXTest_b else "0";
--yHalfCosXNotOne_uid138_fpSinCosXTest(LOGICAL,137)@19
yHalfCosXNotOne_uid138_fpSinCosXTest_a <= yIsHalf_uid54_fpSinCosXTest_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_b <= ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_c <= ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_q <= yHalfCosXNotOne_uid138_fpSinCosXTest_a and yHalfCosXNotOne_uid138_fpSinCosXTest_b and yHalfCosXNotOne_uid138_fpSinCosXTest_c;
--ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b(DELAY,744)@0
ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => exc_I_uid15_fpSinCosXTest_q, xout => ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a(DELAY,743)@0
ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => exc_N_uid17_fpSinCosXTest_q, xout => ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRNaN_uid117_fpSinCosXTest(LOGICAL,116)@19
excRNaN_uid117_fpSinCosXTest_a <= ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q;
excRNaN_uid117_fpSinCosXTest_b <= ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q;
excRNaN_uid117_fpSinCosXTest_q <= excRNaN_uid117_fpSinCosXTest_a or excRNaN_uid117_fpSinCosXTest_b;
--join_uid143_fpSinCosXTest(BITJOIN,142)@19
join_uid143_fpSinCosXTest_q <= ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q & yHalfCosXNotOne_uid138_fpSinCosXTest_q & excRNaN_uid117_fpSinCosXTest_q;
--expSelBitsCos_uid144_fpSinCosXTest(BITJOIN,143)@19
expSelBitsCos_uid144_fpSinCosXTest_q <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q & join_uid143_fpSinCosXTest_q;
--reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0(REG,645)@19
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q <= expSelBitsCos_uid144_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--expSelectorCos_uid145_fpSinCosXTest(LOOKUP,144)@20
expSelectorCos_uid145_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSelectorCos_uid145_fpSinCosXTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q) IS
WHEN "0000" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "0001" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "0010" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "0011" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "0100" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "0101" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "0110" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "0111" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "1000" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "1001" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "1010" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "1011" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "1100" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "1101" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "1110" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "1111" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN OTHERS =>
expSelectorCos_uid145_fpSinCosXTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg(DELAY,1375)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => expSelectorCos_uid145_fpSinCosXTest_q, xout => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt(COUNTER,1301)
-- every=1, low=0, high=13, step=1, init=1
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i = 12 THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i - 13;
ELSE
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg(REG,1302)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux(MUX,1303)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s, ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q, ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem(DUALMEM,1376)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia
);
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq(1 downto 0);
--expRPostExcCos_uid147_fpSinCosXTest(MUX,146)@37
expRPostExcCos_uid147_fpSinCosXTest_s <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q;
expRPostExcCos_uid147_fpSinCosXTest: PROCESS (expRPostExcCos_uid147_fpSinCosXTest_s, en, reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q, cstBias_uid22_fpSinCosXTest_q, cstAllZWE_uid8_fpSinCosXTest_q, cstAllOWE_uid6_fpSinCosXTest_q)
BEGIN
CASE expRPostExcCos_uid147_fpSinCosXTest_s IS
WHEN "00" => expRPostExcCos_uid147_fpSinCosXTest_q <= reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q;
WHEN "01" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstBias_uid22_fpSinCosXTest_q;
WHEN "10" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstAllZWE_uid8_fpSinCosXTest_q;
WHEN "11" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstAllOWE_uid6_fpSinCosXTest_q;
WHEN OTHERS => expRPostExcCos_uid147_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstNaNwF_uid32_fpSinCosXTest(CONSTANT,31)
cstNaNwF_uid32_fpSinCosXTest_q <= "00000000000000000000001";
--fracRCompCos_uid115_fpSinCosXTest(BITSELECT,114)@36
fracRCompCos_uid115_fpSinCosXTest_in <= expFracRCos_uid114_fpSinCosXTest_q(23 downto 0);
fracRCompCos_uid115_fpSinCosXTest_b <= fracRCompCos_uid115_fpSinCosXTest_in(23 downto 1);
--reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2(REG,644)@36
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q <= fracRCompCos_uid115_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor(LOGICAL,1372)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q <= not (ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a or ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b);
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena(REG,1373)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q = "1") THEN
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd(LOGICAL,1374)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b <= en;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a and ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b;
--reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1(REG,613)@19
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q <= excRNaN_uid117_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3(REG,612)@19
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q <= ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q;
END IF;
END IF;
END PROCESS;
--reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2(REG,611)@19
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q;
END IF;
END IF;
END PROCESS;
--reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1(REG,610)@19
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q <= yHalfCosXNotOne_uid138_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--rZOrOne_uid140_fpSinCosXTest(LOGICAL,139)@20
rZOrOne_uid140_fpSinCosXTest_a <= reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q;
rZOrOne_uid140_fpSinCosXTest_b <= reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q;
rZOrOne_uid140_fpSinCosXTest_c <= reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q;
rZOrOne_uid140_fpSinCosXTest_q <= rZOrOne_uid140_fpSinCosXTest_a or rZOrOne_uid140_fpSinCosXTest_b or rZOrOne_uid140_fpSinCosXTest_c;
--join_uid141_fpSinCosXTest(BITJOIN,140)@20
join_uid141_fpSinCosXTest_q <= reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q & rZOrOne_uid140_fpSinCosXTest_q;
--reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1(REG,643)@20
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q <= join_uid141_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg(DELAY,1362)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q, xout => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem(DUALMEM,1363)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia
);
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq(1 downto 0);
--fracRPostExcCos_uid142_fpSinCosXTest(MUX,141)@37
fracRPostExcCos_uid142_fpSinCosXTest_s <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q;
fracRPostExcCos_uid142_fpSinCosXTest: PROCESS (fracRPostExcCos_uid142_fpSinCosXTest_s, en, reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q, cstAllZWF_uid7_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q)
BEGIN
CASE fracRPostExcCos_uid142_fpSinCosXTest_s IS
WHEN "00" => fracRPostExcCos_uid142_fpSinCosXTest_q <= reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q;
WHEN "01" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstAllZWF_uid7_fpSinCosXTest_q;
WHEN "10" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN "11" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN OTHERS => fracRPostExcCos_uid142_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpCos_uid162_fpSinCosXTest(BITJOIN,161)@37
fpCos_uid162_fpSinCosXTest_q <= ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q & expRPostExcCos_uid147_fpSinCosXTest_q & fracRPostExcCos_uid142_fpSinCosXTest_q;
--cstBiasMwShiftM2_uid25_fpSinCosXTest(CONSTANT,24)
cstBiasMwShiftM2_uid25_fpSinCosXTest_q <= "01110001";
--sinXIsXRR_uid41_fpSinCosXTest(COMPARE,40)@16
sinXIsXRR_uid41_fpSinCosXTest_cin <= GND_q;
sinXIsXRR_uid41_fpSinCosXTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid25_fpSinCosXTest_q) & '0';
sinXIsXRR_uid41_fpSinCosXTest_b <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q) & sinXIsXRR_uid41_fpSinCosXTest_cin(0);
sinXIsXRR_uid41_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(sinXIsXRR_uid41_fpSinCosXTest_a) - SIGNED(sinXIsXRR_uid41_fpSinCosXTest_b));
sinXIsXRR_uid41_fpSinCosXTest_n(0) <= not sinXIsXRR_uid41_fpSinCosXTest_o(11);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a(DELAY,756)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsXRR_uid128_fpSinCosXTest(LOGICAL,127)@18
InvSinXIsXRR_uid128_fpSinCosXTest_a <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q;
InvSinXIsXRR_uid128_fpSinCosXTest_q <= not InvSinXIsXRR_uid128_fpSinCosXTest_a;
--signComp_uid129_fpSinCosXTest(LOGICAL,128)@18
signComp_uid129_fpSinCosXTest_a <= InvSinXIsXRR_uid128_fpSinCosXTest_q;
signComp_uid129_fpSinCosXTest_b <= InvSinXIsX_uid127_fpSinCosXTest_q;
signComp_uid129_fpSinCosXTest_c <= intXParity_uid49_fpSinCosXTest_b;
signComp_uid129_fpSinCosXTest_q <= signComp_uid129_fpSinCosXTest_a and signComp_uid129_fpSinCosXTest_b and signComp_uid129_fpSinCosXTest_c;
--signX_uid37_fpSinCosXTest(BITSELECT,36)@0
signX_uid37_fpSinCosXTest_in <= a;
signX_uid37_fpSinCosXTest_b <= signX_uid37_fpSinCosXTest_in(31 downto 31);
--ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a(DELAY,760)@0
ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => signX_uid37_fpSinCosXTest_b, xout => ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid130_fpSinCosXTest(LOGICAL,129)@18
signR_uid130_fpSinCosXTest_a <= ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q;
signR_uid130_fpSinCosXTest_b <= signComp_uid129_fpSinCosXTest_q;
signR_uid130_fpSinCosXTest_q <= signR_uid130_fpSinCosXTest_a xor signR_uid130_fpSinCosXTest_b;
--ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c(DELAY,766)@18
ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => signR_uid130_fpSinCosXTest_q, xout => ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--signRSinFull_uid133_fpSinCosXTest(LOGICAL,132)@20
signRSinFull_uid133_fpSinCosXTest_a <= InvExc_N_uid132_fpSinCosXTest_q;
signRSinFull_uid133_fpSinCosXTest_b <= InvExc_I_uid131_fpSinCosXTest_q;
signRSinFull_uid133_fpSinCosXTest_c <= ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q;
signRSinFull_uid133_fpSinCosXTest_q_i <= signRSinFull_uid133_fpSinCosXTest_a and signRSinFull_uid133_fpSinCosXTest_b and signRSinFull_uid133_fpSinCosXTest_c;
signRSinFull_uid133_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRSinFull_uid133_fpSinCosXTest_q, xin => signRSinFull_uid133_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c(DELAY,769)@21
ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signRSinFull_uid133_fpSinCosXTest_q, xout => ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor(LOGICAL,1359)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q <= not (ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a or ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b);
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top(CONSTANT,1342)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q <= "0100010";
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp(LOGICAL,1343)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q <= "1" when ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a = ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b else "0";
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg(REG,1344)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena(REG,1360)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q = "1") THEN
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd(LOGICAL,1361)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b <= en;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a and ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg(DELAY,1349)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => exp_uid9_fpSinCosXTest_b, xout => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt(COUNTER,1338)
-- every=1, low=0, high=34, step=1, init=1
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i = 33 THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i - 34;
ELSE
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i,6));
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg(REG,1339)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux(MUX,1340)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem(DUALMEM,1350)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 6,
numwords_a => 35,
width_b => 8,
widthad_b => 6,
numwords_b => 35,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia
);
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a(DELAY,1228)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1(REG,605)@35
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor(LOGICAL,1309)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q <= not (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a or ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena(REG,1310)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd(LOGICAL,1311)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b <= en;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a and ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b;
--oFracXRRSmallXRR_uid90_fpSinCosXTest(BITSELECT,89)@16
oFracXRRSmallXRR_uid90_fpSinCosXTest_in <= oFracXRR_uid43_uid43_fpSinCosXTest_q;
oFracXRRSmallXRR_uid90_fpSinCosXTest_b <= oFracXRRSmallXRR_uid90_fpSinCosXTest_in(53 downto 28);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg(DELAY,1299)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => oFracXRRSmallXRR_uid90_fpSinCosXTest_b, xout => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem(DUALMEM,1300)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 4,
numwords_a => 14,
width_b => 26,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia
);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq(25 downto 0);
--reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1(REG,577)@20
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
END IF;
END IF;
END PROCESS;
--zSin_uid60_fpSinCosXTest(MUX,59)@21
zSin_uid60_fpSinCosXTest_s <= reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q;
zSin_uid60_fpSinCosXTest: PROCESS (zSin_uid60_fpSinCosXTest_s, en, reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q, reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q)
BEGIN
CASE zSin_uid60_fpSinCosXTest_s IS
WHEN "0" => zSin_uid60_fpSinCosXTest_q <= reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q;
WHEN "1" => zSin_uid60_fpSinCosXTest_q <= reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q;
WHEN OTHERS => zSin_uid60_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--addr_uid81_fpSinCosXTest(BITSELECT,80)@21
addr_uid81_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q;
addr_uid81_fpSinCosXTest_b <= addr_uid81_fpSinCosXTest_in(64 downto 57);
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0(REG,595)@21
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q <= addr_uid81_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid398_tableGensinPiZ_lutmem(DUALMEM,529)@22
memoryC2_uid398_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC2_uid398_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC2_uid398_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q;
memoryC2_uid398_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC2_uid398_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid398_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid398_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid398_tableGensinPiZ_lutmem_iq,
address_a => memoryC2_uid398_tableGensinPiZ_lutmem_aa,
data_a => memoryC2_uid398_tableGensinPiZ_lutmem_ia
);
memoryC2_uid398_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC2_uid398_tableGensinPiZ_lutmem_q <= memoryC2_uid398_tableGensinPiZ_lutmem_iq(12 downto 0);
--reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1(REG,597)@24
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q <= memoryC2_uid398_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPsinPiZ_uid84_fpSinCosXTest(BITSELECT,83)@21
zPsinPiZ_uid84_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(56 downto 0);
zPsinPiZ_uid84_fpSinCosXTest_b <= zPsinPiZ_uid84_fpSinCosXTest_in(56 downto 42);
--yT1_uid406_polyEvalsinPiZ(BITSELECT,405)@21
yT1_uid406_polyEvalsinPiZ_in <= zPsinPiZ_uid84_fpSinCosXTest_b;
yT1_uid406_polyEvalsinPiZ_b <= yT1_uid406_polyEvalsinPiZ_in(14 downto 2);
--ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg(DELAY,1540)
ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => yT1_uid406_polyEvalsinPiZ_b, xout => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a(DELAY,1219)@21
ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q, xout => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0(REG,596)@24
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q <= ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid502_pT1_uid407_polyEvalsinPiZ(MULT,501)@25
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a),14)) * SIGNED(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b);
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a <= (others => '0');
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b <= (others => '0');
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a <= reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b <= reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q <= prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ(BITSELECT,502)@28
prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in <= prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q;
prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in(25 downto 12);
--highBBits_uid409_polyEvalsinPiZ(BITSELECT,408)@28
highBBits_uid409_polyEvalsinPiZ_in <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b;
highBBits_uid409_polyEvalsinPiZ_b <= highBBits_uid409_polyEvalsinPiZ_in(13 downto 1);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a(DELAY,1221)@21
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => addr_uid81_fpSinCosXTest_b, xout => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0(REG,598)@24
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid396_tableGensinPiZ_lutmem(DUALMEM,528)@25
memoryC1_uid396_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC1_uid396_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC1_uid396_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q;
memoryC1_uid396_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC1_uid396_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid396_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid396_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid396_tableGensinPiZ_lutmem_iq,
address_a => memoryC1_uid396_tableGensinPiZ_lutmem_aa,
data_a => memoryC1_uid396_tableGensinPiZ_lutmem_ia
);
memoryC1_uid396_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC1_uid396_tableGensinPiZ_lutmem_q <= memoryC1_uid396_tableGensinPiZ_lutmem_iq(20 downto 0);
--reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0(REG,599)@27
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q <= memoryC1_uid396_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid410_polyEvalsinPiZ(ADD,409)@28
sumAHighB_uid410_polyEvalsinPiZ_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q(20)) & reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q);
sumAHighB_uid410_polyEvalsinPiZ_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid409_polyEvalsinPiZ_b(12)) & highBBits_uid409_polyEvalsinPiZ_b);
sumAHighB_uid410_polyEvalsinPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid410_polyEvalsinPiZ_a) + SIGNED(sumAHighB_uid410_polyEvalsinPiZ_b));
sumAHighB_uid410_polyEvalsinPiZ_q <= sumAHighB_uid410_polyEvalsinPiZ_o(21 downto 0);
--lowRangeB_uid408_polyEvalsinPiZ(BITSELECT,407)@28
lowRangeB_uid408_polyEvalsinPiZ_in <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b(0 downto 0);
lowRangeB_uid408_polyEvalsinPiZ_b <= lowRangeB_uid408_polyEvalsinPiZ_in(0 downto 0);
--s1_uid408_uid411_polyEvalsinPiZ(BITJOIN,410)@28
s1_uid408_uid411_polyEvalsinPiZ_q <= sumAHighB_uid410_polyEvalsinPiZ_q & lowRangeB_uid408_polyEvalsinPiZ_b;
--reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1(REG,601)@28
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q <= s1_uid408_uid411_polyEvalsinPiZ_q;
END IF;
END IF;
END PROCESS;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor(LOGICAL,1551)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q <= not (ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a or ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b);
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena(REG,1552)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q = "1") THEN
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd(LOGICAL,1553)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b <= en;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a and ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg(DELAY,1541)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => zPsinPiZ_uid84_fpSinCosXTest_b, xout => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem(DUALMEM,1542)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq,
address_a => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa,
data_a => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia
);
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0 <= areset;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq(14 downto 0);
--reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0(REG,600)@28
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid505_pT2_uid413_polyEvalsinPiZ(MULT,504)@29
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a),16)) * SIGNED(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b);
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a <= (others => '0');
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b <= (others => '0');
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a <= reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b <= reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q <= prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ(BITSELECT,505)@32
prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in <= prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q;
prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in(37 downto 14);
--highBBits_uid415_polyEvalsinPiZ(BITSELECT,414)@32
highBBits_uid415_polyEvalsinPiZ_in <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b;
highBBits_uid415_polyEvalsinPiZ_b <= highBBits_uid415_polyEvalsinPiZ_in(23 downto 2);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor(LOGICAL,1564)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q <= not (ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a or ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena(REG,1565)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q = "1") THEN
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd(LOGICAL,1566)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b <= en;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a and ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b;
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg(DELAY,1554)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addr_uid81_fpSinCosXTest_b, xout => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem(DUALMEM,1555)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq,
address_a => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa,
data_a => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia
);
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0(REG,602)@28
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid394_tableGensinPiZ_lutmem(DUALMEM,527)@29
memoryC0_uid394_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC0_uid394_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC0_uid394_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q;
memoryC0_uid394_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC0_uid394_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid394_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid394_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid394_tableGensinPiZ_lutmem_iq,
address_a => memoryC0_uid394_tableGensinPiZ_lutmem_aa,
data_a => memoryC0_uid394_tableGensinPiZ_lutmem_ia
);
memoryC0_uid394_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC0_uid394_tableGensinPiZ_lutmem_q <= memoryC0_uid394_tableGensinPiZ_lutmem_iq(29 downto 0);
--reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0(REG,603)@31
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q <= memoryC0_uid394_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid416_polyEvalsinPiZ(ADD,415)@32
sumAHighB_uid416_polyEvalsinPiZ_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q(29)) & reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q);
sumAHighB_uid416_polyEvalsinPiZ_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid415_polyEvalsinPiZ_b(21)) & highBBits_uid415_polyEvalsinPiZ_b);
sumAHighB_uid416_polyEvalsinPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid416_polyEvalsinPiZ_a) + SIGNED(sumAHighB_uid416_polyEvalsinPiZ_b));
sumAHighB_uid416_polyEvalsinPiZ_q <= sumAHighB_uid416_polyEvalsinPiZ_o(30 downto 0);
--lowRangeB_uid414_polyEvalsinPiZ(BITSELECT,413)@32
lowRangeB_uid414_polyEvalsinPiZ_in <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b(1 downto 0);
lowRangeB_uid414_polyEvalsinPiZ_b <= lowRangeB_uid414_polyEvalsinPiZ_in(1 downto 0);
--s2_uid414_uid417_polyEvalsinPiZ(BITJOIN,416)@32
s2_uid414_uid417_polyEvalsinPiZ_q <= sumAHighB_uid416_polyEvalsinPiZ_q & lowRangeB_uid414_polyEvalsinPiZ_b;
--polyEvalSigsinPiZ_uid86_fpSinCosXTest(BITSELECT,85)@32
polyEvalSigsinPiZ_uid86_fpSinCosXTest_in <= s2_uid414_uid417_polyEvalsinPiZ_q(30 downto 0);
polyEvalSigsinPiZ_uid86_fpSinCosXTest_b <= polyEvalSigsinPiZ_uid86_fpSinCosXTest_in(30 downto 5);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b(DELAY,708)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--multSinOp2_uid91_fpSinCosXTest(MUX,90)@32
multSinOp2_uid91_fpSinCosXTest_s <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q;
multSinOp2_uid91_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSinOp2_uid91_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE multSinOp2_uid91_fpSinCosXTest_s IS
WHEN "0" => multSinOp2_uid91_fpSinCosXTest_q <= polyEvalSigsinPiZ_uid86_fpSinCosXTest_b;
WHEN "1" => multSinOp2_uid91_fpSinCosXTest_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => multSinOp2_uid91_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor(LOGICAL,1320)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q <= not (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a or ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b);
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena(REG,1321)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd(LOGICAL,1322)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b <= en;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a and ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b;
--cPi_uid71_fpSinCosXTest(CONSTANT,70)
cPi_uid71_fpSinCosXTest_q <= "11001001000011111101101011";
--LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest(BITSELECT,309)@27
LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q(63 downto 0);
LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in(63 downto 0);
--leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest(BITJOIN,310)@27
leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b & GND_q;
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor(LOGICAL,1433)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q <= not (ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a or ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b);
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena(REG,1434)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q = "1") THEN
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd(LOGICAL,1435)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b <= en;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a and ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b;
--X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest(BITSELECT,280)@21
X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(32 downto 0);
X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b <= X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in(32 downto 0);
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg(DELAY,1425)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem(DUALMEM,1426)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 33,
widthad_a => 1,
numwords_a => 2,
width_b => 33,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia
);
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq(32 downto 0);
--leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest(BITJOIN,281)@25
leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor(LOGICAL,1444)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q <= not (ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a or ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b);
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena(REG,1445)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q = "1") THEN
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd(LOGICAL,1446)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b <= en;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a and ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg(DELAY,1436)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => zSin_uid60_fpSinCosXTest_q, xout => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem(DUALMEM,1437)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 65,
widthad_a => 1,
numwords_a => 2,
width_b => 65,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia
);
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq(64 downto 0);
--rVStage_uid237_lzcZSin_uid66_fpSinCosXTest(BITSELECT,236)@21
rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q;
rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in(64 downto 1);
--vCount_uid238_lzcZSin_uid66_fpSinCosXTest(LOGICAL,237)@21
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid236_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g(DELAY,903)@22
ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid240_lzcZSin_uid66_fpSinCosXTest(BITSELECT,239)@21
vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(0 downto 0);
vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in(0 downto 0);
--ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b(DELAY,861)@21
ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cStage_uid241_lzcZSin_uid66_fpSinCosXTest(BITJOIN,240)@22
cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q <= ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q & mO_uid239_lzcZSin_uid66_fpSinCosXTest_q;
--ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c(DELAY,863)@21
ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid243_lzcZSin_uid66_fpSinCosXTest(MUX,242)@22
vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid243_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s, en, ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q, cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid245_lzcZSin_uid66_fpSinCosXTest(BITSELECT,244)@22
rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in(63 downto 32);
--vCount_uid246_lzcZSin_uid66_fpSinCosXTest(LOGICAL,245)@22
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f(DELAY,902)@23
ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid247_lzcZSin_uid66_fpSinCosXTest(BITSELECT,246)@22
vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q(31 downto 0);
vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in(31 downto 0);
--ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d(DELAY,870)@22
ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c(DELAY,869)@22
ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid249_lzcZSin_uid66_fpSinCosXTest(MUX,248)@23
vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid249_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s, en, ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q, ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q)
BEGIN
CASE vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q;
WHEN OTHERS => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid251_lzcZSin_uid66_fpSinCosXTest(BITSELECT,250)@23
rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in(31 downto 16);
--vCount_uid252_lzcZSin_uid66_fpSinCosXTest(LOGICAL,251)@23
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b else "0";
--reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4(REG,585)@23
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q <= vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e(DELAY,901)@24
ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid253_lzcZSin_uid66_fpSinCosXTest(BITSELECT,252)@23
vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q(15 downto 0);
vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in(15 downto 0);
--vStagei_uid255_lzcZSin_uid66_fpSinCosXTest(MUX,254)@23
vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid255_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s, en, rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b, vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b;
WHEN "1" => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid257_lzcZSin_uid66_fpSinCosXTest(BITSELECT,256)@23
rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in(15 downto 8);
--reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1(REG,580)@23
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q <= rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid258_lzcZSin_uid66_fpSinCosXTest(LOGICAL,257)@24
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a <= reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q;
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b else "0";
--ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d(DELAY,900)@24
ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid259_lzcZSin_uid66_fpSinCosXTest(BITSELECT,258)@23
vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q(7 downto 0);
vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3(REG,582)@23
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q <= vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid261_lzcZSin_uid66_fpSinCosXTest(MUX,260)@24
vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid261_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s, en, reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q, reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid263_lzcZSin_uid66_fpSinCosXTest(BITSELECT,262)@24
rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in(7 downto 4);
--vCount_uid264_lzcZSin_uid66_fpSinCosXTest(LOGICAL,263)@24
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid265_lzcZSin_uid66_fpSinCosXTest(BITSELECT,264)@24
vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q(3 downto 0);
vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in(3 downto 0);
--reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3(REG,584)@24
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q <= vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2(REG,583)@24
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid267_lzcZSin_uid66_fpSinCosXTest(MUX,266)@25
vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid267_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s, en, reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q, reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid269_lzcZSin_uid66_fpSinCosXTest(BITSELECT,268)@25
rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in(3 downto 2);
--vCount_uid270_lzcZSin_uid66_fpSinCosXTest(LOGICAL,269)@25
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b else "0";
--vStage_uid271_lzcZSin_uid66_fpSinCosXTest(BITSELECT,270)@25
vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q(1 downto 0);
vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in(1 downto 0);
--vStagei_uid273_lzcZSin_uid66_fpSinCosXTest(MUX,272)@25
vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid273_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s, en, rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b, vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b;
WHEN "1" => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid275_lzcZSin_uid66_fpSinCosXTest(BITSELECT,274)@25
rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in(1 downto 1);
--vCount_uid276_lzcZSin_uid66_fpSinCosXTest(LOGICAL,275)@25
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b <= GND_q;
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b else "0";
--r_uid277_lzcZSin_uid66_fpSinCosXTest(BITJOIN,276)@25
r_uid277_lzcZSin_uid66_fpSinCosXTest_q <= ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q & ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q & ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q & ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q & vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q & vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q & vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q;
--leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest(BITSELECT,284)@25
leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q;
leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in(6 downto 5);
--leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest(MUX,285)@25
leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s <= leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b;
leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s, en, ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest(BITSELECT,293)@25
LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(40 downto 0);
LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in(40 downto 0);
--leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest(BITJOIN,294)@25
leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b & leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5(REG,590)@25
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest(BITSELECT,290)@25
LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(48 downto 0);
LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in(48 downto 0);
--leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest(BITJOIN,291)@25
leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4(REG,589)@25
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest(BITSELECT,287)@25
LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(56 downto 0);
LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in(56 downto 0);
--leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest(BITJOIN,288)@25
leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3(REG,588)@25
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2(REG,587)@25
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest(BITSELECT,295)@25
leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1(REG,586)@25
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q <= leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest(MUX,296)@26
leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s <= reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q;
leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s, en, reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest(BITSELECT,304)@26
LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(58 downto 0);
LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b(DELAY,927)@26
ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest(BITJOIN,305)@27
leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q;
--LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest(BITSELECT,301)@26
LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(60 downto 0);
LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b(DELAY,925)@26
ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest(BITJOIN,302)@27
leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest(BITSELECT,298)@26
LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(62 downto 0);
LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in(62 downto 0);
--ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b(DELAY,923)@26
ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest(BITJOIN,299)@27
leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2(REG,592)@26
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest(BITSELECT,306)@25
leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in(2 downto 1);
--ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a(DELAY,1214)@25
ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1(REG,591)@26
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q <= ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest(MUX,307)@27
leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s <= reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q;
leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s, en, reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest(BITSELECT,311)@25
leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b(DELAY,937)@25
ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest(MUX,312)@27
leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s <= ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q;
leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s, en, leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "0" => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "1" => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--pHigh_uid72_fpSinCosXTest(BITSELECT,71)@27
pHigh_uid72_fpSinCosXTest_in <= leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q;
pHigh_uid72_fpSinCosXTest_b <= pHigh_uid72_fpSinCosXTest_in(64 downto 39);
--reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2(REG,594)@27
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q <= pHigh_uid72_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a(DELAY,1216)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1(REG,593)@27
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--p_uid73_fpSinCosXTest(MUX,72)@28
p_uid73_fpSinCosXTest_s <= reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q;
p_uid73_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p_uid73_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE p_uid73_fpSinCosXTest_s IS
WHEN "0" => p_uid73_fpSinCosXTest_q <= reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q;
WHEN "1" => p_uid73_fpSinCosXTest_q <= cPi_uid71_fpSinCosXTest_q;
WHEN OTHERS => p_uid73_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg(DELAY,1312)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => p_uid73_fpSinCosXTest_q, xout => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem(DUALMEM,1313)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 1,
numwords_a => 2,
width_b => 26,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq,
address_a => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa,
data_a => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia
);
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0 <= areset;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq(25 downto 0);
--mulSin_uid92_fpSinCosXTest(MULT,91)@33
mulSin_uid92_fpSinCosXTest_pr <= UNSIGNED(mulSin_uid92_fpSinCosXTest_a) * UNSIGNED(mulSin_uid92_fpSinCosXTest_b);
mulSin_uid92_fpSinCosXTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulSin_uid92_fpSinCosXTest_a <= (others => '0');
mulSin_uid92_fpSinCosXTest_b <= (others => '0');
mulSin_uid92_fpSinCosXTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulSin_uid92_fpSinCosXTest_a <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q;
mulSin_uid92_fpSinCosXTest_b <= multSinOp2_uid91_fpSinCosXTest_q;
mulSin_uid92_fpSinCosXTest_s1 <= STD_LOGIC_VECTOR(mulSin_uid92_fpSinCosXTest_pr);
END IF;
END IF;
END PROCESS;
mulSin_uid92_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulSin_uid92_fpSinCosXTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulSin_uid92_fpSinCosXTest_q <= mulSin_uid92_fpSinCosXTest_s1;
END IF;
END IF;
END PROCESS;
--normBitSin_uid93_fpSinCosXTest(BITSELECT,92)@36
normBitSin_uid93_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q;
normBitSin_uid93_fpSinCosXTest_b <= normBitSin_uid93_fpSinCosXTest_in(51 downto 51);
--join_uid99_fpSinCosXTest(BITJOIN,98)@36
join_uid99_fpSinCosXTest_q <= reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q & normBitSin_uid93_fpSinCosXTest_b;
--sinRndOp_uid100_uid101_fpSinCosXTest(BITJOIN,100)@36
sinRndOp_uid100_uid101_fpSinCosXTest_q <= join_uid99_fpSinCosXTest_q & cstAllZWF_uid7_fpSinCosXTest_q & VCC_q;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor(LOGICAL,1333)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q <= not (ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a or ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b);
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena(REG,1334)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q = "1") THEN
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd(LOGICAL,1335)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b <= en;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a and ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor(LOGICAL,1283)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q <= not (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a or ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b);
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena(REG,1284)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd(LOGICAL,1285)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a and ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg(DELAY,1273)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expXRR_uid38_fpSinCosXTest_b, xout => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem(DUALMEM,1274)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 9,
width_b => 8,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia
);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1(REG,604)@25
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--expSinHC_uid74_fpSinCosXTest(SUB,73)@26
expSinHC_uid74_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expSinHC_uid74_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q);
expSinHC_uid74_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSinHC_uid74_fpSinCosXTest_a) - UNSIGNED(expSinHC_uid74_fpSinCosXTest_b));
expSinHC_uid74_fpSinCosXTest_q <= expSinHC_uid74_fpSinCosXTest_o(8 downto 0);
--expSinHCR_uid75_fpSinCosXTest(BITSELECT,74)@26
expSinHCR_uid75_fpSinCosXTest_in <= expSinHC_uid74_fpSinCosXTest_q(7 downto 0);
expSinHCR_uid75_fpSinCosXTest_b <= expSinHCR_uid75_fpSinCosXTest_in(7 downto 0);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b(DELAY,695)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expPSin_uid76_fpSinCosXTest(MUX,75)@26
expPSin_uid76_fpSinCosXTest_s <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q;
expPSin_uid76_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expPSin_uid76_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expPSin_uid76_fpSinCosXTest_s IS
WHEN "0" => expPSin_uid76_fpSinCosXTest_q <= expSinHCR_uid75_fpSinCosXTest_b;
WHEN "1" => expPSin_uid76_fpSinCosXTest_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => expPSin_uid76_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg(DELAY,1323)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expPSin_uid76_fpSinCosXTest_q, xout => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem(DUALMEM,1324)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 7,
width_b => 8,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia
);
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq(7 downto 0);
--fracRSinPreRndHigh_uid95_fpSinCosXTest(BITSELECT,94)@36
fracRSinPreRndHigh_uid95_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q(50 downto 0);
fracRSinPreRndHigh_uid95_fpSinCosXTest_b <= fracRSinPreRndHigh_uid95_fpSinCosXTest_in(50 downto 27);
--fracRSinPreRndLow_uid96_fpSinCosXTest(BITSELECT,95)@36
fracRSinPreRndLow_uid96_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q(49 downto 0);
fracRSinPreRndLow_uid96_fpSinCosXTest_b <= fracRSinPreRndLow_uid96_fpSinCosXTest_in(49 downto 26);
--fracRSinPreRnd_uid97_fpSinCosXTest(MUX,96)@36
fracRSinPreRnd_uid97_fpSinCosXTest_s <= normBitSin_uid93_fpSinCosXTest_b;
fracRSinPreRnd_uid97_fpSinCosXTest: PROCESS (fracRSinPreRnd_uid97_fpSinCosXTest_s, en, fracRSinPreRndLow_uid96_fpSinCosXTest_b, fracRSinPreRndHigh_uid95_fpSinCosXTest_b)
BEGIN
CASE fracRSinPreRnd_uid97_fpSinCosXTest_s IS
WHEN "0" => fracRSinPreRnd_uid97_fpSinCosXTest_q <= fracRSinPreRndLow_uid96_fpSinCosXTest_b;
WHEN "1" => fracRSinPreRnd_uid97_fpSinCosXTest_q <= fracRSinPreRndHigh_uid95_fpSinCosXTest_b;
WHEN OTHERS => fracRSinPreRnd_uid97_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracRSinPreRnd_uid98_uid98_fpSinCosXTest(BITJOIN,97)@36
expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q & fracRSinPreRnd_uid97_fpSinCosXTest_q;
--expFracRSin_uid102_fpSinCosXTest(ADD,101)@36
expFracRSin_uid102_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q);
expFracRSin_uid102_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0000000" & sinRndOp_uid100_uid101_fpSinCosXTest_q);
expFracRSin_uid102_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRSin_uid102_fpSinCosXTest_a) + UNSIGNED(expFracRSin_uid102_fpSinCosXTest_b));
expFracRSin_uid102_fpSinCosXTest_q <= expFracRSin_uid102_fpSinCosXTest_o(32 downto 0);
--expRCompSin_uid104_fpSinCosXTest(BITSELECT,103)@36
expRCompSin_uid104_fpSinCosXTest_in <= expFracRSin_uid102_fpSinCosXTest_q(31 downto 0);
expRCompSin_uid104_fpSinCosXTest_b <= expRCompSin_uid104_fpSinCosXTest_in(31 downto 24);
--reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2(REG,607)@36
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q <= expRCompSin_uid104_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor(LOGICAL,1537)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q <= not (ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a or ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b);
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena(REG,1538)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q = "1") THEN
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd(LOGICAL,1539)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b <= en;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a and ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b;
--expXIsZero_uid10_fpSinCosXTest(LOGICAL,9)@0
expXIsZero_uid10_fpSinCosXTest_a <= exp_uid9_fpSinCosXTest_b;
expXIsZero_uid10_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
expXIsZero_uid10_fpSinCosXTest_q <= "1" when expXIsZero_uid10_fpSinCosXTest_a = expXIsZero_uid10_fpSinCosXTest_b else "0";
--ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b(DELAY,746)@0
ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => expXIsZero_uid10_fpSinCosXTest_q, xout => ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excSelBitsSin_uid118_fpSinCosXTest(BITJOIN,117)@19
excSelBitsSin_uid118_fpSinCosXTest_q <= excRNaN_uid117_fpSinCosXTest_q & ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q & ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg(DELAY,1527)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => excSelBitsSin_uid118_fpSinCosXTest_q, xout => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem(DUALMEM,1528)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 4,
numwords_a => 14,
width_b => 3,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq,
address_a => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa,
data_a => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia
);
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0 <= areset;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq(2 downto 0);
--reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0(REG,533)@35
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--excSelSin_uid119_fpSinCosXTest(LOOKUP,118)@36
excSelSin_uid119_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excSelSin_uid119_fpSinCosXTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q) IS
WHEN "000" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN "001" => excSelSin_uid119_fpSinCosXTest_q <= "01";
WHEN "010" => excSelSin_uid119_fpSinCosXTest_q <= "10";
WHEN "011" => excSelSin_uid119_fpSinCosXTest_q <= "10";
WHEN "100" => excSelSin_uid119_fpSinCosXTest_q <= "11";
WHEN "101" => excSelSin_uid119_fpSinCosXTest_q <= "11";
WHEN "110" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN "111" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN OTHERS =>
excSelSin_uid119_fpSinCosXTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRPostExcSin_uid126_fpSinCosXTest(MUX,125)@37
expRPostExcSin_uid126_fpSinCosXTest_s <= excSelSin_uid119_fpSinCosXTest_q;
expRPostExcSin_uid126_fpSinCosXTest: PROCESS (expRPostExcSin_uid126_fpSinCosXTest_s, en, reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q, ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q, cstAllZWE_uid8_fpSinCosXTest_q, cstAllOWE_uid6_fpSinCosXTest_q)
BEGIN
CASE expRPostExcSin_uid126_fpSinCosXTest_s IS
WHEN "00" => expRPostExcSin_uid126_fpSinCosXTest_q <= reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q;
WHEN "01" => expRPostExcSin_uid126_fpSinCosXTest_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q;
WHEN "10" => expRPostExcSin_uid126_fpSinCosXTest_q <= cstAllZWE_uid8_fpSinCosXTest_q;
WHEN "11" => expRPostExcSin_uid126_fpSinCosXTest_q <= cstAllOWE_uid6_fpSinCosXTest_q;
WHEN OTHERS => expRPostExcSin_uid126_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor(LOGICAL,1346)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q <= not (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a or ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b);
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena(REG,1347)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd(LOGICAL,1348)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b <= en;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a and ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg(DELAY,1336)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => frac_uid13_fpSinCosXTest_b, xout => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem(DUALMEM,1337)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 6,
numwords_a => 35,
width_b => 23,
widthad_b => 6,
numwords_b => 35,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia
);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq(22 downto 0);
--fracRCompSin_uid103_fpSinCosXTest(BITSELECT,102)@36
fracRCompSin_uid103_fpSinCosXTest_in <= expFracRSin_uid102_fpSinCosXTest_q(23 downto 0);
fracRCompSin_uid103_fpSinCosXTest_b <= fracRCompSin_uid103_fpSinCosXTest_in(23 downto 1);
--reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2(REG,606)@36
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q <= fracRCompSin_uid103_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--fracRPostExcSin_uid122_fpSinCosXTest(MUX,121)@37
fracRPostExcSin_uid122_fpSinCosXTest_s <= excSelSin_uid119_fpSinCosXTest_q;
fracRPostExcSin_uid122_fpSinCosXTest: PROCESS (fracRPostExcSin_uid122_fpSinCosXTest_s, en, reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q, cstAllZWF_uid7_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q)
BEGIN
CASE fracRPostExcSin_uid122_fpSinCosXTest_s IS
WHEN "00" => fracRPostExcSin_uid122_fpSinCosXTest_q <= reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q;
WHEN "01" => fracRPostExcSin_uid122_fpSinCosXTest_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q;
WHEN "10" => fracRPostExcSin_uid122_fpSinCosXTest_q <= cstAllZWF_uid7_fpSinCosXTest_q;
WHEN "11" => fracRPostExcSin_uid122_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN OTHERS => fracRPostExcSin_uid122_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpSin_uid134_fpSinCosXTest(BITJOIN,133)@37
fpSin_uid134_fpSinCosXTest_q <= ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q & expRPostExcSin_uid126_fpSinCosXTest_q & fracRPostExcSin_uid122_fpSinCosXTest_q;
--xOut(GPOUT,4)@37
s <= fpSin_uid134_fpSinCosXTest_q;
c <= fpCos_uid162_fpSinCosXTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_sincos_s5
-- VHDL created on Wed Mar 27 09:55:14 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_sincos_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
s : out std_logic_vector(31 downto 0);
c : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_sincos_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid8_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid22_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid23_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShift_uid24_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid25_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid26_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstZwShiftP1_uid27_fpSinCosXTest_q : std_logic_vector (13 downto 0);
signal cstNaNwF_uid32_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal cstZmwFRRPwSM1_uid52_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal cPi_uid71_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal p_uid73_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal p_uid73_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal expPSin_uid76_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal expPSin_uid76_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal multSinOp2_uid91_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal multSinOp2_uid91_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_a : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_s1 : std_logic_vector (51 downto 0);
signal mulSin_uid92_fpSinCosXTest_pr : UNSIGNED (51 downto 0);
signal mulSin_uid92_fpSinCosXTest_q : std_logic_vector (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_a : std_logic_vector (25 downto 0);
signal mulCos_uid105_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal mulCos_uid105_fpSinCosXTest_s1 : std_logic_vector (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_pr : UNSIGNED (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_q : std_logic_vector (51 downto 0);
signal excSelSin_uid119_fpSinCosXTest_q : std_logic_vector(1 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expSelectorCos_uid145_fpSinCosXTest_q : std_logic_vector(1 downto 0);
signal signRCond2_uid152_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_d : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_d : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q : std_logic_vector (29 downto 0);
signal leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal zs_uid236_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal mO_uid239_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (62 downto 0);
signal zs_uid244_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal zs_uid250_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (5 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(63 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(63 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (47 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a : std_logic_vector (12 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr : SIGNED (26 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q : std_logic_vector (25 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a : std_logic_vector (14 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b : std_logic_vector (22 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr : SIGNED (38 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q : std_logic_vector (37 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a : std_logic_vector (12 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr : SIGNED (26 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q : std_logic_vector (25 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a : std_logic_vector (14 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b : std_logic_vector (22 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr : SIGNED (38 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q : std_logic_vector (37 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0 : std_logic;
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0 : std_logic;
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q : std_logic_vector (39 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a : std_logic_vector(81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b : std_logic_vector(81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o : std_logic_vector (81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q : std_logic_vector (81 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC0_uid394_tableGensinPiZ_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC1_uid396_tableGensinPiZ_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC2_uid398_tableGensinPiZ_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_q : std_logic_vector (12 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC0_uid400_tableGencosPiZ_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC1_uid402_tableGencosPiZ_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC2_uid404_tableGencosPiZ_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_q : std_logic_vector (12 downto 0);
signal reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q : std_logic_vector (2 downto 0);
signal reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q : std_logic_vector (39 downto 0);
signal reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (39 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q : std_logic_vector (26 downto 0);
signal reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (77 downto 0);
signal reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q : std_logic_vector (67 downto 0);
signal reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q : std_logic_vector (66 downto 0);
signal reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q : std_logic_vector (65 downto 0);
signal reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q : std_logic_vector (67 downto 0);
signal reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q : std_logic_vector (25 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q : std_logic_vector (12 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q : std_logic_vector (20 downto 0);
signal reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q : std_logic_vector (22 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q : std_logic_vector (29 downto 0);
signal reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q : std_logic_vector (6 downto 0);
signal reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q : std_logic_vector (22 downto 0);
signal reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q : std_logic_vector (0 downto 0);
signal reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q : std_logic_vector (12 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q : std_logic_vector (20 downto 0);
signal reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q : std_logic_vector (22 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q : std_logic_vector (29 downto 0);
signal reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q : std_logic_vector (25 downto 0);
signal reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q : std_logic_vector (25 downto 0);
signal reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q : std_logic_vector (6 downto 0);
signal reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q : std_logic_vector (22 downto 0);
signal reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q : std_logic_vector (3 downto 0);
signal reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q : std_logic_vector (52 downto 0);
signal ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q : std_logic_vector (65 downto 0);
signal ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q : std_logic_vector (67 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (7 downto 0);
signal ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (66 downto 0);
signal ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (65 downto 0);
signal ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (64 downto 0);
signal ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q : std_logic_vector (63 downto 0);
signal ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q : std_logic_vector (31 downto 0);
signal ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (58 downto 0);
signal ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q : std_logic_vector (63 downto 0);
signal ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q : std_logic_vector (31 downto 0);
signal ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (58 downto 0);
signal ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (76 downto 0);
signal ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (75 downto 0);
signal ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (74 downto 0);
signal ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q : std_logic_vector (12 downto 0);
signal ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q : std_logic_vector (53 downto 0);
signal ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q : std_logic_vector (12 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0 : std_logic;
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q : signal is true;
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q : std_logic_vector (6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0 : std_logic;
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q : signal is true;
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q : signal is true;
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0 : std_logic;
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0 : std_logic;
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0 : std_logic;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq : std_logic;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q : signal is true;
signal sinXIsXRR_uid41_fpSinCosXTest_a : std_logic_vector(11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_b : std_logic_vector(11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_o : std_logic_vector (11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_a : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_b : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_o : std_logic_vector (11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal yIsZero_uid51_fpSinCosXTest_a : std_logic_vector(65 downto 0);
signal yIsZero_uid51_fpSinCosXTest_b : std_logic_vector(65 downto 0);
signal yIsZero_uid51_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal pad_one_uid55_fpSinCosXTest_q : std_logic_vector (66 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_a : std_logic_vector(70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_b : std_logic_vector(70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_o : std_logic_vector (70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_c : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal InvCmpYToOneMinusY_uid61_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCmpYToOneMinusY_uid61_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid127_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid127_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvSinXIsXRR_uid128_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsXRR_uid128_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid131_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid131_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid132_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid132_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid136_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid136_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvCosXONe_uid149_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCosXONe_uid149_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid151_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid151_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvIntXParity_uid155_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvIntXParity_uid155_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal oFracXRR_uid43_uid43_fpSinCosXTest_q : std_logic_vector (53 downto 0);
signal half_uid53_fpSinCosXTest_q : std_logic_vector (65 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal exp_uid9_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal exp_uid9_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal frac_uid13_fpSinCosXTest_in : std_logic_vector (22 downto 0);
signal frac_uid13_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal signX_uid37_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal signX_uid37_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal expFracX_uid166_px_uid33_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal expFracX_uid166_px_uid33_fpSinCosXTest_b : std_logic_vector (30 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_q : std_logic_vector (9 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_a : std_logic_vector(65 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_b : std_logic_vector(65 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_a : std_logic_vector(67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_b : std_logic_vector(67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_o : std_logic_vector (67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal zSin_uid60_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal zSin_uid60_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal zCos_uid64_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal zCos_uid64_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal expSinHC_uid74_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal excRNaN_uid117_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid117_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid117_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracRPostExcSin_uid122_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExcSin_uid122_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal expRPostExcSin_uid126_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExcSin_uid126_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracRPostExcCos_uid142_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExcCos_uid142_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal expRPostExcCos_uid147_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExcCos_uid147_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cosXONe_uid148_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal cosXONe_uid148_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal cosXONe_uid148_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal finalExp_uid209_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal finalExp_uid209_rrx_uid34_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal extendedFracX_uid47_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal normBitSin_uid93_fpSinCosXTest_in : std_logic_vector (51 downto 0);
signal normBitSin_uid93_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal fracRSinPreRndHigh_uid95_fpSinCosXTest_in : std_logic_vector (50 downto 0);
signal fracRSinPreRndHigh_uid95_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracRSinPreRndLow_uid96_fpSinCosXTest_in : std_logic_vector (49 downto 0);
signal fracRSinPreRndLow_uid96_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal normBitCos_uid106_fpSinCosXTest_in : std_logic_vector (51 downto 0);
signal normBitCos_uid106_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal fracRCosPreRndHigh_uid108_fpSinCosXTest_in : std_logic_vector (50 downto 0);
signal fracRCosPreRndHigh_uid108_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracRCosPreRndLow_uid109_fpSinCosXTest_in : std_logic_vector (49 downto 0);
signal fracRCosPreRndLow_uid109_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q : std_logic_vector (52 downto 0);
signal leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b : std_logic_vector (23 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int : std_logic_vector (80 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q : std_logic_vector (80 downto 0);
signal os_uid196_rrx_uid34_fpSinCosXTest_q : std_logic_vector (79 downto 0);
signal leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal join_uid99_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal join_uid141_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal zSinYBottom_uid59_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal zSinYBottom_uid59_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal zSinOMyBottom_uid58_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal zSinOMyBottom_uid58_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal excSelBitsSin_uid118_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal fpSin_uid134_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal join_uid143_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal fpCos_uid162_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int : std_logic_vector (107 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q : std_logic_vector (107 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal fracX_uid187_rrx_uid34_fpSinCosXTest_in : std_logic_vector (22 downto 0);
signal fracX_uid187_rrx_uid34_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal oFracXRRSmallXRR_uid90_fpSinCosXTest_in : std_logic_vector (53 downto 0);
signal oFracXRRSmallXRR_uid90_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal R_uid167_px_uid33_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal InvFracXIsZero_uid16_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid16_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fxpXShiftVal_uid46_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal fxpXShiftVal_uid46_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal addr_uid81_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal addr_uid81_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal zPsinPiZ_uid84_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal zPsinPiZ_uid84_fpSinCosXTest_b : std_logic_vector (14 downto 0);
signal rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (32 downto 0);
signal addr_uid83_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal addr_uid83_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal zPcosPiZ_uid87_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal zPcosPiZ_uid87_fpSinCosXTest_b : std_logic_vector (14 downto 0);
signal rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (32 downto 0);
signal expSinHCR_uid75_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expSinHCR_uid75_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal expPCos_uid79_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expPCos_uid79_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (66 downto 0);
signal LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (66 downto 0);
signal LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (65 downto 0);
signal LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (58 downto 0);
signal rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (58 downto 0);
signal rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (76 downto 0);
signal LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (76 downto 0);
signal LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (75 downto 0);
signal LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (75 downto 0);
signal LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (74 downto 0);
signal LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (74 downto 0);
signal X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (59 downto 0);
signal X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (59 downto 0);
signal X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (55 downto 0);
signal X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (55 downto 0);
signal fracRSinPreRnd_uid97_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal fracRSinPreRnd_uid97_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal fracRCosPreRnd_uid110_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal fracRCosPreRnd_uid110_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal cosRndOp_uid112_uid113_fpSinCosXTest_q : std_logic_vector (24 downto 0);
signal rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal lowRangeB_uid408_polyEvalsinPiZ_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid408_polyEvalsinPiZ_b : std_logic_vector (0 downto 0);
signal highBBits_uid409_polyEvalsinPiZ_in : std_logic_vector (13 downto 0);
signal highBBits_uid409_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid414_polyEvalsinPiZ_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid414_polyEvalsinPiZ_b : std_logic_vector (1 downto 0);
signal highBBits_uid415_polyEvalsinPiZ_in : std_logic_vector (23 downto 0);
signal highBBits_uid415_polyEvalsinPiZ_b : std_logic_vector (21 downto 0);
signal lowRangeB_uid421_polyEvalcosPiZ_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid421_polyEvalcosPiZ_b : std_logic_vector (0 downto 0);
signal highBBits_uid422_polyEvalcosPiZ_in : std_logic_vector (13 downto 0);
signal highBBits_uid422_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid427_polyEvalcosPiZ_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid427_polyEvalcosPiZ_b : std_logic_vector (1 downto 0);
signal highBBits_uid428_polyEvalcosPiZ_in : std_logic_vector (23 downto 0);
signal highBBits_uid428_polyEvalcosPiZ_b : std_logic_vector (21 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in : std_logic_vector (80 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b : std_logic_vector (26 downto 0);
signal fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in : std_logic_vector (76 downto 0);
signal fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b : std_logic_vector (52 downto 0);
signal intXParity_uid49_fpSinCosXTest_in : std_logic_vector (67 downto 0);
signal intXParity_uid49_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal y_uid50_fpSinCosXTest_in : std_logic_vector (66 downto 0);
signal y_uid50_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal sinRndOp_uid100_uid101_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal expSelBitsCos_uid144_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a : std_logic_vector(108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b : std_logic_vector(108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o : std_logic_vector (108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q : std_logic_vector (108 downto 0);
signal oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal expX_uid186_rrx_uid34_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal expX_uid186_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal exc_N_uid17_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal yT1_uid406_polyEvalsinPiZ_in : std_logic_vector (14 downto 0);
signal yT1_uid406_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal yT1_uid419_polyEvalcosPiZ_in : std_logic_vector (14 downto 0);
signal yT1_uid419_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_a : std_logic_vector(32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_b : std_logic_vector(32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_o : std_logic_vector (32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_q : std_logic_vector (30 downto 0);
signal finalFrac_uid208_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal finalFrac_uid208_rrx_uid34_fpSinCosXTest_q : std_logic_vector (52 downto 0);
signal signComp_uid129_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_a : std_logic_vector(32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_b : std_logic_vector(32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_o : std_logic_vector (32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_q : std_logic_vector (32 downto 0);
signal leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal multFracBits_uid199_rrx_uid34_fpSinCosXTest_in : std_logic_vector (77 downto 0);
signal multFracBits_uid199_rrx_uid34_fpSinCosXTest_b : std_logic_vector (77 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b : std_logic_vector (26 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (5 downto 0);
signal fracRCompCos_uid115_fpSinCosXTest_in : std_logic_vector (23 downto 0);
signal fracRCompCos_uid115_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal expRCompSin_uid116_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal expRCompSin_uid116_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal s1_uid408_uid411_polyEvalsinPiZ_q : std_logic_vector (22 downto 0);
signal s2_uid414_uid417_polyEvalsinPiZ_q : std_logic_vector (32 downto 0);
signal s1_uid421_uid424_polyEvalcosPiZ_q : std_logic_vector (22 downto 0);
signal s2_uid427_uid430_polyEvalcosPiZ_q : std_logic_vector (32 downto 0);
signal RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q : std_logic_vector (61 downto 0);
signal signR_uid130_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signR_uid130_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signR_uid130_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal fracRCompSin_uid103_fpSinCosXTest_in : std_logic_vector (23 downto 0);
signal fracRCompSin_uid103_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal expRCompSin_uid104_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal expRCompSin_uid104_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in : std_logic_vector (77 downto 0);
signal multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (61 downto 0);
signal X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (61 downto 0);
signal X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (45 downto 0);
signal X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (45 downto 0);
signal X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (29 downto 0);
signal X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (29 downto 0);
signal expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal polyEvalSigsinPiZ_uid86_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal polyEvalSigsinPiZ_uid86_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal polyEvalSigcosPiZ_uid89_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal polyEvalSigcosPiZ_uid89_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal expXRR_uid38_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal expXRR_uid38_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal fracXRR_uid39_fpSinCosXTest_in : std_logic_vector (52 downto 0);
signal fracXRR_uid39_fpSinCosXTest_b : std_logic_vector (52 downto 0);
signal pHigh_uid72_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal pHigh_uid72_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal pCos_uid77_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal pCos_uid77_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal r_uid277_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (6 downto 0);
signal r_uid356_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (6 downto 0);
signal expCompOut_uid205_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expCompOut_uid205_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (73 downto 0);
signal LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (73 downto 0);
signal LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (69 downto 0);
signal LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (69 downto 0);
signal LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (65 downto 0);
signal LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (56 downto 0);
signal LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (48 downto 0);
signal LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (48 downto 0);
signal LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (40 downto 0);
signal LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (40 downto 0);
signal LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (56 downto 0);
signal LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (48 downto 0);
signal LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (48 downto 0);
signal LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (40 downto 0);
signal LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (40 downto 0);
signal leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
begin
--xIn(GPIN,3)@0
--GND(CONSTANT,0)
GND_q <= "0";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable(LOGICAL,1282)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q <= not ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor(LOGICAL,1422)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q <= not (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a or ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b);
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top(CONSTANT,1418)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q <= "01011";
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp(LOGICAL,1419)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q <= "1" when ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a = ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b else "0";
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg(REG,1420)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena(REG,1423)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd(LOGICAL,1424)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b <= en;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a and ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b;
--expFracX_uid166_px_uid33_fpSinCosXTest(BITSELECT,165)@0
expFracX_uid166_px_uid33_fpSinCosXTest_in <= a(30 downto 0);
expFracX_uid166_px_uid33_fpSinCosXTest_b <= expFracX_uid166_px_uid33_fpSinCosXTest_in(30 downto 0);
--R_uid167_px_uid33_fpSinCosXTest(BITJOIN,166)@0
R_uid167_px_uid33_fpSinCosXTest_q <= GND_q & expFracX_uid166_px_uid33_fpSinCosXTest_b;
--expX_uid186_rrx_uid34_fpSinCosXTest(BITSELECT,185)@0
expX_uid186_rrx_uid34_fpSinCosXTest_in <= R_uid167_px_uid33_fpSinCosXTest_q(30 downto 0);
expX_uid186_rrx_uid34_fpSinCosXTest_b <= expX_uid186_rrx_uid34_fpSinCosXTest_in(30 downto 23);
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg(DELAY,1412)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid186_rrx_uid34_fpSinCosXTest_b, xout => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt(COUNTER,1414)
-- every=1, low=0, high=11, step=1, init=1
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i = 10 THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i - 11;
ELSE
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg(REG,1415)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux(MUX,1416)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem(DUALMEM,1413)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 12,
width_b => 8,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia
);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--zs_uid244_lzcZSin_uid66_fpSinCosXTest(CONSTANT,243)
zs_uid244_lzcZSin_uid66_fpSinCosXTest_q <= "00000000000000000000000000000000";
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor(LOGICAL,1396)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q <= not (ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a or ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b);
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg(REG,1318)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena(REG,1397)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q = "1") THEN
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd(LOGICAL,1398)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b <= en;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a and ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg(DELAY,1388)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid167_px_uid33_fpSinCosXTest_q, xout => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt(COUNTER,1314)
-- every=1, low=0, high=1, step=1, init=1
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i,1));
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg(REG,1315)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux(MUX,1316)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s <= en;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux: PROCESS (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s, ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q, ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q)
BEGIN
CASE ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s IS
WHEN "0" => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
WHEN "1" => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem(DUALMEM,1389)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 1,
numwords_a => 2,
width_b => 32,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq,
address_a => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa,
data_a => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia
);
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0 <= areset;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq(31 downto 0);
--fracX_uid187_rrx_uid34_fpSinCosXTest(BITSELECT,186)@4
fracX_uid187_rrx_uid34_fpSinCosXTest_in <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q(22 downto 0);
fracX_uid187_rrx_uid34_fpSinCosXTest_b <= fracX_uid187_rrx_uid34_fpSinCosXTest_in(22 downto 0);
--oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest(BITJOIN,196)@4
oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q <= VCC_q & fracX_uid187_rrx_uid34_fpSinCosXTest_b;
--prod_uid198_rrx_uid34_fpSinCosXTest_b_0(BITSELECT,518)@4
prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in <= STD_LOGIC_VECTOR("000" & oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q);
prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b <= prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in(26 downto 0);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1(REG,539)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q <= prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShift_uid24_fpSinCosXTest(CONSTANT,23)
cstBiasMwShift_uid24_fpSinCosXTest_q <= "01110011";
--expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest(SUB,191)@0
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expX_uid186_rrx_uid34_fpSinCosXTest_b);
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0" & cstBiasMwShift_uid24_fpSinCosXTest_q);
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b));
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q <= expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o(8 downto 0);
--expXTableAddr_uid193_rrx_uid34_fpSinCosXTest(BITSELECT,192)@0
expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in <= expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q(7 downto 0);
expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b <= expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0(REG,534)@0
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q <= expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem(DUALMEM,514)@1
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia <= (others => '0');
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa <= (others => '0');
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab <= reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q;
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq,
address_a => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa,
data_a => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia
);
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0 <= areset;
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q <= rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1(REG,537)@3
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q <= rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem(DUALMEM,513)@1
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia <= (others => '0');
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa <= (others => '0');
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab <= reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q;
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq,
address_a => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa,
data_a => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia
);
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0 <= areset;
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q <= rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0(REG,536)@3
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q <= rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid196_rrx_uid34_fpSinCosXTest(BITJOIN,195)@4
os_uid196_rrx_uid34_fpSinCosXTest_q <= reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q & reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q;
--prod_uid198_rrx_uid34_fpSinCosXTest_a_2(BITSELECT,517)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in <= STD_LOGIC_VECTOR("0" & os_uid196_rrx_uid34_fpSinCosXTest_q);
prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in(80 downto 54);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0(REG,542)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0(MULT,521)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1;
END IF;
END IF;
END PROCESS;
--ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a(DELAY,1145)@8
ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a : dspba_delay
GENERIC MAP ( width => 54, depth => 1 )
PORT MAP ( xin => prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q, xout => ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--prod_uid198_rrx_uid34_fpSinCosXTest_align_2(BITSHIFT,524)@9
prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int <= ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int(107 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_a_1(BITSELECT,516)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in <= os_uid196_rrx_uid34_fpSinCosXTest_q(53 downto 0);
prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in(53 downto 27);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0(REG,540)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0(MULT,520)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_align_1(BITSHIFT,523)@8
prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int <= prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q & "000000000000000000000000000";
prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int(80 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_a_0(BITSELECT,515)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in <= os_uid196_rrx_uid34_fpSinCosXTest_q(26 downto 0);
prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in(26 downto 0);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0(REG,538)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0(MULT,519)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_align_0(BITSHIFT,522)@8
prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int <= prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int(53 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0(ADD,525)@8
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a <= STD_LOGIC_VECTOR("0000000000000000000000000000" & prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b <= STD_LOGIC_VECTOR("0" & prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a) + UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b));
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o(81 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0(ADD,526)@9
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a <= STD_LOGIC_VECTOR("000000000000000000000000000" & prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b <= STD_LOGIC_VECTOR("0" & prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a) + UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b));
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o(108 downto 0);
--multFracBits_uid199_rrx_uid34_fpSinCosXTest(BITSELECT,198)@9
multFracBits_uid199_rrx_uid34_fpSinCosXTest_in <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q(77 downto 0);
multFracBits_uid199_rrx_uid34_fpSinCosXTest_b <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_in(77 downto 0);
--multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest(BITSELECT,199)@9
multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b;
multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b <= multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in(77 downto 46);
--reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1(REG,544)@9
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,433)@10
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a(DELAY,1178)@10
ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xout => ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5(REG,555)@12
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q <= ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q;
END IF;
END IF;
END PROCESS;
--zs_uid250_lzcZSin_uid66_fpSinCosXTest(CONSTANT,249)
zs_uid250_lzcZSin_uid66_fpSinCosXTest_q <= "0000000000000000";
--mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest(CONSTANT,434)
mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "11111111111111111111111111111111";
--vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,436)@10
vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q, mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,438)@10
rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in(31 downto 16);
--reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1(REG,546)@10
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,439)@11
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4(REG,554)@11
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q <= vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e(DELAY,1081)@12
ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWE_uid8_fpSinCosXTest(CONSTANT,7)
cstAllZWE_uid8_fpSinCosXTest_q <= "00000000";
--vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,440)@10
vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q(15 downto 0);
vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in(15 downto 0);
--reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,548)@10
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,442)@11
vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q, reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,444)@11
rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in(15 downto 8);
--vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,445)@11
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i <= "1" when vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xin => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d(DELAY,1080)@12
ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xout => ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest(CONSTANT,212)
leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q <= "0000";
--vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,446)@11
vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q(7 downto 0);
vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,550)@11
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,549)@11
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,448)@12
vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q, reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,450)@12
rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in(7 downto 4);
--vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,451)@12
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,553)@12
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest(CONSTANT,226)
leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q <= "00";
--vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,452)@12
vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q(3 downto 0);
vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in(3 downto 0);
--vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,454)@12
vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b, vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
WHEN "1" => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,456)@12
rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in(3 downto 2);
--vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,457)@12
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i <= "1" when vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xin => vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,458)@12
vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q(1 downto 0);
vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in(1 downto 0);
--reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,552)@12
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,551)@12
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,460)@13
vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q, reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,462)@13
rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in(1 downto 1);
--vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,463)@13
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= GND_q;
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest(BITJOIN,464)@13
r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q & ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q & ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q & reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q & vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q & vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
--cstBiasM1_uid23_fpSinCosXTest(CONSTANT,22)
cstBiasM1_uid23_fpSinCosXTest_q <= "01111110";
--expCompOutExt_uid204_rrx_uid34_fpSinCosXTest(SUB,203)@13
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("000" & r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q);
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b));
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q <= expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o(8 downto 0);
--expCompOut_uid205_rrx_uid34_fpSinCosXTest(BITSELECT,204)@13
expCompOut_uid205_rrx_uid34_fpSinCosXTest_in <= expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q(7 downto 0);
expCompOut_uid205_rrx_uid34_fpSinCosXTest_b <= expCompOut_uid205_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2(REG,564)@13
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q <= expCompOut_uid205_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--xBranch_uid191_rrx_uid34_fpSinCosXTest(COMPARE,190)@0
xBranch_uid191_rrx_uid34_fpSinCosXTest_cin <= GND_q;
xBranch_uid191_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid24_fpSinCosXTest_q) & '0';
xBranch_uid191_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & expX_uid186_rrx_uid34_fpSinCosXTest_b) & xBranch_uid191_rrx_uid34_fpSinCosXTest_cin(0);
xBranch_uid191_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xBranch_uid191_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(xBranch_uid191_rrx_uid34_fpSinCosXTest_b));
xBranch_uid191_rrx_uid34_fpSinCosXTest_n(0) <= not xBranch_uid191_rrx_uid34_fpSinCosXTest_o(10);
--reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1(REG,563)@0
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q <= xBranch_uid191_rrx_uid34_fpSinCosXTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b(DELAY,829)@1
ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q, xout => ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalExp_uid209_rrx_uid34_fpSinCosXTest(MUX,208)@14
finalExp_uid209_rrx_uid34_fpSinCosXTest_s <= ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q;
finalExp_uid209_rrx_uid34_fpSinCosXTest: PROCESS (finalExp_uid209_rrx_uid34_fpSinCosXTest_s, en, reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q)
BEGIN
CASE finalExp_uid209_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b(DELAY,833)@14
ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => finalExp_uid209_rrx_uid34_fpSinCosXTest_q, xout => ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1409)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a or ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top(CONSTANT,1279)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q <= "01000";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp(LOGICAL,1280)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q <= "1" when ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a = ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b else "0";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg(REG,1281)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1410)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1411)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1399)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid187_rrx_uid34_fpSinCosXTest_b, xout => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt(COUNTER,1275)
-- every=1, low=0, high=8, step=1, init=1
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i = 7 THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i - 8;
ELSE
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg(REG,1276)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux(MUX,1277)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s, ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q, ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1400)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 4,
numwords_a => 9,
width_b => 23,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(22 downto 0);
--ZerosGB_uid206_rrx_uid34_fpSinCosXTest(CONSTANT,205)
ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q <= "000000000000000000000000000000";
--fracXRExt_uid207_rrx_uid34_fpSinCosXTest(BITJOIN,206)@15
fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q & ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q;
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1499)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1500)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1501)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,474)@9
X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(29 downto 0);
X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in(29 downto 0);
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1491)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 30, depth => 1 )
PORT MAP ( xin => X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1492)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 1,
numwords_a => 2,
width_b => 30,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(29 downto 0);
--leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest(CONSTANT,473)
leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,475)@13
leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1488)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1489)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1490)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,471)@9
X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(45 downto 0);
X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in(45 downto 0);
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1480)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1481)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 1,
numwords_a => 2,
width_b => 46,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(45 downto 0);
--leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,472)@13
leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1477)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1478)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1479)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,468)@9
X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(61 downto 0);
X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in(61 downto 0);
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1469)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1470)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 62,
widthad_a => 1,
numwords_a => 2,
width_b => 62,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(61 downto 0);
--leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,469)@13
leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor(LOGICAL,1510)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q <= not (ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a or ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b);
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena(REG,1511)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q = "1") THEN
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd(LOGICAL,1512)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b <= en;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a and ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg(DELAY,1502)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 78, depth => 1 )
PORT MAP ( xin => multFracBits_uid199_rrx_uid34_fpSinCosXTest_b, xout => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem(DUALMEM,1503)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 78,
widthad_a => 1,
numwords_a => 2,
width_b => 78,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia
);
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq(77 downto 0);
--leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,476)@13
leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in(5 downto 4);
--leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,477)@13
leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b;
leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,485)@13
LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(65 downto 0);
LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in(65 downto 0);
--leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest(CONSTANT,218)
leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q <= "000000000000";
--leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,486)@13
leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b & leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5(REG,560)@13
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,482)@13
LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(69 downto 0);
LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in(69 downto 0);
--leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,483)@13
leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4(REG,559)@13
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,479)@13
LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(73 downto 0);
LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in(73 downto 0);
--leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,480)@13
leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3(REG,558)@13
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2(REG,557)@13
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,487)@13
leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1(REG,556)@13
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,488)@14
leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q;
leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,496)@14
LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(74 downto 0);
LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in(74 downto 0);
--ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1112)@14
ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 75, depth => 1 )
PORT MAP ( xin => LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest(CONSTANT,229)
leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q <= "000";
--leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,497)@15
leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,493)@14
LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(75 downto 0);
LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in(75 downto 0);
--ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1110)@14
ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 76, depth => 1 )
PORT MAP ( xin => LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,494)@15
leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,490)@14
LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(76 downto 0);
LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in(76 downto 0);
--ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1108)@14
ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 77, depth => 1 )
PORT MAP ( xin => LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,491)@15
leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & GND_q;
--reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2(REG,562)@14
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,498)@13
leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a(DELAY,1184)@13
ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1(REG,561)@14
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,499)@15
leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q;
leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracCompOut_uid203_rrx_uid34_fpSinCosXTest(BITSELECT,202)@15
fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in <= leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q(76 downto 0);
fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b <= fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in(76 downto 24);
--ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b(DELAY,826)@0
ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => xBranch_uid191_rrx_uid34_fpSinCosXTest_n, xout => ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalFrac_uid208_rrx_uid34_fpSinCosXTest(MUX,207)@15
finalFrac_uid208_rrx_uid34_fpSinCosXTest_s <= ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q;
finalFrac_uid208_rrx_uid34_fpSinCosXTest: PROCESS (finalFrac_uid208_rrx_uid34_fpSinCosXTest_s, en, fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b, fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE finalFrac_uid208_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b;
WHEN "1" => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RRangeRed_uid210_rrx_uid34_fpSinCosXTest(BITJOIN,209)@15
RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q <= GND_q & ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q & finalFrac_uid208_rrx_uid34_fpSinCosXTest_q;
--expXRR_uid38_fpSinCosXTest(BITSELECT,37)@15
expXRR_uid38_fpSinCosXTest_in <= RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q(60 downto 0);
expXRR_uid38_fpSinCosXTest_b <= expXRR_uid38_fpSinCosXTest_in(60 downto 53);
--reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1(REG,565)@15
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q <= expXRR_uid38_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShiftM2_uid26_fpSinCosXTest(CONSTANT,25)
cstBiasMwShiftM2_uid26_fpSinCosXTest_q <= "01110000";
--cosXIsOneXRR_uid42_fpSinCosXTest(COMPARE,41)@16
cosXIsOneXRR_uid42_fpSinCosXTest_cin <= GND_q;
cosXIsOneXRR_uid42_fpSinCosXTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid26_fpSinCosXTest_q) & '0';
cosXIsOneXRR_uid42_fpSinCosXTest_b <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q) & cosXIsOneXRR_uid42_fpSinCosXTest_cin(0);
cosXIsOneXRR_uid42_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(cosXIsOneXRR_uid42_fpSinCosXTest_a) - SIGNED(cosXIsOneXRR_uid42_fpSinCosXTest_b));
cosXIsOneXRR_uid42_fpSinCosXTest_n(0) <= not cosXIsOneXRR_uid42_fpSinCosXTest_o(11);
--exp_uid9_fpSinCosXTest(BITSELECT,8)@0
exp_uid9_fpSinCosXTest_in <= a(30 downto 0);
exp_uid9_fpSinCosXTest_b <= exp_uid9_fpSinCosXTest_in(30 downto 23);
--sinXIsX_uid40_fpSinCosXTest(COMPARE,39)@0
sinXIsX_uid40_fpSinCosXTest_cin <= GND_q;
sinXIsX_uid40_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid24_fpSinCosXTest_q) & '0';
sinXIsX_uid40_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & exp_uid9_fpSinCosXTest_b) & sinXIsX_uid40_fpSinCosXTest_cin(0);
sinXIsX_uid40_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid40_fpSinCosXTest_a) - UNSIGNED(sinXIsX_uid40_fpSinCosXTest_b));
sinXIsX_uid40_fpSinCosXTest_n(0) <= not sinXIsX_uid40_fpSinCosXTest_o(10);
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a(DELAY,789)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--cosXONe_uid148_fpSinCosXTest(LOGICAL,147)@16
cosXONe_uid148_fpSinCosXTest_a <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q;
cosXONe_uid148_fpSinCosXTest_b <= cosXIsOneXRR_uid42_fpSinCosXTest_n;
cosXONe_uid148_fpSinCosXTest_q <= cosXONe_uid148_fpSinCosXTest_a or cosXONe_uid148_fpSinCosXTest_b;
--ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a(DELAY,791)@16
ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => cosXONe_uid148_fpSinCosXTest_q, xout => ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvCosXONe_uid149_fpSinCosXTest(LOGICAL,148)@20
InvCosXONe_uid149_fpSinCosXTest_a <= ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q;
InvCosXONe_uid149_fpSinCosXTest_q <= not InvCosXONe_uid149_fpSinCosXTest_a;
--cstZwShiftP1_uid27_fpSinCosXTest(CONSTANT,26)
cstZwShiftP1_uid27_fpSinCosXTest_q <= "00000000000000";
--fracXRR_uid39_fpSinCosXTest(BITSELECT,38)@15
fracXRR_uid39_fpSinCosXTest_in <= RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q(52 downto 0);
fracXRR_uid39_fpSinCosXTest_b <= fracXRR_uid39_fpSinCosXTest_in(52 downto 0);
--ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a(DELAY,668)@15
ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => fracXRR_uid39_fpSinCosXTest_b, xout => ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracXRR_uid43_uid43_fpSinCosXTest(BITJOIN,42)@16
oFracXRR_uid43_uid43_fpSinCosXTest_q <= VCC_q & ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q;
--extendedFracX_uid47_fpSinCosXTest(BITJOIN,46)@16
extendedFracX_uid47_fpSinCosXTest_q <= cstZwShiftP1_uid27_fpSinCosXTest_q & oFracXRR_uid43_uid43_fpSinCosXTest_q;
--X55dto0_uid220_fxpX_uid48_fpSinCosXTest(BITSELECT,219)@16
X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(55 downto 0);
X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b <= X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in(55 downto 0);
--leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest(BITJOIN,220)@16
leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q <= X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b & leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5(REG,571)@16
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q <= leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--X59dto0_uid217_fxpX_uid48_fpSinCosXTest(BITSELECT,216)@16
X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(59 downto 0);
X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b <= X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in(59 downto 0);
--leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest(BITJOIN,217)@16
leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q <= X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4(REG,570)@16
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q <= leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--X63dto0_uid214_fxpX_uid48_fpSinCosXTest(BITSELECT,213)@16
X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(63 downto 0);
X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b <= X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in(63 downto 0);
--leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest(BITJOIN,214)@16
leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q <= X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3(REG,569)@16
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q <= leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2(REG,568)@16
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q <= extendedFracX_uid47_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--fxpXShiftValExt_uid45_fpSinCosXTest(SUB,44)@16
fxpXShiftValExt_uid45_fpSinCosXTest_a <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q);
fxpXShiftValExt_uid45_fpSinCosXTest_b <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid26_fpSinCosXTest_q);
fxpXShiftValExt_uid45_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(fxpXShiftValExt_uid45_fpSinCosXTest_a) - SIGNED(fxpXShiftValExt_uid45_fpSinCosXTest_b));
fxpXShiftValExt_uid45_fpSinCosXTest_q <= fxpXShiftValExt_uid45_fpSinCosXTest_o(9 downto 0);
--fxpXShiftVal_uid46_fpSinCosXTest(BITSELECT,45)@16
fxpXShiftVal_uid46_fpSinCosXTest_in <= fxpXShiftValExt_uid45_fpSinCosXTest_q(3 downto 0);
fxpXShiftVal_uid46_fpSinCosXTest_b <= fxpXShiftVal_uid46_fpSinCosXTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest(BITSELECT,221)@16
leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in <= fxpXShiftVal_uid46_fpSinCosXTest_b;
leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b <= leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1(REG,567)@16
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q <= leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest(MUX,222)@17
leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s <= reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q;
leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest: PROCESS (leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s, en, reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q, reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q, reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q, reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest(BITSELECT,230)@17
LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(64 downto 0);
LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in(64 downto 0);
--ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b(DELAY,851)@17
ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest(BITJOIN,231)@18
leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q & leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest(BITSELECT,227)@17
LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(65 downto 0);
LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in(65 downto 0);
--ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b(DELAY,849)@17
ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 66, depth => 1 )
PORT MAP ( xin => LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest(BITJOIN,228)@18
leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest(BITSELECT,224)@17
LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(66 downto 0);
LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in(66 downto 0);
--ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b(DELAY,847)@17
ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 67, depth => 1 )
PORT MAP ( xin => LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest(BITJOIN,225)@18
leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q & GND_q;
--reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2(REG,573)@17
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest(BITSELECT,232)@16
leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in <= fxpXShiftVal_uid46_fpSinCosXTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b <= leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a(DELAY,1195)@16
ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b, xout => ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1(REG,572)@17
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q <= ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest(MUX,233)@18
leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s <= reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q;
leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest: PROCESS (leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s, en, reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q, leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q, leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q, leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q;
WHEN "10" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q;
WHEN "11" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid50_fpSinCosXTest(BITSELECT,49)@18
y_uid50_fpSinCosXTest_in <= leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q(66 downto 0);
y_uid50_fpSinCosXTest_b <= y_uid50_fpSinCosXTest_in(66 downto 1);
--ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b(DELAY,680)@18
ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 66, depth => 2 )
PORT MAP ( xin => y_uid50_fpSinCosXTest_b, xout => ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1(REG,575)@18
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q <= y_uid50_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--pad_one_uid55_fpSinCosXTest(BITJOIN,54)@18
pad_one_uid55_fpSinCosXTest_q <= VCC_q & STD_LOGIC_VECTOR((65 downto 1 => GND_q(0)) & GND_q);
--reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0(REG,574)@18
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q <= pad_one_uid55_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--oneMinusY_uid55_fpSinCosXTest(SUB,55)@19
oneMinusY_uid55_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q);
oneMinusY_uid55_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q);
oneMinusY_uid55_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid55_fpSinCosXTest_a) - UNSIGNED(oneMinusY_uid55_fpSinCosXTest_b));
oneMinusY_uid55_fpSinCosXTest_q <= oneMinusY_uid55_fpSinCosXTest_o(67 downto 0);
--reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0(REG,576)@19
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q <= oneMinusY_uid55_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid57_fpSinCosXTest(COMPARE,56)@20
cmpYToOneMinusY_uid57_fpSinCosXTest_cin <= GND_q;
cmpYToOneMinusY_uid57_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q) & '0';
cmpYToOneMinusY_uid57_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q) & cmpYToOneMinusY_uid57_fpSinCosXTest_cin(0);
cmpYToOneMinusY_uid57_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid57_fpSinCosXTest_a) - UNSIGNED(cmpYToOneMinusY_uid57_fpSinCosXTest_b));
cmpYToOneMinusY_uid57_fpSinCosXTest_c(0) <= cmpYToOneMinusY_uid57_fpSinCosXTest_o(70);
--InvCmpYToOneMinusY_uid61_fpSinCosXTest(LOGICAL,60)@20
InvCmpYToOneMinusY_uid61_fpSinCosXTest_a <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
InvCmpYToOneMinusY_uid61_fpSinCosXTest_q <= not InvCmpYToOneMinusY_uid61_fpSinCosXTest_a;
--intXParity_uid49_fpSinCosXTest(BITSELECT,48)@18
intXParity_uid49_fpSinCosXTest_in <= leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q;
intXParity_uid49_fpSinCosXTest_b <= intXParity_uid49_fpSinCosXTest_in(67 downto 67);
--ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b(DELAY,794)@18
ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => intXParity_uid49_fpSinCosXTest_b, xout => ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--yIsZero_uid51_fpSinCosXTest(LOGICAL,50)@19
yIsZero_uid51_fpSinCosXTest_a <= reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q;
yIsZero_uid51_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000000000000000000000000000000000" & GND_q);
yIsZero_uid51_fpSinCosXTest_q <= "1" when yIsZero_uid51_fpSinCosXTest_a = yIsZero_uid51_fpSinCosXTest_b else "0";
--ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a(DELAY,792)@19
ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => yIsZero_uid51_fpSinCosXTest_q, xout => ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvYIsZero_uid151_fpSinCosXTest(LOGICAL,150)@20
InvYIsZero_uid151_fpSinCosXTest_a <= ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q;
InvYIsZero_uid151_fpSinCosXTest_q <= not InvYIsZero_uid151_fpSinCosXTest_a;
--signRCond2_uid152_fpSinCosXTest(LOGICAL,151)@20
signRCond2_uid152_fpSinCosXTest_a <= InvYIsZero_uid151_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_b <= ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q;
signRCond2_uid152_fpSinCosXTest_c <= InvCmpYToOneMinusY_uid61_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_d <= InvCosXONe_uid149_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_q_i <= signRCond2_uid152_fpSinCosXTest_a and signRCond2_uid152_fpSinCosXTest_b and signRCond2_uid152_fpSinCosXTest_c and signRCond2_uid152_fpSinCosXTest_d;
signRCond2_uid152_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRCond2_uid152_fpSinCosXTest_q, xin => signRCond2_uid152_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--InvIntXParity_uid155_fpSinCosXTest(LOGICAL,154)@20
InvIntXParity_uid155_fpSinCosXTest_a <= ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q;
InvIntXParity_uid155_fpSinCosXTest_q <= not InvIntXParity_uid155_fpSinCosXTest_a;
--signRCond1_uid157_fpSinCosXTest(LOGICAL,156)@20
signRCond1_uid157_fpSinCosXTest_a <= InvYIsZero_uid151_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_b <= InvIntXParity_uid155_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_c <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
signRCond1_uid157_fpSinCosXTest_d <= InvCosXONe_uid149_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_q_i <= signRCond1_uid157_fpSinCosXTest_a and signRCond1_uid157_fpSinCosXTest_b and signRCond1_uid157_fpSinCosXTest_c and signRCond1_uid157_fpSinCosXTest_d;
signRCond1_uid157_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRCond1_uid157_fpSinCosXTest_q, xin => signRCond1_uid157_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--signRCos_uid158_fpSinCosXTest(LOGICAL,157)@21
signRCos_uid158_fpSinCosXTest_a <= signRCond1_uid157_fpSinCosXTest_q;
signRCos_uid158_fpSinCosXTest_b <= signRCond2_uid152_fpSinCosXTest_q;
signRCos_uid158_fpSinCosXTest_q <= signRCos_uid158_fpSinCosXTest_a or signRCos_uid158_fpSinCosXTest_b;
--cstAllZWF_uid7_fpSinCosXTest(CONSTANT,6)
cstAllZWF_uid7_fpSinCosXTest_q <= "00000000000000000000000";
--frac_uid13_fpSinCosXTest(BITSELECT,12)@0
frac_uid13_fpSinCosXTest_in <= a(22 downto 0);
frac_uid13_fpSinCosXTest_b <= frac_uid13_fpSinCosXTest_in(22 downto 0);
--fracXIsZero_uid14_fpSinCosXTest(LOGICAL,13)@0
fracXIsZero_uid14_fpSinCosXTest_a <= frac_uid13_fpSinCosXTest_b;
fracXIsZero_uid14_fpSinCosXTest_b <= cstAllZWF_uid7_fpSinCosXTest_q;
fracXIsZero_uid14_fpSinCosXTest_q <= "1" when fracXIsZero_uid14_fpSinCosXTest_a = fracXIsZero_uid14_fpSinCosXTest_b else "0";
--cstAllOWE_uid6_fpSinCosXTest(CONSTANT,5)
cstAllOWE_uid6_fpSinCosXTest_q <= "11111111";
--expXIsMax_uid12_fpSinCosXTest(LOGICAL,11)@0
expXIsMax_uid12_fpSinCosXTest_a <= exp_uid9_fpSinCosXTest_b;
expXIsMax_uid12_fpSinCosXTest_b <= cstAllOWE_uid6_fpSinCosXTest_q;
expXIsMax_uid12_fpSinCosXTest_q <= "1" when expXIsMax_uid12_fpSinCosXTest_a = expXIsMax_uid12_fpSinCosXTest_b else "0";
--exc_I_uid15_fpSinCosXTest(LOGICAL,14)@0
exc_I_uid15_fpSinCosXTest_a <= expXIsMax_uid12_fpSinCosXTest_q;
exc_I_uid15_fpSinCosXTest_b <= fracXIsZero_uid14_fpSinCosXTest_q;
exc_I_uid15_fpSinCosXTest_q <= exc_I_uid15_fpSinCosXTest_a and exc_I_uid15_fpSinCosXTest_b;
--ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a(DELAY,762)@0
ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 20 )
PORT MAP ( xin => exc_I_uid15_fpSinCosXTest_q, xout => ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_I_uid131_fpSinCosXTest(LOGICAL,130)@20
InvExc_I_uid131_fpSinCosXTest_a <= ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q;
InvExc_I_uid131_fpSinCosXTest_q <= not InvExc_I_uid131_fpSinCosXTest_a;
--reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2(REG,649)@20
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q <= InvExc_I_uid131_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--InvFracXIsZero_uid16_fpSinCosXTest(LOGICAL,15)@0
InvFracXIsZero_uid16_fpSinCosXTest_a <= fracXIsZero_uid14_fpSinCosXTest_q;
InvFracXIsZero_uid16_fpSinCosXTest_q <= not InvFracXIsZero_uid16_fpSinCosXTest_a;
--exc_N_uid17_fpSinCosXTest(LOGICAL,16)@0
exc_N_uid17_fpSinCosXTest_a <= expXIsMax_uid12_fpSinCosXTest_q;
exc_N_uid17_fpSinCosXTest_b <= InvFracXIsZero_uid16_fpSinCosXTest_q;
exc_N_uid17_fpSinCosXTest_q <= exc_N_uid17_fpSinCosXTest_a and exc_N_uid17_fpSinCosXTest_b;
--ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a(DELAY,763)@0
ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 20 )
PORT MAP ( xin => exc_N_uid17_fpSinCosXTest_q, xout => ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid132_fpSinCosXTest(LOGICAL,131)@20
InvExc_N_uid132_fpSinCosXTest_a <= ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q;
InvExc_N_uid132_fpSinCosXTest_q <= not InvExc_N_uid132_fpSinCosXTest_a;
--reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1(REG,648)@20
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q <= InvExc_N_uid132_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--signRCosFull_uid161_fpSinCosXTest(LOGICAL,160)@21
signRCosFull_uid161_fpSinCosXTest_a <= reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q;
signRCosFull_uid161_fpSinCosXTest_b <= reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q;
signRCosFull_uid161_fpSinCosXTest_c <= signRCos_uid158_fpSinCosXTest_q;
signRCosFull_uid161_fpSinCosXTest_q <= signRCosFull_uid161_fpSinCosXTest_a and signRCosFull_uid161_fpSinCosXTest_b and signRCosFull_uid161_fpSinCosXTest_c;
--ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c(DELAY,809)@21
ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signRCosFull_uid161_fpSinCosXTest_q, xout => ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid22_fpSinCosXTest(CONSTANT,21)
cstBias_uid22_fpSinCosXTest_q <= "01111111";
--ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a(DELAY,681)@19
ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 68, depth => 1 )
PORT MAP ( xin => oneMinusY_uid55_fpSinCosXTest_q, xout => ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--zSinOMyBottom_uid58_fpSinCosXTest(BITSELECT,57)@20
zSinOMyBottom_uid58_fpSinCosXTest_in <= ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q(64 downto 0);
zSinOMyBottom_uid58_fpSinCosXTest_b <= zSinOMyBottom_uid58_fpSinCosXTest_in(64 downto 0);
--reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3(REG,579)@20
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q <= zSinOMyBottom_uid58_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--zSinYBottom_uid59_fpSinCosXTest(BITSELECT,58)@20
zSinYBottom_uid59_fpSinCosXTest_in <= ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q(64 downto 0);
zSinYBottom_uid59_fpSinCosXTest_b <= zSinYBottom_uid59_fpSinCosXTest_in(64 downto 0);
--reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2(REG,578)@20
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q <= zSinYBottom_uid59_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1(REG,614)@20
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q <= InvCmpYToOneMinusY_uid61_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--zCos_uid64_fpSinCosXTest(MUX,63)@21
zCos_uid64_fpSinCosXTest_s <= reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q;
zCos_uid64_fpSinCosXTest: PROCESS (zCos_uid64_fpSinCosXTest_s, en, reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q, reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q)
BEGIN
CASE zCos_uid64_fpSinCosXTest_s IS
WHEN "0" => zCos_uid64_fpSinCosXTest_q <= reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q;
WHEN "1" => zCos_uid64_fpSinCosXTest_q <= reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q;
WHEN OTHERS => zCos_uid64_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--addr_uid83_fpSinCosXTest(BITSELECT,82)@21
addr_uid83_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q;
addr_uid83_fpSinCosXTest_b <= addr_uid83_fpSinCosXTest_in(64 downto 57);
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0(REG,630)@21
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q <= addr_uid83_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid404_tableGencosPiZ_lutmem(DUALMEM,532)@22
memoryC2_uid404_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC2_uid404_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC2_uid404_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q;
memoryC2_uid404_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC2_uid404_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid404_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid404_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid404_tableGencosPiZ_lutmem_iq,
address_a => memoryC2_uid404_tableGencosPiZ_lutmem_aa,
data_a => memoryC2_uid404_tableGencosPiZ_lutmem_ia
);
memoryC2_uid404_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC2_uid404_tableGencosPiZ_lutmem_q <= memoryC2_uid404_tableGencosPiZ_lutmem_iq(12 downto 0);
--reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1(REG,632)@24
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q <= memoryC2_uid404_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPcosPiZ_uid87_fpSinCosXTest(BITSELECT,86)@21
zPcosPiZ_uid87_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(56 downto 0);
zPcosPiZ_uid87_fpSinCosXTest_b <= zPcosPiZ_uid87_fpSinCosXTest_in(56 downto 42);
--yT1_uid419_polyEvalcosPiZ(BITSELECT,418)@21
yT1_uid419_polyEvalcosPiZ_in <= zPcosPiZ_uid87_fpSinCosXTest_b;
yT1_uid419_polyEvalcosPiZ_b <= yT1_uid419_polyEvalcosPiZ_in(14 downto 2);
--reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0(REG,631)@21
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q <= yT1_uid419_polyEvalcosPiZ_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg(DELAY,1513)
ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q, xout => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a(DELAY,1125)@22
ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q, xout => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid508_pT1_uid420_polyEvalcosPiZ(MULT,507)@25
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a),14)) * SIGNED(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b);
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a <= (others => '0');
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b <= (others => '0');
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a <= ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b <= reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q <= prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ(BITSELECT,508)@28
prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in <= prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q;
prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in(25 downto 12);
--highBBits_uid422_polyEvalcosPiZ(BITSELECT,421)@28
highBBits_uid422_polyEvalcosPiZ_in <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b;
highBBits_uid422_polyEvalcosPiZ_b <= highBBits_uid422_polyEvalcosPiZ_in(13 downto 1);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a(DELAY,1256)@21
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => addr_uid83_fpSinCosXTest_b, xout => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0(REG,633)@24
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid402_tableGencosPiZ_lutmem(DUALMEM,531)@25
memoryC1_uid402_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC1_uid402_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC1_uid402_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q;
memoryC1_uid402_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC1_uid402_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid402_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid402_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid402_tableGencosPiZ_lutmem_iq,
address_a => memoryC1_uid402_tableGencosPiZ_lutmem_aa,
data_a => memoryC1_uid402_tableGencosPiZ_lutmem_ia
);
memoryC1_uid402_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC1_uid402_tableGencosPiZ_lutmem_q <= memoryC1_uid402_tableGencosPiZ_lutmem_iq(20 downto 0);
--reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0(REG,634)@27
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q <= memoryC1_uid402_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid423_polyEvalcosPiZ(ADD,422)@28
sumAHighB_uid423_polyEvalcosPiZ_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q(20)) & reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q);
sumAHighB_uid423_polyEvalcosPiZ_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid422_polyEvalcosPiZ_b(12)) & highBBits_uid422_polyEvalcosPiZ_b);
sumAHighB_uid423_polyEvalcosPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid423_polyEvalcosPiZ_a) + SIGNED(sumAHighB_uid423_polyEvalcosPiZ_b));
sumAHighB_uid423_polyEvalcosPiZ_q <= sumAHighB_uid423_polyEvalcosPiZ_o(21 downto 0);
--lowRangeB_uid421_polyEvalcosPiZ(BITSELECT,420)@28
lowRangeB_uid421_polyEvalcosPiZ_in <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b(0 downto 0);
lowRangeB_uid421_polyEvalcosPiZ_b <= lowRangeB_uid421_polyEvalcosPiZ_in(0 downto 0);
--s1_uid421_uid424_polyEvalcosPiZ(BITJOIN,423)@28
s1_uid421_uid424_polyEvalcosPiZ_q <= sumAHighB_uid423_polyEvalcosPiZ_q & lowRangeB_uid421_polyEvalcosPiZ_b;
--reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1(REG,636)@28
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q <= s1_uid421_uid424_polyEvalcosPiZ_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor(LOGICAL,1524)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q <= not (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a or ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b);
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top(CONSTANT,1520)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q <= "0100";
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp(LOGICAL,1521)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q <= "1" when ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a = ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b else "0";
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg(REG,1522)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena(REG,1525)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd(LOGICAL,1526)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b <= en;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a and ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b;
--reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0(REG,635)@21
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q <= zPcosPiZ_uid87_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg(DELAY,1514)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q, xout => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt(COUNTER,1516)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i = 3 THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i,3));
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg(REG,1517)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux(MUX,1518)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s <= en;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux: PROCESS (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s, ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q, ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem(DUALMEM,1515)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq,
address_a => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa,
data_a => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia
);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0 <= areset;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq(14 downto 0);
--prodXY_uid511_pT2_uid426_polyEvalcosPiZ(MULT,510)@29
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a),16)) * SIGNED(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b);
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a <= (others => '0');
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b <= (others => '0');
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b <= reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q <= prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ(BITSELECT,511)@32
prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in <= prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q;
prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in(37 downto 14);
--highBBits_uid428_polyEvalcosPiZ(BITSELECT,427)@32
highBBits_uid428_polyEvalcosPiZ_in <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b;
highBBits_uid428_polyEvalcosPiZ_b <= highBBits_uid428_polyEvalcosPiZ_in(23 downto 2);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor(LOGICAL,1577)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q <= not (ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a or ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena(REG,1578)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q = "1") THEN
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd(LOGICAL,1579)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b <= en;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a and ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b;
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg(DELAY,1567)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addr_uid83_fpSinCosXTest_b, xout => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem(DUALMEM,1568)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq,
address_a => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa,
data_a => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia
);
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0(REG,637)@28
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid400_tableGencosPiZ_lutmem(DUALMEM,530)@29
memoryC0_uid400_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC0_uid400_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC0_uid400_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q;
memoryC0_uid400_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC0_uid400_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid400_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid400_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid400_tableGencosPiZ_lutmem_iq,
address_a => memoryC0_uid400_tableGencosPiZ_lutmem_aa,
data_a => memoryC0_uid400_tableGencosPiZ_lutmem_ia
);
memoryC0_uid400_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC0_uid400_tableGencosPiZ_lutmem_q <= memoryC0_uid400_tableGencosPiZ_lutmem_iq(29 downto 0);
--reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0(REG,638)@31
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q <= memoryC0_uid400_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid429_polyEvalcosPiZ(ADD,428)@32
sumAHighB_uid429_polyEvalcosPiZ_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q(29)) & reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q);
sumAHighB_uid429_polyEvalcosPiZ_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid428_polyEvalcosPiZ_b(21)) & highBBits_uid428_polyEvalcosPiZ_b);
sumAHighB_uid429_polyEvalcosPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid429_polyEvalcosPiZ_a) + SIGNED(sumAHighB_uid429_polyEvalcosPiZ_b));
sumAHighB_uid429_polyEvalcosPiZ_q <= sumAHighB_uid429_polyEvalcosPiZ_o(30 downto 0);
--lowRangeB_uid427_polyEvalcosPiZ(BITSELECT,426)@32
lowRangeB_uid427_polyEvalcosPiZ_in <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b(1 downto 0);
lowRangeB_uid427_polyEvalcosPiZ_b <= lowRangeB_uid427_polyEvalcosPiZ_in(1 downto 0);
--s2_uid427_uid430_polyEvalcosPiZ(BITJOIN,429)@32
s2_uid427_uid430_polyEvalcosPiZ_q <= sumAHighB_uid429_polyEvalcosPiZ_q & lowRangeB_uid427_polyEvalcosPiZ_b;
--polyEvalSigcosPiZ_uid89_fpSinCosXTest(BITSELECT,88)@32
polyEvalSigcosPiZ_uid89_fpSinCosXTest_in <= s2_uid427_uid430_polyEvalcosPiZ_q(30 downto 0);
polyEvalSigcosPiZ_uid89_fpSinCosXTest_b <= polyEvalSigcosPiZ_uid89_fpSinCosXTest_in(30 downto 5);
--reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1(REG,640)@32
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q <= polyEvalSigcosPiZ_uid89_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor(LOGICAL,1590)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q <= not (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a or ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b);
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top(CONSTANT,1586)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q <= "010";
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp(LOGICAL,1587)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q <= "1" when ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a = ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b else "0";
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg(REG,1588)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena(REG,1591)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd(LOGICAL,1592)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b <= en;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a and ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b;
--LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest(BITSELECT,388)@27
LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q(63 downto 0);
LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in(63 downto 0);
--leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest(BITJOIN,389)@27
leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b & GND_q;
--cstZmwFRRPwSM1_uid52_fpSinCosXTest(CONSTANT,51)
cstZmwFRRPwSM1_uid52_fpSinCosXTest_q <= "00000000000000000000000000000000000000000000000000000000000000000";
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor(LOGICAL,1455)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q <= not (ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a or ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b);
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena(REG,1456)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q = "1") THEN
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd(LOGICAL,1457)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b <= en;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a and ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b;
--X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest(BITSELECT,359)@21
X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(32 downto 0);
X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b <= X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in(32 downto 0);
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg(DELAY,1447)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem(DUALMEM,1448)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 33,
widthad_a => 1,
numwords_a => 2,
width_b => 33,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia
);
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq(32 downto 0);
--leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest(BITJOIN,360)@25
leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor(LOGICAL,1466)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q <= not (ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a or ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b);
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena(REG,1467)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q = "1") THEN
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd(LOGICAL,1468)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b <= en;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a and ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg(DELAY,1458)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => zCos_uid64_fpSinCosXTest_q, xout => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem(DUALMEM,1459)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 65,
widthad_a => 1,
numwords_a => 2,
width_b => 65,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia
);
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq(64 downto 0);
--zs_uid236_lzcZSin_uid66_fpSinCosXTest(CONSTANT,235)
zs_uid236_lzcZSin_uid66_fpSinCosXTest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--rVStage_uid316_lzcZCos_uid69_fpSinCosXTest(BITSELECT,315)@21
rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q;
rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in(64 downto 1);
--vCount_uid317_lzcZCos_uid69_fpSinCosXTest(LOGICAL,316)@21
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid236_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g(DELAY,985)@22
ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid319_lzcZCos_uid69_fpSinCosXTest(BITSELECT,318)@21
vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(0 downto 0);
vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in(0 downto 0);
--ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b(DELAY,943)@21
ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid239_lzcZSin_uid66_fpSinCosXTest(CONSTANT,238)
mO_uid239_lzcZSin_uid66_fpSinCosXTest_q <= "111111111111111111111111111111111111111111111111111111111111111";
--cStage_uid320_lzcZCos_uid69_fpSinCosXTest(BITJOIN,319)@22
cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q <= ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q & mO_uid239_lzcZSin_uid66_fpSinCosXTest_q;
--ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c(DELAY,945)@21
ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid322_lzcZCos_uid69_fpSinCosXTest(MUX,321)@22
vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid322_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s, en, ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q, cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid324_lzcZCos_uid69_fpSinCosXTest(BITSELECT,323)@22
rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in(63 downto 32);
--vCount_uid325_lzcZCos_uid69_fpSinCosXTest(LOGICAL,324)@22
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f(DELAY,984)@23
ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid326_lzcZCos_uid69_fpSinCosXTest(BITSELECT,325)@22
vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q(31 downto 0);
vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in(31 downto 0);
--ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d(DELAY,952)@22
ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c(DELAY,951)@22
ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid328_lzcZCos_uid69_fpSinCosXTest(MUX,327)@23
vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid328_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s, en, ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q, ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q)
BEGIN
CASE vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q;
WHEN OTHERS => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid330_lzcZCos_uid69_fpSinCosXTest(BITSELECT,329)@23
rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in(31 downto 16);
--vCount_uid331_lzcZCos_uid69_fpSinCosXTest(LOGICAL,330)@23
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b else "0";
--reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4(REG,622)@23
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q <= vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e(DELAY,983)@24
ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid332_lzcZCos_uid69_fpSinCosXTest(BITSELECT,331)@23
vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q(15 downto 0);
vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in(15 downto 0);
--vStagei_uid334_lzcZCos_uid69_fpSinCosXTest(MUX,333)@23
vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid334_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s, en, rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b, vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b;
WHEN "1" => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid336_lzcZCos_uid69_fpSinCosXTest(BITSELECT,335)@23
rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in(15 downto 8);
--reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1(REG,617)@23
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q <= rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid337_lzcZCos_uid69_fpSinCosXTest(LOGICAL,336)@24
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a <= reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q;
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b else "0";
--ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d(DELAY,982)@24
ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid338_lzcZCos_uid69_fpSinCosXTest(BITSELECT,337)@23
vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q(7 downto 0);
vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3(REG,619)@23
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q <= vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid340_lzcZCos_uid69_fpSinCosXTest(MUX,339)@24
vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid340_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s, en, reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q, reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid342_lzcZCos_uid69_fpSinCosXTest(BITSELECT,341)@24
rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in(7 downto 4);
--vCount_uid343_lzcZCos_uid69_fpSinCosXTest(LOGICAL,342)@24
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid344_lzcZCos_uid69_fpSinCosXTest(BITSELECT,343)@24
vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q(3 downto 0);
vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in(3 downto 0);
--reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3(REG,621)@24
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q <= vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2(REG,620)@24
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid346_lzcZCos_uid69_fpSinCosXTest(MUX,345)@25
vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid346_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s, en, reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q, reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid348_lzcZCos_uid69_fpSinCosXTest(BITSELECT,347)@25
rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in(3 downto 2);
--vCount_uid349_lzcZCos_uid69_fpSinCosXTest(LOGICAL,348)@25
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b else "0";
--vStage_uid350_lzcZCos_uid69_fpSinCosXTest(BITSELECT,349)@25
vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q(1 downto 0);
vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in(1 downto 0);
--vStagei_uid352_lzcZCos_uid69_fpSinCosXTest(MUX,351)@25
vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid352_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s, en, rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b, vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b;
WHEN "1" => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid354_lzcZCos_uid69_fpSinCosXTest(BITSELECT,353)@25
rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in(1 downto 1);
--vCount_uid355_lzcZCos_uid69_fpSinCosXTest(LOGICAL,354)@25
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b <= GND_q;
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b else "0";
--r_uid356_lzcZCos_uid69_fpSinCosXTest(BITJOIN,355)@25
r_uid356_lzcZCos_uid69_fpSinCosXTest_q <= ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q & ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q & ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q & ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q & vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q & vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q & vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q;
--leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest(BITSELECT,363)@25
leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q;
leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in(6 downto 5);
--leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest(MUX,364)@25
leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s <= leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b;
leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s, en, ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest(BITSELECT,372)@25
LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(40 downto 0);
LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in(40 downto 0);
--leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest(CONSTANT,292)
leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q <= "000000000000000000000000";
--leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest(BITJOIN,373)@25
leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b & leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5(REG,627)@25
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest(BITSELECT,369)@25
LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(48 downto 0);
LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in(48 downto 0);
--leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest(BITJOIN,370)@25
leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4(REG,626)@25
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest(BITSELECT,366)@25
LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(56 downto 0);
LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in(56 downto 0);
--leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest(BITJOIN,367)@25
leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3(REG,625)@25
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2(REG,624)@25
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest(BITSELECT,374)@25
leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1(REG,623)@25
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q <= leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest(MUX,375)@26
leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s <= reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q;
leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s, en, reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest(BITSELECT,383)@26
LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(58 downto 0);
LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1009)@26
ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest(CONSTANT,303)
leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q <= "000000";
--leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest(BITJOIN,384)@27
leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q;
--LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest(BITSELECT,380)@26
LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(60 downto 0);
LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1007)@26
ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest(BITJOIN,381)@27
leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest(BITSELECT,377)@26
LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(62 downto 0);
LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in(62 downto 0);
--ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1005)@26
ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest(BITJOIN,378)@27
leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2(REG,629)@26
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest(BITSELECT,385)@25
leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1(REG,628)@25
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q <= leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1011)@26
ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest(MUX,386)@27
leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s <= ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q;
leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s, en, reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest(BITSELECT,390)@25
leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1019)@25
ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest(MUX,391)@27
leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s <= ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q;
leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s, en, leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "0" => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "1" => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--pCos_uid77_fpSinCosXTest(BITSELECT,76)@27
pCos_uid77_fpSinCosXTest_in <= leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q;
pCos_uid77_fpSinCosXTest_b <= pCos_uid77_fpSinCosXTest_in(64 downto 39);
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg(DELAY,1580)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => pCos_uid77_fpSinCosXTest_b, xout => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt(COUNTER,1582)
-- every=1, low=0, high=2, step=1, init=1
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i = 1 THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i - 2;
ELSE
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i,2));
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg(REG,1583)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux(MUX,1584)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s <= en;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux: PROCESS (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s, ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q, ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q)
BEGIN
CASE ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s IS
WHEN "0" => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q;
WHEN "1" => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem(DUALMEM,1581)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 2,
numwords_a => 3,
width_b => 26,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq,
address_a => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa,
data_a => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia
);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0 <= areset;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq(25 downto 0);
--reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0(REG,639)@32
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--mulCos_uid105_fpSinCosXTest(MULT,104)@33
mulCos_uid105_fpSinCosXTest_pr <= UNSIGNED(mulCos_uid105_fpSinCosXTest_a) * UNSIGNED(mulCos_uid105_fpSinCosXTest_b);
mulCos_uid105_fpSinCosXTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulCos_uid105_fpSinCosXTest_a <= (others => '0');
mulCos_uid105_fpSinCosXTest_b <= (others => '0');
mulCos_uid105_fpSinCosXTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulCos_uid105_fpSinCosXTest_a <= reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q;
mulCos_uid105_fpSinCosXTest_b <= reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q;
mulCos_uid105_fpSinCosXTest_s1 <= STD_LOGIC_VECTOR(mulCos_uid105_fpSinCosXTest_pr);
END IF;
END IF;
END PROCESS;
mulCos_uid105_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulCos_uid105_fpSinCosXTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulCos_uid105_fpSinCosXTest_q <= mulCos_uid105_fpSinCosXTest_s1;
END IF;
END IF;
END PROCESS;
--normBitCos_uid106_fpSinCosXTest(BITSELECT,105)@36
normBitCos_uid106_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q;
normBitCos_uid106_fpSinCosXTest_b <= normBitCos_uid106_fpSinCosXTest_in(51 downto 51);
--cosRndOp_uid112_uid113_fpSinCosXTest(BITJOIN,112)@36
cosRndOp_uid112_uid113_fpSinCosXTest_q <= normBitCos_uid106_fpSinCosXTest_b & cstAllZWF_uid7_fpSinCosXTest_q & VCC_q;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor(LOGICAL,1296)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q <= not (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a or ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b);
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top(CONSTANT,1292)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q <= "0110";
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp(LOGICAL,1293)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q <= "1" when ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a = ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b else "0";
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg(REG,1294)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena(REG,1297)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd(LOGICAL,1298)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b <= en;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a and ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b;
--reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1(REG,641)@25
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg(DELAY,1286)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q, xout => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt(COUNTER,1288)
-- every=1, low=0, high=6, step=1, init=1
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i = 5 THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i - 6;
ELSE
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i,3));
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg(REG,1289)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux(MUX,1290)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s <= en;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux: PROCESS (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s, ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q, ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem(DUALMEM,1287)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 7,
width_b => 7,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia
);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq(6 downto 0);
--expHardCase_uid78_fpSinCosXTest(SUB,77)@35
expHardCase_uid78_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expHardCase_uid78_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q);
expHardCase_uid78_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid78_fpSinCosXTest_a) - UNSIGNED(expHardCase_uid78_fpSinCosXTest_b));
expHardCase_uid78_fpSinCosXTest_q <= expHardCase_uid78_fpSinCosXTest_o(8 downto 0);
--expPCos_uid79_fpSinCosXTest(BITSELECT,78)@35
expPCos_uid79_fpSinCosXTest_in <= expHardCase_uid78_fpSinCosXTest_q(7 downto 0);
expPCos_uid79_fpSinCosXTest_b <= expPCos_uid79_fpSinCosXTest_in(7 downto 0);
--reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1(REG,642)@35
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q <= expPCos_uid79_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--fracRCosPreRndHigh_uid108_fpSinCosXTest(BITSELECT,107)@36
fracRCosPreRndHigh_uid108_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q(50 downto 0);
fracRCosPreRndHigh_uid108_fpSinCosXTest_b <= fracRCosPreRndHigh_uid108_fpSinCosXTest_in(50 downto 27);
--fracRCosPreRndLow_uid109_fpSinCosXTest(BITSELECT,108)@36
fracRCosPreRndLow_uid109_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q(49 downto 0);
fracRCosPreRndLow_uid109_fpSinCosXTest_b <= fracRCosPreRndLow_uid109_fpSinCosXTest_in(49 downto 26);
--fracRCosPreRnd_uid110_fpSinCosXTest(MUX,109)@36
fracRCosPreRnd_uid110_fpSinCosXTest_s <= normBitCos_uid106_fpSinCosXTest_b;
fracRCosPreRnd_uid110_fpSinCosXTest: PROCESS (fracRCosPreRnd_uid110_fpSinCosXTest_s, en, fracRCosPreRndLow_uid109_fpSinCosXTest_b, fracRCosPreRndHigh_uid108_fpSinCosXTest_b)
BEGIN
CASE fracRCosPreRnd_uid110_fpSinCosXTest_s IS
WHEN "0" => fracRCosPreRnd_uid110_fpSinCosXTest_q <= fracRCosPreRndLow_uid109_fpSinCosXTest_b;
WHEN "1" => fracRCosPreRnd_uid110_fpSinCosXTest_q <= fracRCosPreRndHigh_uid108_fpSinCosXTest_b;
WHEN OTHERS => fracRCosPreRnd_uid110_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracRCosPreRnd_uid111_uid111_fpSinCosXTest(BITJOIN,110)@36
expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q <= reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q & fracRCosPreRnd_uid110_fpSinCosXTest_q;
--expFracRCos_uid114_fpSinCosXTest(ADD,113)@36
expFracRCos_uid114_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q);
expFracRCos_uid114_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00000000" & cosRndOp_uid112_uid113_fpSinCosXTest_q);
expFracRCos_uid114_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRCos_uid114_fpSinCosXTest_a) + UNSIGNED(expFracRCos_uid114_fpSinCosXTest_b));
expFracRCos_uid114_fpSinCosXTest_q <= expFracRCos_uid114_fpSinCosXTest_o(32 downto 0);
--expRCompSin_uid116_fpSinCosXTest(BITSELECT,115)@36
expRCompSin_uid116_fpSinCosXTest_in <= expFracRCos_uid114_fpSinCosXTest_q(31 downto 0);
expRCompSin_uid116_fpSinCosXTest_b <= expRCompSin_uid116_fpSinCosXTest_in(31 downto 24);
--reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2(REG,646)@36
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q <= expRCompSin_uid116_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor(LOGICAL,1385)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q <= not (ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a or ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top(CONSTANT,1305)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q <= "01101";
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp(LOGICAL,1306)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q <= "1" when ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a = ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b else "0";
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg(REG,1307)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena(REG,1386)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q = "1") THEN
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd(LOGICAL,1387)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b <= en;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a and ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b;
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a(DELAY,745)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c(DELAY,783)@16
ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => cosXIsOneXRR_uid42_fpSinCosXTest_n, xout => ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--InvCosXIsOneXRR_uid136_fpSinCosXTest(LOGICAL,135)@16
InvCosXIsOneXRR_uid136_fpSinCosXTest_a <= cosXIsOneXRR_uid42_fpSinCosXTest_n;
InvCosXIsOneXRR_uid136_fpSinCosXTest_q <= not InvCosXIsOneXRR_uid136_fpSinCosXTest_a;
--ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c(DELAY,773)@16
ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => InvCosXIsOneXRR_uid136_fpSinCosXTest_q, xout => ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a(DELAY,755)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsX_uid127_fpSinCosXTest(LOGICAL,126)@18
InvSinXIsX_uid127_fpSinCosXTest_a <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q;
InvSinXIsX_uid127_fpSinCosXTest_q <= not InvSinXIsX_uid127_fpSinCosXTest_a;
--ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b(DELAY,772)@18
ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => InvSinXIsX_uid127_fpSinCosXTest_q, xout => ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--half_uid53_fpSinCosXTest(BITJOIN,52)@19
half_uid53_fpSinCosXTest_q <= VCC_q & cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
--yIsHalf_uid54_fpSinCosXTest(LOGICAL,53)@19
yIsHalf_uid54_fpSinCosXTest_a <= reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q;
yIsHalf_uid54_fpSinCosXTest_b <= half_uid53_fpSinCosXTest_q;
yIsHalf_uid54_fpSinCosXTest_q <= "1" when yIsHalf_uid54_fpSinCosXTest_a = yIsHalf_uid54_fpSinCosXTest_b else "0";
--yHalfCosXNotOne_uid138_fpSinCosXTest(LOGICAL,137)@19
yHalfCosXNotOne_uid138_fpSinCosXTest_a <= yIsHalf_uid54_fpSinCosXTest_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_b <= ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_c <= ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_q <= yHalfCosXNotOne_uid138_fpSinCosXTest_a and yHalfCosXNotOne_uid138_fpSinCosXTest_b and yHalfCosXNotOne_uid138_fpSinCosXTest_c;
--ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b(DELAY,744)@0
ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => exc_I_uid15_fpSinCosXTest_q, xout => ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a(DELAY,743)@0
ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => exc_N_uid17_fpSinCosXTest_q, xout => ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRNaN_uid117_fpSinCosXTest(LOGICAL,116)@19
excRNaN_uid117_fpSinCosXTest_a <= ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q;
excRNaN_uid117_fpSinCosXTest_b <= ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q;
excRNaN_uid117_fpSinCosXTest_q <= excRNaN_uid117_fpSinCosXTest_a or excRNaN_uid117_fpSinCosXTest_b;
--join_uid143_fpSinCosXTest(BITJOIN,142)@19
join_uid143_fpSinCosXTest_q <= ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q & yHalfCosXNotOne_uid138_fpSinCosXTest_q & excRNaN_uid117_fpSinCosXTest_q;
--expSelBitsCos_uid144_fpSinCosXTest(BITJOIN,143)@19
expSelBitsCos_uid144_fpSinCosXTest_q <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q & join_uid143_fpSinCosXTest_q;
--reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0(REG,645)@19
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q <= expSelBitsCos_uid144_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--expSelectorCos_uid145_fpSinCosXTest(LOOKUP,144)@20
expSelectorCos_uid145_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSelectorCos_uid145_fpSinCosXTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q) IS
WHEN "0000" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "0001" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "0010" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "0011" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "0100" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "0101" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "0110" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "0111" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "1000" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "1001" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "1010" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "1011" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "1100" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "1101" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "1110" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "1111" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN OTHERS =>
expSelectorCos_uid145_fpSinCosXTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg(DELAY,1375)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => expSelectorCos_uid145_fpSinCosXTest_q, xout => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt(COUNTER,1301)
-- every=1, low=0, high=13, step=1, init=1
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i = 12 THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i - 13;
ELSE
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg(REG,1302)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux(MUX,1303)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s, ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q, ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem(DUALMEM,1376)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia
);
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq(1 downto 0);
--expRPostExcCos_uid147_fpSinCosXTest(MUX,146)@37
expRPostExcCos_uid147_fpSinCosXTest_s <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q;
expRPostExcCos_uid147_fpSinCosXTest: PROCESS (expRPostExcCos_uid147_fpSinCosXTest_s, en, reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q, cstBias_uid22_fpSinCosXTest_q, cstAllZWE_uid8_fpSinCosXTest_q, cstAllOWE_uid6_fpSinCosXTest_q)
BEGIN
CASE expRPostExcCos_uid147_fpSinCosXTest_s IS
WHEN "00" => expRPostExcCos_uid147_fpSinCosXTest_q <= reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q;
WHEN "01" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstBias_uid22_fpSinCosXTest_q;
WHEN "10" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstAllZWE_uid8_fpSinCosXTest_q;
WHEN "11" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstAllOWE_uid6_fpSinCosXTest_q;
WHEN OTHERS => expRPostExcCos_uid147_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstNaNwF_uid32_fpSinCosXTest(CONSTANT,31)
cstNaNwF_uid32_fpSinCosXTest_q <= "00000000000000000000001";
--fracRCompCos_uid115_fpSinCosXTest(BITSELECT,114)@36
fracRCompCos_uid115_fpSinCosXTest_in <= expFracRCos_uid114_fpSinCosXTest_q(23 downto 0);
fracRCompCos_uid115_fpSinCosXTest_b <= fracRCompCos_uid115_fpSinCosXTest_in(23 downto 1);
--reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2(REG,644)@36
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q <= fracRCompCos_uid115_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor(LOGICAL,1372)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q <= not (ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a or ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b);
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena(REG,1373)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q = "1") THEN
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd(LOGICAL,1374)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b <= en;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a and ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b;
--reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1(REG,613)@19
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q <= excRNaN_uid117_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3(REG,612)@19
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q <= ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q;
END IF;
END IF;
END PROCESS;
--reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2(REG,611)@19
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q;
END IF;
END IF;
END PROCESS;
--reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1(REG,610)@19
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q <= yHalfCosXNotOne_uid138_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--rZOrOne_uid140_fpSinCosXTest(LOGICAL,139)@20
rZOrOne_uid140_fpSinCosXTest_a <= reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q;
rZOrOne_uid140_fpSinCosXTest_b <= reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q;
rZOrOne_uid140_fpSinCosXTest_c <= reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q;
rZOrOne_uid140_fpSinCosXTest_q <= rZOrOne_uid140_fpSinCosXTest_a or rZOrOne_uid140_fpSinCosXTest_b or rZOrOne_uid140_fpSinCosXTest_c;
--join_uid141_fpSinCosXTest(BITJOIN,140)@20
join_uid141_fpSinCosXTest_q <= reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q & rZOrOne_uid140_fpSinCosXTest_q;
--reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1(REG,643)@20
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q <= join_uid141_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg(DELAY,1362)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q, xout => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem(DUALMEM,1363)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia
);
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq(1 downto 0);
--fracRPostExcCos_uid142_fpSinCosXTest(MUX,141)@37
fracRPostExcCos_uid142_fpSinCosXTest_s <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q;
fracRPostExcCos_uid142_fpSinCosXTest: PROCESS (fracRPostExcCos_uid142_fpSinCosXTest_s, en, reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q, cstAllZWF_uid7_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q)
BEGIN
CASE fracRPostExcCos_uid142_fpSinCosXTest_s IS
WHEN "00" => fracRPostExcCos_uid142_fpSinCosXTest_q <= reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q;
WHEN "01" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstAllZWF_uid7_fpSinCosXTest_q;
WHEN "10" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN "11" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN OTHERS => fracRPostExcCos_uid142_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpCos_uid162_fpSinCosXTest(BITJOIN,161)@37
fpCos_uid162_fpSinCosXTest_q <= ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q & expRPostExcCos_uid147_fpSinCosXTest_q & fracRPostExcCos_uid142_fpSinCosXTest_q;
--cstBiasMwShiftM2_uid25_fpSinCosXTest(CONSTANT,24)
cstBiasMwShiftM2_uid25_fpSinCosXTest_q <= "01110001";
--sinXIsXRR_uid41_fpSinCosXTest(COMPARE,40)@16
sinXIsXRR_uid41_fpSinCosXTest_cin <= GND_q;
sinXIsXRR_uid41_fpSinCosXTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid25_fpSinCosXTest_q) & '0';
sinXIsXRR_uid41_fpSinCosXTest_b <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q) & sinXIsXRR_uid41_fpSinCosXTest_cin(0);
sinXIsXRR_uid41_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(sinXIsXRR_uid41_fpSinCosXTest_a) - SIGNED(sinXIsXRR_uid41_fpSinCosXTest_b));
sinXIsXRR_uid41_fpSinCosXTest_n(0) <= not sinXIsXRR_uid41_fpSinCosXTest_o(11);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a(DELAY,756)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsXRR_uid128_fpSinCosXTest(LOGICAL,127)@18
InvSinXIsXRR_uid128_fpSinCosXTest_a <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q;
InvSinXIsXRR_uid128_fpSinCosXTest_q <= not InvSinXIsXRR_uid128_fpSinCosXTest_a;
--signComp_uid129_fpSinCosXTest(LOGICAL,128)@18
signComp_uid129_fpSinCosXTest_a <= InvSinXIsXRR_uid128_fpSinCosXTest_q;
signComp_uid129_fpSinCosXTest_b <= InvSinXIsX_uid127_fpSinCosXTest_q;
signComp_uid129_fpSinCosXTest_c <= intXParity_uid49_fpSinCosXTest_b;
signComp_uid129_fpSinCosXTest_q <= signComp_uid129_fpSinCosXTest_a and signComp_uid129_fpSinCosXTest_b and signComp_uid129_fpSinCosXTest_c;
--signX_uid37_fpSinCosXTest(BITSELECT,36)@0
signX_uid37_fpSinCosXTest_in <= a;
signX_uid37_fpSinCosXTest_b <= signX_uid37_fpSinCosXTest_in(31 downto 31);
--ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a(DELAY,760)@0
ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => signX_uid37_fpSinCosXTest_b, xout => ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid130_fpSinCosXTest(LOGICAL,129)@18
signR_uid130_fpSinCosXTest_a <= ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q;
signR_uid130_fpSinCosXTest_b <= signComp_uid129_fpSinCosXTest_q;
signR_uid130_fpSinCosXTest_q <= signR_uid130_fpSinCosXTest_a xor signR_uid130_fpSinCosXTest_b;
--ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c(DELAY,766)@18
ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => signR_uid130_fpSinCosXTest_q, xout => ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--signRSinFull_uid133_fpSinCosXTest(LOGICAL,132)@20
signRSinFull_uid133_fpSinCosXTest_a <= InvExc_N_uid132_fpSinCosXTest_q;
signRSinFull_uid133_fpSinCosXTest_b <= InvExc_I_uid131_fpSinCosXTest_q;
signRSinFull_uid133_fpSinCosXTest_c <= ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q;
signRSinFull_uid133_fpSinCosXTest_q_i <= signRSinFull_uid133_fpSinCosXTest_a and signRSinFull_uid133_fpSinCosXTest_b and signRSinFull_uid133_fpSinCosXTest_c;
signRSinFull_uid133_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRSinFull_uid133_fpSinCosXTest_q, xin => signRSinFull_uid133_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c(DELAY,769)@21
ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signRSinFull_uid133_fpSinCosXTest_q, xout => ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor(LOGICAL,1359)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q <= not (ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a or ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b);
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top(CONSTANT,1342)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q <= "0100010";
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp(LOGICAL,1343)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q <= "1" when ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a = ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b else "0";
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg(REG,1344)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena(REG,1360)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q = "1") THEN
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd(LOGICAL,1361)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b <= en;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a and ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg(DELAY,1349)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => exp_uid9_fpSinCosXTest_b, xout => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt(COUNTER,1338)
-- every=1, low=0, high=34, step=1, init=1
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i = 33 THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i - 34;
ELSE
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i,6));
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg(REG,1339)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux(MUX,1340)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem(DUALMEM,1350)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 6,
numwords_a => 35,
width_b => 8,
widthad_b => 6,
numwords_b => 35,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia
);
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a(DELAY,1228)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1(REG,605)@35
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor(LOGICAL,1309)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q <= not (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a or ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena(REG,1310)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd(LOGICAL,1311)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b <= en;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a and ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b;
--oFracXRRSmallXRR_uid90_fpSinCosXTest(BITSELECT,89)@16
oFracXRRSmallXRR_uid90_fpSinCosXTest_in <= oFracXRR_uid43_uid43_fpSinCosXTest_q;
oFracXRRSmallXRR_uid90_fpSinCosXTest_b <= oFracXRRSmallXRR_uid90_fpSinCosXTest_in(53 downto 28);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg(DELAY,1299)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => oFracXRRSmallXRR_uid90_fpSinCosXTest_b, xout => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem(DUALMEM,1300)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 4,
numwords_a => 14,
width_b => 26,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia
);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq(25 downto 0);
--reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1(REG,577)@20
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
END IF;
END IF;
END PROCESS;
--zSin_uid60_fpSinCosXTest(MUX,59)@21
zSin_uid60_fpSinCosXTest_s <= reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q;
zSin_uid60_fpSinCosXTest: PROCESS (zSin_uid60_fpSinCosXTest_s, en, reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q, reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q)
BEGIN
CASE zSin_uid60_fpSinCosXTest_s IS
WHEN "0" => zSin_uid60_fpSinCosXTest_q <= reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q;
WHEN "1" => zSin_uid60_fpSinCosXTest_q <= reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q;
WHEN OTHERS => zSin_uid60_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--addr_uid81_fpSinCosXTest(BITSELECT,80)@21
addr_uid81_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q;
addr_uid81_fpSinCosXTest_b <= addr_uid81_fpSinCosXTest_in(64 downto 57);
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0(REG,595)@21
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q <= addr_uid81_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid398_tableGensinPiZ_lutmem(DUALMEM,529)@22
memoryC2_uid398_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC2_uid398_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC2_uid398_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q;
memoryC2_uid398_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC2_uid398_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid398_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid398_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid398_tableGensinPiZ_lutmem_iq,
address_a => memoryC2_uid398_tableGensinPiZ_lutmem_aa,
data_a => memoryC2_uid398_tableGensinPiZ_lutmem_ia
);
memoryC2_uid398_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC2_uid398_tableGensinPiZ_lutmem_q <= memoryC2_uid398_tableGensinPiZ_lutmem_iq(12 downto 0);
--reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1(REG,597)@24
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q <= memoryC2_uid398_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPsinPiZ_uid84_fpSinCosXTest(BITSELECT,83)@21
zPsinPiZ_uid84_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(56 downto 0);
zPsinPiZ_uid84_fpSinCosXTest_b <= zPsinPiZ_uid84_fpSinCosXTest_in(56 downto 42);
--yT1_uid406_polyEvalsinPiZ(BITSELECT,405)@21
yT1_uid406_polyEvalsinPiZ_in <= zPsinPiZ_uid84_fpSinCosXTest_b;
yT1_uid406_polyEvalsinPiZ_b <= yT1_uid406_polyEvalsinPiZ_in(14 downto 2);
--ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg(DELAY,1540)
ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => yT1_uid406_polyEvalsinPiZ_b, xout => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a(DELAY,1219)@21
ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q, xout => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0(REG,596)@24
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q <= ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid502_pT1_uid407_polyEvalsinPiZ(MULT,501)@25
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a),14)) * SIGNED(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b);
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a <= (others => '0');
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b <= (others => '0');
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a <= reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b <= reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q <= prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ(BITSELECT,502)@28
prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in <= prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q;
prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in(25 downto 12);
--highBBits_uid409_polyEvalsinPiZ(BITSELECT,408)@28
highBBits_uid409_polyEvalsinPiZ_in <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b;
highBBits_uid409_polyEvalsinPiZ_b <= highBBits_uid409_polyEvalsinPiZ_in(13 downto 1);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a(DELAY,1221)@21
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => addr_uid81_fpSinCosXTest_b, xout => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0(REG,598)@24
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid396_tableGensinPiZ_lutmem(DUALMEM,528)@25
memoryC1_uid396_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC1_uid396_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC1_uid396_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q;
memoryC1_uid396_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC1_uid396_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid396_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid396_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid396_tableGensinPiZ_lutmem_iq,
address_a => memoryC1_uid396_tableGensinPiZ_lutmem_aa,
data_a => memoryC1_uid396_tableGensinPiZ_lutmem_ia
);
memoryC1_uid396_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC1_uid396_tableGensinPiZ_lutmem_q <= memoryC1_uid396_tableGensinPiZ_lutmem_iq(20 downto 0);
--reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0(REG,599)@27
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q <= memoryC1_uid396_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid410_polyEvalsinPiZ(ADD,409)@28
sumAHighB_uid410_polyEvalsinPiZ_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q(20)) & reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q);
sumAHighB_uid410_polyEvalsinPiZ_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid409_polyEvalsinPiZ_b(12)) & highBBits_uid409_polyEvalsinPiZ_b);
sumAHighB_uid410_polyEvalsinPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid410_polyEvalsinPiZ_a) + SIGNED(sumAHighB_uid410_polyEvalsinPiZ_b));
sumAHighB_uid410_polyEvalsinPiZ_q <= sumAHighB_uid410_polyEvalsinPiZ_o(21 downto 0);
--lowRangeB_uid408_polyEvalsinPiZ(BITSELECT,407)@28
lowRangeB_uid408_polyEvalsinPiZ_in <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b(0 downto 0);
lowRangeB_uid408_polyEvalsinPiZ_b <= lowRangeB_uid408_polyEvalsinPiZ_in(0 downto 0);
--s1_uid408_uid411_polyEvalsinPiZ(BITJOIN,410)@28
s1_uid408_uid411_polyEvalsinPiZ_q <= sumAHighB_uid410_polyEvalsinPiZ_q & lowRangeB_uid408_polyEvalsinPiZ_b;
--reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1(REG,601)@28
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q <= s1_uid408_uid411_polyEvalsinPiZ_q;
END IF;
END IF;
END PROCESS;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor(LOGICAL,1551)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q <= not (ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a or ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b);
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena(REG,1552)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q = "1") THEN
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd(LOGICAL,1553)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b <= en;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a and ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg(DELAY,1541)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => zPsinPiZ_uid84_fpSinCosXTest_b, xout => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem(DUALMEM,1542)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq,
address_a => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa,
data_a => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia
);
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0 <= areset;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq(14 downto 0);
--reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0(REG,600)@28
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid505_pT2_uid413_polyEvalsinPiZ(MULT,504)@29
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a),16)) * SIGNED(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b);
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a <= (others => '0');
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b <= (others => '0');
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a <= reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b <= reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q <= prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ(BITSELECT,505)@32
prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in <= prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q;
prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in(37 downto 14);
--highBBits_uid415_polyEvalsinPiZ(BITSELECT,414)@32
highBBits_uid415_polyEvalsinPiZ_in <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b;
highBBits_uid415_polyEvalsinPiZ_b <= highBBits_uid415_polyEvalsinPiZ_in(23 downto 2);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor(LOGICAL,1564)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q <= not (ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a or ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena(REG,1565)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q = "1") THEN
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd(LOGICAL,1566)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b <= en;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a and ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b;
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg(DELAY,1554)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addr_uid81_fpSinCosXTest_b, xout => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem(DUALMEM,1555)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq,
address_a => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa,
data_a => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia
);
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0(REG,602)@28
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid394_tableGensinPiZ_lutmem(DUALMEM,527)@29
memoryC0_uid394_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC0_uid394_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC0_uid394_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q;
memoryC0_uid394_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC0_uid394_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid394_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid394_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid394_tableGensinPiZ_lutmem_iq,
address_a => memoryC0_uid394_tableGensinPiZ_lutmem_aa,
data_a => memoryC0_uid394_tableGensinPiZ_lutmem_ia
);
memoryC0_uid394_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC0_uid394_tableGensinPiZ_lutmem_q <= memoryC0_uid394_tableGensinPiZ_lutmem_iq(29 downto 0);
--reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0(REG,603)@31
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q <= memoryC0_uid394_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid416_polyEvalsinPiZ(ADD,415)@32
sumAHighB_uid416_polyEvalsinPiZ_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q(29)) & reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q);
sumAHighB_uid416_polyEvalsinPiZ_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid415_polyEvalsinPiZ_b(21)) & highBBits_uid415_polyEvalsinPiZ_b);
sumAHighB_uid416_polyEvalsinPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid416_polyEvalsinPiZ_a) + SIGNED(sumAHighB_uid416_polyEvalsinPiZ_b));
sumAHighB_uid416_polyEvalsinPiZ_q <= sumAHighB_uid416_polyEvalsinPiZ_o(30 downto 0);
--lowRangeB_uid414_polyEvalsinPiZ(BITSELECT,413)@32
lowRangeB_uid414_polyEvalsinPiZ_in <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b(1 downto 0);
lowRangeB_uid414_polyEvalsinPiZ_b <= lowRangeB_uid414_polyEvalsinPiZ_in(1 downto 0);
--s2_uid414_uid417_polyEvalsinPiZ(BITJOIN,416)@32
s2_uid414_uid417_polyEvalsinPiZ_q <= sumAHighB_uid416_polyEvalsinPiZ_q & lowRangeB_uid414_polyEvalsinPiZ_b;
--polyEvalSigsinPiZ_uid86_fpSinCosXTest(BITSELECT,85)@32
polyEvalSigsinPiZ_uid86_fpSinCosXTest_in <= s2_uid414_uid417_polyEvalsinPiZ_q(30 downto 0);
polyEvalSigsinPiZ_uid86_fpSinCosXTest_b <= polyEvalSigsinPiZ_uid86_fpSinCosXTest_in(30 downto 5);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b(DELAY,708)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--multSinOp2_uid91_fpSinCosXTest(MUX,90)@32
multSinOp2_uid91_fpSinCosXTest_s <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q;
multSinOp2_uid91_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSinOp2_uid91_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE multSinOp2_uid91_fpSinCosXTest_s IS
WHEN "0" => multSinOp2_uid91_fpSinCosXTest_q <= polyEvalSigsinPiZ_uid86_fpSinCosXTest_b;
WHEN "1" => multSinOp2_uid91_fpSinCosXTest_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => multSinOp2_uid91_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor(LOGICAL,1320)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q <= not (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a or ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b);
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena(REG,1321)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd(LOGICAL,1322)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b <= en;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a and ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b;
--cPi_uid71_fpSinCosXTest(CONSTANT,70)
cPi_uid71_fpSinCosXTest_q <= "11001001000011111101101011";
--LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest(BITSELECT,309)@27
LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q(63 downto 0);
LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in(63 downto 0);
--leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest(BITJOIN,310)@27
leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b & GND_q;
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor(LOGICAL,1433)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q <= not (ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a or ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b);
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena(REG,1434)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q = "1") THEN
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd(LOGICAL,1435)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b <= en;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a and ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b;
--X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest(BITSELECT,280)@21
X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(32 downto 0);
X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b <= X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in(32 downto 0);
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg(DELAY,1425)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem(DUALMEM,1426)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 33,
widthad_a => 1,
numwords_a => 2,
width_b => 33,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia
);
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq(32 downto 0);
--leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest(BITJOIN,281)@25
leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor(LOGICAL,1444)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q <= not (ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a or ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b);
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena(REG,1445)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q = "1") THEN
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd(LOGICAL,1446)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b <= en;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a and ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg(DELAY,1436)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => zSin_uid60_fpSinCosXTest_q, xout => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem(DUALMEM,1437)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 65,
widthad_a => 1,
numwords_a => 2,
width_b => 65,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia
);
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq(64 downto 0);
--rVStage_uid237_lzcZSin_uid66_fpSinCosXTest(BITSELECT,236)@21
rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q;
rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in(64 downto 1);
--vCount_uid238_lzcZSin_uid66_fpSinCosXTest(LOGICAL,237)@21
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid236_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g(DELAY,903)@22
ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid240_lzcZSin_uid66_fpSinCosXTest(BITSELECT,239)@21
vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(0 downto 0);
vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in(0 downto 0);
--ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b(DELAY,861)@21
ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cStage_uid241_lzcZSin_uid66_fpSinCosXTest(BITJOIN,240)@22
cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q <= ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q & mO_uid239_lzcZSin_uid66_fpSinCosXTest_q;
--ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c(DELAY,863)@21
ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid243_lzcZSin_uid66_fpSinCosXTest(MUX,242)@22
vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid243_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s, en, ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q, cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid245_lzcZSin_uid66_fpSinCosXTest(BITSELECT,244)@22
rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in(63 downto 32);
--vCount_uid246_lzcZSin_uid66_fpSinCosXTest(LOGICAL,245)@22
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f(DELAY,902)@23
ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid247_lzcZSin_uid66_fpSinCosXTest(BITSELECT,246)@22
vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q(31 downto 0);
vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in(31 downto 0);
--ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d(DELAY,870)@22
ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c(DELAY,869)@22
ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid249_lzcZSin_uid66_fpSinCosXTest(MUX,248)@23
vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid249_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s, en, ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q, ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q)
BEGIN
CASE vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q;
WHEN OTHERS => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid251_lzcZSin_uid66_fpSinCosXTest(BITSELECT,250)@23
rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in(31 downto 16);
--vCount_uid252_lzcZSin_uid66_fpSinCosXTest(LOGICAL,251)@23
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b else "0";
--reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4(REG,585)@23
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q <= vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e(DELAY,901)@24
ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid253_lzcZSin_uid66_fpSinCosXTest(BITSELECT,252)@23
vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q(15 downto 0);
vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in(15 downto 0);
--vStagei_uid255_lzcZSin_uid66_fpSinCosXTest(MUX,254)@23
vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid255_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s, en, rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b, vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b;
WHEN "1" => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid257_lzcZSin_uid66_fpSinCosXTest(BITSELECT,256)@23
rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in(15 downto 8);
--reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1(REG,580)@23
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q <= rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid258_lzcZSin_uid66_fpSinCosXTest(LOGICAL,257)@24
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a <= reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q;
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b else "0";
--ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d(DELAY,900)@24
ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid259_lzcZSin_uid66_fpSinCosXTest(BITSELECT,258)@23
vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q(7 downto 0);
vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3(REG,582)@23
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q <= vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid261_lzcZSin_uid66_fpSinCosXTest(MUX,260)@24
vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid261_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s, en, reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q, reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid263_lzcZSin_uid66_fpSinCosXTest(BITSELECT,262)@24
rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in(7 downto 4);
--vCount_uid264_lzcZSin_uid66_fpSinCosXTest(LOGICAL,263)@24
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid265_lzcZSin_uid66_fpSinCosXTest(BITSELECT,264)@24
vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q(3 downto 0);
vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in(3 downto 0);
--reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3(REG,584)@24
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q <= vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2(REG,583)@24
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid267_lzcZSin_uid66_fpSinCosXTest(MUX,266)@25
vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid267_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s, en, reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q, reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid269_lzcZSin_uid66_fpSinCosXTest(BITSELECT,268)@25
rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in(3 downto 2);
--vCount_uid270_lzcZSin_uid66_fpSinCosXTest(LOGICAL,269)@25
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b else "0";
--vStage_uid271_lzcZSin_uid66_fpSinCosXTest(BITSELECT,270)@25
vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q(1 downto 0);
vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in(1 downto 0);
--vStagei_uid273_lzcZSin_uid66_fpSinCosXTest(MUX,272)@25
vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid273_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s, en, rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b, vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b;
WHEN "1" => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid275_lzcZSin_uid66_fpSinCosXTest(BITSELECT,274)@25
rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in(1 downto 1);
--vCount_uid276_lzcZSin_uid66_fpSinCosXTest(LOGICAL,275)@25
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b <= GND_q;
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b else "0";
--r_uid277_lzcZSin_uid66_fpSinCosXTest(BITJOIN,276)@25
r_uid277_lzcZSin_uid66_fpSinCosXTest_q <= ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q & ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q & ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q & ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q & vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q & vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q & vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q;
--leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest(BITSELECT,284)@25
leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q;
leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in(6 downto 5);
--leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest(MUX,285)@25
leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s <= leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b;
leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s, en, ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest(BITSELECT,293)@25
LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(40 downto 0);
LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in(40 downto 0);
--leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest(BITJOIN,294)@25
leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b & leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5(REG,590)@25
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest(BITSELECT,290)@25
LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(48 downto 0);
LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in(48 downto 0);
--leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest(BITJOIN,291)@25
leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4(REG,589)@25
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest(BITSELECT,287)@25
LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(56 downto 0);
LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in(56 downto 0);
--leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest(BITJOIN,288)@25
leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3(REG,588)@25
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2(REG,587)@25
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest(BITSELECT,295)@25
leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1(REG,586)@25
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q <= leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest(MUX,296)@26
leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s <= reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q;
leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s, en, reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest(BITSELECT,304)@26
LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(58 downto 0);
LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b(DELAY,927)@26
ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest(BITJOIN,305)@27
leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q;
--LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest(BITSELECT,301)@26
LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(60 downto 0);
LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b(DELAY,925)@26
ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest(BITJOIN,302)@27
leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest(BITSELECT,298)@26
LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(62 downto 0);
LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in(62 downto 0);
--ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b(DELAY,923)@26
ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest(BITJOIN,299)@27
leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2(REG,592)@26
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest(BITSELECT,306)@25
leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in(2 downto 1);
--ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a(DELAY,1214)@25
ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1(REG,591)@26
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q <= ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest(MUX,307)@27
leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s <= reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q;
leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s, en, reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest(BITSELECT,311)@25
leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b(DELAY,937)@25
ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest(MUX,312)@27
leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s <= ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q;
leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s, en, leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "0" => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "1" => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--pHigh_uid72_fpSinCosXTest(BITSELECT,71)@27
pHigh_uid72_fpSinCosXTest_in <= leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q;
pHigh_uid72_fpSinCosXTest_b <= pHigh_uid72_fpSinCosXTest_in(64 downto 39);
--reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2(REG,594)@27
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q <= pHigh_uid72_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a(DELAY,1216)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1(REG,593)@27
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--p_uid73_fpSinCosXTest(MUX,72)@28
p_uid73_fpSinCosXTest_s <= reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q;
p_uid73_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p_uid73_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE p_uid73_fpSinCosXTest_s IS
WHEN "0" => p_uid73_fpSinCosXTest_q <= reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q;
WHEN "1" => p_uid73_fpSinCosXTest_q <= cPi_uid71_fpSinCosXTest_q;
WHEN OTHERS => p_uid73_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg(DELAY,1312)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => p_uid73_fpSinCosXTest_q, xout => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem(DUALMEM,1313)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 1,
numwords_a => 2,
width_b => 26,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq,
address_a => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa,
data_a => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia
);
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0 <= areset;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq(25 downto 0);
--mulSin_uid92_fpSinCosXTest(MULT,91)@33
mulSin_uid92_fpSinCosXTest_pr <= UNSIGNED(mulSin_uid92_fpSinCosXTest_a) * UNSIGNED(mulSin_uid92_fpSinCosXTest_b);
mulSin_uid92_fpSinCosXTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulSin_uid92_fpSinCosXTest_a <= (others => '0');
mulSin_uid92_fpSinCosXTest_b <= (others => '0');
mulSin_uid92_fpSinCosXTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulSin_uid92_fpSinCosXTest_a <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q;
mulSin_uid92_fpSinCosXTest_b <= multSinOp2_uid91_fpSinCosXTest_q;
mulSin_uid92_fpSinCosXTest_s1 <= STD_LOGIC_VECTOR(mulSin_uid92_fpSinCosXTest_pr);
END IF;
END IF;
END PROCESS;
mulSin_uid92_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulSin_uid92_fpSinCosXTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulSin_uid92_fpSinCosXTest_q <= mulSin_uid92_fpSinCosXTest_s1;
END IF;
END IF;
END PROCESS;
--normBitSin_uid93_fpSinCosXTest(BITSELECT,92)@36
normBitSin_uid93_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q;
normBitSin_uid93_fpSinCosXTest_b <= normBitSin_uid93_fpSinCosXTest_in(51 downto 51);
--join_uid99_fpSinCosXTest(BITJOIN,98)@36
join_uid99_fpSinCosXTest_q <= reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q & normBitSin_uid93_fpSinCosXTest_b;
--sinRndOp_uid100_uid101_fpSinCosXTest(BITJOIN,100)@36
sinRndOp_uid100_uid101_fpSinCosXTest_q <= join_uid99_fpSinCosXTest_q & cstAllZWF_uid7_fpSinCosXTest_q & VCC_q;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor(LOGICAL,1333)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q <= not (ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a or ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b);
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena(REG,1334)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q = "1") THEN
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd(LOGICAL,1335)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b <= en;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a and ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor(LOGICAL,1283)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q <= not (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a or ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b);
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena(REG,1284)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd(LOGICAL,1285)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a and ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg(DELAY,1273)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expXRR_uid38_fpSinCosXTest_b, xout => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem(DUALMEM,1274)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 9,
width_b => 8,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia
);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1(REG,604)@25
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--expSinHC_uid74_fpSinCosXTest(SUB,73)@26
expSinHC_uid74_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expSinHC_uid74_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q);
expSinHC_uid74_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSinHC_uid74_fpSinCosXTest_a) - UNSIGNED(expSinHC_uid74_fpSinCosXTest_b));
expSinHC_uid74_fpSinCosXTest_q <= expSinHC_uid74_fpSinCosXTest_o(8 downto 0);
--expSinHCR_uid75_fpSinCosXTest(BITSELECT,74)@26
expSinHCR_uid75_fpSinCosXTest_in <= expSinHC_uid74_fpSinCosXTest_q(7 downto 0);
expSinHCR_uid75_fpSinCosXTest_b <= expSinHCR_uid75_fpSinCosXTest_in(7 downto 0);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b(DELAY,695)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expPSin_uid76_fpSinCosXTest(MUX,75)@26
expPSin_uid76_fpSinCosXTest_s <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q;
expPSin_uid76_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expPSin_uid76_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expPSin_uid76_fpSinCosXTest_s IS
WHEN "0" => expPSin_uid76_fpSinCosXTest_q <= expSinHCR_uid75_fpSinCosXTest_b;
WHEN "1" => expPSin_uid76_fpSinCosXTest_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => expPSin_uid76_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg(DELAY,1323)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expPSin_uid76_fpSinCosXTest_q, xout => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem(DUALMEM,1324)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 7,
width_b => 8,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia
);
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq(7 downto 0);
--fracRSinPreRndHigh_uid95_fpSinCosXTest(BITSELECT,94)@36
fracRSinPreRndHigh_uid95_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q(50 downto 0);
fracRSinPreRndHigh_uid95_fpSinCosXTest_b <= fracRSinPreRndHigh_uid95_fpSinCosXTest_in(50 downto 27);
--fracRSinPreRndLow_uid96_fpSinCosXTest(BITSELECT,95)@36
fracRSinPreRndLow_uid96_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q(49 downto 0);
fracRSinPreRndLow_uid96_fpSinCosXTest_b <= fracRSinPreRndLow_uid96_fpSinCosXTest_in(49 downto 26);
--fracRSinPreRnd_uid97_fpSinCosXTest(MUX,96)@36
fracRSinPreRnd_uid97_fpSinCosXTest_s <= normBitSin_uid93_fpSinCosXTest_b;
fracRSinPreRnd_uid97_fpSinCosXTest: PROCESS (fracRSinPreRnd_uid97_fpSinCosXTest_s, en, fracRSinPreRndLow_uid96_fpSinCosXTest_b, fracRSinPreRndHigh_uid95_fpSinCosXTest_b)
BEGIN
CASE fracRSinPreRnd_uid97_fpSinCosXTest_s IS
WHEN "0" => fracRSinPreRnd_uid97_fpSinCosXTest_q <= fracRSinPreRndLow_uid96_fpSinCosXTest_b;
WHEN "1" => fracRSinPreRnd_uid97_fpSinCosXTest_q <= fracRSinPreRndHigh_uid95_fpSinCosXTest_b;
WHEN OTHERS => fracRSinPreRnd_uid97_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracRSinPreRnd_uid98_uid98_fpSinCosXTest(BITJOIN,97)@36
expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q & fracRSinPreRnd_uid97_fpSinCosXTest_q;
--expFracRSin_uid102_fpSinCosXTest(ADD,101)@36
expFracRSin_uid102_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q);
expFracRSin_uid102_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0000000" & sinRndOp_uid100_uid101_fpSinCosXTest_q);
expFracRSin_uid102_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRSin_uid102_fpSinCosXTest_a) + UNSIGNED(expFracRSin_uid102_fpSinCosXTest_b));
expFracRSin_uid102_fpSinCosXTest_q <= expFracRSin_uid102_fpSinCosXTest_o(32 downto 0);
--expRCompSin_uid104_fpSinCosXTest(BITSELECT,103)@36
expRCompSin_uid104_fpSinCosXTest_in <= expFracRSin_uid102_fpSinCosXTest_q(31 downto 0);
expRCompSin_uid104_fpSinCosXTest_b <= expRCompSin_uid104_fpSinCosXTest_in(31 downto 24);
--reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2(REG,607)@36
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q <= expRCompSin_uid104_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor(LOGICAL,1537)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q <= not (ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a or ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b);
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena(REG,1538)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q = "1") THEN
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd(LOGICAL,1539)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b <= en;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a and ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b;
--expXIsZero_uid10_fpSinCosXTest(LOGICAL,9)@0
expXIsZero_uid10_fpSinCosXTest_a <= exp_uid9_fpSinCosXTest_b;
expXIsZero_uid10_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
expXIsZero_uid10_fpSinCosXTest_q <= "1" when expXIsZero_uid10_fpSinCosXTest_a = expXIsZero_uid10_fpSinCosXTest_b else "0";
--ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b(DELAY,746)@0
ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => expXIsZero_uid10_fpSinCosXTest_q, xout => ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excSelBitsSin_uid118_fpSinCosXTest(BITJOIN,117)@19
excSelBitsSin_uid118_fpSinCosXTest_q <= excRNaN_uid117_fpSinCosXTest_q & ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q & ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg(DELAY,1527)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => excSelBitsSin_uid118_fpSinCosXTest_q, xout => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem(DUALMEM,1528)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 4,
numwords_a => 14,
width_b => 3,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq,
address_a => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa,
data_a => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia
);
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0 <= areset;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq(2 downto 0);
--reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0(REG,533)@35
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--excSelSin_uid119_fpSinCosXTest(LOOKUP,118)@36
excSelSin_uid119_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excSelSin_uid119_fpSinCosXTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q) IS
WHEN "000" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN "001" => excSelSin_uid119_fpSinCosXTest_q <= "01";
WHEN "010" => excSelSin_uid119_fpSinCosXTest_q <= "10";
WHEN "011" => excSelSin_uid119_fpSinCosXTest_q <= "10";
WHEN "100" => excSelSin_uid119_fpSinCosXTest_q <= "11";
WHEN "101" => excSelSin_uid119_fpSinCosXTest_q <= "11";
WHEN "110" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN "111" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN OTHERS =>
excSelSin_uid119_fpSinCosXTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRPostExcSin_uid126_fpSinCosXTest(MUX,125)@37
expRPostExcSin_uid126_fpSinCosXTest_s <= excSelSin_uid119_fpSinCosXTest_q;
expRPostExcSin_uid126_fpSinCosXTest: PROCESS (expRPostExcSin_uid126_fpSinCosXTest_s, en, reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q, ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q, cstAllZWE_uid8_fpSinCosXTest_q, cstAllOWE_uid6_fpSinCosXTest_q)
BEGIN
CASE expRPostExcSin_uid126_fpSinCosXTest_s IS
WHEN "00" => expRPostExcSin_uid126_fpSinCosXTest_q <= reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q;
WHEN "01" => expRPostExcSin_uid126_fpSinCosXTest_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q;
WHEN "10" => expRPostExcSin_uid126_fpSinCosXTest_q <= cstAllZWE_uid8_fpSinCosXTest_q;
WHEN "11" => expRPostExcSin_uid126_fpSinCosXTest_q <= cstAllOWE_uid6_fpSinCosXTest_q;
WHEN OTHERS => expRPostExcSin_uid126_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor(LOGICAL,1346)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q <= not (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a or ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b);
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena(REG,1347)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd(LOGICAL,1348)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b <= en;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a and ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg(DELAY,1336)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => frac_uid13_fpSinCosXTest_b, xout => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem(DUALMEM,1337)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 6,
numwords_a => 35,
width_b => 23,
widthad_b => 6,
numwords_b => 35,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia
);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq(22 downto 0);
--fracRCompSin_uid103_fpSinCosXTest(BITSELECT,102)@36
fracRCompSin_uid103_fpSinCosXTest_in <= expFracRSin_uid102_fpSinCosXTest_q(23 downto 0);
fracRCompSin_uid103_fpSinCosXTest_b <= fracRCompSin_uid103_fpSinCosXTest_in(23 downto 1);
--reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2(REG,606)@36
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q <= fracRCompSin_uid103_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--fracRPostExcSin_uid122_fpSinCosXTest(MUX,121)@37
fracRPostExcSin_uid122_fpSinCosXTest_s <= excSelSin_uid119_fpSinCosXTest_q;
fracRPostExcSin_uid122_fpSinCosXTest: PROCESS (fracRPostExcSin_uid122_fpSinCosXTest_s, en, reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q, cstAllZWF_uid7_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q)
BEGIN
CASE fracRPostExcSin_uid122_fpSinCosXTest_s IS
WHEN "00" => fracRPostExcSin_uid122_fpSinCosXTest_q <= reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q;
WHEN "01" => fracRPostExcSin_uid122_fpSinCosXTest_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q;
WHEN "10" => fracRPostExcSin_uid122_fpSinCosXTest_q <= cstAllZWF_uid7_fpSinCosXTest_q;
WHEN "11" => fracRPostExcSin_uid122_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN OTHERS => fracRPostExcSin_uid122_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpSin_uid134_fpSinCosXTest(BITJOIN,133)@37
fpSin_uid134_fpSinCosXTest_q <= ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q & expRPostExcSin_uid126_fpSinCosXTest_q & fracRPostExcSin_uid122_fpSinCosXTest_q;
--xOut(GPOUT,4)@37
s <= fpSin_uid134_fpSinCosXTest_q;
c <= fpCos_uid162_fpSinCosXTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_sincos_s5
-- VHDL created on Wed Mar 27 09:55:14 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_sincos_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
s : out std_logic_vector(31 downto 0);
c : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_sincos_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid8_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid22_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid23_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShift_uid24_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid25_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid26_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstZwShiftP1_uid27_fpSinCosXTest_q : std_logic_vector (13 downto 0);
signal cstNaNwF_uid32_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal cstZmwFRRPwSM1_uid52_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal cPi_uid71_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal p_uid73_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal p_uid73_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal expPSin_uid76_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal expPSin_uid76_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal multSinOp2_uid91_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal multSinOp2_uid91_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_a : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_s1 : std_logic_vector (51 downto 0);
signal mulSin_uid92_fpSinCosXTest_pr : UNSIGNED (51 downto 0);
signal mulSin_uid92_fpSinCosXTest_q : std_logic_vector (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_a : std_logic_vector (25 downto 0);
signal mulCos_uid105_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal mulCos_uid105_fpSinCosXTest_s1 : std_logic_vector (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_pr : UNSIGNED (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_q : std_logic_vector (51 downto 0);
signal excSelSin_uid119_fpSinCosXTest_q : std_logic_vector(1 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expSelectorCos_uid145_fpSinCosXTest_q : std_logic_vector(1 downto 0);
signal signRCond2_uid152_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_d : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_d : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q : std_logic_vector (29 downto 0);
signal leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal zs_uid236_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal mO_uid239_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (62 downto 0);
signal zs_uid244_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal zs_uid250_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (5 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(63 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(63 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (47 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a : std_logic_vector (12 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr : SIGNED (26 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q : std_logic_vector (25 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a : std_logic_vector (14 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b : std_logic_vector (22 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr : SIGNED (38 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q : std_logic_vector (37 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a : std_logic_vector (12 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr : SIGNED (26 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q : std_logic_vector (25 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a : std_logic_vector (14 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b : std_logic_vector (22 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr : SIGNED (38 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q : std_logic_vector (37 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0 : std_logic;
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0 : std_logic;
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q : std_logic_vector (39 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a : std_logic_vector(81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b : std_logic_vector(81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o : std_logic_vector (81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q : std_logic_vector (81 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC0_uid394_tableGensinPiZ_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC1_uid396_tableGensinPiZ_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC2_uid398_tableGensinPiZ_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_q : std_logic_vector (12 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC0_uid400_tableGencosPiZ_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC1_uid402_tableGencosPiZ_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC2_uid404_tableGencosPiZ_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_q : std_logic_vector (12 downto 0);
signal reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q : std_logic_vector (2 downto 0);
signal reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q : std_logic_vector (39 downto 0);
signal reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (39 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q : std_logic_vector (26 downto 0);
signal reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (77 downto 0);
signal reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q : std_logic_vector (67 downto 0);
signal reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q : std_logic_vector (66 downto 0);
signal reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q : std_logic_vector (65 downto 0);
signal reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q : std_logic_vector (67 downto 0);
signal reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q : std_logic_vector (25 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q : std_logic_vector (12 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q : std_logic_vector (20 downto 0);
signal reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q : std_logic_vector (22 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q : std_logic_vector (29 downto 0);
signal reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q : std_logic_vector (6 downto 0);
signal reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q : std_logic_vector (22 downto 0);
signal reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q : std_logic_vector (0 downto 0);
signal reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q : std_logic_vector (12 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q : std_logic_vector (20 downto 0);
signal reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q : std_logic_vector (22 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q : std_logic_vector (29 downto 0);
signal reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q : std_logic_vector (25 downto 0);
signal reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q : std_logic_vector (25 downto 0);
signal reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q : std_logic_vector (6 downto 0);
signal reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q : std_logic_vector (22 downto 0);
signal reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q : std_logic_vector (3 downto 0);
signal reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q : std_logic_vector (52 downto 0);
signal ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q : std_logic_vector (65 downto 0);
signal ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q : std_logic_vector (67 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (7 downto 0);
signal ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (66 downto 0);
signal ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (65 downto 0);
signal ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (64 downto 0);
signal ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q : std_logic_vector (63 downto 0);
signal ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q : std_logic_vector (31 downto 0);
signal ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (58 downto 0);
signal ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q : std_logic_vector (63 downto 0);
signal ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q : std_logic_vector (31 downto 0);
signal ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (58 downto 0);
signal ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (76 downto 0);
signal ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (75 downto 0);
signal ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (74 downto 0);
signal ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q : std_logic_vector (12 downto 0);
signal ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q : std_logic_vector (53 downto 0);
signal ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q : std_logic_vector (12 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0 : std_logic;
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q : signal is true;
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q : std_logic_vector (6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0 : std_logic;
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q : signal is true;
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q : signal is true;
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0 : std_logic;
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0 : std_logic;
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0 : std_logic;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq : std_logic;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q : signal is true;
signal sinXIsXRR_uid41_fpSinCosXTest_a : std_logic_vector(11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_b : std_logic_vector(11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_o : std_logic_vector (11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_a : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_b : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_o : std_logic_vector (11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal yIsZero_uid51_fpSinCosXTest_a : std_logic_vector(65 downto 0);
signal yIsZero_uid51_fpSinCosXTest_b : std_logic_vector(65 downto 0);
signal yIsZero_uid51_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal pad_one_uid55_fpSinCosXTest_q : std_logic_vector (66 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_a : std_logic_vector(70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_b : std_logic_vector(70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_o : std_logic_vector (70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_c : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal InvCmpYToOneMinusY_uid61_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCmpYToOneMinusY_uid61_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid127_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid127_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvSinXIsXRR_uid128_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsXRR_uid128_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid131_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid131_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid132_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid132_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid136_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid136_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvCosXONe_uid149_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCosXONe_uid149_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid151_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid151_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvIntXParity_uid155_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvIntXParity_uid155_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal oFracXRR_uid43_uid43_fpSinCosXTest_q : std_logic_vector (53 downto 0);
signal half_uid53_fpSinCosXTest_q : std_logic_vector (65 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal exp_uid9_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal exp_uid9_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal frac_uid13_fpSinCosXTest_in : std_logic_vector (22 downto 0);
signal frac_uid13_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal signX_uid37_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal signX_uid37_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal expFracX_uid166_px_uid33_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal expFracX_uid166_px_uid33_fpSinCosXTest_b : std_logic_vector (30 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_q : std_logic_vector (9 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_a : std_logic_vector(65 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_b : std_logic_vector(65 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_a : std_logic_vector(67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_b : std_logic_vector(67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_o : std_logic_vector (67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal zSin_uid60_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal zSin_uid60_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal zCos_uid64_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal zCos_uid64_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal expSinHC_uid74_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal excRNaN_uid117_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid117_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid117_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracRPostExcSin_uid122_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExcSin_uid122_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal expRPostExcSin_uid126_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExcSin_uid126_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracRPostExcCos_uid142_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExcCos_uid142_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal expRPostExcCos_uid147_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExcCos_uid147_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cosXONe_uid148_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal cosXONe_uid148_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal cosXONe_uid148_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal finalExp_uid209_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal finalExp_uid209_rrx_uid34_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal extendedFracX_uid47_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal normBitSin_uid93_fpSinCosXTest_in : std_logic_vector (51 downto 0);
signal normBitSin_uid93_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal fracRSinPreRndHigh_uid95_fpSinCosXTest_in : std_logic_vector (50 downto 0);
signal fracRSinPreRndHigh_uid95_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracRSinPreRndLow_uid96_fpSinCosXTest_in : std_logic_vector (49 downto 0);
signal fracRSinPreRndLow_uid96_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal normBitCos_uid106_fpSinCosXTest_in : std_logic_vector (51 downto 0);
signal normBitCos_uid106_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal fracRCosPreRndHigh_uid108_fpSinCosXTest_in : std_logic_vector (50 downto 0);
signal fracRCosPreRndHigh_uid108_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracRCosPreRndLow_uid109_fpSinCosXTest_in : std_logic_vector (49 downto 0);
signal fracRCosPreRndLow_uid109_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q : std_logic_vector (52 downto 0);
signal leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b : std_logic_vector (23 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int : std_logic_vector (80 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q : std_logic_vector (80 downto 0);
signal os_uid196_rrx_uid34_fpSinCosXTest_q : std_logic_vector (79 downto 0);
signal leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal join_uid99_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal join_uid141_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal zSinYBottom_uid59_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal zSinYBottom_uid59_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal zSinOMyBottom_uid58_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal zSinOMyBottom_uid58_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal excSelBitsSin_uid118_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal fpSin_uid134_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal join_uid143_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal fpCos_uid162_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int : std_logic_vector (107 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q : std_logic_vector (107 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal fracX_uid187_rrx_uid34_fpSinCosXTest_in : std_logic_vector (22 downto 0);
signal fracX_uid187_rrx_uid34_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal oFracXRRSmallXRR_uid90_fpSinCosXTest_in : std_logic_vector (53 downto 0);
signal oFracXRRSmallXRR_uid90_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal R_uid167_px_uid33_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal InvFracXIsZero_uid16_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid16_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fxpXShiftVal_uid46_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal fxpXShiftVal_uid46_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal addr_uid81_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal addr_uid81_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal zPsinPiZ_uid84_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal zPsinPiZ_uid84_fpSinCosXTest_b : std_logic_vector (14 downto 0);
signal rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (32 downto 0);
signal addr_uid83_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal addr_uid83_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal zPcosPiZ_uid87_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal zPcosPiZ_uid87_fpSinCosXTest_b : std_logic_vector (14 downto 0);
signal rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (32 downto 0);
signal expSinHCR_uid75_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expSinHCR_uid75_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal expPCos_uid79_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expPCos_uid79_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (66 downto 0);
signal LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (66 downto 0);
signal LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (65 downto 0);
signal LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (58 downto 0);
signal rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (58 downto 0);
signal rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (76 downto 0);
signal LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (76 downto 0);
signal LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (75 downto 0);
signal LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (75 downto 0);
signal LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (74 downto 0);
signal LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (74 downto 0);
signal X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (59 downto 0);
signal X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (59 downto 0);
signal X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (55 downto 0);
signal X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (55 downto 0);
signal fracRSinPreRnd_uid97_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal fracRSinPreRnd_uid97_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal fracRCosPreRnd_uid110_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal fracRCosPreRnd_uid110_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal cosRndOp_uid112_uid113_fpSinCosXTest_q : std_logic_vector (24 downto 0);
signal rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal lowRangeB_uid408_polyEvalsinPiZ_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid408_polyEvalsinPiZ_b : std_logic_vector (0 downto 0);
signal highBBits_uid409_polyEvalsinPiZ_in : std_logic_vector (13 downto 0);
signal highBBits_uid409_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid414_polyEvalsinPiZ_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid414_polyEvalsinPiZ_b : std_logic_vector (1 downto 0);
signal highBBits_uid415_polyEvalsinPiZ_in : std_logic_vector (23 downto 0);
signal highBBits_uid415_polyEvalsinPiZ_b : std_logic_vector (21 downto 0);
signal lowRangeB_uid421_polyEvalcosPiZ_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid421_polyEvalcosPiZ_b : std_logic_vector (0 downto 0);
signal highBBits_uid422_polyEvalcosPiZ_in : std_logic_vector (13 downto 0);
signal highBBits_uid422_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid427_polyEvalcosPiZ_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid427_polyEvalcosPiZ_b : std_logic_vector (1 downto 0);
signal highBBits_uid428_polyEvalcosPiZ_in : std_logic_vector (23 downto 0);
signal highBBits_uid428_polyEvalcosPiZ_b : std_logic_vector (21 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in : std_logic_vector (80 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b : std_logic_vector (26 downto 0);
signal fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in : std_logic_vector (76 downto 0);
signal fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b : std_logic_vector (52 downto 0);
signal intXParity_uid49_fpSinCosXTest_in : std_logic_vector (67 downto 0);
signal intXParity_uid49_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal y_uid50_fpSinCosXTest_in : std_logic_vector (66 downto 0);
signal y_uid50_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal sinRndOp_uid100_uid101_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal expSelBitsCos_uid144_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a : std_logic_vector(108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b : std_logic_vector(108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o : std_logic_vector (108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q : std_logic_vector (108 downto 0);
signal oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal expX_uid186_rrx_uid34_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal expX_uid186_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal exc_N_uid17_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal yT1_uid406_polyEvalsinPiZ_in : std_logic_vector (14 downto 0);
signal yT1_uid406_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal yT1_uid419_polyEvalcosPiZ_in : std_logic_vector (14 downto 0);
signal yT1_uid419_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_a : std_logic_vector(32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_b : std_logic_vector(32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_o : std_logic_vector (32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_q : std_logic_vector (30 downto 0);
signal finalFrac_uid208_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal finalFrac_uid208_rrx_uid34_fpSinCosXTest_q : std_logic_vector (52 downto 0);
signal signComp_uid129_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_a : std_logic_vector(32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_b : std_logic_vector(32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_o : std_logic_vector (32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_q : std_logic_vector (32 downto 0);
signal leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal multFracBits_uid199_rrx_uid34_fpSinCosXTest_in : std_logic_vector (77 downto 0);
signal multFracBits_uid199_rrx_uid34_fpSinCosXTest_b : std_logic_vector (77 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b : std_logic_vector (26 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (5 downto 0);
signal fracRCompCos_uid115_fpSinCosXTest_in : std_logic_vector (23 downto 0);
signal fracRCompCos_uid115_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal expRCompSin_uid116_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal expRCompSin_uid116_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal s1_uid408_uid411_polyEvalsinPiZ_q : std_logic_vector (22 downto 0);
signal s2_uid414_uid417_polyEvalsinPiZ_q : std_logic_vector (32 downto 0);
signal s1_uid421_uid424_polyEvalcosPiZ_q : std_logic_vector (22 downto 0);
signal s2_uid427_uid430_polyEvalcosPiZ_q : std_logic_vector (32 downto 0);
signal RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q : std_logic_vector (61 downto 0);
signal signR_uid130_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signR_uid130_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signR_uid130_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal fracRCompSin_uid103_fpSinCosXTest_in : std_logic_vector (23 downto 0);
signal fracRCompSin_uid103_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal expRCompSin_uid104_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal expRCompSin_uid104_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in : std_logic_vector (77 downto 0);
signal multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (61 downto 0);
signal X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (61 downto 0);
signal X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (45 downto 0);
signal X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (45 downto 0);
signal X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (29 downto 0);
signal X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (29 downto 0);
signal expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal polyEvalSigsinPiZ_uid86_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal polyEvalSigsinPiZ_uid86_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal polyEvalSigcosPiZ_uid89_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal polyEvalSigcosPiZ_uid89_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal expXRR_uid38_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal expXRR_uid38_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal fracXRR_uid39_fpSinCosXTest_in : std_logic_vector (52 downto 0);
signal fracXRR_uid39_fpSinCosXTest_b : std_logic_vector (52 downto 0);
signal pHigh_uid72_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal pHigh_uid72_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal pCos_uid77_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal pCos_uid77_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal r_uid277_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (6 downto 0);
signal r_uid356_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (6 downto 0);
signal expCompOut_uid205_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expCompOut_uid205_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (73 downto 0);
signal LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (73 downto 0);
signal LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (69 downto 0);
signal LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (69 downto 0);
signal LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (65 downto 0);
signal LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (56 downto 0);
signal LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (48 downto 0);
signal LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (48 downto 0);
signal LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (40 downto 0);
signal LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (40 downto 0);
signal LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (56 downto 0);
signal LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (48 downto 0);
signal LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (48 downto 0);
signal LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (40 downto 0);
signal LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (40 downto 0);
signal leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
begin
--xIn(GPIN,3)@0
--GND(CONSTANT,0)
GND_q <= "0";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable(LOGICAL,1282)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q <= not ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor(LOGICAL,1422)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q <= not (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a or ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b);
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top(CONSTANT,1418)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q <= "01011";
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp(LOGICAL,1419)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q <= "1" when ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a = ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b else "0";
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg(REG,1420)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena(REG,1423)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd(LOGICAL,1424)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b <= en;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a and ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b;
--expFracX_uid166_px_uid33_fpSinCosXTest(BITSELECT,165)@0
expFracX_uid166_px_uid33_fpSinCosXTest_in <= a(30 downto 0);
expFracX_uid166_px_uid33_fpSinCosXTest_b <= expFracX_uid166_px_uid33_fpSinCosXTest_in(30 downto 0);
--R_uid167_px_uid33_fpSinCosXTest(BITJOIN,166)@0
R_uid167_px_uid33_fpSinCosXTest_q <= GND_q & expFracX_uid166_px_uid33_fpSinCosXTest_b;
--expX_uid186_rrx_uid34_fpSinCosXTest(BITSELECT,185)@0
expX_uid186_rrx_uid34_fpSinCosXTest_in <= R_uid167_px_uid33_fpSinCosXTest_q(30 downto 0);
expX_uid186_rrx_uid34_fpSinCosXTest_b <= expX_uid186_rrx_uid34_fpSinCosXTest_in(30 downto 23);
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg(DELAY,1412)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid186_rrx_uid34_fpSinCosXTest_b, xout => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt(COUNTER,1414)
-- every=1, low=0, high=11, step=1, init=1
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i = 10 THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i - 11;
ELSE
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg(REG,1415)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux(MUX,1416)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem(DUALMEM,1413)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 12,
width_b => 8,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia
);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--zs_uid244_lzcZSin_uid66_fpSinCosXTest(CONSTANT,243)
zs_uid244_lzcZSin_uid66_fpSinCosXTest_q <= "00000000000000000000000000000000";
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor(LOGICAL,1396)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q <= not (ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a or ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b);
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg(REG,1318)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena(REG,1397)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q = "1") THEN
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd(LOGICAL,1398)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b <= en;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a and ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg(DELAY,1388)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid167_px_uid33_fpSinCosXTest_q, xout => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt(COUNTER,1314)
-- every=1, low=0, high=1, step=1, init=1
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i,1));
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg(REG,1315)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux(MUX,1316)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s <= en;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux: PROCESS (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s, ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q, ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q)
BEGIN
CASE ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s IS
WHEN "0" => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
WHEN "1" => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem(DUALMEM,1389)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 1,
numwords_a => 2,
width_b => 32,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq,
address_a => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa,
data_a => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia
);
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0 <= areset;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq(31 downto 0);
--fracX_uid187_rrx_uid34_fpSinCosXTest(BITSELECT,186)@4
fracX_uid187_rrx_uid34_fpSinCosXTest_in <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q(22 downto 0);
fracX_uid187_rrx_uid34_fpSinCosXTest_b <= fracX_uid187_rrx_uid34_fpSinCosXTest_in(22 downto 0);
--oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest(BITJOIN,196)@4
oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q <= VCC_q & fracX_uid187_rrx_uid34_fpSinCosXTest_b;
--prod_uid198_rrx_uid34_fpSinCosXTest_b_0(BITSELECT,518)@4
prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in <= STD_LOGIC_VECTOR("000" & oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q);
prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b <= prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in(26 downto 0);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1(REG,539)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q <= prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShift_uid24_fpSinCosXTest(CONSTANT,23)
cstBiasMwShift_uid24_fpSinCosXTest_q <= "01110011";
--expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest(SUB,191)@0
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expX_uid186_rrx_uid34_fpSinCosXTest_b);
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0" & cstBiasMwShift_uid24_fpSinCosXTest_q);
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b));
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q <= expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o(8 downto 0);
--expXTableAddr_uid193_rrx_uid34_fpSinCosXTest(BITSELECT,192)@0
expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in <= expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q(7 downto 0);
expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b <= expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0(REG,534)@0
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q <= expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem(DUALMEM,514)@1
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia <= (others => '0');
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa <= (others => '0');
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab <= reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q;
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq,
address_a => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa,
data_a => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia
);
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0 <= areset;
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q <= rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1(REG,537)@3
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q <= rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem(DUALMEM,513)@1
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia <= (others => '0');
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa <= (others => '0');
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab <= reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q;
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq,
address_a => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa,
data_a => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia
);
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0 <= areset;
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q <= rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0(REG,536)@3
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q <= rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid196_rrx_uid34_fpSinCosXTest(BITJOIN,195)@4
os_uid196_rrx_uid34_fpSinCosXTest_q <= reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q & reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q;
--prod_uid198_rrx_uid34_fpSinCosXTest_a_2(BITSELECT,517)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in <= STD_LOGIC_VECTOR("0" & os_uid196_rrx_uid34_fpSinCosXTest_q);
prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in(80 downto 54);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0(REG,542)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0(MULT,521)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1;
END IF;
END IF;
END PROCESS;
--ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a(DELAY,1145)@8
ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a : dspba_delay
GENERIC MAP ( width => 54, depth => 1 )
PORT MAP ( xin => prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q, xout => ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--prod_uid198_rrx_uid34_fpSinCosXTest_align_2(BITSHIFT,524)@9
prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int <= ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int(107 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_a_1(BITSELECT,516)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in <= os_uid196_rrx_uid34_fpSinCosXTest_q(53 downto 0);
prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in(53 downto 27);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0(REG,540)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0(MULT,520)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_align_1(BITSHIFT,523)@8
prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int <= prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q & "000000000000000000000000000";
prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int(80 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_a_0(BITSELECT,515)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in <= os_uid196_rrx_uid34_fpSinCosXTest_q(26 downto 0);
prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in(26 downto 0);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0(REG,538)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0(MULT,519)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_align_0(BITSHIFT,522)@8
prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int <= prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int(53 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0(ADD,525)@8
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a <= STD_LOGIC_VECTOR("0000000000000000000000000000" & prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b <= STD_LOGIC_VECTOR("0" & prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a) + UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b));
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o(81 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0(ADD,526)@9
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a <= STD_LOGIC_VECTOR("000000000000000000000000000" & prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b <= STD_LOGIC_VECTOR("0" & prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a) + UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b));
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o(108 downto 0);
--multFracBits_uid199_rrx_uid34_fpSinCosXTest(BITSELECT,198)@9
multFracBits_uid199_rrx_uid34_fpSinCosXTest_in <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q(77 downto 0);
multFracBits_uid199_rrx_uid34_fpSinCosXTest_b <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_in(77 downto 0);
--multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest(BITSELECT,199)@9
multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b;
multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b <= multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in(77 downto 46);
--reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1(REG,544)@9
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,433)@10
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a(DELAY,1178)@10
ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xout => ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5(REG,555)@12
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q <= ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q;
END IF;
END IF;
END PROCESS;
--zs_uid250_lzcZSin_uid66_fpSinCosXTest(CONSTANT,249)
zs_uid250_lzcZSin_uid66_fpSinCosXTest_q <= "0000000000000000";
--mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest(CONSTANT,434)
mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "11111111111111111111111111111111";
--vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,436)@10
vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q, mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,438)@10
rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in(31 downto 16);
--reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1(REG,546)@10
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,439)@11
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4(REG,554)@11
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q <= vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e(DELAY,1081)@12
ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWE_uid8_fpSinCosXTest(CONSTANT,7)
cstAllZWE_uid8_fpSinCosXTest_q <= "00000000";
--vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,440)@10
vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q(15 downto 0);
vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in(15 downto 0);
--reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,548)@10
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,442)@11
vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q, reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,444)@11
rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in(15 downto 8);
--vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,445)@11
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i <= "1" when vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xin => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d(DELAY,1080)@12
ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xout => ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest(CONSTANT,212)
leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q <= "0000";
--vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,446)@11
vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q(7 downto 0);
vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,550)@11
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,549)@11
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,448)@12
vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q, reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,450)@12
rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in(7 downto 4);
--vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,451)@12
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,553)@12
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest(CONSTANT,226)
leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q <= "00";
--vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,452)@12
vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q(3 downto 0);
vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in(3 downto 0);
--vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,454)@12
vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b, vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
WHEN "1" => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,456)@12
rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in(3 downto 2);
--vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,457)@12
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i <= "1" when vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xin => vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,458)@12
vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q(1 downto 0);
vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in(1 downto 0);
--reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,552)@12
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,551)@12
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,460)@13
vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q, reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,462)@13
rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in(1 downto 1);
--vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,463)@13
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= GND_q;
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest(BITJOIN,464)@13
r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q & ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q & ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q & reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q & vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q & vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
--cstBiasM1_uid23_fpSinCosXTest(CONSTANT,22)
cstBiasM1_uid23_fpSinCosXTest_q <= "01111110";
--expCompOutExt_uid204_rrx_uid34_fpSinCosXTest(SUB,203)@13
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("000" & r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q);
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b));
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q <= expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o(8 downto 0);
--expCompOut_uid205_rrx_uid34_fpSinCosXTest(BITSELECT,204)@13
expCompOut_uid205_rrx_uid34_fpSinCosXTest_in <= expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q(7 downto 0);
expCompOut_uid205_rrx_uid34_fpSinCosXTest_b <= expCompOut_uid205_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2(REG,564)@13
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q <= expCompOut_uid205_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--xBranch_uid191_rrx_uid34_fpSinCosXTest(COMPARE,190)@0
xBranch_uid191_rrx_uid34_fpSinCosXTest_cin <= GND_q;
xBranch_uid191_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid24_fpSinCosXTest_q) & '0';
xBranch_uid191_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & expX_uid186_rrx_uid34_fpSinCosXTest_b) & xBranch_uid191_rrx_uid34_fpSinCosXTest_cin(0);
xBranch_uid191_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xBranch_uid191_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(xBranch_uid191_rrx_uid34_fpSinCosXTest_b));
xBranch_uid191_rrx_uid34_fpSinCosXTest_n(0) <= not xBranch_uid191_rrx_uid34_fpSinCosXTest_o(10);
--reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1(REG,563)@0
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q <= xBranch_uid191_rrx_uid34_fpSinCosXTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b(DELAY,829)@1
ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q, xout => ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalExp_uid209_rrx_uid34_fpSinCosXTest(MUX,208)@14
finalExp_uid209_rrx_uid34_fpSinCosXTest_s <= ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q;
finalExp_uid209_rrx_uid34_fpSinCosXTest: PROCESS (finalExp_uid209_rrx_uid34_fpSinCosXTest_s, en, reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q)
BEGIN
CASE finalExp_uid209_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b(DELAY,833)@14
ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => finalExp_uid209_rrx_uid34_fpSinCosXTest_q, xout => ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1409)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a or ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top(CONSTANT,1279)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q <= "01000";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp(LOGICAL,1280)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q <= "1" when ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a = ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b else "0";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg(REG,1281)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1410)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1411)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1399)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid187_rrx_uid34_fpSinCosXTest_b, xout => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt(COUNTER,1275)
-- every=1, low=0, high=8, step=1, init=1
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i = 7 THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i - 8;
ELSE
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg(REG,1276)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux(MUX,1277)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s, ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q, ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1400)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 4,
numwords_a => 9,
width_b => 23,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(22 downto 0);
--ZerosGB_uid206_rrx_uid34_fpSinCosXTest(CONSTANT,205)
ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q <= "000000000000000000000000000000";
--fracXRExt_uid207_rrx_uid34_fpSinCosXTest(BITJOIN,206)@15
fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q & ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q;
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1499)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1500)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1501)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,474)@9
X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(29 downto 0);
X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in(29 downto 0);
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1491)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 30, depth => 1 )
PORT MAP ( xin => X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1492)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 1,
numwords_a => 2,
width_b => 30,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(29 downto 0);
--leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest(CONSTANT,473)
leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,475)@13
leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1488)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1489)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1490)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,471)@9
X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(45 downto 0);
X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in(45 downto 0);
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1480)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1481)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 1,
numwords_a => 2,
width_b => 46,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(45 downto 0);
--leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,472)@13
leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1477)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1478)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1479)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,468)@9
X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(61 downto 0);
X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in(61 downto 0);
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1469)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1470)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 62,
widthad_a => 1,
numwords_a => 2,
width_b => 62,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(61 downto 0);
--leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,469)@13
leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor(LOGICAL,1510)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q <= not (ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a or ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b);
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena(REG,1511)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q = "1") THEN
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd(LOGICAL,1512)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b <= en;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a and ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg(DELAY,1502)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 78, depth => 1 )
PORT MAP ( xin => multFracBits_uid199_rrx_uid34_fpSinCosXTest_b, xout => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem(DUALMEM,1503)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 78,
widthad_a => 1,
numwords_a => 2,
width_b => 78,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia
);
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq(77 downto 0);
--leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,476)@13
leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in(5 downto 4);
--leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,477)@13
leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b;
leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,485)@13
LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(65 downto 0);
LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in(65 downto 0);
--leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest(CONSTANT,218)
leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q <= "000000000000";
--leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,486)@13
leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b & leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5(REG,560)@13
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,482)@13
LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(69 downto 0);
LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in(69 downto 0);
--leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,483)@13
leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4(REG,559)@13
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,479)@13
LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(73 downto 0);
LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in(73 downto 0);
--leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,480)@13
leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3(REG,558)@13
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2(REG,557)@13
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,487)@13
leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1(REG,556)@13
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,488)@14
leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q;
leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,496)@14
LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(74 downto 0);
LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in(74 downto 0);
--ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1112)@14
ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 75, depth => 1 )
PORT MAP ( xin => LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest(CONSTANT,229)
leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q <= "000";
--leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,497)@15
leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,493)@14
LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(75 downto 0);
LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in(75 downto 0);
--ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1110)@14
ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 76, depth => 1 )
PORT MAP ( xin => LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,494)@15
leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,490)@14
LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(76 downto 0);
LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in(76 downto 0);
--ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1108)@14
ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 77, depth => 1 )
PORT MAP ( xin => LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,491)@15
leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & GND_q;
--reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2(REG,562)@14
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,498)@13
leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a(DELAY,1184)@13
ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1(REG,561)@14
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,499)@15
leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q;
leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracCompOut_uid203_rrx_uid34_fpSinCosXTest(BITSELECT,202)@15
fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in <= leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q(76 downto 0);
fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b <= fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in(76 downto 24);
--ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b(DELAY,826)@0
ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => xBranch_uid191_rrx_uid34_fpSinCosXTest_n, xout => ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalFrac_uid208_rrx_uid34_fpSinCosXTest(MUX,207)@15
finalFrac_uid208_rrx_uid34_fpSinCosXTest_s <= ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q;
finalFrac_uid208_rrx_uid34_fpSinCosXTest: PROCESS (finalFrac_uid208_rrx_uid34_fpSinCosXTest_s, en, fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b, fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE finalFrac_uid208_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b;
WHEN "1" => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RRangeRed_uid210_rrx_uid34_fpSinCosXTest(BITJOIN,209)@15
RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q <= GND_q & ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q & finalFrac_uid208_rrx_uid34_fpSinCosXTest_q;
--expXRR_uid38_fpSinCosXTest(BITSELECT,37)@15
expXRR_uid38_fpSinCosXTest_in <= RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q(60 downto 0);
expXRR_uid38_fpSinCosXTest_b <= expXRR_uid38_fpSinCosXTest_in(60 downto 53);
--reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1(REG,565)@15
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q <= expXRR_uid38_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShiftM2_uid26_fpSinCosXTest(CONSTANT,25)
cstBiasMwShiftM2_uid26_fpSinCosXTest_q <= "01110000";
--cosXIsOneXRR_uid42_fpSinCosXTest(COMPARE,41)@16
cosXIsOneXRR_uid42_fpSinCosXTest_cin <= GND_q;
cosXIsOneXRR_uid42_fpSinCosXTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid26_fpSinCosXTest_q) & '0';
cosXIsOneXRR_uid42_fpSinCosXTest_b <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q) & cosXIsOneXRR_uid42_fpSinCosXTest_cin(0);
cosXIsOneXRR_uid42_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(cosXIsOneXRR_uid42_fpSinCosXTest_a) - SIGNED(cosXIsOneXRR_uid42_fpSinCosXTest_b));
cosXIsOneXRR_uid42_fpSinCosXTest_n(0) <= not cosXIsOneXRR_uid42_fpSinCosXTest_o(11);
--exp_uid9_fpSinCosXTest(BITSELECT,8)@0
exp_uid9_fpSinCosXTest_in <= a(30 downto 0);
exp_uid9_fpSinCosXTest_b <= exp_uid9_fpSinCosXTest_in(30 downto 23);
--sinXIsX_uid40_fpSinCosXTest(COMPARE,39)@0
sinXIsX_uid40_fpSinCosXTest_cin <= GND_q;
sinXIsX_uid40_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid24_fpSinCosXTest_q) & '0';
sinXIsX_uid40_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & exp_uid9_fpSinCosXTest_b) & sinXIsX_uid40_fpSinCosXTest_cin(0);
sinXIsX_uid40_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid40_fpSinCosXTest_a) - UNSIGNED(sinXIsX_uid40_fpSinCosXTest_b));
sinXIsX_uid40_fpSinCosXTest_n(0) <= not sinXIsX_uid40_fpSinCosXTest_o(10);
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a(DELAY,789)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--cosXONe_uid148_fpSinCosXTest(LOGICAL,147)@16
cosXONe_uid148_fpSinCosXTest_a <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q;
cosXONe_uid148_fpSinCosXTest_b <= cosXIsOneXRR_uid42_fpSinCosXTest_n;
cosXONe_uid148_fpSinCosXTest_q <= cosXONe_uid148_fpSinCosXTest_a or cosXONe_uid148_fpSinCosXTest_b;
--ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a(DELAY,791)@16
ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => cosXONe_uid148_fpSinCosXTest_q, xout => ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvCosXONe_uid149_fpSinCosXTest(LOGICAL,148)@20
InvCosXONe_uid149_fpSinCosXTest_a <= ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q;
InvCosXONe_uid149_fpSinCosXTest_q <= not InvCosXONe_uid149_fpSinCosXTest_a;
--cstZwShiftP1_uid27_fpSinCosXTest(CONSTANT,26)
cstZwShiftP1_uid27_fpSinCosXTest_q <= "00000000000000";
--fracXRR_uid39_fpSinCosXTest(BITSELECT,38)@15
fracXRR_uid39_fpSinCosXTest_in <= RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q(52 downto 0);
fracXRR_uid39_fpSinCosXTest_b <= fracXRR_uid39_fpSinCosXTest_in(52 downto 0);
--ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a(DELAY,668)@15
ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => fracXRR_uid39_fpSinCosXTest_b, xout => ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracXRR_uid43_uid43_fpSinCosXTest(BITJOIN,42)@16
oFracXRR_uid43_uid43_fpSinCosXTest_q <= VCC_q & ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q;
--extendedFracX_uid47_fpSinCosXTest(BITJOIN,46)@16
extendedFracX_uid47_fpSinCosXTest_q <= cstZwShiftP1_uid27_fpSinCosXTest_q & oFracXRR_uid43_uid43_fpSinCosXTest_q;
--X55dto0_uid220_fxpX_uid48_fpSinCosXTest(BITSELECT,219)@16
X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(55 downto 0);
X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b <= X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in(55 downto 0);
--leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest(BITJOIN,220)@16
leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q <= X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b & leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5(REG,571)@16
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q <= leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--X59dto0_uid217_fxpX_uid48_fpSinCosXTest(BITSELECT,216)@16
X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(59 downto 0);
X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b <= X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in(59 downto 0);
--leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest(BITJOIN,217)@16
leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q <= X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4(REG,570)@16
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q <= leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--X63dto0_uid214_fxpX_uid48_fpSinCosXTest(BITSELECT,213)@16
X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(63 downto 0);
X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b <= X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in(63 downto 0);
--leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest(BITJOIN,214)@16
leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q <= X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3(REG,569)@16
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q <= leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2(REG,568)@16
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q <= extendedFracX_uid47_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--fxpXShiftValExt_uid45_fpSinCosXTest(SUB,44)@16
fxpXShiftValExt_uid45_fpSinCosXTest_a <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q);
fxpXShiftValExt_uid45_fpSinCosXTest_b <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid26_fpSinCosXTest_q);
fxpXShiftValExt_uid45_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(fxpXShiftValExt_uid45_fpSinCosXTest_a) - SIGNED(fxpXShiftValExt_uid45_fpSinCosXTest_b));
fxpXShiftValExt_uid45_fpSinCosXTest_q <= fxpXShiftValExt_uid45_fpSinCosXTest_o(9 downto 0);
--fxpXShiftVal_uid46_fpSinCosXTest(BITSELECT,45)@16
fxpXShiftVal_uid46_fpSinCosXTest_in <= fxpXShiftValExt_uid45_fpSinCosXTest_q(3 downto 0);
fxpXShiftVal_uid46_fpSinCosXTest_b <= fxpXShiftVal_uid46_fpSinCosXTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest(BITSELECT,221)@16
leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in <= fxpXShiftVal_uid46_fpSinCosXTest_b;
leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b <= leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1(REG,567)@16
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q <= leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest(MUX,222)@17
leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s <= reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q;
leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest: PROCESS (leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s, en, reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q, reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q, reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q, reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest(BITSELECT,230)@17
LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(64 downto 0);
LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in(64 downto 0);
--ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b(DELAY,851)@17
ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest(BITJOIN,231)@18
leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q & leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest(BITSELECT,227)@17
LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(65 downto 0);
LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in(65 downto 0);
--ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b(DELAY,849)@17
ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 66, depth => 1 )
PORT MAP ( xin => LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest(BITJOIN,228)@18
leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest(BITSELECT,224)@17
LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(66 downto 0);
LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in(66 downto 0);
--ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b(DELAY,847)@17
ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 67, depth => 1 )
PORT MAP ( xin => LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest(BITJOIN,225)@18
leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q & GND_q;
--reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2(REG,573)@17
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest(BITSELECT,232)@16
leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in <= fxpXShiftVal_uid46_fpSinCosXTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b <= leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a(DELAY,1195)@16
ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b, xout => ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1(REG,572)@17
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q <= ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest(MUX,233)@18
leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s <= reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q;
leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest: PROCESS (leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s, en, reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q, leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q, leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q, leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q;
WHEN "10" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q;
WHEN "11" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid50_fpSinCosXTest(BITSELECT,49)@18
y_uid50_fpSinCosXTest_in <= leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q(66 downto 0);
y_uid50_fpSinCosXTest_b <= y_uid50_fpSinCosXTest_in(66 downto 1);
--ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b(DELAY,680)@18
ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 66, depth => 2 )
PORT MAP ( xin => y_uid50_fpSinCosXTest_b, xout => ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1(REG,575)@18
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q <= y_uid50_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--pad_one_uid55_fpSinCosXTest(BITJOIN,54)@18
pad_one_uid55_fpSinCosXTest_q <= VCC_q & STD_LOGIC_VECTOR((65 downto 1 => GND_q(0)) & GND_q);
--reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0(REG,574)@18
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q <= pad_one_uid55_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--oneMinusY_uid55_fpSinCosXTest(SUB,55)@19
oneMinusY_uid55_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q);
oneMinusY_uid55_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q);
oneMinusY_uid55_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid55_fpSinCosXTest_a) - UNSIGNED(oneMinusY_uid55_fpSinCosXTest_b));
oneMinusY_uid55_fpSinCosXTest_q <= oneMinusY_uid55_fpSinCosXTest_o(67 downto 0);
--reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0(REG,576)@19
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q <= oneMinusY_uid55_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid57_fpSinCosXTest(COMPARE,56)@20
cmpYToOneMinusY_uid57_fpSinCosXTest_cin <= GND_q;
cmpYToOneMinusY_uid57_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q) & '0';
cmpYToOneMinusY_uid57_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q) & cmpYToOneMinusY_uid57_fpSinCosXTest_cin(0);
cmpYToOneMinusY_uid57_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid57_fpSinCosXTest_a) - UNSIGNED(cmpYToOneMinusY_uid57_fpSinCosXTest_b));
cmpYToOneMinusY_uid57_fpSinCosXTest_c(0) <= cmpYToOneMinusY_uid57_fpSinCosXTest_o(70);
--InvCmpYToOneMinusY_uid61_fpSinCosXTest(LOGICAL,60)@20
InvCmpYToOneMinusY_uid61_fpSinCosXTest_a <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
InvCmpYToOneMinusY_uid61_fpSinCosXTest_q <= not InvCmpYToOneMinusY_uid61_fpSinCosXTest_a;
--intXParity_uid49_fpSinCosXTest(BITSELECT,48)@18
intXParity_uid49_fpSinCosXTest_in <= leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q;
intXParity_uid49_fpSinCosXTest_b <= intXParity_uid49_fpSinCosXTest_in(67 downto 67);
--ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b(DELAY,794)@18
ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => intXParity_uid49_fpSinCosXTest_b, xout => ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--yIsZero_uid51_fpSinCosXTest(LOGICAL,50)@19
yIsZero_uid51_fpSinCosXTest_a <= reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q;
yIsZero_uid51_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000000000000000000000000000000000" & GND_q);
yIsZero_uid51_fpSinCosXTest_q <= "1" when yIsZero_uid51_fpSinCosXTest_a = yIsZero_uid51_fpSinCosXTest_b else "0";
--ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a(DELAY,792)@19
ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => yIsZero_uid51_fpSinCosXTest_q, xout => ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvYIsZero_uid151_fpSinCosXTest(LOGICAL,150)@20
InvYIsZero_uid151_fpSinCosXTest_a <= ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q;
InvYIsZero_uid151_fpSinCosXTest_q <= not InvYIsZero_uid151_fpSinCosXTest_a;
--signRCond2_uid152_fpSinCosXTest(LOGICAL,151)@20
signRCond2_uid152_fpSinCosXTest_a <= InvYIsZero_uid151_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_b <= ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q;
signRCond2_uid152_fpSinCosXTest_c <= InvCmpYToOneMinusY_uid61_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_d <= InvCosXONe_uid149_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_q_i <= signRCond2_uid152_fpSinCosXTest_a and signRCond2_uid152_fpSinCosXTest_b and signRCond2_uid152_fpSinCosXTest_c and signRCond2_uid152_fpSinCosXTest_d;
signRCond2_uid152_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRCond2_uid152_fpSinCosXTest_q, xin => signRCond2_uid152_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--InvIntXParity_uid155_fpSinCosXTest(LOGICAL,154)@20
InvIntXParity_uid155_fpSinCosXTest_a <= ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q;
InvIntXParity_uid155_fpSinCosXTest_q <= not InvIntXParity_uid155_fpSinCosXTest_a;
--signRCond1_uid157_fpSinCosXTest(LOGICAL,156)@20
signRCond1_uid157_fpSinCosXTest_a <= InvYIsZero_uid151_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_b <= InvIntXParity_uid155_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_c <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
signRCond1_uid157_fpSinCosXTest_d <= InvCosXONe_uid149_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_q_i <= signRCond1_uid157_fpSinCosXTest_a and signRCond1_uid157_fpSinCosXTest_b and signRCond1_uid157_fpSinCosXTest_c and signRCond1_uid157_fpSinCosXTest_d;
signRCond1_uid157_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRCond1_uid157_fpSinCosXTest_q, xin => signRCond1_uid157_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--signRCos_uid158_fpSinCosXTest(LOGICAL,157)@21
signRCos_uid158_fpSinCosXTest_a <= signRCond1_uid157_fpSinCosXTest_q;
signRCos_uid158_fpSinCosXTest_b <= signRCond2_uid152_fpSinCosXTest_q;
signRCos_uid158_fpSinCosXTest_q <= signRCos_uid158_fpSinCosXTest_a or signRCos_uid158_fpSinCosXTest_b;
--cstAllZWF_uid7_fpSinCosXTest(CONSTANT,6)
cstAllZWF_uid7_fpSinCosXTest_q <= "00000000000000000000000";
--frac_uid13_fpSinCosXTest(BITSELECT,12)@0
frac_uid13_fpSinCosXTest_in <= a(22 downto 0);
frac_uid13_fpSinCosXTest_b <= frac_uid13_fpSinCosXTest_in(22 downto 0);
--fracXIsZero_uid14_fpSinCosXTest(LOGICAL,13)@0
fracXIsZero_uid14_fpSinCosXTest_a <= frac_uid13_fpSinCosXTest_b;
fracXIsZero_uid14_fpSinCosXTest_b <= cstAllZWF_uid7_fpSinCosXTest_q;
fracXIsZero_uid14_fpSinCosXTest_q <= "1" when fracXIsZero_uid14_fpSinCosXTest_a = fracXIsZero_uid14_fpSinCosXTest_b else "0";
--cstAllOWE_uid6_fpSinCosXTest(CONSTANT,5)
cstAllOWE_uid6_fpSinCosXTest_q <= "11111111";
--expXIsMax_uid12_fpSinCosXTest(LOGICAL,11)@0
expXIsMax_uid12_fpSinCosXTest_a <= exp_uid9_fpSinCosXTest_b;
expXIsMax_uid12_fpSinCosXTest_b <= cstAllOWE_uid6_fpSinCosXTest_q;
expXIsMax_uid12_fpSinCosXTest_q <= "1" when expXIsMax_uid12_fpSinCosXTest_a = expXIsMax_uid12_fpSinCosXTest_b else "0";
--exc_I_uid15_fpSinCosXTest(LOGICAL,14)@0
exc_I_uid15_fpSinCosXTest_a <= expXIsMax_uid12_fpSinCosXTest_q;
exc_I_uid15_fpSinCosXTest_b <= fracXIsZero_uid14_fpSinCosXTest_q;
exc_I_uid15_fpSinCosXTest_q <= exc_I_uid15_fpSinCosXTest_a and exc_I_uid15_fpSinCosXTest_b;
--ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a(DELAY,762)@0
ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 20 )
PORT MAP ( xin => exc_I_uid15_fpSinCosXTest_q, xout => ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_I_uid131_fpSinCosXTest(LOGICAL,130)@20
InvExc_I_uid131_fpSinCosXTest_a <= ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q;
InvExc_I_uid131_fpSinCosXTest_q <= not InvExc_I_uid131_fpSinCosXTest_a;
--reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2(REG,649)@20
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q <= InvExc_I_uid131_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--InvFracXIsZero_uid16_fpSinCosXTest(LOGICAL,15)@0
InvFracXIsZero_uid16_fpSinCosXTest_a <= fracXIsZero_uid14_fpSinCosXTest_q;
InvFracXIsZero_uid16_fpSinCosXTest_q <= not InvFracXIsZero_uid16_fpSinCosXTest_a;
--exc_N_uid17_fpSinCosXTest(LOGICAL,16)@0
exc_N_uid17_fpSinCosXTest_a <= expXIsMax_uid12_fpSinCosXTest_q;
exc_N_uid17_fpSinCosXTest_b <= InvFracXIsZero_uid16_fpSinCosXTest_q;
exc_N_uid17_fpSinCosXTest_q <= exc_N_uid17_fpSinCosXTest_a and exc_N_uid17_fpSinCosXTest_b;
--ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a(DELAY,763)@0
ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 20 )
PORT MAP ( xin => exc_N_uid17_fpSinCosXTest_q, xout => ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid132_fpSinCosXTest(LOGICAL,131)@20
InvExc_N_uid132_fpSinCosXTest_a <= ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q;
InvExc_N_uid132_fpSinCosXTest_q <= not InvExc_N_uid132_fpSinCosXTest_a;
--reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1(REG,648)@20
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q <= InvExc_N_uid132_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--signRCosFull_uid161_fpSinCosXTest(LOGICAL,160)@21
signRCosFull_uid161_fpSinCosXTest_a <= reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q;
signRCosFull_uid161_fpSinCosXTest_b <= reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q;
signRCosFull_uid161_fpSinCosXTest_c <= signRCos_uid158_fpSinCosXTest_q;
signRCosFull_uid161_fpSinCosXTest_q <= signRCosFull_uid161_fpSinCosXTest_a and signRCosFull_uid161_fpSinCosXTest_b and signRCosFull_uid161_fpSinCosXTest_c;
--ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c(DELAY,809)@21
ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signRCosFull_uid161_fpSinCosXTest_q, xout => ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid22_fpSinCosXTest(CONSTANT,21)
cstBias_uid22_fpSinCosXTest_q <= "01111111";
--ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a(DELAY,681)@19
ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 68, depth => 1 )
PORT MAP ( xin => oneMinusY_uid55_fpSinCosXTest_q, xout => ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--zSinOMyBottom_uid58_fpSinCosXTest(BITSELECT,57)@20
zSinOMyBottom_uid58_fpSinCosXTest_in <= ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q(64 downto 0);
zSinOMyBottom_uid58_fpSinCosXTest_b <= zSinOMyBottom_uid58_fpSinCosXTest_in(64 downto 0);
--reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3(REG,579)@20
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q <= zSinOMyBottom_uid58_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--zSinYBottom_uid59_fpSinCosXTest(BITSELECT,58)@20
zSinYBottom_uid59_fpSinCosXTest_in <= ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q(64 downto 0);
zSinYBottom_uid59_fpSinCosXTest_b <= zSinYBottom_uid59_fpSinCosXTest_in(64 downto 0);
--reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2(REG,578)@20
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q <= zSinYBottom_uid59_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1(REG,614)@20
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q <= InvCmpYToOneMinusY_uid61_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--zCos_uid64_fpSinCosXTest(MUX,63)@21
zCos_uid64_fpSinCosXTest_s <= reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q;
zCos_uid64_fpSinCosXTest: PROCESS (zCos_uid64_fpSinCosXTest_s, en, reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q, reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q)
BEGIN
CASE zCos_uid64_fpSinCosXTest_s IS
WHEN "0" => zCos_uid64_fpSinCosXTest_q <= reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q;
WHEN "1" => zCos_uid64_fpSinCosXTest_q <= reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q;
WHEN OTHERS => zCos_uid64_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--addr_uid83_fpSinCosXTest(BITSELECT,82)@21
addr_uid83_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q;
addr_uid83_fpSinCosXTest_b <= addr_uid83_fpSinCosXTest_in(64 downto 57);
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0(REG,630)@21
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q <= addr_uid83_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid404_tableGencosPiZ_lutmem(DUALMEM,532)@22
memoryC2_uid404_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC2_uid404_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC2_uid404_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q;
memoryC2_uid404_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC2_uid404_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid404_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid404_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid404_tableGencosPiZ_lutmem_iq,
address_a => memoryC2_uid404_tableGencosPiZ_lutmem_aa,
data_a => memoryC2_uid404_tableGencosPiZ_lutmem_ia
);
memoryC2_uid404_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC2_uid404_tableGencosPiZ_lutmem_q <= memoryC2_uid404_tableGencosPiZ_lutmem_iq(12 downto 0);
--reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1(REG,632)@24
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q <= memoryC2_uid404_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPcosPiZ_uid87_fpSinCosXTest(BITSELECT,86)@21
zPcosPiZ_uid87_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(56 downto 0);
zPcosPiZ_uid87_fpSinCosXTest_b <= zPcosPiZ_uid87_fpSinCosXTest_in(56 downto 42);
--yT1_uid419_polyEvalcosPiZ(BITSELECT,418)@21
yT1_uid419_polyEvalcosPiZ_in <= zPcosPiZ_uid87_fpSinCosXTest_b;
yT1_uid419_polyEvalcosPiZ_b <= yT1_uid419_polyEvalcosPiZ_in(14 downto 2);
--reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0(REG,631)@21
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q <= yT1_uid419_polyEvalcosPiZ_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg(DELAY,1513)
ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q, xout => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a(DELAY,1125)@22
ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q, xout => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid508_pT1_uid420_polyEvalcosPiZ(MULT,507)@25
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a),14)) * SIGNED(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b);
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a <= (others => '0');
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b <= (others => '0');
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a <= ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b <= reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q <= prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ(BITSELECT,508)@28
prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in <= prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q;
prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in(25 downto 12);
--highBBits_uid422_polyEvalcosPiZ(BITSELECT,421)@28
highBBits_uid422_polyEvalcosPiZ_in <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b;
highBBits_uid422_polyEvalcosPiZ_b <= highBBits_uid422_polyEvalcosPiZ_in(13 downto 1);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a(DELAY,1256)@21
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => addr_uid83_fpSinCosXTest_b, xout => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0(REG,633)@24
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid402_tableGencosPiZ_lutmem(DUALMEM,531)@25
memoryC1_uid402_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC1_uid402_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC1_uid402_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q;
memoryC1_uid402_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC1_uid402_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid402_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid402_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid402_tableGencosPiZ_lutmem_iq,
address_a => memoryC1_uid402_tableGencosPiZ_lutmem_aa,
data_a => memoryC1_uid402_tableGencosPiZ_lutmem_ia
);
memoryC1_uid402_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC1_uid402_tableGencosPiZ_lutmem_q <= memoryC1_uid402_tableGencosPiZ_lutmem_iq(20 downto 0);
--reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0(REG,634)@27
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q <= memoryC1_uid402_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid423_polyEvalcosPiZ(ADD,422)@28
sumAHighB_uid423_polyEvalcosPiZ_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q(20)) & reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q);
sumAHighB_uid423_polyEvalcosPiZ_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid422_polyEvalcosPiZ_b(12)) & highBBits_uid422_polyEvalcosPiZ_b);
sumAHighB_uid423_polyEvalcosPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid423_polyEvalcosPiZ_a) + SIGNED(sumAHighB_uid423_polyEvalcosPiZ_b));
sumAHighB_uid423_polyEvalcosPiZ_q <= sumAHighB_uid423_polyEvalcosPiZ_o(21 downto 0);
--lowRangeB_uid421_polyEvalcosPiZ(BITSELECT,420)@28
lowRangeB_uid421_polyEvalcosPiZ_in <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b(0 downto 0);
lowRangeB_uid421_polyEvalcosPiZ_b <= lowRangeB_uid421_polyEvalcosPiZ_in(0 downto 0);
--s1_uid421_uid424_polyEvalcosPiZ(BITJOIN,423)@28
s1_uid421_uid424_polyEvalcosPiZ_q <= sumAHighB_uid423_polyEvalcosPiZ_q & lowRangeB_uid421_polyEvalcosPiZ_b;
--reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1(REG,636)@28
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q <= s1_uid421_uid424_polyEvalcosPiZ_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor(LOGICAL,1524)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q <= not (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a or ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b);
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top(CONSTANT,1520)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q <= "0100";
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp(LOGICAL,1521)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q <= "1" when ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a = ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b else "0";
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg(REG,1522)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena(REG,1525)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd(LOGICAL,1526)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b <= en;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a and ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b;
--reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0(REG,635)@21
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q <= zPcosPiZ_uid87_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg(DELAY,1514)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q, xout => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt(COUNTER,1516)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i = 3 THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i,3));
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg(REG,1517)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux(MUX,1518)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s <= en;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux: PROCESS (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s, ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q, ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem(DUALMEM,1515)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq,
address_a => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa,
data_a => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia
);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0 <= areset;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq(14 downto 0);
--prodXY_uid511_pT2_uid426_polyEvalcosPiZ(MULT,510)@29
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a),16)) * SIGNED(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b);
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a <= (others => '0');
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b <= (others => '0');
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b <= reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q <= prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ(BITSELECT,511)@32
prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in <= prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q;
prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in(37 downto 14);
--highBBits_uid428_polyEvalcosPiZ(BITSELECT,427)@32
highBBits_uid428_polyEvalcosPiZ_in <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b;
highBBits_uid428_polyEvalcosPiZ_b <= highBBits_uid428_polyEvalcosPiZ_in(23 downto 2);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor(LOGICAL,1577)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q <= not (ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a or ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena(REG,1578)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q = "1") THEN
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd(LOGICAL,1579)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b <= en;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a and ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b;
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg(DELAY,1567)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addr_uid83_fpSinCosXTest_b, xout => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem(DUALMEM,1568)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq,
address_a => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa,
data_a => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia
);
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0(REG,637)@28
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid400_tableGencosPiZ_lutmem(DUALMEM,530)@29
memoryC0_uid400_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC0_uid400_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC0_uid400_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q;
memoryC0_uid400_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC0_uid400_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid400_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid400_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid400_tableGencosPiZ_lutmem_iq,
address_a => memoryC0_uid400_tableGencosPiZ_lutmem_aa,
data_a => memoryC0_uid400_tableGencosPiZ_lutmem_ia
);
memoryC0_uid400_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC0_uid400_tableGencosPiZ_lutmem_q <= memoryC0_uid400_tableGencosPiZ_lutmem_iq(29 downto 0);
--reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0(REG,638)@31
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q <= memoryC0_uid400_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid429_polyEvalcosPiZ(ADD,428)@32
sumAHighB_uid429_polyEvalcosPiZ_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q(29)) & reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q);
sumAHighB_uid429_polyEvalcosPiZ_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid428_polyEvalcosPiZ_b(21)) & highBBits_uid428_polyEvalcosPiZ_b);
sumAHighB_uid429_polyEvalcosPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid429_polyEvalcosPiZ_a) + SIGNED(sumAHighB_uid429_polyEvalcosPiZ_b));
sumAHighB_uid429_polyEvalcosPiZ_q <= sumAHighB_uid429_polyEvalcosPiZ_o(30 downto 0);
--lowRangeB_uid427_polyEvalcosPiZ(BITSELECT,426)@32
lowRangeB_uid427_polyEvalcosPiZ_in <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b(1 downto 0);
lowRangeB_uid427_polyEvalcosPiZ_b <= lowRangeB_uid427_polyEvalcosPiZ_in(1 downto 0);
--s2_uid427_uid430_polyEvalcosPiZ(BITJOIN,429)@32
s2_uid427_uid430_polyEvalcosPiZ_q <= sumAHighB_uid429_polyEvalcosPiZ_q & lowRangeB_uid427_polyEvalcosPiZ_b;
--polyEvalSigcosPiZ_uid89_fpSinCosXTest(BITSELECT,88)@32
polyEvalSigcosPiZ_uid89_fpSinCosXTest_in <= s2_uid427_uid430_polyEvalcosPiZ_q(30 downto 0);
polyEvalSigcosPiZ_uid89_fpSinCosXTest_b <= polyEvalSigcosPiZ_uid89_fpSinCosXTest_in(30 downto 5);
--reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1(REG,640)@32
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q <= polyEvalSigcosPiZ_uid89_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor(LOGICAL,1590)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q <= not (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a or ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b);
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top(CONSTANT,1586)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q <= "010";
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp(LOGICAL,1587)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q <= "1" when ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a = ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b else "0";
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg(REG,1588)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena(REG,1591)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd(LOGICAL,1592)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b <= en;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a and ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b;
--LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest(BITSELECT,388)@27
LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q(63 downto 0);
LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in(63 downto 0);
--leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest(BITJOIN,389)@27
leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b & GND_q;
--cstZmwFRRPwSM1_uid52_fpSinCosXTest(CONSTANT,51)
cstZmwFRRPwSM1_uid52_fpSinCosXTest_q <= "00000000000000000000000000000000000000000000000000000000000000000";
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor(LOGICAL,1455)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q <= not (ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a or ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b);
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena(REG,1456)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q = "1") THEN
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd(LOGICAL,1457)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b <= en;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a and ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b;
--X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest(BITSELECT,359)@21
X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(32 downto 0);
X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b <= X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in(32 downto 0);
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg(DELAY,1447)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem(DUALMEM,1448)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 33,
widthad_a => 1,
numwords_a => 2,
width_b => 33,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia
);
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq(32 downto 0);
--leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest(BITJOIN,360)@25
leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor(LOGICAL,1466)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q <= not (ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a or ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b);
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena(REG,1467)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q = "1") THEN
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd(LOGICAL,1468)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b <= en;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a and ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg(DELAY,1458)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => zCos_uid64_fpSinCosXTest_q, xout => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem(DUALMEM,1459)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 65,
widthad_a => 1,
numwords_a => 2,
width_b => 65,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia
);
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq(64 downto 0);
--zs_uid236_lzcZSin_uid66_fpSinCosXTest(CONSTANT,235)
zs_uid236_lzcZSin_uid66_fpSinCosXTest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--rVStage_uid316_lzcZCos_uid69_fpSinCosXTest(BITSELECT,315)@21
rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q;
rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in(64 downto 1);
--vCount_uid317_lzcZCos_uid69_fpSinCosXTest(LOGICAL,316)@21
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid236_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g(DELAY,985)@22
ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid319_lzcZCos_uid69_fpSinCosXTest(BITSELECT,318)@21
vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(0 downto 0);
vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in(0 downto 0);
--ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b(DELAY,943)@21
ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid239_lzcZSin_uid66_fpSinCosXTest(CONSTANT,238)
mO_uid239_lzcZSin_uid66_fpSinCosXTest_q <= "111111111111111111111111111111111111111111111111111111111111111";
--cStage_uid320_lzcZCos_uid69_fpSinCosXTest(BITJOIN,319)@22
cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q <= ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q & mO_uid239_lzcZSin_uid66_fpSinCosXTest_q;
--ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c(DELAY,945)@21
ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid322_lzcZCos_uid69_fpSinCosXTest(MUX,321)@22
vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid322_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s, en, ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q, cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid324_lzcZCos_uid69_fpSinCosXTest(BITSELECT,323)@22
rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in(63 downto 32);
--vCount_uid325_lzcZCos_uid69_fpSinCosXTest(LOGICAL,324)@22
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f(DELAY,984)@23
ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid326_lzcZCos_uid69_fpSinCosXTest(BITSELECT,325)@22
vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q(31 downto 0);
vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in(31 downto 0);
--ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d(DELAY,952)@22
ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c(DELAY,951)@22
ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid328_lzcZCos_uid69_fpSinCosXTest(MUX,327)@23
vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid328_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s, en, ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q, ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q)
BEGIN
CASE vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q;
WHEN OTHERS => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid330_lzcZCos_uid69_fpSinCosXTest(BITSELECT,329)@23
rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in(31 downto 16);
--vCount_uid331_lzcZCos_uid69_fpSinCosXTest(LOGICAL,330)@23
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b else "0";
--reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4(REG,622)@23
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q <= vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e(DELAY,983)@24
ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid332_lzcZCos_uid69_fpSinCosXTest(BITSELECT,331)@23
vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q(15 downto 0);
vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in(15 downto 0);
--vStagei_uid334_lzcZCos_uid69_fpSinCosXTest(MUX,333)@23
vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid334_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s, en, rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b, vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b;
WHEN "1" => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid336_lzcZCos_uid69_fpSinCosXTest(BITSELECT,335)@23
rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in(15 downto 8);
--reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1(REG,617)@23
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q <= rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid337_lzcZCos_uid69_fpSinCosXTest(LOGICAL,336)@24
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a <= reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q;
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b else "0";
--ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d(DELAY,982)@24
ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid338_lzcZCos_uid69_fpSinCosXTest(BITSELECT,337)@23
vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q(7 downto 0);
vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3(REG,619)@23
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q <= vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid340_lzcZCos_uid69_fpSinCosXTest(MUX,339)@24
vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid340_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s, en, reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q, reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid342_lzcZCos_uid69_fpSinCosXTest(BITSELECT,341)@24
rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in(7 downto 4);
--vCount_uid343_lzcZCos_uid69_fpSinCosXTest(LOGICAL,342)@24
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid344_lzcZCos_uid69_fpSinCosXTest(BITSELECT,343)@24
vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q(3 downto 0);
vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in(3 downto 0);
--reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3(REG,621)@24
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q <= vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2(REG,620)@24
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid346_lzcZCos_uid69_fpSinCosXTest(MUX,345)@25
vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid346_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s, en, reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q, reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid348_lzcZCos_uid69_fpSinCosXTest(BITSELECT,347)@25
rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in(3 downto 2);
--vCount_uid349_lzcZCos_uid69_fpSinCosXTest(LOGICAL,348)@25
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b else "0";
--vStage_uid350_lzcZCos_uid69_fpSinCosXTest(BITSELECT,349)@25
vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q(1 downto 0);
vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in(1 downto 0);
--vStagei_uid352_lzcZCos_uid69_fpSinCosXTest(MUX,351)@25
vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid352_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s, en, rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b, vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b;
WHEN "1" => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid354_lzcZCos_uid69_fpSinCosXTest(BITSELECT,353)@25
rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in(1 downto 1);
--vCount_uid355_lzcZCos_uid69_fpSinCosXTest(LOGICAL,354)@25
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b <= GND_q;
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b else "0";
--r_uid356_lzcZCos_uid69_fpSinCosXTest(BITJOIN,355)@25
r_uid356_lzcZCos_uid69_fpSinCosXTest_q <= ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q & ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q & ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q & ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q & vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q & vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q & vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q;
--leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest(BITSELECT,363)@25
leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q;
leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in(6 downto 5);
--leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest(MUX,364)@25
leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s <= leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b;
leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s, en, ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest(BITSELECT,372)@25
LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(40 downto 0);
LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in(40 downto 0);
--leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest(CONSTANT,292)
leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q <= "000000000000000000000000";
--leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest(BITJOIN,373)@25
leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b & leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5(REG,627)@25
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest(BITSELECT,369)@25
LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(48 downto 0);
LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in(48 downto 0);
--leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest(BITJOIN,370)@25
leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4(REG,626)@25
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest(BITSELECT,366)@25
LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(56 downto 0);
LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in(56 downto 0);
--leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest(BITJOIN,367)@25
leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3(REG,625)@25
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2(REG,624)@25
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest(BITSELECT,374)@25
leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1(REG,623)@25
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q <= leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest(MUX,375)@26
leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s <= reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q;
leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s, en, reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest(BITSELECT,383)@26
LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(58 downto 0);
LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1009)@26
ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest(CONSTANT,303)
leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q <= "000000";
--leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest(BITJOIN,384)@27
leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q;
--LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest(BITSELECT,380)@26
LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(60 downto 0);
LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1007)@26
ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest(BITJOIN,381)@27
leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest(BITSELECT,377)@26
LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(62 downto 0);
LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in(62 downto 0);
--ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1005)@26
ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest(BITJOIN,378)@27
leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2(REG,629)@26
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest(BITSELECT,385)@25
leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1(REG,628)@25
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q <= leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1011)@26
ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest(MUX,386)@27
leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s <= ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q;
leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s, en, reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest(BITSELECT,390)@25
leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1019)@25
ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest(MUX,391)@27
leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s <= ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q;
leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s, en, leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "0" => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "1" => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--pCos_uid77_fpSinCosXTest(BITSELECT,76)@27
pCos_uid77_fpSinCosXTest_in <= leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q;
pCos_uid77_fpSinCosXTest_b <= pCos_uid77_fpSinCosXTest_in(64 downto 39);
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg(DELAY,1580)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => pCos_uid77_fpSinCosXTest_b, xout => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt(COUNTER,1582)
-- every=1, low=0, high=2, step=1, init=1
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i = 1 THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i - 2;
ELSE
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i,2));
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg(REG,1583)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux(MUX,1584)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s <= en;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux: PROCESS (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s, ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q, ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q)
BEGIN
CASE ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s IS
WHEN "0" => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q;
WHEN "1" => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem(DUALMEM,1581)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 2,
numwords_a => 3,
width_b => 26,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq,
address_a => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa,
data_a => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia
);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0 <= areset;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq(25 downto 0);
--reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0(REG,639)@32
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--mulCos_uid105_fpSinCosXTest(MULT,104)@33
mulCos_uid105_fpSinCosXTest_pr <= UNSIGNED(mulCos_uid105_fpSinCosXTest_a) * UNSIGNED(mulCos_uid105_fpSinCosXTest_b);
mulCos_uid105_fpSinCosXTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulCos_uid105_fpSinCosXTest_a <= (others => '0');
mulCos_uid105_fpSinCosXTest_b <= (others => '0');
mulCos_uid105_fpSinCosXTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulCos_uid105_fpSinCosXTest_a <= reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q;
mulCos_uid105_fpSinCosXTest_b <= reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q;
mulCos_uid105_fpSinCosXTest_s1 <= STD_LOGIC_VECTOR(mulCos_uid105_fpSinCosXTest_pr);
END IF;
END IF;
END PROCESS;
mulCos_uid105_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulCos_uid105_fpSinCosXTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulCos_uid105_fpSinCosXTest_q <= mulCos_uid105_fpSinCosXTest_s1;
END IF;
END IF;
END PROCESS;
--normBitCos_uid106_fpSinCosXTest(BITSELECT,105)@36
normBitCos_uid106_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q;
normBitCos_uid106_fpSinCosXTest_b <= normBitCos_uid106_fpSinCosXTest_in(51 downto 51);
--cosRndOp_uid112_uid113_fpSinCosXTest(BITJOIN,112)@36
cosRndOp_uid112_uid113_fpSinCosXTest_q <= normBitCos_uid106_fpSinCosXTest_b & cstAllZWF_uid7_fpSinCosXTest_q & VCC_q;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor(LOGICAL,1296)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q <= not (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a or ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b);
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top(CONSTANT,1292)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q <= "0110";
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp(LOGICAL,1293)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q <= "1" when ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a = ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b else "0";
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg(REG,1294)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena(REG,1297)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd(LOGICAL,1298)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b <= en;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a and ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b;
--reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1(REG,641)@25
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg(DELAY,1286)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q, xout => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt(COUNTER,1288)
-- every=1, low=0, high=6, step=1, init=1
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i = 5 THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i - 6;
ELSE
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i,3));
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg(REG,1289)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux(MUX,1290)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s <= en;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux: PROCESS (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s, ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q, ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem(DUALMEM,1287)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 7,
width_b => 7,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia
);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq(6 downto 0);
--expHardCase_uid78_fpSinCosXTest(SUB,77)@35
expHardCase_uid78_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expHardCase_uid78_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q);
expHardCase_uid78_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid78_fpSinCosXTest_a) - UNSIGNED(expHardCase_uid78_fpSinCosXTest_b));
expHardCase_uid78_fpSinCosXTest_q <= expHardCase_uid78_fpSinCosXTest_o(8 downto 0);
--expPCos_uid79_fpSinCosXTest(BITSELECT,78)@35
expPCos_uid79_fpSinCosXTest_in <= expHardCase_uid78_fpSinCosXTest_q(7 downto 0);
expPCos_uid79_fpSinCosXTest_b <= expPCos_uid79_fpSinCosXTest_in(7 downto 0);
--reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1(REG,642)@35
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q <= expPCos_uid79_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--fracRCosPreRndHigh_uid108_fpSinCosXTest(BITSELECT,107)@36
fracRCosPreRndHigh_uid108_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q(50 downto 0);
fracRCosPreRndHigh_uid108_fpSinCosXTest_b <= fracRCosPreRndHigh_uid108_fpSinCosXTest_in(50 downto 27);
--fracRCosPreRndLow_uid109_fpSinCosXTest(BITSELECT,108)@36
fracRCosPreRndLow_uid109_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q(49 downto 0);
fracRCosPreRndLow_uid109_fpSinCosXTest_b <= fracRCosPreRndLow_uid109_fpSinCosXTest_in(49 downto 26);
--fracRCosPreRnd_uid110_fpSinCosXTest(MUX,109)@36
fracRCosPreRnd_uid110_fpSinCosXTest_s <= normBitCos_uid106_fpSinCosXTest_b;
fracRCosPreRnd_uid110_fpSinCosXTest: PROCESS (fracRCosPreRnd_uid110_fpSinCosXTest_s, en, fracRCosPreRndLow_uid109_fpSinCosXTest_b, fracRCosPreRndHigh_uid108_fpSinCosXTest_b)
BEGIN
CASE fracRCosPreRnd_uid110_fpSinCosXTest_s IS
WHEN "0" => fracRCosPreRnd_uid110_fpSinCosXTest_q <= fracRCosPreRndLow_uid109_fpSinCosXTest_b;
WHEN "1" => fracRCosPreRnd_uid110_fpSinCosXTest_q <= fracRCosPreRndHigh_uid108_fpSinCosXTest_b;
WHEN OTHERS => fracRCosPreRnd_uid110_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracRCosPreRnd_uid111_uid111_fpSinCosXTest(BITJOIN,110)@36
expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q <= reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q & fracRCosPreRnd_uid110_fpSinCosXTest_q;
--expFracRCos_uid114_fpSinCosXTest(ADD,113)@36
expFracRCos_uid114_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q);
expFracRCos_uid114_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00000000" & cosRndOp_uid112_uid113_fpSinCosXTest_q);
expFracRCos_uid114_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRCos_uid114_fpSinCosXTest_a) + UNSIGNED(expFracRCos_uid114_fpSinCosXTest_b));
expFracRCos_uid114_fpSinCosXTest_q <= expFracRCos_uid114_fpSinCosXTest_o(32 downto 0);
--expRCompSin_uid116_fpSinCosXTest(BITSELECT,115)@36
expRCompSin_uid116_fpSinCosXTest_in <= expFracRCos_uid114_fpSinCosXTest_q(31 downto 0);
expRCompSin_uid116_fpSinCosXTest_b <= expRCompSin_uid116_fpSinCosXTest_in(31 downto 24);
--reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2(REG,646)@36
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q <= expRCompSin_uid116_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor(LOGICAL,1385)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q <= not (ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a or ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top(CONSTANT,1305)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q <= "01101";
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp(LOGICAL,1306)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q <= "1" when ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a = ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b else "0";
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg(REG,1307)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena(REG,1386)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q = "1") THEN
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd(LOGICAL,1387)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b <= en;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a and ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b;
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a(DELAY,745)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c(DELAY,783)@16
ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => cosXIsOneXRR_uid42_fpSinCosXTest_n, xout => ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--InvCosXIsOneXRR_uid136_fpSinCosXTest(LOGICAL,135)@16
InvCosXIsOneXRR_uid136_fpSinCosXTest_a <= cosXIsOneXRR_uid42_fpSinCosXTest_n;
InvCosXIsOneXRR_uid136_fpSinCosXTest_q <= not InvCosXIsOneXRR_uid136_fpSinCosXTest_a;
--ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c(DELAY,773)@16
ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => InvCosXIsOneXRR_uid136_fpSinCosXTest_q, xout => ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a(DELAY,755)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsX_uid127_fpSinCosXTest(LOGICAL,126)@18
InvSinXIsX_uid127_fpSinCosXTest_a <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q;
InvSinXIsX_uid127_fpSinCosXTest_q <= not InvSinXIsX_uid127_fpSinCosXTest_a;
--ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b(DELAY,772)@18
ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => InvSinXIsX_uid127_fpSinCosXTest_q, xout => ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--half_uid53_fpSinCosXTest(BITJOIN,52)@19
half_uid53_fpSinCosXTest_q <= VCC_q & cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
--yIsHalf_uid54_fpSinCosXTest(LOGICAL,53)@19
yIsHalf_uid54_fpSinCosXTest_a <= reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q;
yIsHalf_uid54_fpSinCosXTest_b <= half_uid53_fpSinCosXTest_q;
yIsHalf_uid54_fpSinCosXTest_q <= "1" when yIsHalf_uid54_fpSinCosXTest_a = yIsHalf_uid54_fpSinCosXTest_b else "0";
--yHalfCosXNotOne_uid138_fpSinCosXTest(LOGICAL,137)@19
yHalfCosXNotOne_uid138_fpSinCosXTest_a <= yIsHalf_uid54_fpSinCosXTest_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_b <= ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_c <= ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_q <= yHalfCosXNotOne_uid138_fpSinCosXTest_a and yHalfCosXNotOne_uid138_fpSinCosXTest_b and yHalfCosXNotOne_uid138_fpSinCosXTest_c;
--ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b(DELAY,744)@0
ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => exc_I_uid15_fpSinCosXTest_q, xout => ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a(DELAY,743)@0
ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => exc_N_uid17_fpSinCosXTest_q, xout => ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRNaN_uid117_fpSinCosXTest(LOGICAL,116)@19
excRNaN_uid117_fpSinCosXTest_a <= ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q;
excRNaN_uid117_fpSinCosXTest_b <= ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q;
excRNaN_uid117_fpSinCosXTest_q <= excRNaN_uid117_fpSinCosXTest_a or excRNaN_uid117_fpSinCosXTest_b;
--join_uid143_fpSinCosXTest(BITJOIN,142)@19
join_uid143_fpSinCosXTest_q <= ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q & yHalfCosXNotOne_uid138_fpSinCosXTest_q & excRNaN_uid117_fpSinCosXTest_q;
--expSelBitsCos_uid144_fpSinCosXTest(BITJOIN,143)@19
expSelBitsCos_uid144_fpSinCosXTest_q <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q & join_uid143_fpSinCosXTest_q;
--reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0(REG,645)@19
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q <= expSelBitsCos_uid144_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--expSelectorCos_uid145_fpSinCosXTest(LOOKUP,144)@20
expSelectorCos_uid145_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSelectorCos_uid145_fpSinCosXTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q) IS
WHEN "0000" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "0001" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "0010" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "0011" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "0100" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "0101" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "0110" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "0111" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "1000" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "1001" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "1010" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "1011" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "1100" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "1101" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "1110" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "1111" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN OTHERS =>
expSelectorCos_uid145_fpSinCosXTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg(DELAY,1375)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => expSelectorCos_uid145_fpSinCosXTest_q, xout => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt(COUNTER,1301)
-- every=1, low=0, high=13, step=1, init=1
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i = 12 THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i - 13;
ELSE
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg(REG,1302)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux(MUX,1303)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s, ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q, ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem(DUALMEM,1376)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia
);
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq(1 downto 0);
--expRPostExcCos_uid147_fpSinCosXTest(MUX,146)@37
expRPostExcCos_uid147_fpSinCosXTest_s <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q;
expRPostExcCos_uid147_fpSinCosXTest: PROCESS (expRPostExcCos_uid147_fpSinCosXTest_s, en, reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q, cstBias_uid22_fpSinCosXTest_q, cstAllZWE_uid8_fpSinCosXTest_q, cstAllOWE_uid6_fpSinCosXTest_q)
BEGIN
CASE expRPostExcCos_uid147_fpSinCosXTest_s IS
WHEN "00" => expRPostExcCos_uid147_fpSinCosXTest_q <= reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q;
WHEN "01" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstBias_uid22_fpSinCosXTest_q;
WHEN "10" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstAllZWE_uid8_fpSinCosXTest_q;
WHEN "11" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstAllOWE_uid6_fpSinCosXTest_q;
WHEN OTHERS => expRPostExcCos_uid147_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstNaNwF_uid32_fpSinCosXTest(CONSTANT,31)
cstNaNwF_uid32_fpSinCosXTest_q <= "00000000000000000000001";
--fracRCompCos_uid115_fpSinCosXTest(BITSELECT,114)@36
fracRCompCos_uid115_fpSinCosXTest_in <= expFracRCos_uid114_fpSinCosXTest_q(23 downto 0);
fracRCompCos_uid115_fpSinCosXTest_b <= fracRCompCos_uid115_fpSinCosXTest_in(23 downto 1);
--reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2(REG,644)@36
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q <= fracRCompCos_uid115_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor(LOGICAL,1372)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q <= not (ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a or ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b);
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena(REG,1373)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q = "1") THEN
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd(LOGICAL,1374)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b <= en;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a and ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b;
--reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1(REG,613)@19
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q <= excRNaN_uid117_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3(REG,612)@19
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q <= ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q;
END IF;
END IF;
END PROCESS;
--reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2(REG,611)@19
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q;
END IF;
END IF;
END PROCESS;
--reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1(REG,610)@19
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q <= yHalfCosXNotOne_uid138_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--rZOrOne_uid140_fpSinCosXTest(LOGICAL,139)@20
rZOrOne_uid140_fpSinCosXTest_a <= reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q;
rZOrOne_uid140_fpSinCosXTest_b <= reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q;
rZOrOne_uid140_fpSinCosXTest_c <= reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q;
rZOrOne_uid140_fpSinCosXTest_q <= rZOrOne_uid140_fpSinCosXTest_a or rZOrOne_uid140_fpSinCosXTest_b or rZOrOne_uid140_fpSinCosXTest_c;
--join_uid141_fpSinCosXTest(BITJOIN,140)@20
join_uid141_fpSinCosXTest_q <= reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q & rZOrOne_uid140_fpSinCosXTest_q;
--reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1(REG,643)@20
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q <= join_uid141_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg(DELAY,1362)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q, xout => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem(DUALMEM,1363)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia
);
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq(1 downto 0);
--fracRPostExcCos_uid142_fpSinCosXTest(MUX,141)@37
fracRPostExcCos_uid142_fpSinCosXTest_s <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q;
fracRPostExcCos_uid142_fpSinCosXTest: PROCESS (fracRPostExcCos_uid142_fpSinCosXTest_s, en, reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q, cstAllZWF_uid7_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q)
BEGIN
CASE fracRPostExcCos_uid142_fpSinCosXTest_s IS
WHEN "00" => fracRPostExcCos_uid142_fpSinCosXTest_q <= reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q;
WHEN "01" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstAllZWF_uid7_fpSinCosXTest_q;
WHEN "10" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN "11" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN OTHERS => fracRPostExcCos_uid142_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpCos_uid162_fpSinCosXTest(BITJOIN,161)@37
fpCos_uid162_fpSinCosXTest_q <= ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q & expRPostExcCos_uid147_fpSinCosXTest_q & fracRPostExcCos_uid142_fpSinCosXTest_q;
--cstBiasMwShiftM2_uid25_fpSinCosXTest(CONSTANT,24)
cstBiasMwShiftM2_uid25_fpSinCosXTest_q <= "01110001";
--sinXIsXRR_uid41_fpSinCosXTest(COMPARE,40)@16
sinXIsXRR_uid41_fpSinCosXTest_cin <= GND_q;
sinXIsXRR_uid41_fpSinCosXTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid25_fpSinCosXTest_q) & '0';
sinXIsXRR_uid41_fpSinCosXTest_b <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q) & sinXIsXRR_uid41_fpSinCosXTest_cin(0);
sinXIsXRR_uid41_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(sinXIsXRR_uid41_fpSinCosXTest_a) - SIGNED(sinXIsXRR_uid41_fpSinCosXTest_b));
sinXIsXRR_uid41_fpSinCosXTest_n(0) <= not sinXIsXRR_uid41_fpSinCosXTest_o(11);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a(DELAY,756)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsXRR_uid128_fpSinCosXTest(LOGICAL,127)@18
InvSinXIsXRR_uid128_fpSinCosXTest_a <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q;
InvSinXIsXRR_uid128_fpSinCosXTest_q <= not InvSinXIsXRR_uid128_fpSinCosXTest_a;
--signComp_uid129_fpSinCosXTest(LOGICAL,128)@18
signComp_uid129_fpSinCosXTest_a <= InvSinXIsXRR_uid128_fpSinCosXTest_q;
signComp_uid129_fpSinCosXTest_b <= InvSinXIsX_uid127_fpSinCosXTest_q;
signComp_uid129_fpSinCosXTest_c <= intXParity_uid49_fpSinCosXTest_b;
signComp_uid129_fpSinCosXTest_q <= signComp_uid129_fpSinCosXTest_a and signComp_uid129_fpSinCosXTest_b and signComp_uid129_fpSinCosXTest_c;
--signX_uid37_fpSinCosXTest(BITSELECT,36)@0
signX_uid37_fpSinCosXTest_in <= a;
signX_uid37_fpSinCosXTest_b <= signX_uid37_fpSinCosXTest_in(31 downto 31);
--ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a(DELAY,760)@0
ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => signX_uid37_fpSinCosXTest_b, xout => ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid130_fpSinCosXTest(LOGICAL,129)@18
signR_uid130_fpSinCosXTest_a <= ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q;
signR_uid130_fpSinCosXTest_b <= signComp_uid129_fpSinCosXTest_q;
signR_uid130_fpSinCosXTest_q <= signR_uid130_fpSinCosXTest_a xor signR_uid130_fpSinCosXTest_b;
--ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c(DELAY,766)@18
ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => signR_uid130_fpSinCosXTest_q, xout => ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--signRSinFull_uid133_fpSinCosXTest(LOGICAL,132)@20
signRSinFull_uid133_fpSinCosXTest_a <= InvExc_N_uid132_fpSinCosXTest_q;
signRSinFull_uid133_fpSinCosXTest_b <= InvExc_I_uid131_fpSinCosXTest_q;
signRSinFull_uid133_fpSinCosXTest_c <= ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q;
signRSinFull_uid133_fpSinCosXTest_q_i <= signRSinFull_uid133_fpSinCosXTest_a and signRSinFull_uid133_fpSinCosXTest_b and signRSinFull_uid133_fpSinCosXTest_c;
signRSinFull_uid133_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRSinFull_uid133_fpSinCosXTest_q, xin => signRSinFull_uid133_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c(DELAY,769)@21
ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signRSinFull_uid133_fpSinCosXTest_q, xout => ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor(LOGICAL,1359)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q <= not (ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a or ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b);
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top(CONSTANT,1342)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q <= "0100010";
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp(LOGICAL,1343)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q <= "1" when ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a = ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b else "0";
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg(REG,1344)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena(REG,1360)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q = "1") THEN
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd(LOGICAL,1361)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b <= en;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a and ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg(DELAY,1349)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => exp_uid9_fpSinCosXTest_b, xout => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt(COUNTER,1338)
-- every=1, low=0, high=34, step=1, init=1
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i = 33 THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i - 34;
ELSE
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i,6));
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg(REG,1339)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux(MUX,1340)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem(DUALMEM,1350)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 6,
numwords_a => 35,
width_b => 8,
widthad_b => 6,
numwords_b => 35,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia
);
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a(DELAY,1228)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1(REG,605)@35
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor(LOGICAL,1309)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q <= not (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a or ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena(REG,1310)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd(LOGICAL,1311)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b <= en;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a and ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b;
--oFracXRRSmallXRR_uid90_fpSinCosXTest(BITSELECT,89)@16
oFracXRRSmallXRR_uid90_fpSinCosXTest_in <= oFracXRR_uid43_uid43_fpSinCosXTest_q;
oFracXRRSmallXRR_uid90_fpSinCosXTest_b <= oFracXRRSmallXRR_uid90_fpSinCosXTest_in(53 downto 28);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg(DELAY,1299)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => oFracXRRSmallXRR_uid90_fpSinCosXTest_b, xout => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem(DUALMEM,1300)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 4,
numwords_a => 14,
width_b => 26,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia
);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq(25 downto 0);
--reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1(REG,577)@20
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
END IF;
END IF;
END PROCESS;
--zSin_uid60_fpSinCosXTest(MUX,59)@21
zSin_uid60_fpSinCosXTest_s <= reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q;
zSin_uid60_fpSinCosXTest: PROCESS (zSin_uid60_fpSinCosXTest_s, en, reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q, reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q)
BEGIN
CASE zSin_uid60_fpSinCosXTest_s IS
WHEN "0" => zSin_uid60_fpSinCosXTest_q <= reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q;
WHEN "1" => zSin_uid60_fpSinCosXTest_q <= reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q;
WHEN OTHERS => zSin_uid60_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--addr_uid81_fpSinCosXTest(BITSELECT,80)@21
addr_uid81_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q;
addr_uid81_fpSinCosXTest_b <= addr_uid81_fpSinCosXTest_in(64 downto 57);
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0(REG,595)@21
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q <= addr_uid81_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid398_tableGensinPiZ_lutmem(DUALMEM,529)@22
memoryC2_uid398_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC2_uid398_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC2_uid398_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q;
memoryC2_uid398_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC2_uid398_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid398_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid398_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid398_tableGensinPiZ_lutmem_iq,
address_a => memoryC2_uid398_tableGensinPiZ_lutmem_aa,
data_a => memoryC2_uid398_tableGensinPiZ_lutmem_ia
);
memoryC2_uid398_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC2_uid398_tableGensinPiZ_lutmem_q <= memoryC2_uid398_tableGensinPiZ_lutmem_iq(12 downto 0);
--reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1(REG,597)@24
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q <= memoryC2_uid398_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPsinPiZ_uid84_fpSinCosXTest(BITSELECT,83)@21
zPsinPiZ_uid84_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(56 downto 0);
zPsinPiZ_uid84_fpSinCosXTest_b <= zPsinPiZ_uid84_fpSinCosXTest_in(56 downto 42);
--yT1_uid406_polyEvalsinPiZ(BITSELECT,405)@21
yT1_uid406_polyEvalsinPiZ_in <= zPsinPiZ_uid84_fpSinCosXTest_b;
yT1_uid406_polyEvalsinPiZ_b <= yT1_uid406_polyEvalsinPiZ_in(14 downto 2);
--ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg(DELAY,1540)
ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => yT1_uid406_polyEvalsinPiZ_b, xout => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a(DELAY,1219)@21
ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q, xout => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0(REG,596)@24
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q <= ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid502_pT1_uid407_polyEvalsinPiZ(MULT,501)@25
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a),14)) * SIGNED(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b);
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a <= (others => '0');
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b <= (others => '0');
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a <= reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b <= reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q <= prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ(BITSELECT,502)@28
prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in <= prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q;
prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in(25 downto 12);
--highBBits_uid409_polyEvalsinPiZ(BITSELECT,408)@28
highBBits_uid409_polyEvalsinPiZ_in <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b;
highBBits_uid409_polyEvalsinPiZ_b <= highBBits_uid409_polyEvalsinPiZ_in(13 downto 1);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a(DELAY,1221)@21
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => addr_uid81_fpSinCosXTest_b, xout => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0(REG,598)@24
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid396_tableGensinPiZ_lutmem(DUALMEM,528)@25
memoryC1_uid396_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC1_uid396_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC1_uid396_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q;
memoryC1_uid396_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC1_uid396_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid396_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid396_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid396_tableGensinPiZ_lutmem_iq,
address_a => memoryC1_uid396_tableGensinPiZ_lutmem_aa,
data_a => memoryC1_uid396_tableGensinPiZ_lutmem_ia
);
memoryC1_uid396_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC1_uid396_tableGensinPiZ_lutmem_q <= memoryC1_uid396_tableGensinPiZ_lutmem_iq(20 downto 0);
--reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0(REG,599)@27
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q <= memoryC1_uid396_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid410_polyEvalsinPiZ(ADD,409)@28
sumAHighB_uid410_polyEvalsinPiZ_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q(20)) & reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q);
sumAHighB_uid410_polyEvalsinPiZ_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid409_polyEvalsinPiZ_b(12)) & highBBits_uid409_polyEvalsinPiZ_b);
sumAHighB_uid410_polyEvalsinPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid410_polyEvalsinPiZ_a) + SIGNED(sumAHighB_uid410_polyEvalsinPiZ_b));
sumAHighB_uid410_polyEvalsinPiZ_q <= sumAHighB_uid410_polyEvalsinPiZ_o(21 downto 0);
--lowRangeB_uid408_polyEvalsinPiZ(BITSELECT,407)@28
lowRangeB_uid408_polyEvalsinPiZ_in <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b(0 downto 0);
lowRangeB_uid408_polyEvalsinPiZ_b <= lowRangeB_uid408_polyEvalsinPiZ_in(0 downto 0);
--s1_uid408_uid411_polyEvalsinPiZ(BITJOIN,410)@28
s1_uid408_uid411_polyEvalsinPiZ_q <= sumAHighB_uid410_polyEvalsinPiZ_q & lowRangeB_uid408_polyEvalsinPiZ_b;
--reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1(REG,601)@28
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q <= s1_uid408_uid411_polyEvalsinPiZ_q;
END IF;
END IF;
END PROCESS;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor(LOGICAL,1551)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q <= not (ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a or ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b);
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena(REG,1552)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q = "1") THEN
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd(LOGICAL,1553)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b <= en;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a and ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg(DELAY,1541)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => zPsinPiZ_uid84_fpSinCosXTest_b, xout => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem(DUALMEM,1542)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq,
address_a => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa,
data_a => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia
);
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0 <= areset;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq(14 downto 0);
--reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0(REG,600)@28
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid505_pT2_uid413_polyEvalsinPiZ(MULT,504)@29
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a),16)) * SIGNED(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b);
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a <= (others => '0');
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b <= (others => '0');
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a <= reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b <= reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q <= prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ(BITSELECT,505)@32
prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in <= prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q;
prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in(37 downto 14);
--highBBits_uid415_polyEvalsinPiZ(BITSELECT,414)@32
highBBits_uid415_polyEvalsinPiZ_in <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b;
highBBits_uid415_polyEvalsinPiZ_b <= highBBits_uid415_polyEvalsinPiZ_in(23 downto 2);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor(LOGICAL,1564)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q <= not (ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a or ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena(REG,1565)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q = "1") THEN
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd(LOGICAL,1566)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b <= en;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a and ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b;
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg(DELAY,1554)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addr_uid81_fpSinCosXTest_b, xout => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem(DUALMEM,1555)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq,
address_a => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa,
data_a => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia
);
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0(REG,602)@28
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid394_tableGensinPiZ_lutmem(DUALMEM,527)@29
memoryC0_uid394_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC0_uid394_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC0_uid394_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q;
memoryC0_uid394_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC0_uid394_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid394_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid394_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid394_tableGensinPiZ_lutmem_iq,
address_a => memoryC0_uid394_tableGensinPiZ_lutmem_aa,
data_a => memoryC0_uid394_tableGensinPiZ_lutmem_ia
);
memoryC0_uid394_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC0_uid394_tableGensinPiZ_lutmem_q <= memoryC0_uid394_tableGensinPiZ_lutmem_iq(29 downto 0);
--reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0(REG,603)@31
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q <= memoryC0_uid394_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid416_polyEvalsinPiZ(ADD,415)@32
sumAHighB_uid416_polyEvalsinPiZ_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q(29)) & reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q);
sumAHighB_uid416_polyEvalsinPiZ_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid415_polyEvalsinPiZ_b(21)) & highBBits_uid415_polyEvalsinPiZ_b);
sumAHighB_uid416_polyEvalsinPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid416_polyEvalsinPiZ_a) + SIGNED(sumAHighB_uid416_polyEvalsinPiZ_b));
sumAHighB_uid416_polyEvalsinPiZ_q <= sumAHighB_uid416_polyEvalsinPiZ_o(30 downto 0);
--lowRangeB_uid414_polyEvalsinPiZ(BITSELECT,413)@32
lowRangeB_uid414_polyEvalsinPiZ_in <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b(1 downto 0);
lowRangeB_uid414_polyEvalsinPiZ_b <= lowRangeB_uid414_polyEvalsinPiZ_in(1 downto 0);
--s2_uid414_uid417_polyEvalsinPiZ(BITJOIN,416)@32
s2_uid414_uid417_polyEvalsinPiZ_q <= sumAHighB_uid416_polyEvalsinPiZ_q & lowRangeB_uid414_polyEvalsinPiZ_b;
--polyEvalSigsinPiZ_uid86_fpSinCosXTest(BITSELECT,85)@32
polyEvalSigsinPiZ_uid86_fpSinCosXTest_in <= s2_uid414_uid417_polyEvalsinPiZ_q(30 downto 0);
polyEvalSigsinPiZ_uid86_fpSinCosXTest_b <= polyEvalSigsinPiZ_uid86_fpSinCosXTest_in(30 downto 5);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b(DELAY,708)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--multSinOp2_uid91_fpSinCosXTest(MUX,90)@32
multSinOp2_uid91_fpSinCosXTest_s <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q;
multSinOp2_uid91_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSinOp2_uid91_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE multSinOp2_uid91_fpSinCosXTest_s IS
WHEN "0" => multSinOp2_uid91_fpSinCosXTest_q <= polyEvalSigsinPiZ_uid86_fpSinCosXTest_b;
WHEN "1" => multSinOp2_uid91_fpSinCosXTest_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => multSinOp2_uid91_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor(LOGICAL,1320)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q <= not (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a or ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b);
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena(REG,1321)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd(LOGICAL,1322)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b <= en;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a and ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b;
--cPi_uid71_fpSinCosXTest(CONSTANT,70)
cPi_uid71_fpSinCosXTest_q <= "11001001000011111101101011";
--LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest(BITSELECT,309)@27
LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q(63 downto 0);
LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in(63 downto 0);
--leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest(BITJOIN,310)@27
leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b & GND_q;
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor(LOGICAL,1433)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q <= not (ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a or ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b);
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena(REG,1434)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q = "1") THEN
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd(LOGICAL,1435)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b <= en;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a and ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b;
--X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest(BITSELECT,280)@21
X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(32 downto 0);
X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b <= X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in(32 downto 0);
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg(DELAY,1425)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem(DUALMEM,1426)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 33,
widthad_a => 1,
numwords_a => 2,
width_b => 33,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia
);
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq(32 downto 0);
--leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest(BITJOIN,281)@25
leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor(LOGICAL,1444)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q <= not (ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a or ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b);
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena(REG,1445)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q = "1") THEN
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd(LOGICAL,1446)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b <= en;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a and ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg(DELAY,1436)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => zSin_uid60_fpSinCosXTest_q, xout => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem(DUALMEM,1437)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 65,
widthad_a => 1,
numwords_a => 2,
width_b => 65,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia
);
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq(64 downto 0);
--rVStage_uid237_lzcZSin_uid66_fpSinCosXTest(BITSELECT,236)@21
rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q;
rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in(64 downto 1);
--vCount_uid238_lzcZSin_uid66_fpSinCosXTest(LOGICAL,237)@21
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid236_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g(DELAY,903)@22
ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid240_lzcZSin_uid66_fpSinCosXTest(BITSELECT,239)@21
vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(0 downto 0);
vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in(0 downto 0);
--ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b(DELAY,861)@21
ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cStage_uid241_lzcZSin_uid66_fpSinCosXTest(BITJOIN,240)@22
cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q <= ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q & mO_uid239_lzcZSin_uid66_fpSinCosXTest_q;
--ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c(DELAY,863)@21
ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid243_lzcZSin_uid66_fpSinCosXTest(MUX,242)@22
vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid243_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s, en, ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q, cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid245_lzcZSin_uid66_fpSinCosXTest(BITSELECT,244)@22
rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in(63 downto 32);
--vCount_uid246_lzcZSin_uid66_fpSinCosXTest(LOGICAL,245)@22
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f(DELAY,902)@23
ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid247_lzcZSin_uid66_fpSinCosXTest(BITSELECT,246)@22
vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q(31 downto 0);
vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in(31 downto 0);
--ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d(DELAY,870)@22
ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c(DELAY,869)@22
ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid249_lzcZSin_uid66_fpSinCosXTest(MUX,248)@23
vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid249_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s, en, ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q, ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q)
BEGIN
CASE vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q;
WHEN OTHERS => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid251_lzcZSin_uid66_fpSinCosXTest(BITSELECT,250)@23
rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in(31 downto 16);
--vCount_uid252_lzcZSin_uid66_fpSinCosXTest(LOGICAL,251)@23
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b else "0";
--reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4(REG,585)@23
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q <= vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e(DELAY,901)@24
ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid253_lzcZSin_uid66_fpSinCosXTest(BITSELECT,252)@23
vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q(15 downto 0);
vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in(15 downto 0);
--vStagei_uid255_lzcZSin_uid66_fpSinCosXTest(MUX,254)@23
vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid255_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s, en, rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b, vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b;
WHEN "1" => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid257_lzcZSin_uid66_fpSinCosXTest(BITSELECT,256)@23
rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in(15 downto 8);
--reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1(REG,580)@23
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q <= rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid258_lzcZSin_uid66_fpSinCosXTest(LOGICAL,257)@24
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a <= reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q;
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b else "0";
--ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d(DELAY,900)@24
ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid259_lzcZSin_uid66_fpSinCosXTest(BITSELECT,258)@23
vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q(7 downto 0);
vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3(REG,582)@23
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q <= vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid261_lzcZSin_uid66_fpSinCosXTest(MUX,260)@24
vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid261_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s, en, reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q, reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid263_lzcZSin_uid66_fpSinCosXTest(BITSELECT,262)@24
rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in(7 downto 4);
--vCount_uid264_lzcZSin_uid66_fpSinCosXTest(LOGICAL,263)@24
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid265_lzcZSin_uid66_fpSinCosXTest(BITSELECT,264)@24
vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q(3 downto 0);
vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in(3 downto 0);
--reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3(REG,584)@24
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q <= vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2(REG,583)@24
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid267_lzcZSin_uid66_fpSinCosXTest(MUX,266)@25
vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid267_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s, en, reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q, reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid269_lzcZSin_uid66_fpSinCosXTest(BITSELECT,268)@25
rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in(3 downto 2);
--vCount_uid270_lzcZSin_uid66_fpSinCosXTest(LOGICAL,269)@25
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b else "0";
--vStage_uid271_lzcZSin_uid66_fpSinCosXTest(BITSELECT,270)@25
vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q(1 downto 0);
vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in(1 downto 0);
--vStagei_uid273_lzcZSin_uid66_fpSinCosXTest(MUX,272)@25
vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid273_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s, en, rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b, vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b;
WHEN "1" => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid275_lzcZSin_uid66_fpSinCosXTest(BITSELECT,274)@25
rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in(1 downto 1);
--vCount_uid276_lzcZSin_uid66_fpSinCosXTest(LOGICAL,275)@25
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b <= GND_q;
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b else "0";
--r_uid277_lzcZSin_uid66_fpSinCosXTest(BITJOIN,276)@25
r_uid277_lzcZSin_uid66_fpSinCosXTest_q <= ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q & ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q & ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q & ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q & vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q & vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q & vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q;
--leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest(BITSELECT,284)@25
leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q;
leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in(6 downto 5);
--leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest(MUX,285)@25
leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s <= leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b;
leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s, en, ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest(BITSELECT,293)@25
LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(40 downto 0);
LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in(40 downto 0);
--leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest(BITJOIN,294)@25
leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b & leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5(REG,590)@25
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest(BITSELECT,290)@25
LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(48 downto 0);
LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in(48 downto 0);
--leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest(BITJOIN,291)@25
leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4(REG,589)@25
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest(BITSELECT,287)@25
LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(56 downto 0);
LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in(56 downto 0);
--leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest(BITJOIN,288)@25
leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3(REG,588)@25
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2(REG,587)@25
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest(BITSELECT,295)@25
leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1(REG,586)@25
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q <= leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest(MUX,296)@26
leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s <= reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q;
leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s, en, reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest(BITSELECT,304)@26
LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(58 downto 0);
LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b(DELAY,927)@26
ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest(BITJOIN,305)@27
leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q;
--LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest(BITSELECT,301)@26
LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(60 downto 0);
LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b(DELAY,925)@26
ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest(BITJOIN,302)@27
leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest(BITSELECT,298)@26
LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(62 downto 0);
LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in(62 downto 0);
--ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b(DELAY,923)@26
ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest(BITJOIN,299)@27
leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2(REG,592)@26
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest(BITSELECT,306)@25
leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in(2 downto 1);
--ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a(DELAY,1214)@25
ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1(REG,591)@26
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q <= ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest(MUX,307)@27
leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s <= reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q;
leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s, en, reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest(BITSELECT,311)@25
leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b(DELAY,937)@25
ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest(MUX,312)@27
leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s <= ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q;
leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s, en, leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "0" => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "1" => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--pHigh_uid72_fpSinCosXTest(BITSELECT,71)@27
pHigh_uid72_fpSinCosXTest_in <= leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q;
pHigh_uid72_fpSinCosXTest_b <= pHigh_uid72_fpSinCosXTest_in(64 downto 39);
--reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2(REG,594)@27
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q <= pHigh_uid72_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a(DELAY,1216)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1(REG,593)@27
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--p_uid73_fpSinCosXTest(MUX,72)@28
p_uid73_fpSinCosXTest_s <= reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q;
p_uid73_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p_uid73_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE p_uid73_fpSinCosXTest_s IS
WHEN "0" => p_uid73_fpSinCosXTest_q <= reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q;
WHEN "1" => p_uid73_fpSinCosXTest_q <= cPi_uid71_fpSinCosXTest_q;
WHEN OTHERS => p_uid73_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg(DELAY,1312)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => p_uid73_fpSinCosXTest_q, xout => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem(DUALMEM,1313)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 1,
numwords_a => 2,
width_b => 26,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq,
address_a => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa,
data_a => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia
);
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0 <= areset;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq(25 downto 0);
--mulSin_uid92_fpSinCosXTest(MULT,91)@33
mulSin_uid92_fpSinCosXTest_pr <= UNSIGNED(mulSin_uid92_fpSinCosXTest_a) * UNSIGNED(mulSin_uid92_fpSinCosXTest_b);
mulSin_uid92_fpSinCosXTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulSin_uid92_fpSinCosXTest_a <= (others => '0');
mulSin_uid92_fpSinCosXTest_b <= (others => '0');
mulSin_uid92_fpSinCosXTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulSin_uid92_fpSinCosXTest_a <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q;
mulSin_uid92_fpSinCosXTest_b <= multSinOp2_uid91_fpSinCosXTest_q;
mulSin_uid92_fpSinCosXTest_s1 <= STD_LOGIC_VECTOR(mulSin_uid92_fpSinCosXTest_pr);
END IF;
END IF;
END PROCESS;
mulSin_uid92_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulSin_uid92_fpSinCosXTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulSin_uid92_fpSinCosXTest_q <= mulSin_uid92_fpSinCosXTest_s1;
END IF;
END IF;
END PROCESS;
--normBitSin_uid93_fpSinCosXTest(BITSELECT,92)@36
normBitSin_uid93_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q;
normBitSin_uid93_fpSinCosXTest_b <= normBitSin_uid93_fpSinCosXTest_in(51 downto 51);
--join_uid99_fpSinCosXTest(BITJOIN,98)@36
join_uid99_fpSinCosXTest_q <= reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q & normBitSin_uid93_fpSinCosXTest_b;
--sinRndOp_uid100_uid101_fpSinCosXTest(BITJOIN,100)@36
sinRndOp_uid100_uid101_fpSinCosXTest_q <= join_uid99_fpSinCosXTest_q & cstAllZWF_uid7_fpSinCosXTest_q & VCC_q;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor(LOGICAL,1333)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q <= not (ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a or ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b);
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena(REG,1334)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q = "1") THEN
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd(LOGICAL,1335)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b <= en;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a and ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor(LOGICAL,1283)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q <= not (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a or ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b);
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena(REG,1284)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd(LOGICAL,1285)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a and ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg(DELAY,1273)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expXRR_uid38_fpSinCosXTest_b, xout => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem(DUALMEM,1274)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 9,
width_b => 8,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia
);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1(REG,604)@25
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--expSinHC_uid74_fpSinCosXTest(SUB,73)@26
expSinHC_uid74_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expSinHC_uid74_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q);
expSinHC_uid74_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSinHC_uid74_fpSinCosXTest_a) - UNSIGNED(expSinHC_uid74_fpSinCosXTest_b));
expSinHC_uid74_fpSinCosXTest_q <= expSinHC_uid74_fpSinCosXTest_o(8 downto 0);
--expSinHCR_uid75_fpSinCosXTest(BITSELECT,74)@26
expSinHCR_uid75_fpSinCosXTest_in <= expSinHC_uid74_fpSinCosXTest_q(7 downto 0);
expSinHCR_uid75_fpSinCosXTest_b <= expSinHCR_uid75_fpSinCosXTest_in(7 downto 0);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b(DELAY,695)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expPSin_uid76_fpSinCosXTest(MUX,75)@26
expPSin_uid76_fpSinCosXTest_s <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q;
expPSin_uid76_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expPSin_uid76_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expPSin_uid76_fpSinCosXTest_s IS
WHEN "0" => expPSin_uid76_fpSinCosXTest_q <= expSinHCR_uid75_fpSinCosXTest_b;
WHEN "1" => expPSin_uid76_fpSinCosXTest_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => expPSin_uid76_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg(DELAY,1323)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expPSin_uid76_fpSinCosXTest_q, xout => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem(DUALMEM,1324)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 7,
width_b => 8,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia
);
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq(7 downto 0);
--fracRSinPreRndHigh_uid95_fpSinCosXTest(BITSELECT,94)@36
fracRSinPreRndHigh_uid95_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q(50 downto 0);
fracRSinPreRndHigh_uid95_fpSinCosXTest_b <= fracRSinPreRndHigh_uid95_fpSinCosXTest_in(50 downto 27);
--fracRSinPreRndLow_uid96_fpSinCosXTest(BITSELECT,95)@36
fracRSinPreRndLow_uid96_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q(49 downto 0);
fracRSinPreRndLow_uid96_fpSinCosXTest_b <= fracRSinPreRndLow_uid96_fpSinCosXTest_in(49 downto 26);
--fracRSinPreRnd_uid97_fpSinCosXTest(MUX,96)@36
fracRSinPreRnd_uid97_fpSinCosXTest_s <= normBitSin_uid93_fpSinCosXTest_b;
fracRSinPreRnd_uid97_fpSinCosXTest: PROCESS (fracRSinPreRnd_uid97_fpSinCosXTest_s, en, fracRSinPreRndLow_uid96_fpSinCosXTest_b, fracRSinPreRndHigh_uid95_fpSinCosXTest_b)
BEGIN
CASE fracRSinPreRnd_uid97_fpSinCosXTest_s IS
WHEN "0" => fracRSinPreRnd_uid97_fpSinCosXTest_q <= fracRSinPreRndLow_uid96_fpSinCosXTest_b;
WHEN "1" => fracRSinPreRnd_uid97_fpSinCosXTest_q <= fracRSinPreRndHigh_uid95_fpSinCosXTest_b;
WHEN OTHERS => fracRSinPreRnd_uid97_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracRSinPreRnd_uid98_uid98_fpSinCosXTest(BITJOIN,97)@36
expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q & fracRSinPreRnd_uid97_fpSinCosXTest_q;
--expFracRSin_uid102_fpSinCosXTest(ADD,101)@36
expFracRSin_uid102_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q);
expFracRSin_uid102_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0000000" & sinRndOp_uid100_uid101_fpSinCosXTest_q);
expFracRSin_uid102_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRSin_uid102_fpSinCosXTest_a) + UNSIGNED(expFracRSin_uid102_fpSinCosXTest_b));
expFracRSin_uid102_fpSinCosXTest_q <= expFracRSin_uid102_fpSinCosXTest_o(32 downto 0);
--expRCompSin_uid104_fpSinCosXTest(BITSELECT,103)@36
expRCompSin_uid104_fpSinCosXTest_in <= expFracRSin_uid102_fpSinCosXTest_q(31 downto 0);
expRCompSin_uid104_fpSinCosXTest_b <= expRCompSin_uid104_fpSinCosXTest_in(31 downto 24);
--reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2(REG,607)@36
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q <= expRCompSin_uid104_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor(LOGICAL,1537)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q <= not (ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a or ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b);
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena(REG,1538)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q = "1") THEN
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd(LOGICAL,1539)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b <= en;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a and ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b;
--expXIsZero_uid10_fpSinCosXTest(LOGICAL,9)@0
expXIsZero_uid10_fpSinCosXTest_a <= exp_uid9_fpSinCosXTest_b;
expXIsZero_uid10_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
expXIsZero_uid10_fpSinCosXTest_q <= "1" when expXIsZero_uid10_fpSinCosXTest_a = expXIsZero_uid10_fpSinCosXTest_b else "0";
--ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b(DELAY,746)@0
ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => expXIsZero_uid10_fpSinCosXTest_q, xout => ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excSelBitsSin_uid118_fpSinCosXTest(BITJOIN,117)@19
excSelBitsSin_uid118_fpSinCosXTest_q <= excRNaN_uid117_fpSinCosXTest_q & ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q & ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg(DELAY,1527)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => excSelBitsSin_uid118_fpSinCosXTest_q, xout => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem(DUALMEM,1528)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 4,
numwords_a => 14,
width_b => 3,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq,
address_a => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa,
data_a => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia
);
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0 <= areset;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq(2 downto 0);
--reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0(REG,533)@35
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--excSelSin_uid119_fpSinCosXTest(LOOKUP,118)@36
excSelSin_uid119_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excSelSin_uid119_fpSinCosXTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q) IS
WHEN "000" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN "001" => excSelSin_uid119_fpSinCosXTest_q <= "01";
WHEN "010" => excSelSin_uid119_fpSinCosXTest_q <= "10";
WHEN "011" => excSelSin_uid119_fpSinCosXTest_q <= "10";
WHEN "100" => excSelSin_uid119_fpSinCosXTest_q <= "11";
WHEN "101" => excSelSin_uid119_fpSinCosXTest_q <= "11";
WHEN "110" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN "111" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN OTHERS =>
excSelSin_uid119_fpSinCosXTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRPostExcSin_uid126_fpSinCosXTest(MUX,125)@37
expRPostExcSin_uid126_fpSinCosXTest_s <= excSelSin_uid119_fpSinCosXTest_q;
expRPostExcSin_uid126_fpSinCosXTest: PROCESS (expRPostExcSin_uid126_fpSinCosXTest_s, en, reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q, ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q, cstAllZWE_uid8_fpSinCosXTest_q, cstAllOWE_uid6_fpSinCosXTest_q)
BEGIN
CASE expRPostExcSin_uid126_fpSinCosXTest_s IS
WHEN "00" => expRPostExcSin_uid126_fpSinCosXTest_q <= reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q;
WHEN "01" => expRPostExcSin_uid126_fpSinCosXTest_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q;
WHEN "10" => expRPostExcSin_uid126_fpSinCosXTest_q <= cstAllZWE_uid8_fpSinCosXTest_q;
WHEN "11" => expRPostExcSin_uid126_fpSinCosXTest_q <= cstAllOWE_uid6_fpSinCosXTest_q;
WHEN OTHERS => expRPostExcSin_uid126_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor(LOGICAL,1346)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q <= not (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a or ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b);
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena(REG,1347)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd(LOGICAL,1348)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b <= en;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a and ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg(DELAY,1336)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => frac_uid13_fpSinCosXTest_b, xout => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem(DUALMEM,1337)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 6,
numwords_a => 35,
width_b => 23,
widthad_b => 6,
numwords_b => 35,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia
);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq(22 downto 0);
--fracRCompSin_uid103_fpSinCosXTest(BITSELECT,102)@36
fracRCompSin_uid103_fpSinCosXTest_in <= expFracRSin_uid102_fpSinCosXTest_q(23 downto 0);
fracRCompSin_uid103_fpSinCosXTest_b <= fracRCompSin_uid103_fpSinCosXTest_in(23 downto 1);
--reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2(REG,606)@36
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q <= fracRCompSin_uid103_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--fracRPostExcSin_uid122_fpSinCosXTest(MUX,121)@37
fracRPostExcSin_uid122_fpSinCosXTest_s <= excSelSin_uid119_fpSinCosXTest_q;
fracRPostExcSin_uid122_fpSinCosXTest: PROCESS (fracRPostExcSin_uid122_fpSinCosXTest_s, en, reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q, cstAllZWF_uid7_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q)
BEGIN
CASE fracRPostExcSin_uid122_fpSinCosXTest_s IS
WHEN "00" => fracRPostExcSin_uid122_fpSinCosXTest_q <= reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q;
WHEN "01" => fracRPostExcSin_uid122_fpSinCosXTest_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q;
WHEN "10" => fracRPostExcSin_uid122_fpSinCosXTest_q <= cstAllZWF_uid7_fpSinCosXTest_q;
WHEN "11" => fracRPostExcSin_uid122_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN OTHERS => fracRPostExcSin_uid122_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpSin_uid134_fpSinCosXTest(BITJOIN,133)@37
fpSin_uid134_fpSinCosXTest_q <= ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q & expRPostExcSin_uid126_fpSinCosXTest_q & fracRPostExcSin_uid122_fpSinCosXTest_q;
--xOut(GPOUT,4)@37
s <= fpSin_uid134_fpSinCosXTest_q;
c <= fpCos_uid162_fpSinCosXTest_q;
end normal;
|
-- $Id: sys_tst_rlink_cuff_n2.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2012-2013 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_rlink_cuff_n2 - syn
-- Description: rlink tester design for nexys2 with fx2 interface
--
-- Dependencies: vlib/xlib/dcm_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio_rbus
-- bplib/fx2lib/fx2_2fifoctl_as [sys_conf_fx2_type="as2"]
-- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"]
-- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"]
-- tst_rlink_cuff
-- bplib/nxcramlib/nx_cram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.3; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz
-- 2013-01-04 469 13.3 O76d xc3s1200e-4 846 1798 160 1215 p 16.3 ic2/ 50
-- 2012-12-29 466 13.3 O76d xc3s1200e-4 808 1739 160 1172 p 16.3 as2/ 50
-- 2013-01-02 467 13.3 O76d xc3s1200e-4 843 1792 160 1209 p 15.2 ic2/ 50
-- 2012-12-29 466 13.3 O76d xc3s1200e-4 863 1850 192 1266 p 13.6 ic3/ 50
--
-- Revision History:
-- Date Rev Version Comment
-- 2012-12-29 466 1.0 Initial version; derived from sys_tst_fx2loop_n2
-- the now obsoleted sys_tst_rlink_n2_cuff design
------------------------------------------------------------------------------
-- Usage of Nexys 2 Switches, Buttons, LEDs:
--
-- SWI(7:3) no function (only connected to sn_humanio_rbus)
-- (2) 0 -> int/ext RS242 port for rlink
-- 1 -> use USB interface for rlink
-- (1) 1 enable XON
-- (0) 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob
-- 1 -> Pmod B/top RS232 port /
--
-- LED(7) SER_MONI.abact
-- (6:2) no function (only connected to sn_humanio_rbus)
-- (0) timer 0 busy
-- (1) timer 1 busy
--
-- DSP: SER_MONI.clkdiv (from auto bauder)
-- for SWI(2)='0' (serport)
-- DP(3) not SER_MONI.txok (shows tx back preasure)
-- (2) SER_MONI.txact (shows tx activity)
-- (1) not SER_MONI.rxok (shows rx back preasure)
-- (0) SER_MONI.rxact (shows rx activity)
-- for SWI(2)='1' (fx2)
-- DP(3) FX2_TX2BUSY (shows tx2 back preasure)
-- (2) FX2_TX2ENA(stretched) (shows tx2 activity)
-- (1) FX2_TXENA(streched) (shows tx activity)
-- (0) FX2_RXVAL(stretched) (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.rblib.all;
use work.fx2lib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_rlink_cuff_n2 is -- top level
-- implements nexys2_fusp_cuff_aif
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit; -- fusp: rs232 tx
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end sys_tst_rlink_cuff_n2;
architecture syn of sys_tst_rlink_cuff_n2 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RXSD : slbit := '0';
signal TXSD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal FX2_RXDATA : slv8 := (others=>'0');
signal FX2_RXVAL : slbit := '0';
signal FX2_RXHOLD : slbit := '0';
signal FX2_RXAEMPTY : slbit := '0';
signal FX2_TXDATA : slv8 := (others=>'0');
signal FX2_TXENA : slbit := '0';
signal FX2_TXBUSY : slbit := '0';
signal FX2_TXAFULL : slbit := '0';
signal FX2_TX2DATA : slv8 := (others=>'0');
signal FX2_TX2ENA : slbit := '0';
signal FX2_TX2BUSY : slbit := '0';
signal FX2_TX2AFULL : slbit := '0';
signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
constant rbaddr_hio : slv8 := "11000000"; -- 110000xx
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
DCM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => I_CLK50,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7, -- good for up to 127 MHz !
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0),
RXD => RXSD,
TXD => TXSD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
HIO : sn_humanio_rbus
generic map (
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
FX2_CNTL_AS : if sys_conf_fx2_type = "as2" generate
CNTL : fx2_2fifoctl_as
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1,
PETOWIDTH => sys_conf_fx2_petowidth,
RDPWLDELAY => sys_conf_fx2_rdpwldelay,
RDPWHDELAY => sys_conf_fx2_rdpwhdelay,
WRPWLDELAY => sys_conf_fx2_wrpwldelay,
WRPWHDELAY => sys_conf_fx2_wrpwhdelay,
FLAGDELAY => sys_conf_fx2_flagdelay)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_AS;
FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate
CNTL : fx2_2fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_IC;
FX2_CNTL_IC3 : if sys_conf_fx2_type = "ic3" generate
CNTL : fx2_3fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1,
TX2AFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
TX2DATA => FX2_TX2DATA,
TX2ENA => FX2_TX2ENA,
TX2BUSY => FX2_TX2BUSY,
TX2AFULL => FX2_TX2AFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_IC3;
TST : entity work.tst_rlink_cuff
port map (
CLK => CLK,
RESET => '0',
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RB_MREQ_TOP => RB_MREQ,
RB_SRES_TOP => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
RXSD => RXSD,
TXSD => TXSD,
RTS_N => RTS_N,
CTS_N => CTS_N,
FX2_RXDATA => FX2_RXDATA,
FX2_RXVAL => FX2_RXVAL,
FX2_RXHOLD => FX2_RXHOLD,
FX2_TXDATA => FX2_TXDATA,
FX2_TXENA => FX2_TXENA,
FX2_TXBUSY => FX2_TXBUSY,
FX2_TX2DATA => FX2_TX2DATA,
FX2_TX2ENA => FX2_TX2ENA,
FX2_TX2BUSY => FX2_TX2BUSY,
FX2_MONI => FX2_MONI
);
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
end syn;
|
-- file: Clock8346_clk_wiz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___108.000______0.000______50.0______221.150____300.991
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity Clock8346_clk_wiz is
port
(-- Clock in ports
clk_in1 : in std_logic;
-- Clock out ports
clk_out1 : out std_logic;
-- Status and control signals
locked : out std_logic
);
end Clock8346_clk_wiz;
architecture xilinx of Clock8346_clk_wiz is
-- Input clock buffering / unused connectors
signal clk_in1_Clock8346 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout_Clock8346 : std_logic;
signal clkfbout_buf_Clock8346 : std_logic;
signal clkfboutb_unused : std_logic;
signal clk_out1_Clock8346 : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1_unused : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
signal locked_int : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_ibufg : IBUF
port map
(O => clk_in1_Clock8346,
I => clk_in1);
-- Clocking PRIMITIVE
--------------------------------------
-- Instantiation of the MMCM PRIMITIVE
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
plle2_adv_inst : PLLE2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
COMPENSATION => "BUF_IN",
DIVCLK_DIVIDE => 5,
CLKFBOUT_MULT => 54,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 10,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN1_PERIOD => 10.0)
port map
-- Output clocks
(
CLKFBOUT => clkfbout_Clock8346,
CLKOUT0 => clk_out1_Clock8346,
CLKOUT1 => clkout1_unused,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
-- Input clock control
CLKFBIN => clkfbout_buf_Clock8346,
CLKIN1 => clk_in1_Clock8346,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Other control and status signals
LOCKED => locked_int,
PWRDWN => '0',
RST => '0');
locked <= locked_int;
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf_Clock8346,
I => clkfbout_Clock8346);
clkout1_buf : BUFG
port map
(O => clk_out1,
I => clk_out1_Clock8346);
end xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity gcr_encoder is
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp );
end gcr_encoder;
architecture regmap of gcr_encoder is
signal shift_reg : std_logic_vector(0 to 31);
signal encoded : std_logic_vector(0 to 39);
begin
process(clock)
begin
if rising_edge(clock) then
resp <= c_io_resp_init;
if req.write='1' then
resp.ack <= '1';
shift_reg <= shift_reg(8 to 31) & req.data;
elsif req.read='1' then
resp.ack <= '1';
case req.address(3 downto 0) is
when X"0" =>
resp.data <= encoded(0 to 7);
when X"1" =>
resp.data <= encoded(8 to 15);
when X"2" =>
resp.data <= encoded(16 to 23);
when X"3" =>
resp.data <= encoded(24 to 31);
when others =>
resp.data <= encoded(32 to 39);
end case;
end if;
if reset='1' then
shift_reg <= X"00000000";
end if;
end if;
end process;
r_encoders: for i in 0 to 7 generate
i_bin2gcr: entity work.bin2gcr
port map (
d_in => shift_reg(4*i to 3+4*i),
d_out => encoded(5*i to 4+5*i) );
end generate;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity gcr_encoder is
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp );
end gcr_encoder;
architecture regmap of gcr_encoder is
signal shift_reg : std_logic_vector(0 to 31);
signal encoded : std_logic_vector(0 to 39);
begin
process(clock)
begin
if rising_edge(clock) then
resp <= c_io_resp_init;
if req.write='1' then
resp.ack <= '1';
shift_reg <= shift_reg(8 to 31) & req.data;
elsif req.read='1' then
resp.ack <= '1';
case req.address(3 downto 0) is
when X"0" =>
resp.data <= encoded(0 to 7);
when X"1" =>
resp.data <= encoded(8 to 15);
when X"2" =>
resp.data <= encoded(16 to 23);
when X"3" =>
resp.data <= encoded(24 to 31);
when others =>
resp.data <= encoded(32 to 39);
end case;
end if;
if reset='1' then
shift_reg <= X"00000000";
end if;
end if;
end process;
r_encoders: for i in 0 to 7 generate
i_bin2gcr: entity work.bin2gcr
port map (
d_in => shift_reg(4*i to 3+4*i),
d_out => encoded(5*i to 4+5*i) );
end generate;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity gcr_encoder is
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp );
end gcr_encoder;
architecture regmap of gcr_encoder is
signal shift_reg : std_logic_vector(0 to 31);
signal encoded : std_logic_vector(0 to 39);
begin
process(clock)
begin
if rising_edge(clock) then
resp <= c_io_resp_init;
if req.write='1' then
resp.ack <= '1';
shift_reg <= shift_reg(8 to 31) & req.data;
elsif req.read='1' then
resp.ack <= '1';
case req.address(3 downto 0) is
when X"0" =>
resp.data <= encoded(0 to 7);
when X"1" =>
resp.data <= encoded(8 to 15);
when X"2" =>
resp.data <= encoded(16 to 23);
when X"3" =>
resp.data <= encoded(24 to 31);
when others =>
resp.data <= encoded(32 to 39);
end case;
end if;
if reset='1' then
shift_reg <= X"00000000";
end if;
end if;
end process;
r_encoders: for i in 0 to 7 generate
i_bin2gcr: entity work.bin2gcr
port map (
d_in => shift_reg(4*i to 3+4*i),
d_out => encoded(5*i to 4+5*i) );
end generate;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity gcr_encoder is
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp );
end gcr_encoder;
architecture regmap of gcr_encoder is
signal shift_reg : std_logic_vector(0 to 31);
signal encoded : std_logic_vector(0 to 39);
begin
process(clock)
begin
if rising_edge(clock) then
resp <= c_io_resp_init;
if req.write='1' then
resp.ack <= '1';
shift_reg <= shift_reg(8 to 31) & req.data;
elsif req.read='1' then
resp.ack <= '1';
case req.address(3 downto 0) is
when X"0" =>
resp.data <= encoded(0 to 7);
when X"1" =>
resp.data <= encoded(8 to 15);
when X"2" =>
resp.data <= encoded(16 to 23);
when X"3" =>
resp.data <= encoded(24 to 31);
when others =>
resp.data <= encoded(32 to 39);
end case;
end if;
if reset='1' then
shift_reg <= X"00000000";
end if;
end if;
end process;
r_encoders: for i in 0 to 7 generate
i_bin2gcr: entity work.bin2gcr
port map (
d_in => shift_reg(4*i to 3+4*i),
d_out => encoded(5*i to 4+5*i) );
end generate;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity gcr_encoder is
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp );
end gcr_encoder;
architecture regmap of gcr_encoder is
signal shift_reg : std_logic_vector(0 to 31);
signal encoded : std_logic_vector(0 to 39);
begin
process(clock)
begin
if rising_edge(clock) then
resp <= c_io_resp_init;
if req.write='1' then
resp.ack <= '1';
shift_reg <= shift_reg(8 to 31) & req.data;
elsif req.read='1' then
resp.ack <= '1';
case req.address(3 downto 0) is
when X"0" =>
resp.data <= encoded(0 to 7);
when X"1" =>
resp.data <= encoded(8 to 15);
when X"2" =>
resp.data <= encoded(16 to 23);
when X"3" =>
resp.data <= encoded(24 to 31);
when others =>
resp.data <= encoded(32 to 39);
end case;
end if;
if reset='1' then
shift_reg <= X"00000000";
end if;
end if;
end process;
r_encoders: for i in 0 to 7 generate
i_bin2gcr: entity work.bin2gcr
port map (
d_in => shift_reg(4*i to 3+4*i),
d_out => encoded(5*i to 4+5*i) );
end generate;
end;
|
library verilog;
use verilog.vl_types.all;
entity reservation_alu1_entry is
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iREMOVE_VALID : in vl_logic;
iREGISTER_VALID : in vl_logic;
oINFO_REGIST_LOCK: out vl_logic;
iREGISTER_DESTINATION_SYSREG: in vl_logic;
iREGISTER_WRITEBACK: in vl_logic;
iREGISTER_CMD : in vl_logic_vector(4 downto 0);
iREGISTER_AFE : in vl_logic_vector(3 downto 0);
iREGISTER_SYS_REG: in vl_logic;
iREGISTER_LOGIC : in vl_logic;
iREGISTER_SHIFT : in vl_logic;
iREGISTER_ADDER : in vl_logic;
iREGISTER_MUL : in vl_logic;
iREGISTER_SDIV : in vl_logic;
iREGISTER_UDIV : in vl_logic;
iREGISTER_FLAGS_OPT_VALID: in vl_logic;
iREGISTER_FLAGS_REGNAME: in vl_logic_vector(3 downto 0);
iREGISTER_SOURCE0_VALID: in vl_logic;
iREGISTER_SOURCE0: in vl_logic_vector(31 downto 0);
iREGISTER_SOURCE1_VALID: in vl_logic;
iREGISTER_SOURCE1: in vl_logic_vector(31 downto 0);
iREGISTER_PCR : in vl_logic_vector(31 downto 0);
iREGISTER_LOGIC_DEST: in vl_logic_vector(4 downto 0);
iREGISTER_DESTINATION_REGNAME: in vl_logic_vector(5 downto 0);
iREGISTER_COMMIT_TAG: in vl_logic_vector(5 downto 0);
iALU1_VALID : in vl_logic;
iALU1_DESTINATION_REGNAME: in vl_logic_vector(5 downto 0);
iALU1_WRITEBACK : in vl_logic;
iALU1_DATA : in vl_logic_vector(31 downto 0);
iALU2_VALID : in vl_logic;
iALU2_DESTINATION_REGNAME: in vl_logic_vector(5 downto 0);
iALU2_WRITEBACK : in vl_logic;
iALU2_DATA : in vl_logic_vector(31 downto 0);
iALU3_VALID : in vl_logic;
iALU3_DESTINATION_REGNAME: in vl_logic_vector(5 downto 0);
iALU3_DATA : in vl_logic_vector(31 downto 0);
iEXOUT_VALID : in vl_logic;
oINFO_ENTRY_VALID: out vl_logic;
oINFO_MATCHING : out vl_logic;
oINFO_DESTINATION_SYSREG: out vl_logic;
oINFO_WRITEBACK : out vl_logic;
oINFO_CMD : out vl_logic_vector(4 downto 0);
oINFO_AFE : out vl_logic_vector(3 downto 0);
oINFO_SYS_REG : out vl_logic;
oINFO_LOGIC : out vl_logic;
oINFO_SHIFT : out vl_logic;
oINFO_ADDER : out vl_logic;
oINFO_MUL : out vl_logic;
oINFO_SDIV : out vl_logic;
oINFO_UDIV : out vl_logic;
oINFO_FLAGS_OPT_VALID: out vl_logic;
oINFO_FLAGS_REGNAME: out vl_logic_vector(3 downto 0);
oINFO_SOURCE0_VALID: out vl_logic;
oINFO_SOURCE0 : out vl_logic_vector(31 downto 0);
oINFO_SOURCE1_VALID: out vl_logic;
oINFO_SOURCE1 : out vl_logic_vector(31 downto 0);
oINFO_PCR : out vl_logic_vector(31 downto 0);
oINFO_LOGIC_DEST: out vl_logic_vector(4 downto 0);
oINFO_DESTINATION_REGNAME: out vl_logic_vector(5 downto 0);
oINFO_COMMIT_TAG: out vl_logic_vector(5 downto 0)
);
end reservation_alu1_entry;
|
-------------------------------------------------------------------------------
--
-- Title : plb_master_handler
-- Design : POWERLINK
--
-------------------------------------------------------------------------------
--
-- File : c:\my_designs\POWERLINK\src\plb_master_handler.vhd
-- Generated : Mon Nov 7 13:17:30 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- 2011-08-03 V0.01 zelenkaj First version
-- 2011-12-01 V0.02 zelenkaj Fixed read transfer error (dst_rdy_n earlier)
-- 2011-12-05 V0.03 zelenkaj Avoid preset of FFs
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity plb_master_handler is
generic(
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
dma_highadr_g : integer := 31;
C_MAC_DMA_PLB_NATIVE_DWIDTH : integer := 32;
C_MAC_DMA_PLB_AWIDTH : integer := 32;
m_burstcount_width_g : integer := 4
);
port(
MAC_DMA_CLK : in std_logic;
MAC_DMA_Rst : in std_logic;
Bus2MAC_DMA_Mst_CmdAck : in std_logic := '0';
Bus2MAC_DMA_Mst_Cmplt : in std_logic := '0';
Bus2MAC_DMA_Mst_Error : in std_logic := '0';
Bus2MAC_DMA_Mst_Rearbitrate : in std_logic := '0';
Bus2MAC_DMA_Mst_Cmd_Timeout : in std_logic := '0';
Bus2MAC_DMA_MstRd_d : in std_logic_vector(C_MAC_DMA_PLB_NATIVE_DWIDTH-1 downto 0);
Bus2MAC_DMA_MstRd_rem : in std_logic_vector(C_MAC_DMA_PLB_NATIVE_DWIDTH/8-1 downto 0);
Bus2MAC_DMA_MstRd_sof_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_eof_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_src_rdy_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_src_dsc_n : in std_logic := '1';
Bus2MAC_DMA_MstWr_dst_rdy_n : in std_logic := '1';
Bus2MAC_DMA_MstWr_dst_dsc_n : in std_logic := '1';
MAC_DMA2Bus_MstRd_Req : out std_logic := '0';
MAC_DMA2Bus_MstWr_Req : out std_logic := '0';
MAC_DMA2Bus_Mst_Type : out std_logic := '0';
MAC_DMA2Bus_Mst_Addr : out std_logic_vector(C_MAC_DMA_PLB_AWIDTH-1 downto 0);
MAC_DMA2Bus_Mst_Length : out std_logic_vector(11 downto 0);
MAC_DMA2Bus_Mst_BE : out std_logic_vector(C_MAC_DMA_PLB_NATIVE_DWIDTH/8-1 downto 0);
MAC_DMA2Bus_Mst_Lock : out std_logic := '0';
MAC_DMA2Bus_Mst_Reset : out std_logic := '0';
MAC_DMA2Bus_MstRd_dst_rdy_n : out std_logic := '1';
MAC_DMA2Bus_MstRd_dst_dsc_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_d : out std_logic_vector(C_MAC_DMA_PLB_NATIVE_DWIDTH-1 downto 0);
MAC_DMA2Bus_MstWr_rem : out std_logic_vector(C_MAC_DMA_PLB_NATIVE_DWIDTH/8-1 downto 0);
MAC_DMA2Bus_MstWr_sof_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_eof_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_src_rdy_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_src_dsc_n : out std_logic := '1';
m_read : in std_logic := '0';
m_write : in std_logic := '0';
m_byteenable : in std_logic_vector(3 downto 0);
m_address : in std_logic_vector(dma_highadr_g downto 0);
m_writedata : in std_logic_vector(31 downto 0);
m_burstcount : in std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : in std_logic_vector(m_burstcount_width_g-1 downto 0);
m_readdata : out std_logic_vector(31 downto 0);
m_waitrequest : out std_logic := '1';
m_readdatavalid : out std_logic := '0';
m_clk : out std_logic
);
end plb_master_handler;
architecture plb_master_handler of plb_master_handler is
signal clk, rst : std_logic;
--signals for requesting transfers
signal m_write_s, m_read_s, m_wrd_en_n : std_logic;
signal m_write_l, m_read_l : std_logic;
signal m_write_rise, m_read_rise : std_logic;
signal m_write_fall, m_read_fall : std_logic;
signal mst_write_req, mst_write_req_next : std_logic;
signal mst_read_req, mst_read_req_next : std_logic;
--what if master wants to req new transfer, but previous is not yet completed (= no Mst_Cmplt pulse!!!)
signal mst_done : std_logic;
--signals for the transfer
type tran_t is (idle, sof, tran, eof, seof, wait4cmplt); --seof = start/end of frame (single beat)
signal wr_tran, wr_tran_next : tran_t;
signal rd_tran : tran_t;
--avoid preset of FFs
signal MAC_DMA2Bus_MstRd_dst_rdy : std_logic;
begin
--some assignments..
m_clk <= MAC_DMA_CLK;
clk <= MAC_DMA_CLK;
rst <= MAC_DMA_Rst;
mst_done <= Bus2MAC_DMA_Mst_Cmplt;
m_write_s <= m_write and not m_wrd_en_n; --NOTE: write/read enable is low-active!
m_read_s <= m_read and not m_wrd_en_n; --NOTE: write/read enable is low-active!
--reserved
MAC_DMA2Bus_Mst_Lock <= '0';
MAC_DMA2Bus_Mst_Reset <= '0';
--delay some signals..
del_proc : process(clk, rst)
begin
if rst = '1' then
m_write_l <= '0'; m_read_l <= '0';
m_wrd_en_n <= '0'; --is low-active to avoid preset of FF
elsif rising_edge(clk) then
m_write_l <= m_write_s; m_read_l <= m_read_s;
if mst_done = '1' then
m_wrd_en_n <= '0';
elsif m_write_fall = '1' or m_read_fall = '1' then
m_wrd_en_n <= '1'; --write/read done, wait for Mst_Cmplt
end if;
end if;
end process;
--generate pulse if write/read is asserted
m_write_rise <= '1' when m_write_l = '0' and m_write_s = '1' else '0';
m_read_rise <= '1' when m_read_l = '0' and m_read_s = '1' else '0';
m_write_fall <= '1' when m_write_l = '1' and m_write_s = '0' else '0';
m_read_fall <= '1' when m_read_l = '1' and m_read_s = '0' else '0';
--generate req qualifiers
req_proc : process(clk, rst)
begin
if rst = '1' then
mst_write_req <= '0'; mst_read_req <= '0';
MAC_DMA2Bus_MstRd_dst_rdy <= '0';
elsif rising_edge(clk) then
mst_write_req <= mst_write_req_next; mst_read_req <= mst_read_req_next;
if m_read_s = '1' then
MAC_DMA2Bus_MstRd_dst_rdy <= '1';
elsif rd_tran = eof and Bus2MAC_DMA_MstRd_src_rdy_n = '0' then
MAC_DMA2Bus_MstRd_dst_rdy <= '0';
end if;
end if;
end process;
MAC_DMA2Bus_MstRd_dst_rdy_n <= not MAC_DMA2Bus_MstRd_dst_rdy;
mst_write_req_next <= '0' when mst_write_req = '1' and Bus2MAC_DMA_Mst_CmdAck = '1' else
'1' when mst_write_req = '0' and m_write_rise = '1' else
mst_write_req;
mst_read_req_next <= '0' when mst_read_req = '1' and Bus2MAC_DMA_Mst_CmdAck = '1' else
'1' when mst_read_req = '0' and m_read_rise = '1' else
mst_read_req;
MAC_DMA2Bus_MstRd_Req <= mst_read_req;
MAC_DMA2Bus_MstWr_Req <= mst_write_req;
MAC_DMA2Bus_Mst_Type <= '0' when m_burstcount < 2 else --single beat
mst_read_req or mst_write_req; --we are talking about bursts..
--assign address, byteenable and burst size
MAC_DMA2Bus_Mst_Addr <= m_address;
MAC_DMA2Bus_Mst_BE <= "1111";
MAC_DMA2Bus_Mst_Length <= conv_std_logic_vector(conv_integer(m_burstcount),
MAC_DMA2Bus_Mst_Length'length - 2) & "00"; -- dword x 4 = byte
--write/read link
wrd_proc : process(clk, rst)
begin
if rst = '1' then
wr_tran <= idle;
elsif rising_edge(clk) then
wr_tran <= wr_tran_next;
end if;
end process;
--generate fsm for write and read transfers
wr_tran_next <=
seof when wr_tran = idle and mst_write_req_next = '1' and (m_burstcount <= 1 or m_burstcount'length = 1) else
sof when wr_tran = idle and mst_write_req_next = '1' and m_burstcount'length > 1 else
eof when wr_tran = sof and Bus2MAC_DMA_MstWr_dst_rdy_n = '0' and m_burstcount = 2 and m_burstcount'length > 1 else
tran when wr_tran = sof and Bus2MAC_DMA_MstWr_dst_rdy_n = '0' and m_burstcount'length > 1 else
eof when wr_tran = tran and m_burstcounter <= 2 and Bus2MAC_DMA_MstWr_dst_rdy_n = '0' and m_burstcount'length > 1 else
wait4cmplt when (wr_tran = eof or wr_tran = seof) and Bus2MAC_DMA_MstWr_dst_rdy_n = '0' else
idle when wr_tran = wait4cmplt and mst_done = '1' else
wr_tran;
rd_tran <=
seof when Bus2MAC_DMA_MstRd_sof_n = '0' and Bus2MAC_DMA_MstRd_eof_n = '0' else
sof when Bus2MAC_DMA_MstRd_sof_n = '0' else
eof when Bus2MAC_DMA_MstRd_eof_n = '0' else
tran when Bus2MAC_DMA_MstRd_src_rdy_n = '0' else
idle;
--set write qualifiers
MAC_DMA2Bus_MstWr_sof_n <= '0' when wr_tran = sof or wr_tran = seof else '1';
MAC_DMA2Bus_MstWr_eof_n <= '0' when wr_tran = eof or wr_tran = seof else '1';
MAC_DMA2Bus_MstWr_src_rdy_n <= '0' when wr_tran /= idle and wr_tran /= wait4cmplt else '1';
MAC_DMA2Bus_MstWr_src_dsc_n <= '1'; --no support
MAC_DMA2Bus_MstWr_rem <= (others => '0'); --no support
--set read qualifiers
MAC_DMA2Bus_MstRd_dst_dsc_n <= '1'; --no support
--connect ipif with avalon
m_waitrequest <= --waitrequest if not ready or no write active
not m_write when Bus2MAC_DMA_MstWr_dst_rdy_n = '0' else
not m_read when mst_read_req = '1' and Bus2MAC_DMA_Mst_CmdAck = '1' else '1';
m_readdatavalid <= not Bus2MAC_DMA_MstRd_src_rdy_n;
MAC_DMA2Bus_MstWr_d <= m_writedata;
m_readdata <= Bus2MAC_DMA_MstRd_d;
end plb_master_handler;
|
-------------------------------------------------------------------------------
--
-- Title : plb_master_handler
-- Design : POWERLINK
--
-------------------------------------------------------------------------------
--
-- File : c:\my_designs\POWERLINK\src\plb_master_handler.vhd
-- Generated : Mon Nov 7 13:17:30 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- 2011-08-03 V0.01 zelenkaj First version
-- 2011-12-01 V0.02 zelenkaj Fixed read transfer error (dst_rdy_n earlier)
-- 2011-12-05 V0.03 zelenkaj Avoid preset of FFs
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity plb_master_handler is
generic(
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
dma_highadr_g : integer := 31;
C_MAC_DMA_PLB_NATIVE_DWIDTH : integer := 32;
C_MAC_DMA_PLB_AWIDTH : integer := 32;
m_burstcount_width_g : integer := 4
);
port(
MAC_DMA_CLK : in std_logic;
MAC_DMA_Rst : in std_logic;
Bus2MAC_DMA_Mst_CmdAck : in std_logic := '0';
Bus2MAC_DMA_Mst_Cmplt : in std_logic := '0';
Bus2MAC_DMA_Mst_Error : in std_logic := '0';
Bus2MAC_DMA_Mst_Rearbitrate : in std_logic := '0';
Bus2MAC_DMA_Mst_Cmd_Timeout : in std_logic := '0';
Bus2MAC_DMA_MstRd_d : in std_logic_vector(C_MAC_DMA_PLB_NATIVE_DWIDTH-1 downto 0);
Bus2MAC_DMA_MstRd_rem : in std_logic_vector(C_MAC_DMA_PLB_NATIVE_DWIDTH/8-1 downto 0);
Bus2MAC_DMA_MstRd_sof_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_eof_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_src_rdy_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_src_dsc_n : in std_logic := '1';
Bus2MAC_DMA_MstWr_dst_rdy_n : in std_logic := '1';
Bus2MAC_DMA_MstWr_dst_dsc_n : in std_logic := '1';
MAC_DMA2Bus_MstRd_Req : out std_logic := '0';
MAC_DMA2Bus_MstWr_Req : out std_logic := '0';
MAC_DMA2Bus_Mst_Type : out std_logic := '0';
MAC_DMA2Bus_Mst_Addr : out std_logic_vector(C_MAC_DMA_PLB_AWIDTH-1 downto 0);
MAC_DMA2Bus_Mst_Length : out std_logic_vector(11 downto 0);
MAC_DMA2Bus_Mst_BE : out std_logic_vector(C_MAC_DMA_PLB_NATIVE_DWIDTH/8-1 downto 0);
MAC_DMA2Bus_Mst_Lock : out std_logic := '0';
MAC_DMA2Bus_Mst_Reset : out std_logic := '0';
MAC_DMA2Bus_MstRd_dst_rdy_n : out std_logic := '1';
MAC_DMA2Bus_MstRd_dst_dsc_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_d : out std_logic_vector(C_MAC_DMA_PLB_NATIVE_DWIDTH-1 downto 0);
MAC_DMA2Bus_MstWr_rem : out std_logic_vector(C_MAC_DMA_PLB_NATIVE_DWIDTH/8-1 downto 0);
MAC_DMA2Bus_MstWr_sof_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_eof_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_src_rdy_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_src_dsc_n : out std_logic := '1';
m_read : in std_logic := '0';
m_write : in std_logic := '0';
m_byteenable : in std_logic_vector(3 downto 0);
m_address : in std_logic_vector(dma_highadr_g downto 0);
m_writedata : in std_logic_vector(31 downto 0);
m_burstcount : in std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : in std_logic_vector(m_burstcount_width_g-1 downto 0);
m_readdata : out std_logic_vector(31 downto 0);
m_waitrequest : out std_logic := '1';
m_readdatavalid : out std_logic := '0';
m_clk : out std_logic
);
end plb_master_handler;
architecture plb_master_handler of plb_master_handler is
signal clk, rst : std_logic;
--signals for requesting transfers
signal m_write_s, m_read_s, m_wrd_en_n : std_logic;
signal m_write_l, m_read_l : std_logic;
signal m_write_rise, m_read_rise : std_logic;
signal m_write_fall, m_read_fall : std_logic;
signal mst_write_req, mst_write_req_next : std_logic;
signal mst_read_req, mst_read_req_next : std_logic;
--what if master wants to req new transfer, but previous is not yet completed (= no Mst_Cmplt pulse!!!)
signal mst_done : std_logic;
--signals for the transfer
type tran_t is (idle, sof, tran, eof, seof, wait4cmplt); --seof = start/end of frame (single beat)
signal wr_tran, wr_tran_next : tran_t;
signal rd_tran : tran_t;
--avoid preset of FFs
signal MAC_DMA2Bus_MstRd_dst_rdy : std_logic;
begin
--some assignments..
m_clk <= MAC_DMA_CLK;
clk <= MAC_DMA_CLK;
rst <= MAC_DMA_Rst;
mst_done <= Bus2MAC_DMA_Mst_Cmplt;
m_write_s <= m_write and not m_wrd_en_n; --NOTE: write/read enable is low-active!
m_read_s <= m_read and not m_wrd_en_n; --NOTE: write/read enable is low-active!
--reserved
MAC_DMA2Bus_Mst_Lock <= '0';
MAC_DMA2Bus_Mst_Reset <= '0';
--delay some signals..
del_proc : process(clk, rst)
begin
if rst = '1' then
m_write_l <= '0'; m_read_l <= '0';
m_wrd_en_n <= '0'; --is low-active to avoid preset of FF
elsif rising_edge(clk) then
m_write_l <= m_write_s; m_read_l <= m_read_s;
if mst_done = '1' then
m_wrd_en_n <= '0';
elsif m_write_fall = '1' or m_read_fall = '1' then
m_wrd_en_n <= '1'; --write/read done, wait for Mst_Cmplt
end if;
end if;
end process;
--generate pulse if write/read is asserted
m_write_rise <= '1' when m_write_l = '0' and m_write_s = '1' else '0';
m_read_rise <= '1' when m_read_l = '0' and m_read_s = '1' else '0';
m_write_fall <= '1' when m_write_l = '1' and m_write_s = '0' else '0';
m_read_fall <= '1' when m_read_l = '1' and m_read_s = '0' else '0';
--generate req qualifiers
req_proc : process(clk, rst)
begin
if rst = '1' then
mst_write_req <= '0'; mst_read_req <= '0';
MAC_DMA2Bus_MstRd_dst_rdy <= '0';
elsif rising_edge(clk) then
mst_write_req <= mst_write_req_next; mst_read_req <= mst_read_req_next;
if m_read_s = '1' then
MAC_DMA2Bus_MstRd_dst_rdy <= '1';
elsif rd_tran = eof and Bus2MAC_DMA_MstRd_src_rdy_n = '0' then
MAC_DMA2Bus_MstRd_dst_rdy <= '0';
end if;
end if;
end process;
MAC_DMA2Bus_MstRd_dst_rdy_n <= not MAC_DMA2Bus_MstRd_dst_rdy;
mst_write_req_next <= '0' when mst_write_req = '1' and Bus2MAC_DMA_Mst_CmdAck = '1' else
'1' when mst_write_req = '0' and m_write_rise = '1' else
mst_write_req;
mst_read_req_next <= '0' when mst_read_req = '1' and Bus2MAC_DMA_Mst_CmdAck = '1' else
'1' when mst_read_req = '0' and m_read_rise = '1' else
mst_read_req;
MAC_DMA2Bus_MstRd_Req <= mst_read_req;
MAC_DMA2Bus_MstWr_Req <= mst_write_req;
MAC_DMA2Bus_Mst_Type <= '0' when m_burstcount < 2 else --single beat
mst_read_req or mst_write_req; --we are talking about bursts..
--assign address, byteenable and burst size
MAC_DMA2Bus_Mst_Addr <= m_address;
MAC_DMA2Bus_Mst_BE <= "1111";
MAC_DMA2Bus_Mst_Length <= conv_std_logic_vector(conv_integer(m_burstcount),
MAC_DMA2Bus_Mst_Length'length - 2) & "00"; -- dword x 4 = byte
--write/read link
wrd_proc : process(clk, rst)
begin
if rst = '1' then
wr_tran <= idle;
elsif rising_edge(clk) then
wr_tran <= wr_tran_next;
end if;
end process;
--generate fsm for write and read transfers
wr_tran_next <=
seof when wr_tran = idle and mst_write_req_next = '1' and (m_burstcount <= 1 or m_burstcount'length = 1) else
sof when wr_tran = idle and mst_write_req_next = '1' and m_burstcount'length > 1 else
eof when wr_tran = sof and Bus2MAC_DMA_MstWr_dst_rdy_n = '0' and m_burstcount = 2 and m_burstcount'length > 1 else
tran when wr_tran = sof and Bus2MAC_DMA_MstWr_dst_rdy_n = '0' and m_burstcount'length > 1 else
eof when wr_tran = tran and m_burstcounter <= 2 and Bus2MAC_DMA_MstWr_dst_rdy_n = '0' and m_burstcount'length > 1 else
wait4cmplt when (wr_tran = eof or wr_tran = seof) and Bus2MAC_DMA_MstWr_dst_rdy_n = '0' else
idle when wr_tran = wait4cmplt and mst_done = '1' else
wr_tran;
rd_tran <=
seof when Bus2MAC_DMA_MstRd_sof_n = '0' and Bus2MAC_DMA_MstRd_eof_n = '0' else
sof when Bus2MAC_DMA_MstRd_sof_n = '0' else
eof when Bus2MAC_DMA_MstRd_eof_n = '0' else
tran when Bus2MAC_DMA_MstRd_src_rdy_n = '0' else
idle;
--set write qualifiers
MAC_DMA2Bus_MstWr_sof_n <= '0' when wr_tran = sof or wr_tran = seof else '1';
MAC_DMA2Bus_MstWr_eof_n <= '0' when wr_tran = eof or wr_tran = seof else '1';
MAC_DMA2Bus_MstWr_src_rdy_n <= '0' when wr_tran /= idle and wr_tran /= wait4cmplt else '1';
MAC_DMA2Bus_MstWr_src_dsc_n <= '1'; --no support
MAC_DMA2Bus_MstWr_rem <= (others => '0'); --no support
--set read qualifiers
MAC_DMA2Bus_MstRd_dst_dsc_n <= '1'; --no support
--connect ipif with avalon
m_waitrequest <= --waitrequest if not ready or no write active
not m_write when Bus2MAC_DMA_MstWr_dst_rdy_n = '0' else
not m_read when mst_read_req = '1' and Bus2MAC_DMA_Mst_CmdAck = '1' else '1';
m_readdatavalid <= not Bus2MAC_DMA_MstRd_src_rdy_n;
MAC_DMA2Bus_MstWr_d <= m_writedata;
m_readdata <= Bus2MAC_DMA_MstRd_d;
end plb_master_handler;
|
-- Copyright (C) 2014 Roland Dobai
--
-- This file is part of ZyEHW.
--
-- ZyEHW is free software: you can redistribute it and/or modify it under the
-- terms of the GNU General Public License as published by the Free Software
-- Foundation, either version 3 of the License, or (at your option) any later
-- version.
--
-- ZyEHW is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ZyEHW. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use work.zyehw_pkg.all;
entity input_pipeline is
port (
clk: in std_logic;
input: in cgp_input_t;
output: out input_col_t
);
end input_pipeline;
architecture behav_input_pipeline of input_pipeline is
type input_double_col_t is array (0 to (primary_inputs-1),
0 to (2*columns-1)) of cgp_t;
signal input_pipeline_arr: input_double_col_t;
begin
first_col: for i in 0 to (primary_inputs-1) generate
input_pipeline_arr(i, 0) <= input(i);
end generate;
row: for i in 0 to (primary_inputs-1) generate
col: for j in 1 to (2*columns-1) generate
process (clk) is
begin
if (clk'event and clk = '1') then
input_pipeline_arr(i, j) <=
input_pipeline_arr(i, j-1);
end if;
end process;
end generate;
end generate;
output_row: for i in 0 to (primary_inputs-1) generate
output_col: for j in 0 to (columns-1) generate
output(i, j) <= input_pipeline_arr(i, 2*j);
end generate;
end generate;
end behav_input_pipeline;
|
library ieee;
use ieee.std_logic_1164.all;
entity alu is
port (
n : in std_logic_vector (3 downto 0);
m : in std_logic_vector (3 downto 0);
opcode : in std_logic_vector (1 downto 0);
d : out std_logic_vector (3 downto 0);
cout : out std_logic
);
end alu;
architecture behavioral of alu is
component carry_ripple_adder
port (
a : in std_logic_vector (3 downto 0);
b : in std_logic_vector (3 downto 0);
ci : in std_logic;
s : out std_logic_vector (3 downto 0);
co : out std_logic
);
end component;
signal m_inverted : std_logic_vector (3 downto 0);
signal nand_result : std_logic_vector (3 downto 0);
signal nor_result : std_logic_vector (3 downto 0);
signal adder_result : std_logic_vector (3 downto 0);
signal adder_carry_out : std_logic;
signal operation_type : std_logic;
signal sub : std_logic;
begin
-- Make sense from control bits
operation_type <= opcode(1); -- Are we doing logical or arithmetic operation?
sub <= opcode(0); -- Are we doing addition/NAND or subtraction/NOR?
-- Here we calculate inverted bits for subtraction if necessary
m_inverted(0) <= not m(0);
m_inverted(1) <= not m(1);
m_inverted(2) <= not m(2);
m_inverted(3) <= not m(3);
-- Addition
adder_instance: carry_ripple_adder
port map(
a => n,
b => m_inverted,
ci => '1',
s => adder_result,
co => adder_carry_out
);
-- Logical NAND operation
nand_result(0) <= not m(0) and n(0);
nand_result(1) <= not m(1) and n(1);
nand_result(2) <= not m(2) and n(2);
nand_result(3) <= not m(3) and n(3);
-- Logical NOR operation
nor_result(0) <= not m(0) or n(0);
nor_result(1) <= not m(1) or n(1);
nor_result(2) <= not m(2) or n(2);
nor_result(3) <= not m(3) or n(3);
-- Select output based on which operation was requested
d <= nand_result when opcode ="10" else
nor_result when opcode ="11" else
adder_result;
-- Carry out bit
cout <= (adder_carry_out xor sub) when operation_type = '0' else
'0';
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity alu is
port (
n : in std_logic_vector (3 downto 0);
m : in std_logic_vector (3 downto 0);
opcode : in std_logic_vector (1 downto 0);
d : out std_logic_vector (3 downto 0);
cout : out std_logic
);
end alu;
architecture behavioral of alu is
component carry_ripple_adder
port (
a : in std_logic_vector (3 downto 0);
b : in std_logic_vector (3 downto 0);
ci : in std_logic;
s : out std_logic_vector (3 downto 0);
co : out std_logic
);
end component;
signal m_inverted : std_logic_vector (3 downto 0);
signal nand_result : std_logic_vector (3 downto 0);
signal nor_result : std_logic_vector (3 downto 0);
signal adder_result : std_logic_vector (3 downto 0);
signal adder_carry_out : std_logic;
signal operation_type : std_logic;
signal sub : std_logic;
begin
-- Make sense from control bits
operation_type <= opcode(1); -- Are we doing logical or arithmetic operation?
sub <= opcode(0); -- Are we doing addition/NAND or subtraction/NOR?
-- Here we calculate inverted bits for subtraction if necessary
m_inverted(0) <= not m(0);
m_inverted(1) <= not m(1);
m_inverted(2) <= not m(2);
m_inverted(3) <= not m(3);
-- Addition
adder_instance: carry_ripple_adder
port map(
a => n,
b => m_inverted,
ci => '1',
s => adder_result,
co => adder_carry_out
);
-- Logical NAND operation
nand_result(0) <= not m(0) and n(0);
nand_result(1) <= not m(1) and n(1);
nand_result(2) <= not m(2) and n(2);
nand_result(3) <= not m(3) and n(3);
-- Logical NOR operation
nor_result(0) <= not m(0) or n(0);
nor_result(1) <= not m(1) or n(1);
nor_result(2) <= not m(2) or n(2);
nor_result(3) <= not m(3) or n(3);
-- Select output based on which operation was requested
d <= nand_result when opcode ="10" else
nor_result when opcode ="11" else
adder_result;
-- Carry out bit
cout <= (adder_carry_out xor sub) when operation_type = '0' else
'0';
end;
|
--+-------------------------------------------------------------------------------------------------+
--| |
--| File: pcidmux.vhd |
--| |
--| Project: pci32tLite |
--| |
--| Description: Data Multiplex wb <-> regs <-> pci |
--| Data Multiplex D16 whisbone <-> D32 PCI. |
--| |
--+-------------------------------------------------------------------------------------------------+
--+-----------------------------------------------------------------+
--| |
--| Copyright (C) 2005-2008 Peio Azkarate, [email protected] |
--| |
--| This source file may be used and distributed without |
--| restriction provided that this copyright statement is not |
--| removed from the file and that any derivative work contains |
--| the original copyright notice and the associated disclaimer. |
--| |
--| This source file is free software; you can redistribute it |
--| and/or modify it under the terms of the GNU Lesser General |
--| Public License as published by the Free Software Foundation; |
--| either version 2.1 of the License, or (at your option) any |
--| later version. |
--| |
--| This source is distributed in the hope that it will be |
--| useful, but WITHOUT ANY WARRANTY; without even the implied |
--| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
--| PURPOSE. See the GNU Lesser General Public License for more |
--| details. |
--| |
--| You should have received a copy of the GNU Lesser General |
--| Public License along with this source; if not, download it |
--| from http://www.opencores.org/lgpl.shtml |
--| |
--+-----------------------------------------------------------------+
--+-----------------------------------------------------------------------------+
--| LIBRARIES |
--+-----------------------------------------------------------------------------+
library ieee;
use ieee.std_logic_1164.all;
--+-----------------------------------------------------------------------------+
--| ENTITY |
--+-----------------------------------------------------------------------------+
entity pcidmux is
generic (
BARS : string := "1BARMEM";
WBSIZE : integer := 16;
WBENDIAN : string := "BIG"
);
port (
-- General
clk_i : in std_logic;
rst_i : in std_logic;
--
d_in : in std_logic_vector(31 downto 0);
d_out : out std_logic_vector(31 downto 0);
--
wbdatLD_i : in std_logic;
rdcfg_i : in std_logic;
cbe_i : in std_logic_vector(3 downto 0);
--
wb_dat_i : in std_logic_vector((WBSIZE-1) downto 0);
wb_dat_o : out std_logic_vector((WBSIZE-1) downto 0);
rg_dat_i : in std_logic_vector(31 downto 0);
rg_dat_o : out std_logic_vector(31 downto 0)
);
end pcidmux;
architecture rtl of pcidmux is
--+-----------------------------------------------------------------------------+
--| COMPONENTS |
--+-----------------------------------------------------------------------------+
--+-----------------------------------------------------------------------------+
--| CONSTANTS |
--+-----------------------------------------------------------------------------+
--+-----------------------------------------------------------------------------+
--| SIGNALS |
--+-----------------------------------------------------------------------------+
signal pcidatin : std_logic_vector(31 downto 0);
signal pcidatout : std_logic_vector(31 downto 0);
signal wb_dat_is : std_logic_vector((WBSIZE-1) downto 0);
signal wbrgdMX : std_logic;
signal wbdMX : std_logic_vector(1 downto 0);
begin
-- Mux control signals
wbrgdMX <= not rdcfg_i;
wbdMX(0) <= '0' when ( cbe_i(0) = '0' or cbe_i(2) = '0' ) else '1';
wbdMX(1) <= '0' when ( cbe_i(0) = '0' or cbe_i(1) = '0' ) else '1';
--+-------------------------------------------------------------------------+
--| Load Whisbone Datain |
--+-------------------------------------------------------------------------+
WBDATLD: process( rst_i, clk_i, wbdatLD_i, wb_dat_i )
begin
if( rst_i = '1' ) then
wb_dat_is <= ( others => '1' );
elsif( rising_edge(clk_i) ) then
if ( wbdatLD_i = '1' ) then
wb_dat_is <= wb_dat_i;
end if;
end if;
end process WBDATLD;
--+-------------------------------------------------------------------------+
--| Route PCI data in toward Registers and Whisbone |
--+-------------------------------------------------------------------------+
rg_dat_o <= pcidatin;
--+-------------------------------------------------------------------------+
--| PCI <-> WB Data route and swap |
--+-------------------------------------------------------------------------+
--+-----------------------------------------+
--| PCI(Little endian) <-> WB(Little endian)|
--| WB bus 32Bits |
--+-----------------------------------------+
dat32: if (WBSIZE = 32 and WBENDIAN = "LITTLE") generate
pcidatout(31 downto 0) <= wb_dat_is(31 downto 0) when ( wbrgdMX = '1' ) else rg_dat_i(31 downto 0);
wb_dat_o(31 downto 0) <= pcidatin(31 downto 0);
end generate;
--+-----------------------------------------+
--| PCI(Little endian) <-> WB(Big endian) |
--| WB bus 16Bits |
--+-----------------------------------------+
dat16b: if (WBSIZE = 16 and WBENDIAN = "BIG") generate
--pcidatout(31 downto 24) <= wb_dat_is(7 downto 0) when ( wbrgdMX_i = '1' ) else rg_dat_i(31 downto 24);
--pcidatout(23 downto 16) <= wb_dat_is(15 downto 8) when ( wbrgdMX_i = '1' ) else rg_dat_i(23 downto 16);
--pcidatout(15 downto 8) <= wb_dat_is(7 downto 0) when ( wbrgdMX_i = '1' ) else rg_dat_i(15 downto 8);
--pcidatout(7 downto 0) <= wb_dat_is(15 downto 8) when ( wbrgdMX_i = '1' ) else rg_dat_i(7 downto 0);
--wb_dat_o(15 downto 8) <= pcidatin(23 downto 16) when ( wbdMX_i(1) = '1' ) else pcidatin(7 downto 0);
--wb_dat_o(7 downto 0) <= pcidatin(31 downto 24) when ( wbdMX_i(1) = '1' ) else pcidatin(15 downto 8);
PCIWBMUX: process(cbe_i, pcidatin, wbrgdMX, wb_dat_is, rg_dat_i)
begin
case cbe_i is
when b"1100" =>
wb_dat_o(7 downto 0) <= pcidatin(7 downto 0);
wb_dat_o(15 downto 8) <= pcidatin(15 downto 8);
when b"0011" =>
wb_dat_o(7 downto 0) <= pcidatin(23 downto 16);
wb_dat_o(15 downto 8) <= pcidatin(31 downto 24);
when b"1110" =>
wb_dat_o(7 downto 0) <= (others => '1');
wb_dat_o(15 downto 8) <= pcidatin(7 downto 0);
when b"1101" =>
wb_dat_o(7 downto 0) <= pcidatin(15 downto 8);
wb_dat_o(15 downto 8) <= (others => '1');
when b"1011" =>
wb_dat_o(7 downto 0) <= (others => '1');
wb_dat_o(15 downto 8) <= pcidatin(23 downto 16);
when b"0111" =>
wb_dat_o(7 downto 0) <= pcidatin(31 downto 24);
wb_dat_o(15 downto 8) <= (others => '1');
when others =>
wb_dat_o(15 downto 0) <= pcidatin(15 downto 0);
end case;
if (wbrgdMX = '1') then
case cbe_i is
when b"1100" =>
pcidatout(31 downto 16) <= (others => '1');
pcidatout(15 downto 0) <= wb_dat_is(15 downto 0);
when b"0011" =>
pcidatout(31 downto 16) <= wb_dat_is(15 downto 0);
pcidatout(15 downto 0) <= (others => '1');
when b"1110" =>
pcidatout(31 downto 8) <= (others => '1');
pcidatout(7 downto 0) <= wb_dat_is(15 downto 8);
when b"1101" =>
pcidatout(31 downto 16) <= (others => '1');
pcidatout(15 downto 8) <= wb_dat_is(7 downto 0);
pcidatout(7 downto 0) <= (others => '1');
when b"1011" =>
pcidatout(31 downto 24) <= (others => '1');
pcidatout(23 downto 16) <= wb_dat_is(15 downto 8);
pcidatout(15 downto 0) <= (others => '1');
when b"0111" =>
pcidatout(31 downto 24) <= wb_dat_is(7 downto 0);
pcidatout(23 downto 0) <= (others => '1');
when others =>
pcidatout(15 downto 0) <= wb_dat_is(15 downto 0);
pcidatout(31 downto 16) <= (others => '1');
end case;
else
pcidatout(31 downto 0) <= rg_dat_i(31 downto 0);
end if;
end process PCIWBMUX;
end generate;
--+-----------------------------------------+
--| PCI(Little endian) <-> WB(Little endian)|
--| WB bus 16Bits |
--+-----------------------------------------+
dat16l: if (WBSIZE = 16 and WBENDIAN = "LITTLE") generate
pcidatout(31 downto 16) <= wb_dat_is when ( wbrgdMX = '1' ) else rg_dat_i(31 downto 16);
pcidatout(15 downto 0) <= wb_dat_is when ( wbrgdMX = '1' ) else rg_dat_i(15 downto 0);
wb_dat_o(15 downto 0) <= pcidatin(31 downto 16) when ( wbdMX(1) = '1' ) else pcidatin(15 downto 0);
end generate;
--+-----------------------------------------+
--| PCI(Little endian) <-> WB(Little endian)|
--| WB bus 8Bits |
--+-----------------------------------------+
dat8l: if (WBSIZE = 8 and WBENDIAN = "LITTLE") generate
--pcidatout(31 downto 24) <= wb_dat_is(7 downto 0);
--pcidatout(23 downto 16) <= wb_dat_is(7 downto 0);
--pcidatout(15 downto 8) <= wb_dat_is(7 downto 0);
--pcidatout(7 downto 0) <= wb_dat_is(7 downto 0);
pcidatout(31 downto 24) <= wb_dat_is(7 downto 0) when ( wbrgdMX = '1' ) else rg_dat_i(31 downto 24);
pcidatout(23 downto 16) <= wb_dat_is(7 downto 0) when ( wbrgdMX = '1' ) else rg_dat_i(23 downto 16);
pcidatout(15 downto 8) <= wb_dat_is(7 downto 0) when ( wbrgdMX = '1' ) else rg_dat_i(15 downto 8);
pcidatout(7 downto 0) <= wb_dat_is(7 downto 0) when ( wbrgdMX = '1' ) else rg_dat_i(7 downto 0);
with wbdMX select
wb_dat_o(7 downto 0) <= pcidatin(7 downto 0) when "00",
pcidatin(15 downto 8) when "01",
pcidatin(23 downto 16) when "10",
pcidatin(31 downto 24) when "11",
(others => '0') when others;
end generate;
--+-------------------------------------------------------------------------+
--| PCI data in/out
--+-------------------------------------------------------------------------+
pcidatin <= d_in;
d_out <= pcidatout;
end rtl;
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-17.11:31:30)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY ewf_ibea_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2: IN unsigned(0 TO 30);
output1, output2, output3, output4, output5: OUT unsigned(0 TO 31));
END ewf_ibea_entity;
ARCHITECTURE ewf_ibea_description OF ewf_ibea_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register6: unsigned(0 TO 31) := "00000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
WHEN "00000010" =>
register2 := register1 + 3;
WHEN "00000011" =>
register3 := register2 + 5;
register4 := input2 + 6;
WHEN "00000100" =>
register3 := register4 + register3;
WHEN "00000101" =>
register5 := register3 * 8;
WHEN "00000110" =>
register6 := register3 * 10;
register5 := register2 + register5;
WHEN "00000111" =>
register3 := register3 + register5;
register2 := register2 + register5;
WHEN "00001000" =>
register6 := register4 + register6;
register2 := register2 * 12;
WHEN "00001001" =>
register4 := register4 + register6;
output1 <= register6 + register3;
WHEN "00001010" =>
register3 := register4 * 15;
register2 := register1 + register2;
WHEN "00001011" =>
register1 := register1 + register2;
WHEN "00001100" =>
register1 := register1 * 17;
register4 := register5 + register2;
WHEN "00001101" =>
register1 := register1 + 19;
WHEN "00001110" =>
output2 <= register2 + register1;
register1 := register4 + 22;
WHEN "00001111" =>
register2 := register1 * 24;
WHEN "00010000" =>
register2 := register2 + 26;
WHEN "00010001" =>
output3 <= register1 + register2;
register1 := register3 + 29;
WHEN "00010010" =>
register2 := register6 + register1;
WHEN "00010011" =>
register2 := register2 + 31;
WHEN "00010100" =>
register3 := register2 * 33;
register4 := register1 + 35;
WHEN "00010101" =>
register3 := register3 + 37;
register4 := register4 * 39;
WHEN "00010110" =>
output4 <= register2 + register3;
output5 <= register1 + register4;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END ewf_ibea_description; |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- altera vhdl_input_version vhdl_2008
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package avblabs_common_pkg is
procedure write_sr_flag (
signal flag : out std_logic;
constant baseaddr : natural;
constant bitpos : natural;
signal addr : in std_logic_vector;
signal data : in std_logic_vector;
signal be : in std_logic_vector
);
procedure write_reg (
signal reg : out std_logic_vector;
constant baseaddr : natural;
signal addr : in std_logic_vector;
signal data : in std_logic_vector;
signal be : in std_logic_vector
);
function ulen (arg : natural) return natural;
function slen (arg : integer) return natural;
function bin_to_gray (inputs: unsigned) return std_logic_vector;
function gray_to_bin (inputs: std_logic_vector) return unsigned;
function fifo_not_full (
wrptr : std_logic_vector;
rdptr : std_logic_vector
) return std_logic;
function fifo_not_empty (
wrptr : std_logic_vector;
rdptr : std_logic_vector
) return std_logic;
function fifo_water_level (
wrptr : std_logic_vector;
rdptr : std_logic_vector
) return unsigned;
end package;
package body avblabs_common_pkg is
procedure write_sr_flag (
signal flag : out std_logic;
constant baseaddr : natural;
constant bitpos : natural;
signal addr : in std_logic_vector;
signal data : in std_logic_vector;
signal be : in std_logic_vector
) is
begin
if unsigned(addr(addr'left downto addr'right + 1)) = baseaddr / 2 then
if be(bitpos / 8) and data(bitpos) then
flag <= not addr(addr'right);
end if;
end if;
end procedure;
procedure write_reg (
signal reg : out std_logic_vector;
constant baseaddr : natural;
signal addr : in std_logic_vector;
signal data : in std_logic_vector;
signal be : in std_logic_vector
) is
begin
if unsigned(addr) = baseaddr then
for i in reg'range loop
if be(i / 8) then
reg(i) <= data(i);
end if;
end loop;
end if;
end procedure;
function ulen (arg : natural) return natural is
begin
if arg < 2 then
return 1;
else
return ulen(arg / 2) + 1;
end if;
end function;
function slen (arg : integer) return natural is
begin
if arg < 0 then
return ulen(abs(arg) - 1) + 1;
else
return ulen(arg) + 1;
end if;
end function;
function bin_to_gray (inputs: unsigned) return std_logic_vector is
begin
return std_logic_vector(inputs xor ('0' & inputs(inputs'left downto inputs'right + 1)));
end function;
function gray_to_bin_i (inputs: std_logic_vector) return std_logic_vector is
variable u_result : std_logic_vector(inputs'left downto inputs'length / 2 + inputs'right);
variable l_result : std_logic_vector(inputs'length / 2 + inputs'right - 1 downto inputs'right);
begin
u_result := inputs(u_result'range);
l_result := inputs(l_result'range);
if u_result'length > 1 then
u_result := gray_to_bin_i(u_result);
end if;
if l_result'length > 1 then
l_result := gray_to_bin_i(l_result);
end if;
l_result := l_result xor (l_result'range => u_result(u_result'right));
return u_result & l_result;
end function;
function gray_to_bin (inputs: std_logic_vector) return unsigned is
-- variable result : unsigned(inputs'range);
begin
-- result(result'left) := inputs(inputs'left);
-- for i in inputs'left - 1 downto inputs'right loop
-- result(i) := inputs(i) xor result(i + 1);
-- end loop;
-- return result;
return unsigned(gray_to_bin_i(inputs));
end function;
function fifo_not_full (
wrptr : std_logic_vector;
rdptr : std_logic_vector
) return std_logic is
begin
if wrptr(wrptr'left - 2 downto 0) = rdptr(rdptr'left - 2 downto 0) then
return (wrptr(wrptr'left) xor rdptr(rdptr'left)) nand (wrptr(wrptr'left - 1) xor rdptr(rdptr'left - 1));
else
return '1';
end if;
end function;
function fifo_not_empty (
wrptr : std_logic_vector;
rdptr : std_logic_vector
) return std_logic is
begin
if wrptr = rdptr then
return '0';
else
return '1';
end if;
end function;
function fifo_water_level (
wrptr : std_logic_vector;
rdptr : std_logic_vector
) return unsigned is
variable wraddr : std_logic_vector(wrptr'left - 1 downto wrptr'right);
variable rdaddr : std_logic_vector(rdptr'left - 1 downto rdptr'right);
begin
wraddr := (wrptr(wrptr'left) xor wrptr(wrptr'left - 1)) & wrptr(wrptr'left - 2 downto 0);
rdaddr := (rdptr(rdptr'left) xor rdptr(rdptr'left - 1)) & rdptr(rdptr'left - 2 downto 0);
return gray_to_bin(wraddr) - gray_to_bin(rdaddr);
end function;
end package body;
|
library ieee;
use ieee.std_logic_1164.all;
entity map3 is
port
(
F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15: out std_logic_vector(31 downto 0)
);
end map3;
architecture map3_struct of map3 is
begin
F0 <= "00000000000000000000110000000000";
F1 <= "00000001000000011000110000011000";
F2 <= "00000000100000000100000000011000";
F3 <= "00000000010000000000001100000100";
F4 <= "00000000000000001000000000000000";
F5 <= "00000000000000011000001000000010";
F6 <= "00000000000000111000000010001110";
F7 <= "00000000000000000000000000000000";
F8 <= "00000010000000000000010000000010";
F9 <= "00000000000000011000110001000110";
F10 <= "00000100000000001000000000110000";
F11 <= "00000000011000001000000000100000";
F12 <= "00000000011000000100000000000000";
F13 <= "00000010000000000000110000100000";
F14 <= "00000000010000000000000011011000";
F15 <= "00010000000010000100000000011000";
end map3_struct; |
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Description: --
-- --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity Generic_Equalizer_Low_Pass is
port(clk : in std_logic;
reset : in std_logic;
input : in std_logic_vector(15 downto 0);
output : out std_logic_vector(15 downto 0));
end Generic_Equalizer_Low_Pass;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture behaviour of Generic_Equalizer_Low_Pass is
begin
Generic_Equalizer : entity work.Generic_Equalizer
generic map(NO_SECTIONS => 9,
INPUT_WIDTH => 16,
INPUT_FRACT => 14,
OUTPUT_WIDTH => 16,
OUTPUT_FRACT => 14,
SCALE_WIDTH => 16,
SCALE_FRACT => (14,14,14,14,14,14,14,14,14,14),
INTERNAL_WIDTH => 30,
INTERNAL_FRACT => 24,
COEFF_WIDTH_B => 16,
COEFF_FRACT_B => (16,14,14,14,14,14,14,14,14),
COEFF_WIDTH_A => 16,
COEFF_FRACT_A => (14,14,14,14,14,14,14,14,14))
port map(clk => clk,
reset => reset,
x => input,
scale => (x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"),
b0 => (x"3e74"
& x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"),
b1 => (x"8a7f"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"),
b2 => (x"3777"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"),
a1 => (x"754C"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"),
a2 => (x"C9E0"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"),
y => output);
end architecture; |
----------------------------------------------------------------------------------
-- Company: Gadget Factory
-- Engineer: Alvaro Lopes
--
-- Create Date: 13:56:50 12/10/2013
-- Design Name:
-- Module Name: TEMPLATE_zpuino_wb_Wishbone - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This is an example template to use for your own Wishbone Peripherals.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
-- This example uses asynchronous outputs.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity BENCHY_zpuino_wb_waveform_generator is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
clk_in : in STD_LOGIC;
sin_out : OUT std_logic_vector(11 downto 0);
cos_out : OUT std_logic_vector(11 downto 0);
--squ_out : OUT std_logic_vector(11 downto 0);
saw_out : OUT std_logic_vector(11 downto 0);
sin_dac_out : OUT std_logic;
cos_dac_out : OUT std_logic;
squ_dac_out : OUT std_logic;
saw_dac_out : OUT std_logic
--all_dac_out : OUT std_logic
);
end entity BENCHY_zpuino_wb_waveform_generator;
architecture rtl of BENCHY_zpuino_wb_waveform_generator is
COMPONENT waveform_gen
PORT(
clk : IN std_logic;
reset : IN std_logic;
phase_inc : IN std_logic_vector(31 downto 0);
sin_out : OUT std_logic_vector(11 downto 0);
cos_out : OUT std_logic_vector(11 downto 0);
squ_out : OUT std_logic_vector(11 downto 0);
saw_out : OUT std_logic_vector(11 downto 0)
);
END COMPONENT;
COMPONENT AUDIO_zpuino_sa_sigmadeltaDAC
generic (
BITS: integer := 12
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end COMPONENT;
--Define your registers here
signal phase_inc_r : std_logic_vector(31 downto 0) := x"028c1980"; --x"028c1980" should give an output of 1Mhz. Wofram Alpha: x=10,y=(x*2^32)/(100 + .5)
-- signal waveform_sel: std_logic_vector(7 downto 0) := "00000010"; --Default to sine wave output
signal dac_in_s: std_logic_vector(11 downto 0);
signal sin_out_s: std_logic_vector(11 downto 0);
signal cos_out_s: std_logic_vector(11 downto 0);
signal squ_out_s: std_logic_vector(11 downto 0);
signal saw_out_s: std_logic_vector(11 downto 0);
-- signal register0: std_logic_vector(31 downto 0); -- Register 0 (32 bits)
-- signal register1: std_logic_vector(31 downto 0); -- Register 1 (32 bits)
-- signal register2: std_logic_vector(7 downto 0); -- Register 2 (8 bits)
--signal nReset : std_logic;
--Wishbone signals - Don't touch.
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- End unpacking Wishbone signals
--nReset <= not wb_rst_i;
-- Asynchronous acknowledge
wb_ack_o <= '1' when wb_cyc_i='1' and wb_stb_i='1' else '0';
-- Multiplex the data output (asynchronous)
process(phase_inc_r, wb_adr_i)
begin
-- Multiplex the read depending on the address. Use only the 2 lowest bits of addr
case wb_adr_i(3 downto 2) is
when "00" =>
wb_dat_o <= phase_inc_r; -- Output register0
-- when "01" =>
-- wb_dat_o(31 downto 0) <= (others => '0'); -- We put all upper 24 bits to zero
-- wb_dat_o(7 downto 0) <= waveform_sel; -- since register1 only has 8 bits
-- when "10" =>
-- wb_dat_o(31 downto 0) <= (others => '0'); -- We put all upper 24 bits to zero
-- wb_dat_o(7 downto 0) <= register2; -- since register2 only has 8 bits
when others =>
wb_dat_o <= (others => 'X'); -- Return undefined for all other addresses
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
if wb_rst_i='1' then
-- Reset request, put register1 and register2 with zeroes,
-- put register 3 with binary 10101010b
phase_inc_r <= (others => '0');
--waveform_sel <= (others => '0');
-- register2 <= "10101010";
else -- Not reset
-- Check if someone is writing
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
-- Yes, it's a write. See for which register based on address
case wb_adr_i(3 downto 2) is
when "00" =>
phase_inc_r <= wb_dat_i; -- Set register0
-- when "01" =>
-- waveform_sel <= wb_dat_i(7 downto 0); -- Set register1
-- when "10" =>
-- register2 <= wb_dat_i(7 downto 0); -- Only lower 8 bits for register2
when others =>
null; -- Nothing to do for other addresses
end case;
end if;
end if;
end if;
end process;
sin_out <= sin_out_s;
cos_out <= cos_out_s;
--squ_out <= squ_out_s;
saw_out <= saw_out_s;
Inst_waveform_gen: waveform_gen PORT MAP(
clk => wb_clk_i,
reset => '1',
phase_inc => phase_inc_r,
sin_out => sin_out_s,
cos_out => cos_out_s,
squ_out => squ_out_s,
saw_out => saw_out_s
);
Inst_dac1: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => sin_dac_out,
data_in => sin_out_s,
clk_96Mhz => clk_in
);
Inst_dac2: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => cos_dac_out,
data_in => cos_out_s,
clk_96Mhz => clk_in
);
Inst_dac3: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => squ_dac_out,
data_in => squ_out_s,
clk_96Mhz => clk_in
);
Inst_dac4: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => saw_dac_out,
data_in => saw_out_s,
clk_96Mhz => clk_in
);
-- process (waveform_sel,sin_out_s,cos_out_s,squ_out_s,saw_out_s)
-- begin
-- case waveform_sel(1 downto 0) is
-- when "00" => dac_in_s <= sin_out_s;
-- when "01" => dac_in_s <= cos_out_s;
-- when "10" => dac_in_s <= squ_out_s;
-- when "11" => dac_in_s <= saw_out_s;
-- when others => dac_in_s <= squ_out_s;
-- end case;
-- end process;
end rtl;
|
----------------------------------------------------------------------------------
-- Company: Gadget Factory
-- Engineer: Alvaro Lopes
--
-- Create Date: 13:56:50 12/10/2013
-- Design Name:
-- Module Name: TEMPLATE_zpuino_wb_Wishbone - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This is an example template to use for your own Wishbone Peripherals.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
-- This example uses asynchronous outputs.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity BENCHY_zpuino_wb_waveform_generator is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
clk_in : in STD_LOGIC;
sin_out : OUT std_logic_vector(11 downto 0);
cos_out : OUT std_logic_vector(11 downto 0);
--squ_out : OUT std_logic_vector(11 downto 0);
saw_out : OUT std_logic_vector(11 downto 0);
sin_dac_out : OUT std_logic;
cos_dac_out : OUT std_logic;
squ_dac_out : OUT std_logic;
saw_dac_out : OUT std_logic
--all_dac_out : OUT std_logic
);
end entity BENCHY_zpuino_wb_waveform_generator;
architecture rtl of BENCHY_zpuino_wb_waveform_generator is
COMPONENT waveform_gen
PORT(
clk : IN std_logic;
reset : IN std_logic;
phase_inc : IN std_logic_vector(31 downto 0);
sin_out : OUT std_logic_vector(11 downto 0);
cos_out : OUT std_logic_vector(11 downto 0);
squ_out : OUT std_logic_vector(11 downto 0);
saw_out : OUT std_logic_vector(11 downto 0)
);
END COMPONENT;
COMPONENT AUDIO_zpuino_sa_sigmadeltaDAC
generic (
BITS: integer := 12
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end COMPONENT;
--Define your registers here
signal phase_inc_r : std_logic_vector(31 downto 0) := x"028c1980"; --x"028c1980" should give an output of 1Mhz. Wofram Alpha: x=10,y=(x*2^32)/(100 + .5)
-- signal waveform_sel: std_logic_vector(7 downto 0) := "00000010"; --Default to sine wave output
signal dac_in_s: std_logic_vector(11 downto 0);
signal sin_out_s: std_logic_vector(11 downto 0);
signal cos_out_s: std_logic_vector(11 downto 0);
signal squ_out_s: std_logic_vector(11 downto 0);
signal saw_out_s: std_logic_vector(11 downto 0);
-- signal register0: std_logic_vector(31 downto 0); -- Register 0 (32 bits)
-- signal register1: std_logic_vector(31 downto 0); -- Register 1 (32 bits)
-- signal register2: std_logic_vector(7 downto 0); -- Register 2 (8 bits)
--signal nReset : std_logic;
--Wishbone signals - Don't touch.
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- End unpacking Wishbone signals
--nReset <= not wb_rst_i;
-- Asynchronous acknowledge
wb_ack_o <= '1' when wb_cyc_i='1' and wb_stb_i='1' else '0';
-- Multiplex the data output (asynchronous)
process(phase_inc_r, wb_adr_i)
begin
-- Multiplex the read depending on the address. Use only the 2 lowest bits of addr
case wb_adr_i(3 downto 2) is
when "00" =>
wb_dat_o <= phase_inc_r; -- Output register0
-- when "01" =>
-- wb_dat_o(31 downto 0) <= (others => '0'); -- We put all upper 24 bits to zero
-- wb_dat_o(7 downto 0) <= waveform_sel; -- since register1 only has 8 bits
-- when "10" =>
-- wb_dat_o(31 downto 0) <= (others => '0'); -- We put all upper 24 bits to zero
-- wb_dat_o(7 downto 0) <= register2; -- since register2 only has 8 bits
when others =>
wb_dat_o <= (others => 'X'); -- Return undefined for all other addresses
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
if wb_rst_i='1' then
-- Reset request, put register1 and register2 with zeroes,
-- put register 3 with binary 10101010b
phase_inc_r <= (others => '0');
--waveform_sel <= (others => '0');
-- register2 <= "10101010";
else -- Not reset
-- Check if someone is writing
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
-- Yes, it's a write. See for which register based on address
case wb_adr_i(3 downto 2) is
when "00" =>
phase_inc_r <= wb_dat_i; -- Set register0
-- when "01" =>
-- waveform_sel <= wb_dat_i(7 downto 0); -- Set register1
-- when "10" =>
-- register2 <= wb_dat_i(7 downto 0); -- Only lower 8 bits for register2
when others =>
null; -- Nothing to do for other addresses
end case;
end if;
end if;
end if;
end process;
sin_out <= sin_out_s;
cos_out <= cos_out_s;
--squ_out <= squ_out_s;
saw_out <= saw_out_s;
Inst_waveform_gen: waveform_gen PORT MAP(
clk => wb_clk_i,
reset => '1',
phase_inc => phase_inc_r,
sin_out => sin_out_s,
cos_out => cos_out_s,
squ_out => squ_out_s,
saw_out => saw_out_s
);
Inst_dac1: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => sin_dac_out,
data_in => sin_out_s,
clk_96Mhz => clk_in
);
Inst_dac2: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => cos_dac_out,
data_in => cos_out_s,
clk_96Mhz => clk_in
);
Inst_dac3: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => squ_dac_out,
data_in => squ_out_s,
clk_96Mhz => clk_in
);
Inst_dac4: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => saw_dac_out,
data_in => saw_out_s,
clk_96Mhz => clk_in
);
-- process (waveform_sel,sin_out_s,cos_out_s,squ_out_s,saw_out_s)
-- begin
-- case waveform_sel(1 downto 0) is
-- when "00" => dac_in_s <= sin_out_s;
-- when "01" => dac_in_s <= cos_out_s;
-- when "10" => dac_in_s <= squ_out_s;
-- when "11" => dac_in_s <= saw_out_s;
-- when others => dac_in_s <= squ_out_s;
-- end case;
-- end process;
end rtl;
|
----------------------------------------------------------------------------------
-- Company: Gadget Factory
-- Engineer: Alvaro Lopes
--
-- Create Date: 13:56:50 12/10/2013
-- Design Name:
-- Module Name: TEMPLATE_zpuino_wb_Wishbone - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This is an example template to use for your own Wishbone Peripherals.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
-- This example uses asynchronous outputs.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity BENCHY_zpuino_wb_waveform_generator is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
clk_in : in STD_LOGIC;
sin_out : OUT std_logic_vector(11 downto 0);
cos_out : OUT std_logic_vector(11 downto 0);
--squ_out : OUT std_logic_vector(11 downto 0);
saw_out : OUT std_logic_vector(11 downto 0);
sin_dac_out : OUT std_logic;
cos_dac_out : OUT std_logic;
squ_dac_out : OUT std_logic;
saw_dac_out : OUT std_logic
--all_dac_out : OUT std_logic
);
end entity BENCHY_zpuino_wb_waveform_generator;
architecture rtl of BENCHY_zpuino_wb_waveform_generator is
COMPONENT waveform_gen
PORT(
clk : IN std_logic;
reset : IN std_logic;
phase_inc : IN std_logic_vector(31 downto 0);
sin_out : OUT std_logic_vector(11 downto 0);
cos_out : OUT std_logic_vector(11 downto 0);
squ_out : OUT std_logic_vector(11 downto 0);
saw_out : OUT std_logic_vector(11 downto 0)
);
END COMPONENT;
COMPONENT AUDIO_zpuino_sa_sigmadeltaDAC
generic (
BITS: integer := 12
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end COMPONENT;
--Define your registers here
signal phase_inc_r : std_logic_vector(31 downto 0) := x"028c1980"; --x"028c1980" should give an output of 1Mhz. Wofram Alpha: x=10,y=(x*2^32)/(100 + .5)
-- signal waveform_sel: std_logic_vector(7 downto 0) := "00000010"; --Default to sine wave output
signal dac_in_s: std_logic_vector(11 downto 0);
signal sin_out_s: std_logic_vector(11 downto 0);
signal cos_out_s: std_logic_vector(11 downto 0);
signal squ_out_s: std_logic_vector(11 downto 0);
signal saw_out_s: std_logic_vector(11 downto 0);
-- signal register0: std_logic_vector(31 downto 0); -- Register 0 (32 bits)
-- signal register1: std_logic_vector(31 downto 0); -- Register 1 (32 bits)
-- signal register2: std_logic_vector(7 downto 0); -- Register 2 (8 bits)
--signal nReset : std_logic;
--Wishbone signals - Don't touch.
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- End unpacking Wishbone signals
--nReset <= not wb_rst_i;
-- Asynchronous acknowledge
wb_ack_o <= '1' when wb_cyc_i='1' and wb_stb_i='1' else '0';
-- Multiplex the data output (asynchronous)
process(phase_inc_r, wb_adr_i)
begin
-- Multiplex the read depending on the address. Use only the 2 lowest bits of addr
case wb_adr_i(3 downto 2) is
when "00" =>
wb_dat_o <= phase_inc_r; -- Output register0
-- when "01" =>
-- wb_dat_o(31 downto 0) <= (others => '0'); -- We put all upper 24 bits to zero
-- wb_dat_o(7 downto 0) <= waveform_sel; -- since register1 only has 8 bits
-- when "10" =>
-- wb_dat_o(31 downto 0) <= (others => '0'); -- We put all upper 24 bits to zero
-- wb_dat_o(7 downto 0) <= register2; -- since register2 only has 8 bits
when others =>
wb_dat_o <= (others => 'X'); -- Return undefined for all other addresses
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
if wb_rst_i='1' then
-- Reset request, put register1 and register2 with zeroes,
-- put register 3 with binary 10101010b
phase_inc_r <= (others => '0');
--waveform_sel <= (others => '0');
-- register2 <= "10101010";
else -- Not reset
-- Check if someone is writing
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
-- Yes, it's a write. See for which register based on address
case wb_adr_i(3 downto 2) is
when "00" =>
phase_inc_r <= wb_dat_i; -- Set register0
-- when "01" =>
-- waveform_sel <= wb_dat_i(7 downto 0); -- Set register1
-- when "10" =>
-- register2 <= wb_dat_i(7 downto 0); -- Only lower 8 bits for register2
when others =>
null; -- Nothing to do for other addresses
end case;
end if;
end if;
end if;
end process;
sin_out <= sin_out_s;
cos_out <= cos_out_s;
--squ_out <= squ_out_s;
saw_out <= saw_out_s;
Inst_waveform_gen: waveform_gen PORT MAP(
clk => wb_clk_i,
reset => '1',
phase_inc => phase_inc_r,
sin_out => sin_out_s,
cos_out => cos_out_s,
squ_out => squ_out_s,
saw_out => saw_out_s
);
Inst_dac1: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => sin_dac_out,
data_in => sin_out_s,
clk_96Mhz => clk_in
);
Inst_dac2: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => cos_dac_out,
data_in => cos_out_s,
clk_96Mhz => clk_in
);
Inst_dac3: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => squ_dac_out,
data_in => squ_out_s,
clk_96Mhz => clk_in
);
Inst_dac4: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => saw_dac_out,
data_in => saw_out_s,
clk_96Mhz => clk_in
);
-- process (waveform_sel,sin_out_s,cos_out_s,squ_out_s,saw_out_s)
-- begin
-- case waveform_sel(1 downto 0) is
-- when "00" => dac_in_s <= sin_out_s;
-- when "01" => dac_in_s <= cos_out_s;
-- when "10" => dac_in_s <= squ_out_s;
-- when "11" => dac_in_s <= saw_out_s;
-- when others => dac_in_s <= squ_out_s;
-- end case;
-- end process;
end rtl;
|
----------------------------------------------------------------------------------
-- Company: Gadget Factory
-- Engineer: Alvaro Lopes
--
-- Create Date: 13:56:50 12/10/2013
-- Design Name:
-- Module Name: TEMPLATE_zpuino_wb_Wishbone - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This is an example template to use for your own Wishbone Peripherals.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
-- This example uses asynchronous outputs.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity BENCHY_zpuino_wb_waveform_generator is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
clk_in : in STD_LOGIC;
sin_out : OUT std_logic_vector(11 downto 0);
cos_out : OUT std_logic_vector(11 downto 0);
--squ_out : OUT std_logic_vector(11 downto 0);
saw_out : OUT std_logic_vector(11 downto 0);
sin_dac_out : OUT std_logic;
cos_dac_out : OUT std_logic;
squ_dac_out : OUT std_logic;
saw_dac_out : OUT std_logic
--all_dac_out : OUT std_logic
);
end entity BENCHY_zpuino_wb_waveform_generator;
architecture rtl of BENCHY_zpuino_wb_waveform_generator is
COMPONENT waveform_gen
PORT(
clk : IN std_logic;
reset : IN std_logic;
phase_inc : IN std_logic_vector(31 downto 0);
sin_out : OUT std_logic_vector(11 downto 0);
cos_out : OUT std_logic_vector(11 downto 0);
squ_out : OUT std_logic_vector(11 downto 0);
saw_out : OUT std_logic_vector(11 downto 0)
);
END COMPONENT;
COMPONENT AUDIO_zpuino_sa_sigmadeltaDAC
generic (
BITS: integer := 12
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end COMPONENT;
--Define your registers here
signal phase_inc_r : std_logic_vector(31 downto 0) := x"028c1980"; --x"028c1980" should give an output of 1Mhz. Wofram Alpha: x=10,y=(x*2^32)/(100 + .5)
-- signal waveform_sel: std_logic_vector(7 downto 0) := "00000010"; --Default to sine wave output
signal dac_in_s: std_logic_vector(11 downto 0);
signal sin_out_s: std_logic_vector(11 downto 0);
signal cos_out_s: std_logic_vector(11 downto 0);
signal squ_out_s: std_logic_vector(11 downto 0);
signal saw_out_s: std_logic_vector(11 downto 0);
-- signal register0: std_logic_vector(31 downto 0); -- Register 0 (32 bits)
-- signal register1: std_logic_vector(31 downto 0); -- Register 1 (32 bits)
-- signal register2: std_logic_vector(7 downto 0); -- Register 2 (8 bits)
--signal nReset : std_logic;
--Wishbone signals - Don't touch.
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- End unpacking Wishbone signals
--nReset <= not wb_rst_i;
-- Asynchronous acknowledge
wb_ack_o <= '1' when wb_cyc_i='1' and wb_stb_i='1' else '0';
-- Multiplex the data output (asynchronous)
process(phase_inc_r, wb_adr_i)
begin
-- Multiplex the read depending on the address. Use only the 2 lowest bits of addr
case wb_adr_i(3 downto 2) is
when "00" =>
wb_dat_o <= phase_inc_r; -- Output register0
-- when "01" =>
-- wb_dat_o(31 downto 0) <= (others => '0'); -- We put all upper 24 bits to zero
-- wb_dat_o(7 downto 0) <= waveform_sel; -- since register1 only has 8 bits
-- when "10" =>
-- wb_dat_o(31 downto 0) <= (others => '0'); -- We put all upper 24 bits to zero
-- wb_dat_o(7 downto 0) <= register2; -- since register2 only has 8 bits
when others =>
wb_dat_o <= (others => 'X'); -- Return undefined for all other addresses
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
if wb_rst_i='1' then
-- Reset request, put register1 and register2 with zeroes,
-- put register 3 with binary 10101010b
phase_inc_r <= (others => '0');
--waveform_sel <= (others => '0');
-- register2 <= "10101010";
else -- Not reset
-- Check if someone is writing
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
-- Yes, it's a write. See for which register based on address
case wb_adr_i(3 downto 2) is
when "00" =>
phase_inc_r <= wb_dat_i; -- Set register0
-- when "01" =>
-- waveform_sel <= wb_dat_i(7 downto 0); -- Set register1
-- when "10" =>
-- register2 <= wb_dat_i(7 downto 0); -- Only lower 8 bits for register2
when others =>
null; -- Nothing to do for other addresses
end case;
end if;
end if;
end if;
end process;
sin_out <= sin_out_s;
cos_out <= cos_out_s;
--squ_out <= squ_out_s;
saw_out <= saw_out_s;
Inst_waveform_gen: waveform_gen PORT MAP(
clk => wb_clk_i,
reset => '1',
phase_inc => phase_inc_r,
sin_out => sin_out_s,
cos_out => cos_out_s,
squ_out => squ_out_s,
saw_out => saw_out_s
);
Inst_dac1: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => sin_dac_out,
data_in => sin_out_s,
clk_96Mhz => clk_in
);
Inst_dac2: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => cos_dac_out,
data_in => cos_out_s,
clk_96Mhz => clk_in
);
Inst_dac3: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => squ_dac_out,
data_in => squ_out_s,
clk_96Mhz => clk_in
);
Inst_dac4: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => saw_dac_out,
data_in => saw_out_s,
clk_96Mhz => clk_in
);
-- process (waveform_sel,sin_out_s,cos_out_s,squ_out_s,saw_out_s)
-- begin
-- case waveform_sel(1 downto 0) is
-- when "00" => dac_in_s <= sin_out_s;
-- when "01" => dac_in_s <= cos_out_s;
-- when "10" => dac_in_s <= squ_out_s;
-- when "11" => dac_in_s <= saw_out_s;
-- when others => dac_in_s <= squ_out_s;
-- end case;
-- end process;
end rtl;
|
----------------------------------------------------------------------------------
-- Company: Gadget Factory
-- Engineer: Alvaro Lopes
--
-- Create Date: 13:56:50 12/10/2013
-- Design Name:
-- Module Name: TEMPLATE_zpuino_wb_Wishbone - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This is an example template to use for your own Wishbone Peripherals.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
-- This example uses asynchronous outputs.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity BENCHY_zpuino_wb_waveform_generator is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
clk_in : in STD_LOGIC;
sin_out : OUT std_logic_vector(11 downto 0);
cos_out : OUT std_logic_vector(11 downto 0);
--squ_out : OUT std_logic_vector(11 downto 0);
saw_out : OUT std_logic_vector(11 downto 0);
sin_dac_out : OUT std_logic;
cos_dac_out : OUT std_logic;
squ_dac_out : OUT std_logic;
saw_dac_out : OUT std_logic
--all_dac_out : OUT std_logic
);
end entity BENCHY_zpuino_wb_waveform_generator;
architecture rtl of BENCHY_zpuino_wb_waveform_generator is
COMPONENT waveform_gen
PORT(
clk : IN std_logic;
reset : IN std_logic;
phase_inc : IN std_logic_vector(31 downto 0);
sin_out : OUT std_logic_vector(11 downto 0);
cos_out : OUT std_logic_vector(11 downto 0);
squ_out : OUT std_logic_vector(11 downto 0);
saw_out : OUT std_logic_vector(11 downto 0)
);
END COMPONENT;
COMPONENT AUDIO_zpuino_sa_sigmadeltaDAC
generic (
BITS: integer := 12
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end COMPONENT;
--Define your registers here
signal phase_inc_r : std_logic_vector(31 downto 0) := x"028c1980"; --x"028c1980" should give an output of 1Mhz. Wofram Alpha: x=10,y=(x*2^32)/(100 + .5)
-- signal waveform_sel: std_logic_vector(7 downto 0) := "00000010"; --Default to sine wave output
signal dac_in_s: std_logic_vector(11 downto 0);
signal sin_out_s: std_logic_vector(11 downto 0);
signal cos_out_s: std_logic_vector(11 downto 0);
signal squ_out_s: std_logic_vector(11 downto 0);
signal saw_out_s: std_logic_vector(11 downto 0);
-- signal register0: std_logic_vector(31 downto 0); -- Register 0 (32 bits)
-- signal register1: std_logic_vector(31 downto 0); -- Register 1 (32 bits)
-- signal register2: std_logic_vector(7 downto 0); -- Register 2 (8 bits)
--signal nReset : std_logic;
--Wishbone signals - Don't touch.
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- End unpacking Wishbone signals
--nReset <= not wb_rst_i;
-- Asynchronous acknowledge
wb_ack_o <= '1' when wb_cyc_i='1' and wb_stb_i='1' else '0';
-- Multiplex the data output (asynchronous)
process(phase_inc_r, wb_adr_i)
begin
-- Multiplex the read depending on the address. Use only the 2 lowest bits of addr
case wb_adr_i(3 downto 2) is
when "00" =>
wb_dat_o <= phase_inc_r; -- Output register0
-- when "01" =>
-- wb_dat_o(31 downto 0) <= (others => '0'); -- We put all upper 24 bits to zero
-- wb_dat_o(7 downto 0) <= waveform_sel; -- since register1 only has 8 bits
-- when "10" =>
-- wb_dat_o(31 downto 0) <= (others => '0'); -- We put all upper 24 bits to zero
-- wb_dat_o(7 downto 0) <= register2; -- since register2 only has 8 bits
when others =>
wb_dat_o <= (others => 'X'); -- Return undefined for all other addresses
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
if wb_rst_i='1' then
-- Reset request, put register1 and register2 with zeroes,
-- put register 3 with binary 10101010b
phase_inc_r <= (others => '0');
--waveform_sel <= (others => '0');
-- register2 <= "10101010";
else -- Not reset
-- Check if someone is writing
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
-- Yes, it's a write. See for which register based on address
case wb_adr_i(3 downto 2) is
when "00" =>
phase_inc_r <= wb_dat_i; -- Set register0
-- when "01" =>
-- waveform_sel <= wb_dat_i(7 downto 0); -- Set register1
-- when "10" =>
-- register2 <= wb_dat_i(7 downto 0); -- Only lower 8 bits for register2
when others =>
null; -- Nothing to do for other addresses
end case;
end if;
end if;
end if;
end process;
sin_out <= sin_out_s;
cos_out <= cos_out_s;
--squ_out <= squ_out_s;
saw_out <= saw_out_s;
Inst_waveform_gen: waveform_gen PORT MAP(
clk => wb_clk_i,
reset => '1',
phase_inc => phase_inc_r,
sin_out => sin_out_s,
cos_out => cos_out_s,
squ_out => squ_out_s,
saw_out => saw_out_s
);
Inst_dac1: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => sin_dac_out,
data_in => sin_out_s,
clk_96Mhz => clk_in
);
Inst_dac2: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => cos_dac_out,
data_in => cos_out_s,
clk_96Mhz => clk_in
);
Inst_dac3: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => squ_dac_out,
data_in => squ_out_s,
clk_96Mhz => clk_in
);
Inst_dac4: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => saw_dac_out,
data_in => saw_out_s,
clk_96Mhz => clk_in
);
-- process (waveform_sel,sin_out_s,cos_out_s,squ_out_s,saw_out_s)
-- begin
-- case waveform_sel(1 downto 0) is
-- when "00" => dac_in_s <= sin_out_s;
-- when "01" => dac_in_s <= cos_out_s;
-- when "10" => dac_in_s <= squ_out_s;
-- when "11" => dac_in_s <= saw_out_s;
-- when others => dac_in_s <= squ_out_s;
-- end case;
-- end process;
end rtl;
|
----------------------------------------------------------------------------------
-- Company: Gadget Factory
-- Engineer: Alvaro Lopes
--
-- Create Date: 13:56:50 12/10/2013
-- Design Name:
-- Module Name: TEMPLATE_zpuino_wb_Wishbone - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This is an example template to use for your own Wishbone Peripherals.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
-- This example uses asynchronous outputs.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity BENCHY_zpuino_wb_waveform_generator is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
clk_in : in STD_LOGIC;
sin_out : OUT std_logic_vector(11 downto 0);
cos_out : OUT std_logic_vector(11 downto 0);
--squ_out : OUT std_logic_vector(11 downto 0);
saw_out : OUT std_logic_vector(11 downto 0);
sin_dac_out : OUT std_logic;
cos_dac_out : OUT std_logic;
squ_dac_out : OUT std_logic;
saw_dac_out : OUT std_logic
--all_dac_out : OUT std_logic
);
end entity BENCHY_zpuino_wb_waveform_generator;
architecture rtl of BENCHY_zpuino_wb_waveform_generator is
COMPONENT waveform_gen
PORT(
clk : IN std_logic;
reset : IN std_logic;
phase_inc : IN std_logic_vector(31 downto 0);
sin_out : OUT std_logic_vector(11 downto 0);
cos_out : OUT std_logic_vector(11 downto 0);
squ_out : OUT std_logic_vector(11 downto 0);
saw_out : OUT std_logic_vector(11 downto 0)
);
END COMPONENT;
COMPONENT AUDIO_zpuino_sa_sigmadeltaDAC
generic (
BITS: integer := 12
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end COMPONENT;
--Define your registers here
signal phase_inc_r : std_logic_vector(31 downto 0) := x"028c1980"; --x"028c1980" should give an output of 1Mhz. Wofram Alpha: x=10,y=(x*2^32)/(100 + .5)
-- signal waveform_sel: std_logic_vector(7 downto 0) := "00000010"; --Default to sine wave output
signal dac_in_s: std_logic_vector(11 downto 0);
signal sin_out_s: std_logic_vector(11 downto 0);
signal cos_out_s: std_logic_vector(11 downto 0);
signal squ_out_s: std_logic_vector(11 downto 0);
signal saw_out_s: std_logic_vector(11 downto 0);
-- signal register0: std_logic_vector(31 downto 0); -- Register 0 (32 bits)
-- signal register1: std_logic_vector(31 downto 0); -- Register 1 (32 bits)
-- signal register2: std_logic_vector(7 downto 0); -- Register 2 (8 bits)
--signal nReset : std_logic;
--Wishbone signals - Don't touch.
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- End unpacking Wishbone signals
--nReset <= not wb_rst_i;
-- Asynchronous acknowledge
wb_ack_o <= '1' when wb_cyc_i='1' and wb_stb_i='1' else '0';
-- Multiplex the data output (asynchronous)
process(phase_inc_r, wb_adr_i)
begin
-- Multiplex the read depending on the address. Use only the 2 lowest bits of addr
case wb_adr_i(3 downto 2) is
when "00" =>
wb_dat_o <= phase_inc_r; -- Output register0
-- when "01" =>
-- wb_dat_o(31 downto 0) <= (others => '0'); -- We put all upper 24 bits to zero
-- wb_dat_o(7 downto 0) <= waveform_sel; -- since register1 only has 8 bits
-- when "10" =>
-- wb_dat_o(31 downto 0) <= (others => '0'); -- We put all upper 24 bits to zero
-- wb_dat_o(7 downto 0) <= register2; -- since register2 only has 8 bits
when others =>
wb_dat_o <= (others => 'X'); -- Return undefined for all other addresses
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
if wb_rst_i='1' then
-- Reset request, put register1 and register2 with zeroes,
-- put register 3 with binary 10101010b
phase_inc_r <= (others => '0');
--waveform_sel <= (others => '0');
-- register2 <= "10101010";
else -- Not reset
-- Check if someone is writing
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
-- Yes, it's a write. See for which register based on address
case wb_adr_i(3 downto 2) is
when "00" =>
phase_inc_r <= wb_dat_i; -- Set register0
-- when "01" =>
-- waveform_sel <= wb_dat_i(7 downto 0); -- Set register1
-- when "10" =>
-- register2 <= wb_dat_i(7 downto 0); -- Only lower 8 bits for register2
when others =>
null; -- Nothing to do for other addresses
end case;
end if;
end if;
end if;
end process;
sin_out <= sin_out_s;
cos_out <= cos_out_s;
--squ_out <= squ_out_s;
saw_out <= saw_out_s;
Inst_waveform_gen: waveform_gen PORT MAP(
clk => wb_clk_i,
reset => '1',
phase_inc => phase_inc_r,
sin_out => sin_out_s,
cos_out => cos_out_s,
squ_out => squ_out_s,
saw_out => saw_out_s
);
Inst_dac1: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => sin_dac_out,
data_in => sin_out_s,
clk_96Mhz => clk_in
);
Inst_dac2: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => cos_dac_out,
data_in => cos_out_s,
clk_96Mhz => clk_in
);
Inst_dac3: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => squ_dac_out,
data_in => squ_out_s,
clk_96Mhz => clk_in
);
Inst_dac4: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => saw_dac_out,
data_in => saw_out_s,
clk_96Mhz => clk_in
);
-- process (waveform_sel,sin_out_s,cos_out_s,squ_out_s,saw_out_s)
-- begin
-- case waveform_sel(1 downto 0) is
-- when "00" => dac_in_s <= sin_out_s;
-- when "01" => dac_in_s <= cos_out_s;
-- when "10" => dac_in_s <= squ_out_s;
-- when "11" => dac_in_s <= saw_out_s;
-- when others => dac_in_s <= squ_out_s;
-- end case;
-- end process;
end rtl;
|
----------------------------------------------------------------------------------
-- Company: Gadget Factory
-- Engineer: Alvaro Lopes
--
-- Create Date: 13:56:50 12/10/2013
-- Design Name:
-- Module Name: TEMPLATE_zpuino_wb_Wishbone - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This is an example template to use for your own Wishbone Peripherals.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
-- This example uses asynchronous outputs.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity BENCHY_zpuino_wb_waveform_generator is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
clk_in : in STD_LOGIC;
sin_out : OUT std_logic_vector(11 downto 0);
cos_out : OUT std_logic_vector(11 downto 0);
--squ_out : OUT std_logic_vector(11 downto 0);
saw_out : OUT std_logic_vector(11 downto 0);
sin_dac_out : OUT std_logic;
cos_dac_out : OUT std_logic;
squ_dac_out : OUT std_logic;
saw_dac_out : OUT std_logic
--all_dac_out : OUT std_logic
);
end entity BENCHY_zpuino_wb_waveform_generator;
architecture rtl of BENCHY_zpuino_wb_waveform_generator is
COMPONENT waveform_gen
PORT(
clk : IN std_logic;
reset : IN std_logic;
phase_inc : IN std_logic_vector(31 downto 0);
sin_out : OUT std_logic_vector(11 downto 0);
cos_out : OUT std_logic_vector(11 downto 0);
squ_out : OUT std_logic_vector(11 downto 0);
saw_out : OUT std_logic_vector(11 downto 0)
);
END COMPONENT;
COMPONENT AUDIO_zpuino_sa_sigmadeltaDAC
generic (
BITS: integer := 12
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end COMPONENT;
--Define your registers here
signal phase_inc_r : std_logic_vector(31 downto 0) := x"028c1980"; --x"028c1980" should give an output of 1Mhz. Wofram Alpha: x=10,y=(x*2^32)/(100 + .5)
-- signal waveform_sel: std_logic_vector(7 downto 0) := "00000010"; --Default to sine wave output
signal dac_in_s: std_logic_vector(11 downto 0);
signal sin_out_s: std_logic_vector(11 downto 0);
signal cos_out_s: std_logic_vector(11 downto 0);
signal squ_out_s: std_logic_vector(11 downto 0);
signal saw_out_s: std_logic_vector(11 downto 0);
-- signal register0: std_logic_vector(31 downto 0); -- Register 0 (32 bits)
-- signal register1: std_logic_vector(31 downto 0); -- Register 1 (32 bits)
-- signal register2: std_logic_vector(7 downto 0); -- Register 2 (8 bits)
--signal nReset : std_logic;
--Wishbone signals - Don't touch.
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- End unpacking Wishbone signals
--nReset <= not wb_rst_i;
-- Asynchronous acknowledge
wb_ack_o <= '1' when wb_cyc_i='1' and wb_stb_i='1' else '0';
-- Multiplex the data output (asynchronous)
process(phase_inc_r, wb_adr_i)
begin
-- Multiplex the read depending on the address. Use only the 2 lowest bits of addr
case wb_adr_i(3 downto 2) is
when "00" =>
wb_dat_o <= phase_inc_r; -- Output register0
-- when "01" =>
-- wb_dat_o(31 downto 0) <= (others => '0'); -- We put all upper 24 bits to zero
-- wb_dat_o(7 downto 0) <= waveform_sel; -- since register1 only has 8 bits
-- when "10" =>
-- wb_dat_o(31 downto 0) <= (others => '0'); -- We put all upper 24 bits to zero
-- wb_dat_o(7 downto 0) <= register2; -- since register2 only has 8 bits
when others =>
wb_dat_o <= (others => 'X'); -- Return undefined for all other addresses
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
if wb_rst_i='1' then
-- Reset request, put register1 and register2 with zeroes,
-- put register 3 with binary 10101010b
phase_inc_r <= (others => '0');
--waveform_sel <= (others => '0');
-- register2 <= "10101010";
else -- Not reset
-- Check if someone is writing
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
-- Yes, it's a write. See for which register based on address
case wb_adr_i(3 downto 2) is
when "00" =>
phase_inc_r <= wb_dat_i; -- Set register0
-- when "01" =>
-- waveform_sel <= wb_dat_i(7 downto 0); -- Set register1
-- when "10" =>
-- register2 <= wb_dat_i(7 downto 0); -- Only lower 8 bits for register2
when others =>
null; -- Nothing to do for other addresses
end case;
end if;
end if;
end if;
end process;
sin_out <= sin_out_s;
cos_out <= cos_out_s;
--squ_out <= squ_out_s;
saw_out <= saw_out_s;
Inst_waveform_gen: waveform_gen PORT MAP(
clk => wb_clk_i,
reset => '1',
phase_inc => phase_inc_r,
sin_out => sin_out_s,
cos_out => cos_out_s,
squ_out => squ_out_s,
saw_out => saw_out_s
);
Inst_dac1: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => sin_dac_out,
data_in => sin_out_s,
clk_96Mhz => clk_in
);
Inst_dac2: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => cos_dac_out,
data_in => cos_out_s,
clk_96Mhz => clk_in
);
Inst_dac3: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => squ_dac_out,
data_in => squ_out_s,
clk_96Mhz => clk_in
);
Inst_dac4: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => saw_dac_out,
data_in => saw_out_s,
clk_96Mhz => clk_in
);
-- process (waveform_sel,sin_out_s,cos_out_s,squ_out_s,saw_out_s)
-- begin
-- case waveform_sel(1 downto 0) is
-- when "00" => dac_in_s <= sin_out_s;
-- when "01" => dac_in_s <= cos_out_s;
-- when "10" => dac_in_s <= squ_out_s;
-- when "11" => dac_in_s <= saw_out_s;
-- when others => dac_in_s <= squ_out_s;
-- end case;
-- end process;
end rtl;
|
----------------------------------------------------------------------------------
-- Company: Gadget Factory
-- Engineer: Alvaro Lopes
--
-- Create Date: 13:56:50 12/10/2013
-- Design Name:
-- Module Name: TEMPLATE_zpuino_wb_Wishbone - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This is an example template to use for your own Wishbone Peripherals.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
-- This example uses asynchronous outputs.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity BENCHY_zpuino_wb_waveform_generator is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
clk_in : in STD_LOGIC;
sin_out : OUT std_logic_vector(11 downto 0);
cos_out : OUT std_logic_vector(11 downto 0);
--squ_out : OUT std_logic_vector(11 downto 0);
saw_out : OUT std_logic_vector(11 downto 0);
sin_dac_out : OUT std_logic;
cos_dac_out : OUT std_logic;
squ_dac_out : OUT std_logic;
saw_dac_out : OUT std_logic
--all_dac_out : OUT std_logic
);
end entity BENCHY_zpuino_wb_waveform_generator;
architecture rtl of BENCHY_zpuino_wb_waveform_generator is
COMPONENT waveform_gen
PORT(
clk : IN std_logic;
reset : IN std_logic;
phase_inc : IN std_logic_vector(31 downto 0);
sin_out : OUT std_logic_vector(11 downto 0);
cos_out : OUT std_logic_vector(11 downto 0);
squ_out : OUT std_logic_vector(11 downto 0);
saw_out : OUT std_logic_vector(11 downto 0)
);
END COMPONENT;
COMPONENT AUDIO_zpuino_sa_sigmadeltaDAC
generic (
BITS: integer := 12
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end COMPONENT;
--Define your registers here
signal phase_inc_r : std_logic_vector(31 downto 0) := x"028c1980"; --x"028c1980" should give an output of 1Mhz. Wofram Alpha: x=10,y=(x*2^32)/(100 + .5)
-- signal waveform_sel: std_logic_vector(7 downto 0) := "00000010"; --Default to sine wave output
signal dac_in_s: std_logic_vector(11 downto 0);
signal sin_out_s: std_logic_vector(11 downto 0);
signal cos_out_s: std_logic_vector(11 downto 0);
signal squ_out_s: std_logic_vector(11 downto 0);
signal saw_out_s: std_logic_vector(11 downto 0);
-- signal register0: std_logic_vector(31 downto 0); -- Register 0 (32 bits)
-- signal register1: std_logic_vector(31 downto 0); -- Register 1 (32 bits)
-- signal register2: std_logic_vector(7 downto 0); -- Register 2 (8 bits)
--signal nReset : std_logic;
--Wishbone signals - Don't touch.
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- End unpacking Wishbone signals
--nReset <= not wb_rst_i;
-- Asynchronous acknowledge
wb_ack_o <= '1' when wb_cyc_i='1' and wb_stb_i='1' else '0';
-- Multiplex the data output (asynchronous)
process(phase_inc_r, wb_adr_i)
begin
-- Multiplex the read depending on the address. Use only the 2 lowest bits of addr
case wb_adr_i(3 downto 2) is
when "00" =>
wb_dat_o <= phase_inc_r; -- Output register0
-- when "01" =>
-- wb_dat_o(31 downto 0) <= (others => '0'); -- We put all upper 24 bits to zero
-- wb_dat_o(7 downto 0) <= waveform_sel; -- since register1 only has 8 bits
-- when "10" =>
-- wb_dat_o(31 downto 0) <= (others => '0'); -- We put all upper 24 bits to zero
-- wb_dat_o(7 downto 0) <= register2; -- since register2 only has 8 bits
when others =>
wb_dat_o <= (others => 'X'); -- Return undefined for all other addresses
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
if wb_rst_i='1' then
-- Reset request, put register1 and register2 with zeroes,
-- put register 3 with binary 10101010b
phase_inc_r <= (others => '0');
--waveform_sel <= (others => '0');
-- register2 <= "10101010";
else -- Not reset
-- Check if someone is writing
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
-- Yes, it's a write. See for which register based on address
case wb_adr_i(3 downto 2) is
when "00" =>
phase_inc_r <= wb_dat_i; -- Set register0
-- when "01" =>
-- waveform_sel <= wb_dat_i(7 downto 0); -- Set register1
-- when "10" =>
-- register2 <= wb_dat_i(7 downto 0); -- Only lower 8 bits for register2
when others =>
null; -- Nothing to do for other addresses
end case;
end if;
end if;
end if;
end process;
sin_out <= sin_out_s;
cos_out <= cos_out_s;
--squ_out <= squ_out_s;
saw_out <= saw_out_s;
Inst_waveform_gen: waveform_gen PORT MAP(
clk => wb_clk_i,
reset => '1',
phase_inc => phase_inc_r,
sin_out => sin_out_s,
cos_out => cos_out_s,
squ_out => squ_out_s,
saw_out => saw_out_s
);
Inst_dac1: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => sin_dac_out,
data_in => sin_out_s,
clk_96Mhz => clk_in
);
Inst_dac2: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => cos_dac_out,
data_in => cos_out_s,
clk_96Mhz => clk_in
);
Inst_dac3: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => squ_dac_out,
data_in => squ_out_s,
clk_96Mhz => clk_in
);
Inst_dac4: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => saw_dac_out,
data_in => saw_out_s,
clk_96Mhz => clk_in
);
-- process (waveform_sel,sin_out_s,cos_out_s,squ_out_s,saw_out_s)
-- begin
-- case waveform_sel(1 downto 0) is
-- when "00" => dac_in_s <= sin_out_s;
-- when "01" => dac_in_s <= cos_out_s;
-- when "10" => dac_in_s <= squ_out_s;
-- when "11" => dac_in_s <= saw_out_s;
-- when others => dac_in_s <= squ_out_s;
-- end case;
-- end process;
end rtl;
|
----------------------------------------------------------------------------------
-- Company: Gadget Factory
-- Engineer: Alvaro Lopes
--
-- Create Date: 13:56:50 12/10/2013
-- Design Name:
-- Module Name: TEMPLATE_zpuino_wb_Wishbone - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This is an example template to use for your own Wishbone Peripherals.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
-- This example uses asynchronous outputs.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity BENCHY_zpuino_wb_waveform_generator is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
clk_in : in STD_LOGIC;
sin_out : OUT std_logic_vector(11 downto 0);
cos_out : OUT std_logic_vector(11 downto 0);
--squ_out : OUT std_logic_vector(11 downto 0);
saw_out : OUT std_logic_vector(11 downto 0);
sin_dac_out : OUT std_logic;
cos_dac_out : OUT std_logic;
squ_dac_out : OUT std_logic;
saw_dac_out : OUT std_logic
--all_dac_out : OUT std_logic
);
end entity BENCHY_zpuino_wb_waveform_generator;
architecture rtl of BENCHY_zpuino_wb_waveform_generator is
COMPONENT waveform_gen
PORT(
clk : IN std_logic;
reset : IN std_logic;
phase_inc : IN std_logic_vector(31 downto 0);
sin_out : OUT std_logic_vector(11 downto 0);
cos_out : OUT std_logic_vector(11 downto 0);
squ_out : OUT std_logic_vector(11 downto 0);
saw_out : OUT std_logic_vector(11 downto 0)
);
END COMPONENT;
COMPONENT AUDIO_zpuino_sa_sigmadeltaDAC
generic (
BITS: integer := 12
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end COMPONENT;
--Define your registers here
signal phase_inc_r : std_logic_vector(31 downto 0) := x"028c1980"; --x"028c1980" should give an output of 1Mhz. Wofram Alpha: x=10,y=(x*2^32)/(100 + .5)
-- signal waveform_sel: std_logic_vector(7 downto 0) := "00000010"; --Default to sine wave output
signal dac_in_s: std_logic_vector(11 downto 0);
signal sin_out_s: std_logic_vector(11 downto 0);
signal cos_out_s: std_logic_vector(11 downto 0);
signal squ_out_s: std_logic_vector(11 downto 0);
signal saw_out_s: std_logic_vector(11 downto 0);
-- signal register0: std_logic_vector(31 downto 0); -- Register 0 (32 bits)
-- signal register1: std_logic_vector(31 downto 0); -- Register 1 (32 bits)
-- signal register2: std_logic_vector(7 downto 0); -- Register 2 (8 bits)
--signal nReset : std_logic;
--Wishbone signals - Don't touch.
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- End unpacking Wishbone signals
--nReset <= not wb_rst_i;
-- Asynchronous acknowledge
wb_ack_o <= '1' when wb_cyc_i='1' and wb_stb_i='1' else '0';
-- Multiplex the data output (asynchronous)
process(phase_inc_r, wb_adr_i)
begin
-- Multiplex the read depending on the address. Use only the 2 lowest bits of addr
case wb_adr_i(3 downto 2) is
when "00" =>
wb_dat_o <= phase_inc_r; -- Output register0
-- when "01" =>
-- wb_dat_o(31 downto 0) <= (others => '0'); -- We put all upper 24 bits to zero
-- wb_dat_o(7 downto 0) <= waveform_sel; -- since register1 only has 8 bits
-- when "10" =>
-- wb_dat_o(31 downto 0) <= (others => '0'); -- We put all upper 24 bits to zero
-- wb_dat_o(7 downto 0) <= register2; -- since register2 only has 8 bits
when others =>
wb_dat_o <= (others => 'X'); -- Return undefined for all other addresses
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
if wb_rst_i='1' then
-- Reset request, put register1 and register2 with zeroes,
-- put register 3 with binary 10101010b
phase_inc_r <= (others => '0');
--waveform_sel <= (others => '0');
-- register2 <= "10101010";
else -- Not reset
-- Check if someone is writing
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
-- Yes, it's a write. See for which register based on address
case wb_adr_i(3 downto 2) is
when "00" =>
phase_inc_r <= wb_dat_i; -- Set register0
-- when "01" =>
-- waveform_sel <= wb_dat_i(7 downto 0); -- Set register1
-- when "10" =>
-- register2 <= wb_dat_i(7 downto 0); -- Only lower 8 bits for register2
when others =>
null; -- Nothing to do for other addresses
end case;
end if;
end if;
end if;
end process;
sin_out <= sin_out_s;
cos_out <= cos_out_s;
--squ_out <= squ_out_s;
saw_out <= saw_out_s;
Inst_waveform_gen: waveform_gen PORT MAP(
clk => wb_clk_i,
reset => '1',
phase_inc => phase_inc_r,
sin_out => sin_out_s,
cos_out => cos_out_s,
squ_out => squ_out_s,
saw_out => saw_out_s
);
Inst_dac1: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => sin_dac_out,
data_in => sin_out_s,
clk_96Mhz => clk_in
);
Inst_dac2: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => cos_dac_out,
data_in => cos_out_s,
clk_96Mhz => clk_in
);
Inst_dac3: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => squ_dac_out,
data_in => squ_out_s,
clk_96Mhz => clk_in
);
Inst_dac4: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => saw_dac_out,
data_in => saw_out_s,
clk_96Mhz => clk_in
);
-- process (waveform_sel,sin_out_s,cos_out_s,squ_out_s,saw_out_s)
-- begin
-- case waveform_sel(1 downto 0) is
-- when "00" => dac_in_s <= sin_out_s;
-- when "01" => dac_in_s <= cos_out_s;
-- when "10" => dac_in_s <= squ_out_s;
-- when "11" => dac_in_s <= saw_out_s;
-- when others => dac_in_s <= squ_out_s;
-- end case;
-- end process;
end rtl;
|
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