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----------------------------------------------------------------------------------
-- Company: Gadget Factory
-- Engineer: Alvaro Lopes
--
-- Create Date: 13:56:50 12/10/2013
-- Design Name:
-- Module Name: TEMPLATE_zpuino_wb_Wishbone - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This is an example template to use for your own Wishbone Peripherals.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
-- This example uses asynchronous outputs.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity BENCHY_zpuino_wb_waveform_generator is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
clk_in : in STD_LOGIC;
sin_out : OUT std_logic_vector(11 downto 0);
cos_out : OUT std_logic_vector(11 downto 0);
--squ_out : OUT std_logic_vector(11 downto 0);
saw_out : OUT std_logic_vector(11 downto 0);
sin_dac_out : OUT std_logic;
cos_dac_out : OUT std_logic;
squ_dac_out : OUT std_logic;
saw_dac_out : OUT std_logic
--all_dac_out : OUT std_logic
);
end entity BENCHY_zpuino_wb_waveform_generator;
architecture rtl of BENCHY_zpuino_wb_waveform_generator is
COMPONENT waveform_gen
PORT(
clk : IN std_logic;
reset : IN std_logic;
phase_inc : IN std_logic_vector(31 downto 0);
sin_out : OUT std_logic_vector(11 downto 0);
cos_out : OUT std_logic_vector(11 downto 0);
squ_out : OUT std_logic_vector(11 downto 0);
saw_out : OUT std_logic_vector(11 downto 0)
);
END COMPONENT;
COMPONENT AUDIO_zpuino_sa_sigmadeltaDAC
generic (
BITS: integer := 12
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end COMPONENT;
--Define your registers here
signal phase_inc_r : std_logic_vector(31 downto 0) := x"028c1980"; --x"028c1980" should give an output of 1Mhz. Wofram Alpha: x=10,y=(x*2^32)/(100 + .5)
-- signal waveform_sel: std_logic_vector(7 downto 0) := "00000010"; --Default to sine wave output
signal dac_in_s: std_logic_vector(11 downto 0);
signal sin_out_s: std_logic_vector(11 downto 0);
signal cos_out_s: std_logic_vector(11 downto 0);
signal squ_out_s: std_logic_vector(11 downto 0);
signal saw_out_s: std_logic_vector(11 downto 0);
-- signal register0: std_logic_vector(31 downto 0); -- Register 0 (32 bits)
-- signal register1: std_logic_vector(31 downto 0); -- Register 1 (32 bits)
-- signal register2: std_logic_vector(7 downto 0); -- Register 2 (8 bits)
--signal nReset : std_logic;
--Wishbone signals - Don't touch.
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- End unpacking Wishbone signals
--nReset <= not wb_rst_i;
-- Asynchronous acknowledge
wb_ack_o <= '1' when wb_cyc_i='1' and wb_stb_i='1' else '0';
-- Multiplex the data output (asynchronous)
process(phase_inc_r, wb_adr_i)
begin
-- Multiplex the read depending on the address. Use only the 2 lowest bits of addr
case wb_adr_i(3 downto 2) is
when "00" =>
wb_dat_o <= phase_inc_r; -- Output register0
-- when "01" =>
-- wb_dat_o(31 downto 0) <= (others => '0'); -- We put all upper 24 bits to zero
-- wb_dat_o(7 downto 0) <= waveform_sel; -- since register1 only has 8 bits
-- when "10" =>
-- wb_dat_o(31 downto 0) <= (others => '0'); -- We put all upper 24 bits to zero
-- wb_dat_o(7 downto 0) <= register2; -- since register2 only has 8 bits
when others =>
wb_dat_o <= (others => 'X'); -- Return undefined for all other addresses
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
if wb_rst_i='1' then
-- Reset request, put register1 and register2 with zeroes,
-- put register 3 with binary 10101010b
phase_inc_r <= (others => '0');
--waveform_sel <= (others => '0');
-- register2 <= "10101010";
else -- Not reset
-- Check if someone is writing
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
-- Yes, it's a write. See for which register based on address
case wb_adr_i(3 downto 2) is
when "00" =>
phase_inc_r <= wb_dat_i; -- Set register0
-- when "01" =>
-- waveform_sel <= wb_dat_i(7 downto 0); -- Set register1
-- when "10" =>
-- register2 <= wb_dat_i(7 downto 0); -- Only lower 8 bits for register2
when others =>
null; -- Nothing to do for other addresses
end case;
end if;
end if;
end if;
end process;
sin_out <= sin_out_s;
cos_out <= cos_out_s;
--squ_out <= squ_out_s;
saw_out <= saw_out_s;
Inst_waveform_gen: waveform_gen PORT MAP(
clk => wb_clk_i,
reset => '1',
phase_inc => phase_inc_r,
sin_out => sin_out_s,
cos_out => cos_out_s,
squ_out => squ_out_s,
saw_out => saw_out_s
);
Inst_dac1: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => sin_dac_out,
data_in => sin_out_s,
clk_96Mhz => clk_in
);
Inst_dac2: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => cos_dac_out,
data_in => cos_out_s,
clk_96Mhz => clk_in
);
Inst_dac3: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => squ_dac_out,
data_in => squ_out_s,
clk_96Mhz => clk_in
);
Inst_dac4: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => saw_dac_out,
data_in => saw_out_s,
clk_96Mhz => clk_in
);
-- process (waveform_sel,sin_out_s,cos_out_s,squ_out_s,saw_out_s)
-- begin
-- case waveform_sel(1 downto 0) is
-- when "00" => dac_in_s <= sin_out_s;
-- when "01" => dac_in_s <= cos_out_s;
-- when "10" => dac_in_s <= squ_out_s;
-- when "11" => dac_in_s <= saw_out_s;
-- when others => dac_in_s <= squ_out_s;
-- end case;
-- end process;
end rtl;
|
----------------------------------------------------------------------------------
-- Company: Gadget Factory
-- Engineer: Alvaro Lopes
--
-- Create Date: 13:56:50 12/10/2013
-- Design Name:
-- Module Name: TEMPLATE_zpuino_wb_Wishbone - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This is an example template to use for your own Wishbone Peripherals.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
-- This example uses asynchronous outputs.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity BENCHY_zpuino_wb_waveform_generator is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
clk_in : in STD_LOGIC;
sin_out : OUT std_logic_vector(11 downto 0);
cos_out : OUT std_logic_vector(11 downto 0);
--squ_out : OUT std_logic_vector(11 downto 0);
saw_out : OUT std_logic_vector(11 downto 0);
sin_dac_out : OUT std_logic;
cos_dac_out : OUT std_logic;
squ_dac_out : OUT std_logic;
saw_dac_out : OUT std_logic
--all_dac_out : OUT std_logic
);
end entity BENCHY_zpuino_wb_waveform_generator;
architecture rtl of BENCHY_zpuino_wb_waveform_generator is
COMPONENT waveform_gen
PORT(
clk : IN std_logic;
reset : IN std_logic;
phase_inc : IN std_logic_vector(31 downto 0);
sin_out : OUT std_logic_vector(11 downto 0);
cos_out : OUT std_logic_vector(11 downto 0);
squ_out : OUT std_logic_vector(11 downto 0);
saw_out : OUT std_logic_vector(11 downto 0)
);
END COMPONENT;
COMPONENT AUDIO_zpuino_sa_sigmadeltaDAC
generic (
BITS: integer := 12
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end COMPONENT;
--Define your registers here
signal phase_inc_r : std_logic_vector(31 downto 0) := x"028c1980"; --x"028c1980" should give an output of 1Mhz. Wofram Alpha: x=10,y=(x*2^32)/(100 + .5)
-- signal waveform_sel: std_logic_vector(7 downto 0) := "00000010"; --Default to sine wave output
signal dac_in_s: std_logic_vector(11 downto 0);
signal sin_out_s: std_logic_vector(11 downto 0);
signal cos_out_s: std_logic_vector(11 downto 0);
signal squ_out_s: std_logic_vector(11 downto 0);
signal saw_out_s: std_logic_vector(11 downto 0);
-- signal register0: std_logic_vector(31 downto 0); -- Register 0 (32 bits)
-- signal register1: std_logic_vector(31 downto 0); -- Register 1 (32 bits)
-- signal register2: std_logic_vector(7 downto 0); -- Register 2 (8 bits)
--signal nReset : std_logic;
--Wishbone signals - Don't touch.
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- End unpacking Wishbone signals
--nReset <= not wb_rst_i;
-- Asynchronous acknowledge
wb_ack_o <= '1' when wb_cyc_i='1' and wb_stb_i='1' else '0';
-- Multiplex the data output (asynchronous)
process(phase_inc_r, wb_adr_i)
begin
-- Multiplex the read depending on the address. Use only the 2 lowest bits of addr
case wb_adr_i(3 downto 2) is
when "00" =>
wb_dat_o <= phase_inc_r; -- Output register0
-- when "01" =>
-- wb_dat_o(31 downto 0) <= (others => '0'); -- We put all upper 24 bits to zero
-- wb_dat_o(7 downto 0) <= waveform_sel; -- since register1 only has 8 bits
-- when "10" =>
-- wb_dat_o(31 downto 0) <= (others => '0'); -- We put all upper 24 bits to zero
-- wb_dat_o(7 downto 0) <= register2; -- since register2 only has 8 bits
when others =>
wb_dat_o <= (others => 'X'); -- Return undefined for all other addresses
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
if wb_rst_i='1' then
-- Reset request, put register1 and register2 with zeroes,
-- put register 3 with binary 10101010b
phase_inc_r <= (others => '0');
--waveform_sel <= (others => '0');
-- register2 <= "10101010";
else -- Not reset
-- Check if someone is writing
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
-- Yes, it's a write. See for which register based on address
case wb_adr_i(3 downto 2) is
when "00" =>
phase_inc_r <= wb_dat_i; -- Set register0
-- when "01" =>
-- waveform_sel <= wb_dat_i(7 downto 0); -- Set register1
-- when "10" =>
-- register2 <= wb_dat_i(7 downto 0); -- Only lower 8 bits for register2
when others =>
null; -- Nothing to do for other addresses
end case;
end if;
end if;
end if;
end process;
sin_out <= sin_out_s;
cos_out <= cos_out_s;
--squ_out <= squ_out_s;
saw_out <= saw_out_s;
Inst_waveform_gen: waveform_gen PORT MAP(
clk => wb_clk_i,
reset => '1',
phase_inc => phase_inc_r,
sin_out => sin_out_s,
cos_out => cos_out_s,
squ_out => squ_out_s,
saw_out => saw_out_s
);
Inst_dac1: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => sin_dac_out,
data_in => sin_out_s,
clk_96Mhz => clk_in
);
Inst_dac2: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => cos_dac_out,
data_in => cos_out_s,
clk_96Mhz => clk_in
);
Inst_dac3: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => squ_dac_out,
data_in => squ_out_s,
clk_96Mhz => clk_in
);
Inst_dac4: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => saw_dac_out,
data_in => saw_out_s,
clk_96Mhz => clk_in
);
-- process (waveform_sel,sin_out_s,cos_out_s,squ_out_s,saw_out_s)
-- begin
-- case waveform_sel(1 downto 0) is
-- when "00" => dac_in_s <= sin_out_s;
-- when "01" => dac_in_s <= cos_out_s;
-- when "10" => dac_in_s <= squ_out_s;
-- when "11" => dac_in_s <= saw_out_s;
-- when others => dac_in_s <= squ_out_s;
-- end case;
-- end process;
end rtl;
|
----------------------------------------------------------------------------------
-- Company: Gadget Factory
-- Engineer: Alvaro Lopes
--
-- Create Date: 13:56:50 12/10/2013
-- Design Name:
-- Module Name: TEMPLATE_zpuino_wb_Wishbone - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This is an example template to use for your own Wishbone Peripherals.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
-- This example uses asynchronous outputs.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity BENCHY_zpuino_wb_waveform_generator is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
clk_in : in STD_LOGIC;
sin_out : OUT std_logic_vector(11 downto 0);
cos_out : OUT std_logic_vector(11 downto 0);
--squ_out : OUT std_logic_vector(11 downto 0);
saw_out : OUT std_logic_vector(11 downto 0);
sin_dac_out : OUT std_logic;
cos_dac_out : OUT std_logic;
squ_dac_out : OUT std_logic;
saw_dac_out : OUT std_logic
--all_dac_out : OUT std_logic
);
end entity BENCHY_zpuino_wb_waveform_generator;
architecture rtl of BENCHY_zpuino_wb_waveform_generator is
COMPONENT waveform_gen
PORT(
clk : IN std_logic;
reset : IN std_logic;
phase_inc : IN std_logic_vector(31 downto 0);
sin_out : OUT std_logic_vector(11 downto 0);
cos_out : OUT std_logic_vector(11 downto 0);
squ_out : OUT std_logic_vector(11 downto 0);
saw_out : OUT std_logic_vector(11 downto 0)
);
END COMPONENT;
COMPONENT AUDIO_zpuino_sa_sigmadeltaDAC
generic (
BITS: integer := 12
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end COMPONENT;
--Define your registers here
signal phase_inc_r : std_logic_vector(31 downto 0) := x"028c1980"; --x"028c1980" should give an output of 1Mhz. Wofram Alpha: x=10,y=(x*2^32)/(100 + .5)
-- signal waveform_sel: std_logic_vector(7 downto 0) := "00000010"; --Default to sine wave output
signal dac_in_s: std_logic_vector(11 downto 0);
signal sin_out_s: std_logic_vector(11 downto 0);
signal cos_out_s: std_logic_vector(11 downto 0);
signal squ_out_s: std_logic_vector(11 downto 0);
signal saw_out_s: std_logic_vector(11 downto 0);
-- signal register0: std_logic_vector(31 downto 0); -- Register 0 (32 bits)
-- signal register1: std_logic_vector(31 downto 0); -- Register 1 (32 bits)
-- signal register2: std_logic_vector(7 downto 0); -- Register 2 (8 bits)
--signal nReset : std_logic;
--Wishbone signals - Don't touch.
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- End unpacking Wishbone signals
--nReset <= not wb_rst_i;
-- Asynchronous acknowledge
wb_ack_o <= '1' when wb_cyc_i='1' and wb_stb_i='1' else '0';
-- Multiplex the data output (asynchronous)
process(phase_inc_r, wb_adr_i)
begin
-- Multiplex the read depending on the address. Use only the 2 lowest bits of addr
case wb_adr_i(3 downto 2) is
when "00" =>
wb_dat_o <= phase_inc_r; -- Output register0
-- when "01" =>
-- wb_dat_o(31 downto 0) <= (others => '0'); -- We put all upper 24 bits to zero
-- wb_dat_o(7 downto 0) <= waveform_sel; -- since register1 only has 8 bits
-- when "10" =>
-- wb_dat_o(31 downto 0) <= (others => '0'); -- We put all upper 24 bits to zero
-- wb_dat_o(7 downto 0) <= register2; -- since register2 only has 8 bits
when others =>
wb_dat_o <= (others => 'X'); -- Return undefined for all other addresses
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
if wb_rst_i='1' then
-- Reset request, put register1 and register2 with zeroes,
-- put register 3 with binary 10101010b
phase_inc_r <= (others => '0');
--waveform_sel <= (others => '0');
-- register2 <= "10101010";
else -- Not reset
-- Check if someone is writing
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
-- Yes, it's a write. See for which register based on address
case wb_adr_i(3 downto 2) is
when "00" =>
phase_inc_r <= wb_dat_i; -- Set register0
-- when "01" =>
-- waveform_sel <= wb_dat_i(7 downto 0); -- Set register1
-- when "10" =>
-- register2 <= wb_dat_i(7 downto 0); -- Only lower 8 bits for register2
when others =>
null; -- Nothing to do for other addresses
end case;
end if;
end if;
end if;
end process;
sin_out <= sin_out_s;
cos_out <= cos_out_s;
--squ_out <= squ_out_s;
saw_out <= saw_out_s;
Inst_waveform_gen: waveform_gen PORT MAP(
clk => wb_clk_i,
reset => '1',
phase_inc => phase_inc_r,
sin_out => sin_out_s,
cos_out => cos_out_s,
squ_out => squ_out_s,
saw_out => saw_out_s
);
Inst_dac1: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => sin_dac_out,
data_in => sin_out_s,
clk_96Mhz => clk_in
);
Inst_dac2: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => cos_dac_out,
data_in => cos_out_s,
clk_96Mhz => clk_in
);
Inst_dac3: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => squ_dac_out,
data_in => squ_out_s,
clk_96Mhz => clk_in
);
Inst_dac4: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => saw_dac_out,
data_in => saw_out_s,
clk_96Mhz => clk_in
);
-- process (waveform_sel,sin_out_s,cos_out_s,squ_out_s,saw_out_s)
-- begin
-- case waveform_sel(1 downto 0) is
-- when "00" => dac_in_s <= sin_out_s;
-- when "01" => dac_in_s <= cos_out_s;
-- when "10" => dac_in_s <= squ_out_s;
-- when "11" => dac_in_s <= saw_out_s;
-- when others => dac_in_s <= squ_out_s;
-- end case;
-- end process;
end rtl;
|
----------------------------------------------------------------------------------
-- Company: Gadget Factory
-- Engineer: Alvaro Lopes
--
-- Create Date: 13:56:50 12/10/2013
-- Design Name:
-- Module Name: TEMPLATE_zpuino_wb_Wishbone - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This is an example template to use for your own Wishbone Peripherals.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
-- This example uses asynchronous outputs.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity BENCHY_zpuino_wb_waveform_generator is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
clk_in : in STD_LOGIC;
sin_out : OUT std_logic_vector(11 downto 0);
cos_out : OUT std_logic_vector(11 downto 0);
--squ_out : OUT std_logic_vector(11 downto 0);
saw_out : OUT std_logic_vector(11 downto 0);
sin_dac_out : OUT std_logic;
cos_dac_out : OUT std_logic;
squ_dac_out : OUT std_logic;
saw_dac_out : OUT std_logic
--all_dac_out : OUT std_logic
);
end entity BENCHY_zpuino_wb_waveform_generator;
architecture rtl of BENCHY_zpuino_wb_waveform_generator is
COMPONENT waveform_gen
PORT(
clk : IN std_logic;
reset : IN std_logic;
phase_inc : IN std_logic_vector(31 downto 0);
sin_out : OUT std_logic_vector(11 downto 0);
cos_out : OUT std_logic_vector(11 downto 0);
squ_out : OUT std_logic_vector(11 downto 0);
saw_out : OUT std_logic_vector(11 downto 0)
);
END COMPONENT;
COMPONENT AUDIO_zpuino_sa_sigmadeltaDAC
generic (
BITS: integer := 12
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end COMPONENT;
--Define your registers here
signal phase_inc_r : std_logic_vector(31 downto 0) := x"028c1980"; --x"028c1980" should give an output of 1Mhz. Wofram Alpha: x=10,y=(x*2^32)/(100 + .5)
-- signal waveform_sel: std_logic_vector(7 downto 0) := "00000010"; --Default to sine wave output
signal dac_in_s: std_logic_vector(11 downto 0);
signal sin_out_s: std_logic_vector(11 downto 0);
signal cos_out_s: std_logic_vector(11 downto 0);
signal squ_out_s: std_logic_vector(11 downto 0);
signal saw_out_s: std_logic_vector(11 downto 0);
-- signal register0: std_logic_vector(31 downto 0); -- Register 0 (32 bits)
-- signal register1: std_logic_vector(31 downto 0); -- Register 1 (32 bits)
-- signal register2: std_logic_vector(7 downto 0); -- Register 2 (8 bits)
--signal nReset : std_logic;
--Wishbone signals - Don't touch.
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- End unpacking Wishbone signals
--nReset <= not wb_rst_i;
-- Asynchronous acknowledge
wb_ack_o <= '1' when wb_cyc_i='1' and wb_stb_i='1' else '0';
-- Multiplex the data output (asynchronous)
process(phase_inc_r, wb_adr_i)
begin
-- Multiplex the read depending on the address. Use only the 2 lowest bits of addr
case wb_adr_i(3 downto 2) is
when "00" =>
wb_dat_o <= phase_inc_r; -- Output register0
-- when "01" =>
-- wb_dat_o(31 downto 0) <= (others => '0'); -- We put all upper 24 bits to zero
-- wb_dat_o(7 downto 0) <= waveform_sel; -- since register1 only has 8 bits
-- when "10" =>
-- wb_dat_o(31 downto 0) <= (others => '0'); -- We put all upper 24 bits to zero
-- wb_dat_o(7 downto 0) <= register2; -- since register2 only has 8 bits
when others =>
wb_dat_o <= (others => 'X'); -- Return undefined for all other addresses
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
if wb_rst_i='1' then
-- Reset request, put register1 and register2 with zeroes,
-- put register 3 with binary 10101010b
phase_inc_r <= (others => '0');
--waveform_sel <= (others => '0');
-- register2 <= "10101010";
else -- Not reset
-- Check if someone is writing
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
-- Yes, it's a write. See for which register based on address
case wb_adr_i(3 downto 2) is
when "00" =>
phase_inc_r <= wb_dat_i; -- Set register0
-- when "01" =>
-- waveform_sel <= wb_dat_i(7 downto 0); -- Set register1
-- when "10" =>
-- register2 <= wb_dat_i(7 downto 0); -- Only lower 8 bits for register2
when others =>
null; -- Nothing to do for other addresses
end case;
end if;
end if;
end if;
end process;
sin_out <= sin_out_s;
cos_out <= cos_out_s;
--squ_out <= squ_out_s;
saw_out <= saw_out_s;
Inst_waveform_gen: waveform_gen PORT MAP(
clk => wb_clk_i,
reset => '1',
phase_inc => phase_inc_r,
sin_out => sin_out_s,
cos_out => cos_out_s,
squ_out => squ_out_s,
saw_out => saw_out_s
);
Inst_dac1: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => sin_dac_out,
data_in => sin_out_s,
clk_96Mhz => clk_in
);
Inst_dac2: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => cos_dac_out,
data_in => cos_out_s,
clk_96Mhz => clk_in
);
Inst_dac3: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => squ_dac_out,
data_in => squ_out_s,
clk_96Mhz => clk_in
);
Inst_dac4: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => saw_dac_out,
data_in => saw_out_s,
clk_96Mhz => clk_in
);
-- process (waveform_sel,sin_out_s,cos_out_s,squ_out_s,saw_out_s)
-- begin
-- case waveform_sel(1 downto 0) is
-- when "00" => dac_in_s <= sin_out_s;
-- when "01" => dac_in_s <= cos_out_s;
-- when "10" => dac_in_s <= squ_out_s;
-- when "11" => dac_in_s <= saw_out_s;
-- when others => dac_in_s <= squ_out_s;
-- end case;
-- end process;
end rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc269.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p03n01i00269ent IS
END c03s01b03x00p03n01i00269ent;
ARCHITECTURE c03s01b03x00p03n01i00269arch OF c03s01b03x00p03n01i00269ent IS
type T is
range 1 to 100
units
I -- failure_here
J = 2 I;
K = 2 J;
L = 10 K;
end units;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b03x00p03n01i00269 - Missing semicolon."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p03n01i00269arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc269.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p03n01i00269ent IS
END c03s01b03x00p03n01i00269ent;
ARCHITECTURE c03s01b03x00p03n01i00269arch OF c03s01b03x00p03n01i00269ent IS
type T is
range 1 to 100
units
I -- failure_here
J = 2 I;
K = 2 J;
L = 10 K;
end units;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b03x00p03n01i00269 - Missing semicolon."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p03n01i00269arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc269.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p03n01i00269ent IS
END c03s01b03x00p03n01i00269ent;
ARCHITECTURE c03s01b03x00p03n01i00269arch OF c03s01b03x00p03n01i00269ent IS
type T is
range 1 to 100
units
I -- failure_here
J = 2 I;
K = 2 J;
L = 10 K;
end units;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b03x00p03n01i00269 - Missing semicolon."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p03n01i00269arch;
|
architecture ARCH of ENTITY is
begin
PROC_1 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1 =>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_1;
PROC_2 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1=>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_2;
end architecture ARCH;
|
-- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
entity ovl_next is
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
num_cks : positive := 1;
check_overlapping : ovl_chk_overlap := OVL_CHK_OVERLAP_OFF;
check_missing_start : ovl_ctrl := OVL_OFF;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
start_event : in std_logic;
test_expr : in std_logic;
fire : out std_logic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end entity ovl_next;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:28:56 12/10/2016
-- Design Name:
-- Module Name: byte_swapper - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity byte_swapper is
Port ( din : in STD_LOGIC_VECTOR (31 downto 0);
dout : out STD_LOGIC_VECTOR (31 downto 0));
end byte_swapper;
architecture Behavioral of byte_swapper is
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral: architecture is "TRUE";
subtype tWord is std_logic_vector(31 downto 0);
function doSwapBytes(d : tWord) return tWord is
begin
return d(7 downto 0)&d(15 downto 8)&d(23 downto 16)&d(31 downto 24);
end;
begin
dout <= doSwapBytes(din);
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
entity MEMWBRegister is
port(
clk, MemtoRegIn, RegWriteIn: in std_logic;
WriteRegisterIn: in std_logic_vector(4 downto 0);
ReadDataIn, ALUResultIn: in std_logic_vector(31 downto 0);
MemtoRegOut, RegWriteOut: out std_logic;
WriteRegisterOut: out std_logic_vector(4 downto 0);
ReadDataOut, ALUResultOut: out std_logic_vector(31 downto 0)
);
end MEMWBRegister;
architecture Structural of MEMWBRegister is
signal MemtoReg, RegWrite: std_logic := '0';
signal WriteRegister: std_logic_vector(4 downto 0) := "00000";
signal ReadData, ALUResult: std_logic_vector(31 downto 0) := X"00000000";
begin
MemtoRegOut <= MemtoReg;
RegWriteOut <= RegWrite;
WriteRegisterOut <= WriteRegister;
ReadDataOut <= ReadData;
ALUResultOut <= ALUResult;
process(clk)
begin
if rising_edge(clk) then
MemtoReg <= MemtoRegIn;
RegWrite <= RegWriteIn;
WriteRegister <= WriteRegisterIn;
ReadData <= ReadDataIn;
ALUResult <= ALUResultIn;
end if;
end process;
end Structural;
|
--------------------------------------------------------------------------------
-- InputIEEE_11_52_to_11_52
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors: Florent de Dinechin (2008)
--------------------------------------------------------------------------------
-- Pipeline depth: 1 cycles
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;
entity InputIEEE_11_52_to_11_52 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(63 downto 0);
R : out std_logic_vector(11+52+2 downto 0) );
end entity;
architecture arch of InputIEEE_11_52_to_11_52 is
signal expX, expX_d1 : std_logic_vector(10 downto 0);
signal fracX : std_logic_vector(51 downto 0);
signal sX, sX_d1 : std_logic;
signal expZero, expZero_d1 : std_logic;
signal expInfty, expInfty_d1 : std_logic;
signal fracZero, fracZero_d1 : std_logic;
signal reprSubNormal, reprSubNormal_d1 : std_logic;
signal sfracX, sfracX_d1 : std_logic_vector(51 downto 0);
signal fracR : std_logic_vector(51 downto 0);
signal expR : std_logic_vector(10 downto 0);
signal infinity : std_logic;
signal zero : std_logic;
signal NaN : std_logic;
signal exnR : std_logic_vector(1 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
expX_d1 <= expX;
sX_d1 <= sX;
expZero_d1 <= expZero;
expInfty_d1 <= expInfty;
fracZero_d1 <= fracZero;
reprSubNormal_d1 <= reprSubNormal;
sfracX_d1 <= sfracX;
end if;
end process;
expX <= X(62 downto 52);
fracX <= X(51 downto 0);
sX <= X(63);
expZero <= '1' when expX = (10 downto 0 => '0') else '0';
expInfty <= '1' when expX = (10 downto 0 => '1') else '0';
fracZero <= '1' when fracX = (51 downto 0 => '0') else '0';
reprSubNormal <= fracX(51);
-- since we have one more exponent value than IEEE (field 0...0, value emin-1),
-- we can represent subnormal numbers whose mantissa field begins with a 1
sfracX <= fracX(50 downto 0) & '0' when (expZero='1' and reprSubNormal='1') else fracX;
----------------Synchro barrier, entering cycle 1----------------
fracR <= sfracX_d1;
-- copy exponent. This will be OK even for subnormals, zero and infty since in such cases the exn bits will prevail
expR <= expX_d1;
infinity <= expInfty_d1 and fracZero_d1;
zero <= expZero_d1 and not reprSubNormal_d1;
NaN <= expInfty_d1 and not fracZero_d1;
exnR <=
"00" when zero='1'
else "10" when infinity='1'
else "11" when NaN='1'
else "01" ; -- normal number
R <= exnR & sX_d1 & expR & fracR;
end architecture;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
ENTITY mux_tb IS
END mux_tb;
architecture mux_tb_arch of mux_tb is
component mux is
port(clk : in std_logic;
input0 : in std_logic_vector(31 downto 0);
input1 : in std_logic_vector(31 downto 0);
selectInput : in std_logic;
selectOutput : out std_logic_vector(31 downto 0)
);
end component;
constant clk_period : time := 1 ns;
signal clk : std_logic := '0';
signal muxValue1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal muxValue2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal selection : STD_LOGIC;
signal muxOutput : STD_LOGIC_VECTOR(31 DOWNTO 0);
begin
muxFetch : mux
port map(
clk => clk,
input2 => muxValue2,
input1 => muxValue1,
selectInput => selection,
selectOutput => muxOutput
);
clk_process : process
BEGIN
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
test_process : process
BEGIN
wait for clk_period;
report "STARTING SIMULATION \n";
muxValue1 <= "11111111111111111111111111111111";
muxValue2 <= "00000000000000000000000000000000";
selection <= '1';
wait for clk_period;
selection <= '0';
wait;
end process;
end mux_tb_arch; |
entity bounds10 is
end entity;
architecture test of bounds10 is
begin
process is
variable n : integer;
variable a : bit_vector(3 downto 0);
variable b : bit_vector(7 downto 0);
begin
n := 7;
wait for 1 ns;
a := b(n downto 0);
wait;
end process;
end architecture;
|
entity bounds10 is
end entity;
architecture test of bounds10 is
begin
process is
variable n : integer;
variable a : bit_vector(3 downto 0);
variable b : bit_vector(7 downto 0);
begin
n := 7;
wait for 1 ns;
a := b(n downto 0);
wait;
end process;
end architecture;
|
entity bounds10 is
end entity;
architecture test of bounds10 is
begin
process is
variable n : integer;
variable a : bit_vector(3 downto 0);
variable b : bit_vector(7 downto 0);
begin
n := 7;
wait for 1 ns;
a := b(n downto 0);
wait;
end process;
end architecture;
|
entity bounds10 is
end entity;
architecture test of bounds10 is
begin
process is
variable n : integer;
variable a : bit_vector(3 downto 0);
variable b : bit_vector(7 downto 0);
begin
n := 7;
wait for 1 ns;
a := b(n downto 0);
wait;
end process;
end architecture;
|
entity bounds10 is
end entity;
architecture test of bounds10 is
begin
process is
variable n : integer;
variable a : bit_vector(3 downto 0);
variable b : bit_vector(7 downto 0);
begin
n := 7;
wait for 1 ns;
a := b(n downto 0);
wait;
end process;
end architecture;
|
-- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use work.tb_package.all;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
COMPONENT tb_master
PORT(
done_i : IN std_logic_vector(gen_number downto 0);
command_o : OUT command_rec
);
END COMPONENT;
COMPONENT reset_gen
Port (
command_i : in command_rec;
reset_o : out std_logic;
done_o : out std_logic_vector(gen_number downto 0)
);
END COMPONENT;
COMPONENT clock_gen
Port (
command_i : in command_rec;
clk_o : out std_logic;
done_o : out std_logic_vector(gen_number downto 0)
);
END COMPONENT;
COMPONENT enable_gen
Port (
command_i : in command_rec;
enable_o : out std_logic;
done_o : out std_logic_vector(gen_number downto 0)
);
END COMPONENT;
COMPONENT bit_in_gen
Port (
command_i : in command_rec;
enable_o : out std_logic;
done_o : out std_logic_vector(gen_number downto 0)
);
END COMPONENT;
COMPONENT out_tracer
Port (
clk_i : in std_logic;
out_data_i : in std_logic_vector(7 downto 0)
);
END COMPONENT;
-- *************************************************************
-- D U T
-- *************************************************************
COMPONENT shiftreg
Port (
clk : in std_logic;
rst : in std_logic;
leftShift : in std_logic;
rightShift : in std_logic;
leftIn : in std_logic;
rightIn : in std_logic;
regOut : out std_logic_vector(7 downto 0) := (others => '0')
);
END COMPONENT;
signal done_i : std_logic_vector(gen_number downto 0);
signal command_o : command_rec;
signal s_reset : std_logic;
signal s_not_reset : std_logic;
signal s_clk : std_logic;
signal s_enable : std_logic;
signal s_not_enable : std_logic;
signal s_bit_in : std_logic;
signal s_not_bit_in : std_logic;
signal s_out_data_o : std_logic_vector(7 downto 0);
BEGIN
i_tb_master: tb_master PORT MAP(
done_i => done_i,
command_o => command_o
);
i_reset_gen: reset_gen PORT MAP(
command_i => command_o,
reset_o => s_reset,
done_o => done_i
);
i_clock_gen: clock_gen PORT MAP(
command_i => command_o,
clk_o => s_clk,
done_o => done_i
);
i_enable_gen: enable_gen PORT MAP(
command_i => command_o,
enable_o => s_enable,
done_o => done_i
);
i_bit_in_gen: bit_in_gen PORT MAP(
command_i => command_o,
enable_o => s_bit_in,
done_o => done_i
);
i_out_tracer: out_tracer PORT MAP(
clk_i => s_clk,
out_data_i => s_out_data_o
);
-- *************************************************************
-- D U T
-- *************************************************************
i_shiftreg: shiftreg PORT MAP(
clk => s_clk,
rst => s_reset,
leftShift => s_enable,
rightShift => s_not_enable,
leftIn => s_not_bit_in,
rightIn => s_bit_in,
regOut => s_out_data_o
);
-- *************************************************************
-- assignements
-- *************************************************************
done_i(2) <= '0';
done_i(3) <= '0';
done_i(4) <= '0';
done_i(0) <= 'Z';
done_i(1) <= 'Z';
done_i(5) <= 'Z';
done_i(6) <= 'Z';
s_not_reset <= not s_reset;
s_not_enable <= not s_enable;
s_not_bit_in <= not s_bit_in;
END;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_0_1;
USE fifo_generator_v13_0_1.fifo_generator_v13_0_1;
ENTITY FiFo IS
PORT (
clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END FiFo;
ARCHITECTURE FiFo_arch OF FiFo IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF FiFo_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_0_1 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_0_1;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 core_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v13_0_1
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 6,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 8,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 8,
C_ENABLE_RLOCS => 0,
C_FAMILY => "artix7",
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 0,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "512x36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 62,
C_PROG_FULL_THRESH_NEGATE_VAL => 61,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 6,
C_RD_DEPTH => 64,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 6,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 0,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 6,
C_WR_DEPTH => 64,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 6,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 2,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 2,
C_IMPLEMENTATION_TYPE_RACH => 2,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => clk,
rst => '0',
srst => '0',
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END FiFo_arch;
|
library ieee;
use ieee.std_logic_1164.all;
entity IDEXRegister is
port(
clk, ALUSrcIn, BranchIn, MemWriteIn, MemReadIn, MemtoRegIn, RegDstIn, RegWriteIn: in std_logic;
ALUOpIn: std_logic_vector(1 downto 0);
AddressIn, InstructionIn, ReadDataOneIn, ReadDataTwoIn: std_logic_vector(31 downto 0);
ALUSrcOut, BranchOut, MemWriteOut, MemReadOut, MemtoRegOut, RegDstOut, RegWriteOut: out std_logic;
ALUOpOut: out std_logic_vector(1 downto 0);
AddressOut, InstructionOut, ReadDataOneOut, ReadDataTwoOut: out std_logic_vector(31 downto 0)
);
end IDEXRegister;
architecture Structural of IDEXRegister is
signal ALUSrc, Branch, MemWrite, MemRead, MemtoReg, RegDst, RegWrite: std_logic := '0';
signal ALUOp: std_logic_vector(1 downto 0) := "00";
signal Address, Instruction, ReadDataOne, ReadDataTwo: std_logic_vector(31 downto 0) := X"00000000";
begin
AddressOut <= Address;
ALUOPOut <= ALUOp;
ALUSrcOut <= ALUSrc;
BranchOut <= Branch;
InstructionOut <= Instruction;
MemWriteOut <= MemWrite;
MemReadOut <= MemRead;
MemtoRegOut <= MemtoReg;
ReadDataOneOut <= ReadDataOne;
ReadDataTwoOut <= ReadDataTwo;
RegDstOut <= RegDst;
RegWriteOut <= RegWrite;
process(clk)
begin
if rising_edge(clk) then
Address <= AddressIn;
ALUOp <= ALUOpIn;
ALUSrc <= ALUSrcIn;
Branch <= BranchIn;
Instruction <= InstructionIn;
MemWrite <= MemWriteIn;
MemRead <= MemReadIn;
MemtoReg <= MemtoRegIn;
ReadDataOne <= ReadDataOneIn;
ReadDataTwo <= ReadDataTwoIn;
RegDst <= RegDstIn;
RegWrite <= RegWriteIn;
end if;
end process;
end Structural;
|
--
---- comp_defs - package
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
---- Filename: comp_defs.vhd
---- Version: v3.0
-- Description: Component declarations for all black box netlists generated by
-- running COREGEN when XST elaborated the client core
----
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_quad_spi.
--
-- Structure:
--
-- axi_quad_spi.vhd
-- |--Legacy_mode
-- |-- axi_lite_ipif.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--Enhanced_mode
-- |--axi_qspi_enhanced_mode.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--XIP_mode
-- |-- axi_lite_ipif.vhd
-- |-- xip_cntrl_reg.vhd
-- |-- reset_sync_module.vhd
-- |-- xip_status_reg.vhd
-- |-- axi_qspi_xip_if.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- comp_defs.vhd -- (helper lib)
-------------------------------------------------------------------------------
-- Author:
-- ~~~~~~
-- SK - 19/01/2011
-- - This package is defined to have component instantiation of the
-- distributed memory used in the core.
-- ^^^^^^
-- ~~~~~~
-- SK - 12/12/2011
-- - Upgraded distributed memory generation instance from dist_mem_gen_v6_2 to
-- dist_mem_gen_v6_4.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. Instantiated the component dist_mem_gen_v8_0 - latest version
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
--library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
--library dist_mem_gen_v6_3;
-- use dist_mem_gen_v6_3.all;
--
--library dist_mem_gen_v6_4;
-- use dist_mem_gen_v6_4.all;
library dist_mem_gen_v8_0;
use dist_mem_gen_v8_0.all;
package comp_defs is
--
-- -- component declaration
-- component dist_mem_gen_v6_3
-- -------------------
-- generic(
-- c_has_clk : integer := 1;
-- c_read_mif : integer := 0;
-- c_has_qspo : integer := 0;
-- c_addr_width : integer := 8;
-- c_width : integer := 15;
-- c_family : string := "virtex7"; -- "virtex6";
-- c_sync_enable : integer := 1;
-- c_depth : integer := 256;
-- c_has_qspo_srst : integer := 1;
-- c_mem_init_file : string := "null.mif";
-- c_default_data : string := "0";
-- ------------------------
-- c_has_qdpo_clk : integer := 0;
-- c_has_qdpo_ce : integer := 0;
-- c_parser_type : integer := 1;
-- c_has_d : integer := 0;
-- c_has_spo : integer := 0;
-- c_reg_a_d_inputs : integer := 0;
-- c_has_we : integer := 0;
-- c_pipeline_stages : integer := 0;
-- c_has_qdpo_rst : integer := 0;
-- c_reg_dpra_input : integer := 0;
-- c_qualify_we : integer := 0;
-- c_has_qdpo_srst : integer := 0;
-- c_has_dpra : integer := 0;
-- c_qce_joined : integer := 0;
-- c_mem_type : integer := 0;
-- c_has_i_ce : integer := 0;
-- c_has_dpo : integer := 0;
-- c_has_spra : integer := 0;
-- c_has_qspo_ce : integer := 0;
-- c_has_qspo_rst : integer := 0;
-- c_has_qdpo : integer := 0
-- -------------------------
-- );
-- port(
-- a : in std_logic_vector(c_addr_width-1-(4*c_has_spra*boolean'pos(c_addr_width > 4)) downto 0) := (others => '0');
-- d : in std_logic_vector(c_width-1 downto 0) := (others => '0');
-- dpra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- spra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- clk : in std_logic := '0';
-- we : in std_logic := '0';
-- i_ce : in std_logic := '1';
-- qspo_ce : in std_logic := '1';
-- qdpo_ce : in std_logic := '1';
-- qdpo_clk : in std_logic := '0';
-- qspo_rst : in std_logic := '0';
-- qdpo_rst : in std_logic := '0';
-- qspo_srst : in std_logic := '0';
-- qdpo_srst : in std_logic := '0';
-- spo : out std_logic_vector(c_width-1 downto 0);
-- dpo : out std_logic_vector(c_width-1 downto 0);
-- qspo : out std_logic_vector(c_width-1 downto 0);
-- qdpo : out std_logic_vector(c_width-1 downto 0)
-- );
-- end component;
--
-- -- The following tells XST that dist_mem_gen_v6_2 is a black box which
-- -- should be generated. The command given by the value of this attribute
-- -- Note the fully qualified SIM (JAVA class) name that forms the
-- -- basis of the core
--
-- --xcc exclude
--
-- -- attribute box_type : string;
-- -- attribute GENERATOR_DEFAULT : string;
-- --
-- -- attribute box_type of dist_mem_gen_v6_3 : component is "black_box";
-- -- attribute GENERATOR_DEFAULT of dist_mem_gen_v6_3 : component is "generatecore com.xilinx.ip.dist_mem_gen_v6_3.dist_mem_gen_v6_3";
-- --xcc include
--
-- -- component declaration for dist_mem_gen_v6_4
-- component dist_mem_gen_v6_4
-- -------------------
-- generic(
-- c_has_clk : integer := 1;
-- c_read_mif : integer := 0;
-- c_has_qspo : integer := 0;
-- c_addr_width : integer := 8;
-- c_width : integer := 15;
-- c_family : string := "virtex7"; -- "virtex6";
-- c_sync_enable : integer := 1;
-- c_depth : integer := 256;
-- c_has_qspo_srst : integer := 1;
-- c_mem_init_file : string := "null.mif";
-- c_default_data : string := "0";
-- ------------------------
-- c_has_qdpo_clk : integer := 0;
-- c_has_qdpo_ce : integer := 0;
-- c_parser_type : integer := 1;
-- c_has_d : integer := 0;
-- c_has_spo : integer := 0;
-- c_reg_a_d_inputs : integer := 0;
-- c_has_we : integer := 0;
-- c_pipeline_stages : integer := 0;
-- c_has_qdpo_rst : integer := 0;
-- c_reg_dpra_input : integer := 0;
-- c_qualify_we : integer := 0;
-- c_has_qdpo_srst : integer := 0;
-- c_has_dpra : integer := 0;
-- c_qce_joined : integer := 0;
-- c_mem_type : integer := 0;
-- c_has_i_ce : integer := 0;
-- c_has_dpo : integer := 0;
-- c_has_spra : integer := 0;
-- c_has_qspo_ce : integer := 0;
-- c_has_qspo_rst : integer := 0;
-- c_has_qdpo : integer := 0
-- -------------------------
-- );
-- port(
-- a : in std_logic_vector(c_addr_width-1-(4*c_has_spra*boolean'pos(c_addr_width > 4)) downto 0) := (others => '0');
-- d : in std_logic_vector(c_width-1 downto 0) := (others => '0');
-- dpra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- spra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- clk : in std_logic := '0';
-- we : in std_logic := '0';
-- i_ce : in std_logic := '1';
-- qspo_ce : in std_logic := '1';
-- qdpo_ce : in std_logic := '1';
-- qdpo_clk : in std_logic := '0';
-- qspo_rst : in std_logic := '0';
-- qdpo_rst : in std_logic := '0';
-- qspo_srst : in std_logic := '0';
-- qdpo_srst : in std_logic := '0';
-- spo : out std_logic_vector(c_width-1 downto 0);
-- dpo : out std_logic_vector(c_width-1 downto 0);
-- qspo : out std_logic_vector(c_width-1 downto 0);
-- qdpo : out std_logic_vector(c_width-1 downto 0)
-- );
-- end component;
--
-- -- The following tells XST that dist_mem_gen_v6_4 is a black box which
-- -- should be generated. The command given by the value of this attribute
-- -- Note the fully qualified SIM (JAVA class) name that forms the
-- -- basis of the core
--
-- --xcc exclude
--
-- -- attribute box_type of dist_mem_gen_v6_4 : component is "black_box";
-- -- attribute GENERATOR_DEFAULT of dist_mem_gen_v6_4 : component is "generatecore com.xilinx.ip.dist_mem_gen_v6_4.dist_mem_gen_v6_4";
--
-- --xcc include
-- 1/8/2013 added the latest version of dist_mem_gen_v8_0
-- component declaration for dist_mem_gen_v8_0
component dist_mem_gen_v8_0
-------------------
generic(
C_HAS_CLK : integer := 1;
C_READ_MIF : integer := 0;
C_HAS_QSPO : integer := 0;
C_ADDR_WIDTH : integer := 8;
C_WIDTH : integer := 15;
C_FAMILY : string := "virtex7"; -- "virtex6";
C_SYNC_ENABLE : integer := 1;
C_DEPTH : integer := 256;
C_HAS_QSPO_SRST : integer := 1;
C_MEM_INIT_FILE : string := "null.mif";
C_DEFAULT_DATA : string := "0";
------------------------
C_HAS_QDPO_CLK : integer := 0;
C_HAS_QDPO_CE : integer := 0;
C_PARSER_TYPE : integer := 1;
C_HAS_D : integer := 0;
C_HAS_SPO : integer := 0;
C_REG_A_D_INPUTS : integer := 0;
C_HAS_WE : integer := 0;
C_PIPELINE_STAGES : integer := 0;
C_HAS_QDPO_RST : integer := 0;
C_REG_DPRA_INPUT : integer := 0;
C_QUALIFY_WE : integer := 0;
C_HAS_QDPO_SRST : integer := 0;
C_HAS_DPRA : integer := 0;
C_QCE_JOINED : integer := 0;
C_MEM_TYPE : integer := 0;
C_HAS_I_CE : integer := 0;
C_HAS_DPO : integer := 0;
-- C_HAS_SPRA : integer := 0; -- removed from dist mem gen core
C_HAS_QSPO_CE : integer := 0;
C_HAS_QSPO_RST : integer := 0;
C_HAS_QDPO : integer := 0
-------------------------
);
port(
a : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
d : in std_logic_vector(c_width-1 downto 0) := (others => '0');
dpra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- spra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0'); -- 2/12/2013
clk : in std_logic := '0';
we : in std_logic := '0';
i_ce : in std_logic := '1';
qspo_ce : in std_logic := '1';
qdpo_ce : in std_logic := '1';
qdpo_clk : in std_logic := '0';
qspo_rst : in std_logic := '0';
qdpo_rst : in std_logic := '0';
qspo_srst : in std_logic := '0';
qdpo_srst : in std_logic := '0';
spo : out std_logic_vector(c_width-1 downto 0);
dpo : out std_logic_vector(c_width-1 downto 0);
qspo : out std_logic_vector(c_width-1 downto 0);
qdpo : out std_logic_vector(c_width-1 downto 0)
);
end component;
-- The following tells XST that dist_mem_gen_v8_0 is a black box which
-- should be generated. The command given by the value of this attribute
-- Note the fully qualified SIM (JAVA class) name that forms the
-- basis of the core
--xcc exclude
-- attribute box_type of dist_mem_gen_v8_0 : component is "black_box";
-- attribute GENERATOR_DEFAULT of dist_mem_gen_v8_0 : component is "generatecore com.xilinx.ip.dist_mem_gen_v8_0.dist_mem_gen_v8_0";
--xcc include
end comp_defs;
|
library verilog;
use verilog.vl_types.all;
entity tester is
port(
clk : out vl_logic;
data : out vl_logic_vector(7 downto 0)
);
end tester;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================================================================================================
-- Package: Project specific configuration.
--
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Description:
-- ------------------------------------
-- This is a template file.
-- The global package common/config evaluates the settings declared in this file.
--
-- Usage:
-- 1) Copy this file into your project's source directory and rename it to my_config.vhdl.
-- 2) Add file to library "poc" in your synthesis tool.
-- 3) Change setup appropriately.
--
-- License:
-- ============================================================================================================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany, Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================================================================================================
library PoC;
package my_config is
-- Change these lines to setup configuration.
constant MY_BOARD : string := "DE4"; -- Altera DE4 - Altera Stratix IV reference design board: EP4SGX230KF40C2
constant MY_DEVICE : string := "None"; -- infer from MY_BOARD
-- For internal use only
constant MY_VERBOSE : boolean := FALSE;
end package;
package body my_config is
end package body;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ioblock0_e
--
-- Generated
-- by: wig
-- on: Wed Jul 5 16:53:23 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ioblock0_e-e.vhd,v 1.3 2006/07/10 07:30:08 wig Exp $
-- $Date: 2006/07/10 07:30:08 $
-- $Log: ioblock0_e-e.vhd,v $
-- Revision 1.3 2006/07/10 07:30:08 wig
-- Updated more testcasess.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ioblock0_e
--
entity ioblock0_e is
-- Generics:
-- No Generated Generics for Entity ioblock0_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity ioblock0_e
p_mix_data_i1_go : out std_ulogic_vector(7 downto 0);
p_mix_data_o1_gi : in std_ulogic_vector(7 downto 0);
p_mix_iosel_0_0_0_gi : in std_ulogic;
p_mix_pad_di_1_gi : in std_ulogic;
p_mix_pad_do_2_go : out std_ulogic;
p_mix_pad_en_2_go : out std_ulogic
-- End of Generated Port for Entity ioblock0_e
);
end ioblock0_e;
--
-- End of Generated Entity ioblock0_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_quad_spi:3.2
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_quad_spi_v3_2_10;
USE axi_quad_spi_v3_2_10.axi_quad_spi;
ENTITY system_axi_quad_spi_shield_0 IS
PORT (
ext_spi_clk : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
io0_i : IN STD_LOGIC;
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC;
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
sck_i : IN STD_LOGIC;
sck_o : OUT STD_LOGIC;
sck_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC
);
END system_axi_quad_spi_shield_0;
ARCHITECTURE system_axi_quad_spi_shield_0_arch OF system_axi_quad_spi_shield_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_quad_spi_shield_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_quad_spi IS
GENERIC (
Async_Clk : INTEGER;
C_FAMILY : STRING;
C_SELECT_XPM : INTEGER;
C_SUB_FAMILY : STRING;
C_INSTANCE : STRING;
C_SPI_MEM_ADDR_BITS : INTEGER;
C_TYPE_OF_AXI4_INTERFACE : INTEGER;
C_XIP_MODE : INTEGER;
C_UC_FAMILY : INTEGER;
C_FIFO_DEPTH : INTEGER;
C_SCK_RATIO : INTEGER;
C_DUAL_QUAD_MODE : INTEGER;
C_NUM_SS_BITS : INTEGER;
C_NUM_TRANSFER_BITS : INTEGER;
C_SPI_MODE : INTEGER;
C_USE_STARTUP : INTEGER;
C_USE_STARTUP_EXT : INTEGER;
C_SPI_MEMORY : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI4_ADDR_WIDTH : INTEGER;
C_S_AXI4_DATA_WIDTH : INTEGER;
C_S_AXI4_ID_WIDTH : INTEGER;
C_SHARED_STARTUP : INTEGER;
C_S_AXI4_BASEADDR : STD_LOGIC_VECTOR;
C_S_AXI4_HIGHADDR : STD_LOGIC_VECTOR;
C_LSB_STUP : INTEGER
);
PORT (
ext_spi_clk : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi4_aclk : IN STD_LOGIC;
s_axi4_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi4_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_awaddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_awlock : IN STD_LOGIC;
s_axi4_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awvalid : IN STD_LOGIC;
s_axi4_awready : OUT STD_LOGIC;
s_axi4_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_wlast : IN STD_LOGIC;
s_axi4_wvalid : IN STD_LOGIC;
s_axi4_wready : OUT STD_LOGIC;
s_axi4_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_bvalid : OUT STD_LOGIC;
s_axi4_bready : IN STD_LOGIC;
s_axi4_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_araddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_arlock : IN STD_LOGIC;
s_axi4_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arvalid : IN STD_LOGIC;
s_axi4_arready : OUT STD_LOGIC;
s_axi4_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_rlast : OUT STD_LOGIC;
s_axi4_rvalid : OUT STD_LOGIC;
s_axi4_rready : IN STD_LOGIC;
io0_i : IN STD_LOGIC;
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC;
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
io2_i : IN STD_LOGIC;
io2_o : OUT STD_LOGIC;
io2_t : OUT STD_LOGIC;
io3_i : IN STD_LOGIC;
io3_o : OUT STD_LOGIC;
io3_t : OUT STD_LOGIC;
io0_1_i : IN STD_LOGIC;
io0_1_o : OUT STD_LOGIC;
io0_1_t : OUT STD_LOGIC;
io1_1_i : IN STD_LOGIC;
io1_1_o : OUT STD_LOGIC;
io1_1_t : OUT STD_LOGIC;
io2_1_i : IN STD_LOGIC;
io2_1_o : OUT STD_LOGIC;
io2_1_t : OUT STD_LOGIC;
io3_1_i : IN STD_LOGIC;
io3_1_o : OUT STD_LOGIC;
io3_1_t : OUT STD_LOGIC;
spisel : IN STD_LOGIC;
sck_i : IN STD_LOGIC;
sck_o : OUT STD_LOGIC;
sck_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC;
ss_1_i : IN STD_LOGIC;
ss_1_o : OUT STD_LOGIC;
ss_1_t : OUT STD_LOGIC;
cfgclk : OUT STD_LOGIC;
cfgmclk : OUT STD_LOGIC;
eos : OUT STD_LOGIC;
preq : OUT STD_LOGIC;
clk : IN STD_LOGIC;
gsr : IN STD_LOGIC;
gts : IN STD_LOGIC;
keyclearb : IN STD_LOGIC;
usrcclkts : IN STD_LOGIC;
usrdoneo : IN STD_LOGIC;
usrdonets : IN STD_LOGIC;
pack : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC
);
END COMPONENT axi_quad_spi;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF ext_spi_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 spi_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 lite_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 lite_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF io0_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_I";
ATTRIBUTE X_INTERFACE_INFO OF io0_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_O";
ATTRIBUTE X_INTERFACE_INFO OF io0_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_T";
ATTRIBUTE X_INTERFACE_INFO OF io1_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_I";
ATTRIBUTE X_INTERFACE_INFO OF io1_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_O";
ATTRIBUTE X_INTERFACE_INFO OF io1_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_T";
ATTRIBUTE X_INTERFACE_INFO OF sck_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_I";
ATTRIBUTE X_INTERFACE_INFO OF sck_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_O";
ATTRIBUTE X_INTERFACE_INFO OF sck_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_T";
ATTRIBUTE X_INTERFACE_INFO OF ss_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_I";
ATTRIBUTE X_INTERFACE_INFO OF ss_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_O";
ATTRIBUTE X_INTERFACE_INFO OF ss_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_T";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
BEGIN
U0 : axi_quad_spi
GENERIC MAP (
Async_Clk => 0,
C_FAMILY => "artix7",
C_SELECT_XPM => 0,
C_SUB_FAMILY => "artix7",
C_INSTANCE => "axi_quad_spi_inst",
C_SPI_MEM_ADDR_BITS => 24,
C_TYPE_OF_AXI4_INTERFACE => 0,
C_XIP_MODE => 0,
C_UC_FAMILY => 0,
C_FIFO_DEPTH => 16,
C_SCK_RATIO => 16,
C_DUAL_QUAD_MODE => 0,
C_NUM_SS_BITS => 1,
C_NUM_TRANSFER_BITS => 8,
C_SPI_MODE => 0,
C_USE_STARTUP => 0,
C_USE_STARTUP_EXT => 0,
C_SPI_MEMORY => 1,
C_S_AXI_ADDR_WIDTH => 7,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI4_ADDR_WIDTH => 24,
C_S_AXI4_DATA_WIDTH => 32,
C_S_AXI4_ID_WIDTH => 1,
C_SHARED_STARTUP => 0,
C_S_AXI4_BASEADDR => X"FFFFFFFF",
C_S_AXI4_HIGHADDR => X"00000000",
C_LSB_STUP => 0
)
PORT MAP (
ext_spi_clk => ext_spi_clk,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi4_aclk => '0',
s_axi4_aresetn => '0',
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi4_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi4_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
s_axi4_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi4_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi4_awlock => '0',
s_axi4_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_awvalid => '0',
s_axi4_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi4_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_wlast => '0',
s_axi4_wvalid => '0',
s_axi4_bready => '0',
s_axi4_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi4_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
s_axi4_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi4_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi4_arlock => '0',
s_axi4_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_arvalid => '0',
s_axi4_rready => '0',
io0_i => io0_i,
io0_o => io0_o,
io0_t => io0_t,
io1_i => io1_i,
io1_o => io1_o,
io1_t => io1_t,
io2_i => '0',
io3_i => '0',
io0_1_i => '0',
io1_1_i => '0',
io2_1_i => '0',
io3_1_i => '0',
spisel => '1',
sck_i => sck_i,
sck_o => sck_o,
sck_t => sck_t,
ss_i => ss_i,
ss_o => ss_o,
ss_t => ss_t,
ss_1_i => '0',
clk => '0',
gsr => '0',
gts => '0',
keyclearb => '0',
usrcclkts => '0',
usrdoneo => '1',
usrdonets => '0',
pack => '0',
ip2intc_irpt => ip2intc_irpt
);
END system_axi_quad_spi_shield_0_arch;
|
entity slice1 is
end entity;
architecture test of slice1 is
type int_vector is array (integer range <>) of integer;
signal x : int_vector(0 to 3);
begin
process is
variable u : int_vector(5 downto 2);
variable v : int_vector(0 to 3);
begin
v := ( 1, 2, 3, 4 );
v(1 to 2) := ( 6, 7 );
assert v = ( 1, 6, 7, 4 );
assert v(2 to 3) = ( 7, 4 );
x <= ( 1, 2, 3, 4 );
wait for 1 ns;
x(1 to 2) <= ( 6, 7 );
wait for 1 ns;
assert x = ( 1, 6, 7, 4 );
assert x(2 to 3) = ( 7, 4 );
u := ( 1, 2, 3, 4);
assert u = ( 1, 2, 3, 4);
u(4 downto 3) := ( 6, 7 );
assert u = ( 1, 6, 7, 4 );
assert u(3 downto 2) = ( 7, 4 );
wait;
end process;
end architecture;
|
entity slice1 is
end entity;
architecture test of slice1 is
type int_vector is array (integer range <>) of integer;
signal x : int_vector(0 to 3);
begin
process is
variable u : int_vector(5 downto 2);
variable v : int_vector(0 to 3);
begin
v := ( 1, 2, 3, 4 );
v(1 to 2) := ( 6, 7 );
assert v = ( 1, 6, 7, 4 );
assert v(2 to 3) = ( 7, 4 );
x <= ( 1, 2, 3, 4 );
wait for 1 ns;
x(1 to 2) <= ( 6, 7 );
wait for 1 ns;
assert x = ( 1, 6, 7, 4 );
assert x(2 to 3) = ( 7, 4 );
u := ( 1, 2, 3, 4);
assert u = ( 1, 2, 3, 4);
u(4 downto 3) := ( 6, 7 );
assert u = ( 1, 6, 7, 4 );
assert u(3 downto 2) = ( 7, 4 );
wait;
end process;
end architecture;
|
entity slice1 is
end entity;
architecture test of slice1 is
type int_vector is array (integer range <>) of integer;
signal x : int_vector(0 to 3);
begin
process is
variable u : int_vector(5 downto 2);
variable v : int_vector(0 to 3);
begin
v := ( 1, 2, 3, 4 );
v(1 to 2) := ( 6, 7 );
assert v = ( 1, 6, 7, 4 );
assert v(2 to 3) = ( 7, 4 );
x <= ( 1, 2, 3, 4 );
wait for 1 ns;
x(1 to 2) <= ( 6, 7 );
wait for 1 ns;
assert x = ( 1, 6, 7, 4 );
assert x(2 to 3) = ( 7, 4 );
u := ( 1, 2, 3, 4);
assert u = ( 1, 2, 3, 4);
u(4 downto 3) := ( 6, 7 );
assert u = ( 1, 6, 7, 4 );
assert u(3 downto 2) = ( 7, 4 );
wait;
end process;
end architecture;
|
entity slice1 is
end entity;
architecture test of slice1 is
type int_vector is array (integer range <>) of integer;
signal x : int_vector(0 to 3);
begin
process is
variable u : int_vector(5 downto 2);
variable v : int_vector(0 to 3);
begin
v := ( 1, 2, 3, 4 );
v(1 to 2) := ( 6, 7 );
assert v = ( 1, 6, 7, 4 );
assert v(2 to 3) = ( 7, 4 );
x <= ( 1, 2, 3, 4 );
wait for 1 ns;
x(1 to 2) <= ( 6, 7 );
wait for 1 ns;
assert x = ( 1, 6, 7, 4 );
assert x(2 to 3) = ( 7, 4 );
u := ( 1, 2, 3, 4);
assert u = ( 1, 2, 3, 4);
u(4 downto 3) := ( 6, 7 );
assert u = ( 1, 6, 7, 4 );
assert u(3 downto 2) = ( 7, 4 );
wait;
end process;
end architecture;
|
entity slice1 is
end entity;
architecture test of slice1 is
type int_vector is array (integer range <>) of integer;
signal x : int_vector(0 to 3);
begin
process is
variable u : int_vector(5 downto 2);
variable v : int_vector(0 to 3);
begin
v := ( 1, 2, 3, 4 );
v(1 to 2) := ( 6, 7 );
assert v = ( 1, 6, 7, 4 );
assert v(2 to 3) = ( 7, 4 );
x <= ( 1, 2, 3, 4 );
wait for 1 ns;
x(1 to 2) <= ( 6, 7 );
wait for 1 ns;
assert x = ( 1, 6, 7, 4 );
assert x(2 to 3) = ( 7, 4 );
u := ( 1, 2, 3, 4);
assert u = ( 1, 2, 3, 4);
u(4 downto 3) := ( 6, 7 );
assert u = ( 1, 6, 7, 4 );
assert u(3 downto 2) = ( 7, 4 );
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_tb_pc is
end entity top_tb_pc;
architecture top_tb_pc_behav of top_tb_pc is
alias slv is std_logic_vector;
subtype slv512 is slv(511 downto 0);
subtype slv256 is slv(255 downto 0);
subtype slv32 is slv(31 downto 0);
subtype word is unsigned(31 downto 0);
component pll is
port (
inclk0 : in std_logic := '0';
c0 : out std_logic
);
end component pll;
component sha256_pc is
generic (
default_h : boolean := true
);
port (
clk : in std_logic;
reset : in std_logic;
msg_in : in std_logic_vector(511 downto 0);
h_in : in std_logic_vector(255 downto 0) := (others => '0');
digest : out std_logic_vector(255 downto 0)
);
end component sha256_pc;
component sha256_qp is
generic (
default_h : boolean := true
);
port (
clk : in std_logic;
reset : in std_logic;
msg_in : in std_logic_vector(511 downto 0);
h_in : in std_logic_vector(255 downto 0) := (others => '0');
digest : out std_logic_vector(255 downto 0)
);
end component sha256_qp;
constant NUM_CORES : natural := 4;
-- SHA256_SEL = 0 => sha256_pc, uses precalculated H + K + W technique
-- SHA256_SEL = 1 => sha256_qp, uses quasi-pipelining technique
constant SHA256_SEL : natural := 0;
constant tclk_40 : time := 25 ns;
type data_array is array(NUM_CORES-1 downto 0) of slv512;
type digest_array is array(NUM_CORES-1 downto 0) of slv256;
type nonce_array is array(NUM_CORES-1 downto 0) of word;
signal OSC_CLK : std_logic := '0';
signal clk : std_logic;
signal reset : std_logic := '0';
signal data_1 : data_array;
signal digest_1 : digest_array;
signal data_2 : data_array;
signal digest_2 : digest_array;
signal data_in : slv256;
signal h_in : slv256;
signal q_data_in : slv256 := (others => '0');
signal q_h_in : slv256 := (others => '0');
signal q_nonce : nonce_array;
signal q_golden_nonce : slv32 := (others => '0');
begin
reset <= '1','0' after 2.5 * tclk_40;
data_in <= X"00000000000000000000000080000000000000002194261a9395e64dbed17115";
h_in <= X"228ea4732a3c9ba860c009cda7252b9161a5e75ec8c582a5f106abb3af41f790";
clk_gen: process is
begin
OSC_CLK <= not OSC_CLK;
wait for tclk_40/2;
end process clk_gen;
pll_inst: pll
port map (
inclk0 => OSC_CLK,
c0 => clk
);
sha256_gen: for i in NUM_CORES-1 downto 0 generate
data_1(i) <= X"000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000" & slv(q_nonce(i)) & q_data_in(95 downto 0);
data_2(i) <= X"0000010000000000000000000000000000000000000000000000000080000000" & digest_1(i);
sha256_pc_gen: if SHA256_SEL = 0 generate
sha256_1: sha256_pc
generic map (
default_h => false
)
port map (
clk => clk,
reset => reset,
msg_in => data_1(i),
h_in => q_h_in,
digest => digest_1(i)
);
sha256_2: sha256_pc
generic map (
default_h => true
)
port map (
clk => clk,
reset => reset,
msg_in => data_2(i),
digest => digest_2(i)
);
end generate sha256_pc_gen;
sha256_qp_gen: if SHA256_SEL = 1 generate
sha256_1: sha256_qp
generic map (
default_h => false
)
port map (
clk => clk,
reset => reset,
msg_in => data_1(i),
h_in => q_h_in,
digest => digest_1(i)
);
sha256_2: sha256_qp
generic map (
default_h => true
)
port map (
clk => clk,
reset => reset,
msg_in => data_2(i),
digest => digest_2(i)
);
end generate sha256_qp_gen;
end generate sha256_gen;
registers: process(clk, reset)
begin
if reset = '1' then
q_data_in <= (others => '0');
q_h_in <= (others => '0');
q_nonce(0) <= X"0e33337a" - 256;
for i in NUM_CORES-1 downto 1 loop
q_nonce(i) <= q_nonce(0) + i;
end loop;
q_golden_nonce <= (others => '0');
elsif rising_edge(clk) then
q_data_in <= data_in;
q_h_in <= h_in;
for i in NUM_CORES-1 downto 0 loop
q_nonce(i) <= q_nonce(0) + i + NUM_CORES;
if digest_2(i)(255 downto 224) = X"00000000" then
if SHA256_SEL = 0 then
q_golden_nonce <= slv(q_nonce(i) - NUM_CORES*131);
else
q_golden_nonce <= slv(q_nonce(i) - NUM_CORES*134);
end if;
end if;
end loop;
end if;
end process registers;
end architecture top_tb_pc_behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_tb_pc is
end entity top_tb_pc;
architecture top_tb_pc_behav of top_tb_pc is
alias slv is std_logic_vector;
subtype slv512 is slv(511 downto 0);
subtype slv256 is slv(255 downto 0);
subtype slv32 is slv(31 downto 0);
subtype word is unsigned(31 downto 0);
component pll is
port (
inclk0 : in std_logic := '0';
c0 : out std_logic
);
end component pll;
component sha256_pc is
generic (
default_h : boolean := true
);
port (
clk : in std_logic;
reset : in std_logic;
msg_in : in std_logic_vector(511 downto 0);
h_in : in std_logic_vector(255 downto 0) := (others => '0');
digest : out std_logic_vector(255 downto 0)
);
end component sha256_pc;
component sha256_qp is
generic (
default_h : boolean := true
);
port (
clk : in std_logic;
reset : in std_logic;
msg_in : in std_logic_vector(511 downto 0);
h_in : in std_logic_vector(255 downto 0) := (others => '0');
digest : out std_logic_vector(255 downto 0)
);
end component sha256_qp;
constant NUM_CORES : natural := 4;
-- SHA256_SEL = 0 => sha256_pc, uses precalculated H + K + W technique
-- SHA256_SEL = 1 => sha256_qp, uses quasi-pipelining technique
constant SHA256_SEL : natural := 0;
constant tclk_40 : time := 25 ns;
type data_array is array(NUM_CORES-1 downto 0) of slv512;
type digest_array is array(NUM_CORES-1 downto 0) of slv256;
type nonce_array is array(NUM_CORES-1 downto 0) of word;
signal OSC_CLK : std_logic := '0';
signal clk : std_logic;
signal reset : std_logic := '0';
signal data_1 : data_array;
signal digest_1 : digest_array;
signal data_2 : data_array;
signal digest_2 : digest_array;
signal data_in : slv256;
signal h_in : slv256;
signal q_data_in : slv256 := (others => '0');
signal q_h_in : slv256 := (others => '0');
signal q_nonce : nonce_array;
signal q_golden_nonce : slv32 := (others => '0');
begin
reset <= '1','0' after 2.5 * tclk_40;
data_in <= X"00000000000000000000000080000000000000002194261a9395e64dbed17115";
h_in <= X"228ea4732a3c9ba860c009cda7252b9161a5e75ec8c582a5f106abb3af41f790";
clk_gen: process is
begin
OSC_CLK <= not OSC_CLK;
wait for tclk_40/2;
end process clk_gen;
pll_inst: pll
port map (
inclk0 => OSC_CLK,
c0 => clk
);
sha256_gen: for i in NUM_CORES-1 downto 0 generate
data_1(i) <= X"000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000" & slv(q_nonce(i)) & q_data_in(95 downto 0);
data_2(i) <= X"0000010000000000000000000000000000000000000000000000000080000000" & digest_1(i);
sha256_pc_gen: if SHA256_SEL = 0 generate
sha256_1: sha256_pc
generic map (
default_h => false
)
port map (
clk => clk,
reset => reset,
msg_in => data_1(i),
h_in => q_h_in,
digest => digest_1(i)
);
sha256_2: sha256_pc
generic map (
default_h => true
)
port map (
clk => clk,
reset => reset,
msg_in => data_2(i),
digest => digest_2(i)
);
end generate sha256_pc_gen;
sha256_qp_gen: if SHA256_SEL = 1 generate
sha256_1: sha256_qp
generic map (
default_h => false
)
port map (
clk => clk,
reset => reset,
msg_in => data_1(i),
h_in => q_h_in,
digest => digest_1(i)
);
sha256_2: sha256_qp
generic map (
default_h => true
)
port map (
clk => clk,
reset => reset,
msg_in => data_2(i),
digest => digest_2(i)
);
end generate sha256_qp_gen;
end generate sha256_gen;
registers: process(clk, reset)
begin
if reset = '1' then
q_data_in <= (others => '0');
q_h_in <= (others => '0');
q_nonce(0) <= X"0e33337a" - 256;
for i in NUM_CORES-1 downto 1 loop
q_nonce(i) <= q_nonce(0) + i;
end loop;
q_golden_nonce <= (others => '0');
elsif rising_edge(clk) then
q_data_in <= data_in;
q_h_in <= h_in;
for i in NUM_CORES-1 downto 0 loop
q_nonce(i) <= q_nonce(0) + i + NUM_CORES;
if digest_2(i)(255 downto 224) = X"00000000" then
if SHA256_SEL = 0 then
q_golden_nonce <= slv(q_nonce(i) - NUM_CORES*131);
else
q_golden_nonce <= slv(q_nonce(i) - NUM_CORES*134);
end if;
end if;
end loop;
end if;
end process registers;
end architecture top_tb_pc_behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_tb_pc is
end entity top_tb_pc;
architecture top_tb_pc_behav of top_tb_pc is
alias slv is std_logic_vector;
subtype slv512 is slv(511 downto 0);
subtype slv256 is slv(255 downto 0);
subtype slv32 is slv(31 downto 0);
subtype word is unsigned(31 downto 0);
component pll is
port (
inclk0 : in std_logic := '0';
c0 : out std_logic
);
end component pll;
component sha256_pc is
generic (
default_h : boolean := true
);
port (
clk : in std_logic;
reset : in std_logic;
msg_in : in std_logic_vector(511 downto 0);
h_in : in std_logic_vector(255 downto 0) := (others => '0');
digest : out std_logic_vector(255 downto 0)
);
end component sha256_pc;
component sha256_qp is
generic (
default_h : boolean := true
);
port (
clk : in std_logic;
reset : in std_logic;
msg_in : in std_logic_vector(511 downto 0);
h_in : in std_logic_vector(255 downto 0) := (others => '0');
digest : out std_logic_vector(255 downto 0)
);
end component sha256_qp;
constant NUM_CORES : natural := 4;
-- SHA256_SEL = 0 => sha256_pc, uses precalculated H + K + W technique
-- SHA256_SEL = 1 => sha256_qp, uses quasi-pipelining technique
constant SHA256_SEL : natural := 0;
constant tclk_40 : time := 25 ns;
type data_array is array(NUM_CORES-1 downto 0) of slv512;
type digest_array is array(NUM_CORES-1 downto 0) of slv256;
type nonce_array is array(NUM_CORES-1 downto 0) of word;
signal OSC_CLK : std_logic := '0';
signal clk : std_logic;
signal reset : std_logic := '0';
signal data_1 : data_array;
signal digest_1 : digest_array;
signal data_2 : data_array;
signal digest_2 : digest_array;
signal data_in : slv256;
signal h_in : slv256;
signal q_data_in : slv256 := (others => '0');
signal q_h_in : slv256 := (others => '0');
signal q_nonce : nonce_array;
signal q_golden_nonce : slv32 := (others => '0');
begin
reset <= '1','0' after 2.5 * tclk_40;
data_in <= X"00000000000000000000000080000000000000002194261a9395e64dbed17115";
h_in <= X"228ea4732a3c9ba860c009cda7252b9161a5e75ec8c582a5f106abb3af41f790";
clk_gen: process is
begin
OSC_CLK <= not OSC_CLK;
wait for tclk_40/2;
end process clk_gen;
pll_inst: pll
port map (
inclk0 => OSC_CLK,
c0 => clk
);
sha256_gen: for i in NUM_CORES-1 downto 0 generate
data_1(i) <= X"000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000" & slv(q_nonce(i)) & q_data_in(95 downto 0);
data_2(i) <= X"0000010000000000000000000000000000000000000000000000000080000000" & digest_1(i);
sha256_pc_gen: if SHA256_SEL = 0 generate
sha256_1: sha256_pc
generic map (
default_h => false
)
port map (
clk => clk,
reset => reset,
msg_in => data_1(i),
h_in => q_h_in,
digest => digest_1(i)
);
sha256_2: sha256_pc
generic map (
default_h => true
)
port map (
clk => clk,
reset => reset,
msg_in => data_2(i),
digest => digest_2(i)
);
end generate sha256_pc_gen;
sha256_qp_gen: if SHA256_SEL = 1 generate
sha256_1: sha256_qp
generic map (
default_h => false
)
port map (
clk => clk,
reset => reset,
msg_in => data_1(i),
h_in => q_h_in,
digest => digest_1(i)
);
sha256_2: sha256_qp
generic map (
default_h => true
)
port map (
clk => clk,
reset => reset,
msg_in => data_2(i),
digest => digest_2(i)
);
end generate sha256_qp_gen;
end generate sha256_gen;
registers: process(clk, reset)
begin
if reset = '1' then
q_data_in <= (others => '0');
q_h_in <= (others => '0');
q_nonce(0) <= X"0e33337a" - 256;
for i in NUM_CORES-1 downto 1 loop
q_nonce(i) <= q_nonce(0) + i;
end loop;
q_golden_nonce <= (others => '0');
elsif rising_edge(clk) then
q_data_in <= data_in;
q_h_in <= h_in;
for i in NUM_CORES-1 downto 0 loop
q_nonce(i) <= q_nonce(0) + i + NUM_CORES;
if digest_2(i)(255 downto 224) = X"00000000" then
if SHA256_SEL = 0 then
q_golden_nonce <= slv(q_nonce(i) - NUM_CORES*131);
else
q_golden_nonce <= slv(q_nonce(i) - NUM_CORES*134);
end if;
end if;
end loop;
end if;
end process registers;
end architecture top_tb_pc_behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_tb_pc is
end entity top_tb_pc;
architecture top_tb_pc_behav of top_tb_pc is
alias slv is std_logic_vector;
subtype slv512 is slv(511 downto 0);
subtype slv256 is slv(255 downto 0);
subtype slv32 is slv(31 downto 0);
subtype word is unsigned(31 downto 0);
component pll is
port (
inclk0 : in std_logic := '0';
c0 : out std_logic
);
end component pll;
component sha256_pc is
generic (
default_h : boolean := true
);
port (
clk : in std_logic;
reset : in std_logic;
msg_in : in std_logic_vector(511 downto 0);
h_in : in std_logic_vector(255 downto 0) := (others => '0');
digest : out std_logic_vector(255 downto 0)
);
end component sha256_pc;
component sha256_qp is
generic (
default_h : boolean := true
);
port (
clk : in std_logic;
reset : in std_logic;
msg_in : in std_logic_vector(511 downto 0);
h_in : in std_logic_vector(255 downto 0) := (others => '0');
digest : out std_logic_vector(255 downto 0)
);
end component sha256_qp;
constant NUM_CORES : natural := 4;
-- SHA256_SEL = 0 => sha256_pc, uses precalculated H + K + W technique
-- SHA256_SEL = 1 => sha256_qp, uses quasi-pipelining technique
constant SHA256_SEL : natural := 0;
constant tclk_40 : time := 25 ns;
type data_array is array(NUM_CORES-1 downto 0) of slv512;
type digest_array is array(NUM_CORES-1 downto 0) of slv256;
type nonce_array is array(NUM_CORES-1 downto 0) of word;
signal OSC_CLK : std_logic := '0';
signal clk : std_logic;
signal reset : std_logic := '0';
signal data_1 : data_array;
signal digest_1 : digest_array;
signal data_2 : data_array;
signal digest_2 : digest_array;
signal data_in : slv256;
signal h_in : slv256;
signal q_data_in : slv256 := (others => '0');
signal q_h_in : slv256 := (others => '0');
signal q_nonce : nonce_array;
signal q_golden_nonce : slv32 := (others => '0');
begin
reset <= '1','0' after 2.5 * tclk_40;
data_in <= X"00000000000000000000000080000000000000002194261a9395e64dbed17115";
h_in <= X"228ea4732a3c9ba860c009cda7252b9161a5e75ec8c582a5f106abb3af41f790";
clk_gen: process is
begin
OSC_CLK <= not OSC_CLK;
wait for tclk_40/2;
end process clk_gen;
pll_inst: pll
port map (
inclk0 => OSC_CLK,
c0 => clk
);
sha256_gen: for i in NUM_CORES-1 downto 0 generate
data_1(i) <= X"000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000" & slv(q_nonce(i)) & q_data_in(95 downto 0);
data_2(i) <= X"0000010000000000000000000000000000000000000000000000000080000000" & digest_1(i);
sha256_pc_gen: if SHA256_SEL = 0 generate
sha256_1: sha256_pc
generic map (
default_h => false
)
port map (
clk => clk,
reset => reset,
msg_in => data_1(i),
h_in => q_h_in,
digest => digest_1(i)
);
sha256_2: sha256_pc
generic map (
default_h => true
)
port map (
clk => clk,
reset => reset,
msg_in => data_2(i),
digest => digest_2(i)
);
end generate sha256_pc_gen;
sha256_qp_gen: if SHA256_SEL = 1 generate
sha256_1: sha256_qp
generic map (
default_h => false
)
port map (
clk => clk,
reset => reset,
msg_in => data_1(i),
h_in => q_h_in,
digest => digest_1(i)
);
sha256_2: sha256_qp
generic map (
default_h => true
)
port map (
clk => clk,
reset => reset,
msg_in => data_2(i),
digest => digest_2(i)
);
end generate sha256_qp_gen;
end generate sha256_gen;
registers: process(clk, reset)
begin
if reset = '1' then
q_data_in <= (others => '0');
q_h_in <= (others => '0');
q_nonce(0) <= X"0e33337a" - 256;
for i in NUM_CORES-1 downto 1 loop
q_nonce(i) <= q_nonce(0) + i;
end loop;
q_golden_nonce <= (others => '0');
elsif rising_edge(clk) then
q_data_in <= data_in;
q_h_in <= h_in;
for i in NUM_CORES-1 downto 0 loop
q_nonce(i) <= q_nonce(0) + i + NUM_CORES;
if digest_2(i)(255 downto 224) = X"00000000" then
if SHA256_SEL = 0 then
q_golden_nonce <= slv(q_nonce(i) - NUM_CORES*131);
else
q_golden_nonce <= slv(q_nonce(i) - NUM_CORES*134);
end if;
end if;
end loop;
end if;
end process registers;
end architecture top_tb_pc_behav;
|
entity tb_testrec is
end tb_testrec;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_testrec is
signal a : std_logic;
signal b : std_logic;
begin
dut: entity work.testrec
port map (a, b);
process
begin
wait for 1 ns;
assert b = '0' severity failure;
wait;
end process;
end behav;
|
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | __ <
-- | | | | | | \ | | | | |__> )
-- |____| |____| |__| \__| |__| |_______/
--
-- NTB University of Applied Sciences in Technology
--
-- Campus Buchs - Werdenbergstrasse 4 - 9471 Buchs - Switzerland
-- Campus Waldau - Schoenauweg 4 - 9013 St. Gallen - Switzerland
--
-- Web http://www.ntb.ch Tel. +41 81 755 33 11
--
-------------------------------------------------------------------------------
-- Copyright 2013 NTB University of Applied Sciences in Technology
-------------------------------------------------------------------------------
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.i2c_master_pkg.ALL;
-------------------------------------------------------------------------------
-- PACKAGE DEFINITION
-------------------------------------------------------------------------------
PACKAGE itg3200_pkg IS
CONSTANT NR_OF_DATA_REGS : INTEGER := 6;
CONSTANT WAIT_CYCLES : INTEGER := 2014;
CONSTANT WHO_AM_I : STD_LOGIC_VECTOR(REGISTER_WIDTH - 1 DOWNTO 0) := x"00";
CONSTANT SMPLRT_DIV : STD_LOGIC_VECTOR(REGISTER_WIDTH - 1 DOWNTO 0) := x"15";
CONSTANT DLPF_FS : STD_LOGIC_VECTOR(REGISTER_WIDTH - 1 DOWNTO 0) := x"16";
CONSTANT INT_CFG : STD_LOGIC_VECTOR(REGISTER_WIDTH - 1 DOWNTO 0) := x"17";
CONSTANT INT_STATUS : STD_LOGIC_VECTOR(REGISTER_WIDTH - 1 DOWNTO 0) := x"1A";
CONSTANT TEMP_OUT_H : STD_LOGIC_VECTOR(REGISTER_WIDTH - 1 DOWNTO 0) := x"1B";
CONSTANT TEMP_OUT_L : STD_LOGIC_VECTOR(REGISTER_WIDTH - 1 DOWNTO 0) := x"1C";
CONSTANT GYRO_XOUT_H : STD_LOGIC_VECTOR(REGISTER_WIDTH - 1 DOWNTO 0) := x"1D";
CONSTANT GYRO_XOUT_L : STD_LOGIC_VECTOR(REGISTER_WIDTH - 1 DOWNTO 0) := x"1E";
CONSTANT GYRO_YOUT_H : STD_LOGIC_VECTOR(REGISTER_WIDTH - 1 DOWNTO 0) := x"1F";
CONSTANT GYRO_YOUT_L : STD_LOGIC_VECTOR(REGISTER_WIDTH - 1 DOWNTO 0) := x"20";
CONSTANT GYRO_ZOUT_H : STD_LOGIC_VECTOR(REGISTER_WIDTH - 1 DOWNTO 0) := x"21";
CONSTANT GYRO_ZOUT_L : STD_LOGIC_VECTOR(REGISTER_WIDTH - 1 DOWNTO 0) := x"22";
CONSTANT PWR_MGM : STD_LOGIC_VECTOR(REGISTER_WIDTH - 1 DOWNTO 0) := x"3E";
Type t_data_regs IS ARRAY(NR_OF_DATA_REGS-1 DOWNTO 0) OF STD_LOGIC_VECTOR(REGISTER_WIDTH - 1 DOWNTO 0);
COMPONENT itg3200 IS
GENERIC(
BASE_CLK : INTEGER := 250000000
);
PORT(
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
--i2c signals
osl_scl : OUT STD_LOGIC;
oisl_sda : INOUT STD_LOGIC;
--internal signals
isl_start : IN STD_LOGIC;
ot_data : OUT t_data_regs
);
END COMPONENT itg3200;
END PACKAGE itg3200_pkg;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.itg3200_pkg.ALL;
USE work.i2c_master_pkg.ALL;
-------------------------------------------------------------------------------
-- ENTITIY
-------------------------------------------------------------------------------
ENTITY itg3200 IS
GENERIC(
BASE_CLK : INTEGER := 250000000
);
PORT(
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
--i2c signals
osl_scl : OUT STD_LOGIC;
oisl_sda : INOUT STD_LOGIC;
--internal signals
isl_start : IN STD_LOGIC;
ot_data : OUT t_data_regs
);
END ENTITY itg3200;
-------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF itg3200 IS
TYPE t_states IS ( idle,write_power_mode,write_samplerate,read_gyro_out
);
TYPE t_internal_register IS RECORD
state : t_states;
dev_address : STD_LOGIC_VECTOR(DEV_ADDRESS_WIDTH-1 DOWNTO 0);
byte_count : UNSIGNED(3 DOWNTO 0);
out_data : t_data_regs;
register_address : STD_LOGIC_VECTOR(REGISTER_WIDTH-1 DOWNTO 0);
write_data : STD_LOGIC_VECTOR(REGISTER_WIDTH-1 DOWNTO 0);
start_transfer : STD_LOGIC;
write_n_read : STD_LOGIC;
enable_burst_transfer : STD_LOGIC;
END RECORD;
CONSTANT INTERNAL_REG_RESET : t_internal_register := (
state => idle,
byte_count => (OTHERS => '0'),
out_data => (OTHERS => (OTHERS => '0')),
dev_address => (OTHERS => '0'),
register_address => (OTHERS => '0'),
write_data => (OTHERS => '0'),
start_transfer => '0',
write_n_read => '0',
enable_burst_transfer => '0'
);
SIGNAL ri, ri_next : t_internal_register := INTERNAL_REG_RESET;
SIGNAL read_data : STD_LOGIC_VECTOR(REGISTER_WIDTH-1 DOWNTO 0);
SIGNAL transfer_done : STD_LOGIC;
BEGIN
--create component
my_i2c : i2c_master
GENERIC MAP(
BASE_CLK => 250000000
)
PORT MAP(
isl_clk => isl_clk,
isl_reset_n => isl_reset_n,
osl_scl => osl_scl,
oisl_sda => oisl_sda,
--internal signals
islv_dev_address => ri.dev_address,
islv_register_address => ri.register_address,
islv_write_data => ri.write_data,
oslv_read_data => read_data,
isl_start_transfer => ri.start_transfer,
isl_write_n_read => ri.write_n_read,
isl_enable_burst_transfer => ri.enable_burst_transfer,
osl_transfer_done => transfer_done
);
--------------------------------------------
-- combinatorial process
--------------------------------------------
comb_process: PROCESS(ri, isl_reset_n,transfer_done,read_data,isl_start)
VARIABLE vi: t_internal_register;
BEGIN
-- keep variables stable
vi:=ri;
CASE vi.state IS
WHEN idle =>
IF(isl_start = '1') THEN
vi.state := write_power_mode;
END IF;
WHEN write_power_mode =>
vi.dev_address := "1101000";
vi.register_address := DLPF_FS;
vi.write_data := x"19";
vi.start_transfer := '1';
vi.write_n_read := '1';
vi.enable_burst_transfer := '0';
IF(transfer_done = '1') THEN
vi.start_transfer := '0';
vi.state := write_samplerate;
END IF;
WHEN write_samplerate =>
vi.dev_address := "1101000";
vi.register_address := PWR_MGM;
vi.write_data := x"03";
vi.start_transfer := '1';
vi.write_n_read := '1';
vi.enable_burst_transfer := '0';
IF(transfer_done = '1') THEN
vi.start_transfer := '0';
vi.state := read_gyro_out;
vi.byte_count := (OTHERS => '0');
vi.enable_burst_transfer := '1';
END IF;
WHEN read_gyro_out =>
vi.dev_address := "1101000";
vi.register_address := GYRO_XOUT_H;
vi.start_transfer := '1';
vi.write_n_read := '0';
IF(transfer_done = '1') THEN
vi.out_data(to_integer(vi.byte_count)) := read_data;
vi.byte_count := vi.byte_count + 1;
IF(vi.byte_count = NR_OF_DATA_REGS-1) THEN
vi.enable_burst_transfer := '0';
ELSIF(vi.byte_count = NR_OF_DATA_REGS) THEN
vi.start_transfer := '0';
vi.enable_burst_transfer := '1';
vi.byte_count := (OTHERS => '0');
vi.state := read_gyro_out;
END IF;
END IF;
WHEN OTHERS =>
vi.state := idle;
END CASE;
--reset
IF isl_reset_n = '0' THEN
vi:= INTERNAL_REG_RESET;
END IF;
-- setting outputs
ri_next <= vi;
END PROCESS comb_process;
--------------------------------------------
-- registered process
--------------------------------------------
reg_process: PROCESS (isl_clk)
BEGIN
IF rising_edge(isl_clk) THEN
ri <= ri_next;
END IF;
END PROCESS reg_process;
ot_data <= ri.out_data;
END ARCHITECTURE rtl;
|
-------------------------------------------------------------------------------------
-- FILE NAME : tb_packer_128.vhd
-- AUTHOR : Luis
-- COMPANY :
-- UNITS : Entity - tb_packer_128
-- Architecture - Behavioral
-- LANGUAGE : VHDL
-- DATE : May 21, 2010
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- LIBRARIES
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
Library UNISIM;
use UNISIM.vcomponents.all;
-------------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------------
entity tb_packer_128 is
end tb_packer_128;
-------------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------------
architecture Behavioral of tb_packer_128 is
-------------------------------------------------------------------------------------
-- CONSTANTS
-------------------------------------------------------------------------------------
constant CLK_200_MHZ : time := 5 ns;
constant CLK_100_MHZ : time := 10 ns;
constant CLK_300_MHZ : time := 3.3333 ns;
constant CLK_25_MHZ : time := 40 ns;
constant CLK_167_MHZ : time := 6 ns;
-----------------------------------------------------------------------------------
-- SIGNALS
-----------------------------------------------------------------------------------
signal sysclk_p : std_logic := '1';
signal sysclk_n : std_logic := '0';
signal clk : std_logic := '1';
signal rst : std_logic := '1';
signal rstn : std_logic := '0';
signal din : std_logic_vector(127 downto 0);
signal val_in : std_logic;
signal sample : std_logic_vector(15 downto 0);
signal dout : std_logic_vector(127 downto 0);
signal val_out : std_logic;
signal din_64bit : std_logic_vector(63 downto 0);
signal validin_64bit : std_logic;
signal dout_64bit : std_logic_vector(63 downto 0);
signal validout_64bit : std_logic;
--***********************************************************************************
begin
--***********************************************************************************
-- Clock & reset generation
sysclk_p <= not sysclk_p after CLK_100_MHZ/2;
sysclk_n <= not sysclk_p;
clk <= not clk after CLK_100_MHZ / 2;
rst <= '0' after CLK_100_MHZ * 10;
rstn <= '1' after CLK_100_MHZ * 10;
-----------------------------------------------------------------------------------
-- Unit under test
-----------------------------------------------------------------------------------
packer_128_inst0 :
entity work.packer_128
port map (
clk_in => clk,
rst_in => rst,
val_in => val_in(127 downto 0),
data_in => din,
val_out => val_out(127 downto 0),
data_out => dout,
test_mode => '1'
);
--pack_16to12_inst0:
--entity work.pack_16to12
--port map(
-- clk => clk,
-- rst => rst,
-- enable => '1',
-- data_in_dval => validin_64bit,
-- data_in => din_64bit,
-- data_in_stop => open,
-- data_out_dval => dout_64bit,
-- data_out => validout_64bit,
-- data_out_stop => '0'
--);
-----------------------------------------------------------------------------------
-- Stimulus
-----------------------------------------------------------------------------------
process(clk, rst)
begin
if rising_edge(clk) then
if rst = '1' then
val_in <= '0';
sample <= (others=>'0');
else
val_in <= '1';
sample <= sample + 8;
end if;
end if;
end process;
--din(15 downto 0) <= sample + 0;
--din(31 downto 16) <= sample + 1;
--din(47 downto 32) <= sample + 2;
--din(63 downto 48) <= sample + 3;
--din(79 downto 64) <= sample + 4;
--din(95 downto 80) <= sample + 5;
--din(111 downto 96) <= sample + 6;
--din(127 downto 112) <= sample + 7;
din(15 downto 0) <= x"0" & x"AAA";
din(31 downto 16) <= x"0" & x"BBB";
din(47 downto 32) <= x"0" & x"CCC";
din(63 downto 48) <= x"0" & x"DDD";
din(79 downto 64) <= x"0" & x"EEE";
din(95 downto 80) <= x"0" & x"FFF";
din(111 downto 96) <= x"0" & x"999";
din(127 downto 112) <= x"0" & x"888";
--***********************************************************************************
end architecture Behavioral;
--***********************************************************************************
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2011 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.i2c.all;
use gaisler.can.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
-- pragma translate_off
use gaisler.sim.all;
library unisim;
use unisim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic; -- 50 MHz main clock
clk2 : in std_ulogic; -- User clock
clk125 : in std_ulogic; -- 125 MHz clock from PHY
wdogn : out std_ulogic;
address : out std_logic_vector(24 downto 0);
data : inout std_logic_vector(31 downto 24);
oen : out std_ulogic;
writen : out std_ulogic;
romsn : out std_logic;
ddr_clk : out std_logic;
ddr_clkb : out std_logic;
ddr_cke : out std_logic;
ddr_odt : out std_logic;
ddr_we : out std_ulogic; -- ddr write enable
ddr_ras : out std_ulogic; -- ddr ras
ddr_csn : out std_ulogic; -- ddr csn
ddr_cas : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (1 downto 0); -- ddr dqs n
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (2 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
ddr_rzq : inout std_ulogic;
ddr_zio : inout std_ulogic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
ctsn1 : in std_ulogic; -- UART1 ctsn
rtsn1 : out std_ulogic; -- UART1 trsn
txd2 : out std_ulogic; -- UART2 tx data
rxd2 : in std_ulogic; -- UART2 rx data
ctsn2 : in std_ulogic; -- UART2 ctsn
rtsn2 : out std_ulogic; -- UART2 rtsn
pio : inout std_logic_vector(17 downto 0); -- I/O port
genio : inout std_logic_vector(59 downto 0); -- I/O port
switch : in std_logic_vector(9 downto 0); -- I/O port
led : out std_logic_vector(3 downto 0); -- I/O port
erx_clk : in std_ulogic;
emdio : inout std_logic; -- ethernet PHY interface
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
emdint : in std_ulogic;
etx_clk : out std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
emdc : out std_ulogic;
ps2clk : inout std_logic_vector(1 downto 0);
ps2data : inout std_logic_vector(1 downto 0);
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
ddc_scl : inout std_ulogic;
ddc_sda : inout std_ulogic;
dvi_iic_scl : inout std_logic;
dvi_iic_sda : inout std_logic;
tft_lcd_data : out std_logic_vector(11 downto 0);
tft_lcd_clk_p : out std_ulogic;
tft_lcd_clk_n : out std_ulogic;
tft_lcd_hsync : out std_ulogic;
tft_lcd_vsync : out std_ulogic;
tft_lcd_de : out std_ulogic;
tft_lcd_reset_b : out std_ulogic;
spw_clk : in std_ulogic;
spw_rxdp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxdn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdn : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsn : out std_logic_vector(0 to CFG_SPW_NUM-1);
-- SPI flash
spi_sel_n : inout std_ulogic;
spi_clk : out std_ulogic;
spi_mosi : out std_ulogic
);
end;
architecture rtl of leon3mp is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component IODELAY2
generic (
COUNTER_WRAPAROUND : string := "WRAPAROUND";
DATA_RATE : string := "SDR";
DELAY_SRC : string := "IO";
IDELAY2_VALUE : integer := 0;
IDELAY_MODE : string := "NORMAL";
IDELAY_TYPE : string := "DEFAULT";
IDELAY_VALUE : integer := 0;
ODELAY_VALUE : integer := 0;
SERDES_MODE : string := "NONE";
SIM_TAPDELAY_VALUE : integer := 75
);
port (
BUSY : out std_ulogic;
DATAOUT : out std_ulogic;
DATAOUT2 : out std_ulogic;
DOUT : out std_ulogic;
TOUT : out std_ulogic;
CAL : in std_ulogic;
CE : in std_ulogic;
CLK : in std_ulogic;
IDATAIN : in std_ulogic;
INC : in std_ulogic;
IOCLK0 : in std_ulogic;
IOCLK1 : in std_ulogic;
ODATAIN : in std_ulogic;
RST : in std_ulogic;
T : in std_ulogic
);
end component;
attribute syn_netlist_hierarchy : boolean;
attribute syn_netlist_hierarchy of rtl : architecture is false;
constant use_eth_input_delay : integer := 1;
constant use_eth_output_delay : integer := 1;
constant use_eth_data_output_delay : integer := 1;
constant use_eth_input_delay_clk : integer := 0;
constant use_gtx_clk : integer := 0;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := CFG_NCPU+CFG_AHB_UART+CFG_GRETH+
CFG_AHB_JTAG+CFG_SPW_NUM*CFG_SPW_EN;
signal vcc, gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi, apbi2 : apb_slv_in_type;
signal apbo, apbo2 : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal vahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal vahbmo : ahb_mst_out_type;
signal clkm, rstn, rstraw, sdclkl : std_ulogic;
signal clk_200 : std_ulogic;
signal clk25, clk40, clk65 : std_ulogic;
signal cgi, cgi2, cgi3 : clkgen_in_type;
signal cgo, cgo2, cgo3 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gmiii, rgmiii, rgmiii_buf, rgmii_pad : eth_in_type;
signal gmiio, rgmiio : eth_out_type;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal gpioi2 : gpio_in_type;
signal gpioo2 : gpio_out_type;
signal gpioi3 : gpio_in_type;
signal gpioo3 : gpio_out_type;
signal can_lrx, can_ltx : std_logic_vector(0 to 7);
signal lock, calib_done, clkml, lclk, rst, ndsuact, wdogl : std_ulogic := '0';
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ethclk, ddr2clk : std_ulogic;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal spmi2 : spimctrl_in_type;
signal spmo2 : spimctrl_out_type;
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := CFG_CAN;
constant DDR2_FREQ : integer := 200000; -- DDR2 input frequency in KHz
signal spwi : grspw_in_type_vector(0 to CFG_SPW_NUM-1);
signal spwo : grspw_out_type_vector(0 to CFG_SPW_NUM-1);
signal dtmp : std_logic_vector(CFG_SPW_NUM*CFG_SPW_PORTS-1 downto 0);
signal stmp : std_logic_vector(CFG_SPW_NUM*CFG_SPW_PORTS-1 downto 0);
signal spw_rxtxclk : std_ulogic;
signal spw_rxclkn : std_ulogic;
signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM*CFG_SPW_PORTS);
signal spw_rstn : std_ulogic;
signal spw_rstn_sync : std_ulogic;
signal stati : ahbstat_in_type;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
signal rstgtxn : std_logic;
signal idelay_reset_cnt : std_logic_vector(3 downto 0);
signal idelay_cal_cnt : std_logic_vector(3 downto 0);
signal idelayctrl_reset : std_logic;
signal idelayctrl_cal : std_logic;
signal rgmiii_rx_clk_n : std_logic;
signal rgmiii_rx_clk_n_buf : std_logic;
signal rgmiio_tx_clk,rgmiio_tx_en : std_logic;
signal rgmiio_txd : std_logic_vector(3 downto 0);
-- Used for connecting input/output signals to the DDR2 controller
signal core_ddr_clk : std_logic_vector(2 downto 0);
signal core_ddr_clkb : std_logic_vector(2 downto 0);
signal core_ddr_cke : std_logic_vector(1 downto 0);
signal core_ddr_csb : std_logic_vector(1 downto 0);
signal core_ddr_ad : std_logic_vector(13 downto 0);
signal core_ddr_odt : std_logic_vector(1 downto 0);
constant SPW_LOOP_BACK : integer := 0;
signal video_clk, clk50, clk100, spw100 : std_logic; -- signals to vga_clkgen.
signal clk_sel : std_logic_vector(1 downto 0);
signal clkvga, clkvga_p, clkvga_n : std_ulogic;
signal clk_125, clk_125_pll, clk_125_bufg : std_ulogic;
signal nerror : std_ulogic;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of clk50 : signal is true;
attribute syn_preserve of clk50 : signal is true;
attribute keep of clk50 : signal is true;
attribute syn_keep of video_clk : signal is true;
attribute syn_preserve of video_clk : signal is true;
attribute keep of video_clk : signal is true;
attribute syn_preserve of ddr2clk : signal is true;
attribute keep of ddr2clk : signal is true;
attribute syn_keep of ddr2clk : signal is true;
attribute syn_preserve of spw100 : signal is true;
attribute keep of spw100 : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of clkm : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1'; gnd <= '0';
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
ddr2clk <= lclk;
ethclk <= lclk;
no_clk_mig : if CFG_MIG_DDR2 = 0 generate
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo, open, clk50, clk100);
rst0 : rstgen -- reset generator
generic map(syncin => 1)
port map (rst, clkm, lock, rstn, rstraw);
end generate;
clk_mig : if CFG_MIG_DDR2 = 1 generate
clk50 <= clkm;
rstraw <= rst;
cgo.clklock <= '1';
end generate;
resetn_pad : inpad generic map (tech => padtech) port map (resetn, rst);
lock <= cgo.clklock and calib_done;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 16)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
nosh : if CFG_GRFPUSH = 0 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ft -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE, CFG_BP,
CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm);
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ftsh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE,
CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm, fpi(i), fpo(i));
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
nerror <= dbgo(0).error;
led1_pad : odpad generic map (tech => padtech) port map (led(1), nerror);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (switch(7), dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (switch(8), dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (led(0), ndsuact);
ndsuact <= not dsuo.active;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; ahbso(2) <= ahbs_none;
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (rxd2, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (txd2, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
memi.brdyn <= '0'; memi.bexcn <= '1';
mctrl0 : if CFG_MCTRL_LEON2 /= 0 generate
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
paddr => 0, srbanks => 2, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS,
pageburst => CFG_MCTRL_PAGE, rammask => 0, iomask => 0)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 25, tech => padtech)
port map (address, memo.address(24 downto 0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
bdr : for i in 0 to 0 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
nomctrl : if CFG_MCTRL_LEON2 = 0 generate
romsn <= '1'; ahbso(0) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 6, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(6));
-- pragma translate_on
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
ddr_csn <= '0';
mig_gen : if (CFG_MIG_DDR2 = 1) generate
ddrc : entity work.ahb2mig_grxc6s_2p
generic map(
hindex => 4, haddr => 16#400#, hmask => 16#F80#,
pindex => 0, paddr => 0, vgamst => CFG_SVGA_ENABLE, vgaburst => 64,
clkdiv => 10)
port map(
mcb3_dram_dq => ddr_dq,
mcb3_dram_a => ddr_ad,
mcb3_dram_ba => ddr_ba,
mcb3_dram_ras_n => ddr_ras,
mcb3_dram_cas_n => ddr_cas,
mcb3_dram_we_n => ddr_we,
mcb3_dram_odt => ddr_odt,
mcb3_dram_cke => ddr_cke,
mcb3_dram_dm => ddr_dm(0),
mcb3_dram_udqs => ddr_dqs(1),
mcb3_dram_udqs_n => ddr_dqsn(1),
mcb3_rzq => ddr_rzq,
mcb3_zio => ddr_zio,
mcb3_dram_udm => ddr_dm(1),
mcb3_dram_dqs => ddr_dqs(0),
mcb3_dram_dqs_n => ddr_dqsn(0),
mcb3_dram_ck => ddr_clk,
mcb3_dram_ck_n => ddr_clkb,
ahbsi => ahbsi,
ahbso => ahbso(4),
ahbmi => vahbmi,
ahbmo => vahbmo,
apbi => apbi2,
apbo => apbo2(0),
calib_done => calib_done,
rst_n_syn => rstn,
rst_n_async => rstraw,
clk_amba => clkm,
clk_mem_n => ddr2clk,
clk_mem_p => ddr2clk,
test_error => open,
clk_125 => clk_125,
clk_100 => clk100
);
end generate;
noddr : if (CFG_DDR2SP+CFG_MIG_DDR2) = 0 generate calib_done <= '1'; end generate;
----------------------------------------------------------------------
--- SPI Memory Controller--------------------------------------------
----------------------------------------------------------------------
spimc: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 1 generate
spimctrl0 : spimctrl -- SPI Memory Controller
generic map (hindex => 3, hirq => 7, faddr => 16#e00#, fmask => 16#ff8#,
ioaddr => 16#002#, iomask => 16#fff#,
spliten => CFG_SPLIT, oepol => 0,
sdcard => CFG_SPIMCTRL_SDCARD,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER,
pwrupcnt => CFG_SPIMCTRL_PWRUPCNT)
port map (rstn, clkm, ahbsi, ahbso(3), spmi, spmo);
-- MISO is shared with Flash data 0
spmi.miso <= memi.data(24);
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, spmo.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, spmo.sck);
slvsel0_pad : odpad generic map (tech => padtech)
port map (spi_sel_n, spmo.csn);
end generate;
nospimc: if ((CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 0) or
(CFG_SPICTRL_ENABLE = 1 and CFG_SPIMCTRL = 1) or
(CFG_SPICTRL_ENABLE = 1 and CFG_SPIMCTRL = 0))generate
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, '0');
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, '0');
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
apb1 : apbctrl -- AHB/APB bridge
generic map (hindex => 13, haddr => CFG_APBADDR+1, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(13), apbi2, apbo2 );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
rxd1_pad : inpad generic map (tech => padtech) port map (rxd1, u1i.rxd);
txd1_pad : outpad generic map (tech => padtech) port map (txd1, u1o.txd);
cts1_pad : inpad generic map (tech => padtech) port map (ctsn1, u1i.ctsn);
rts1_pad : outpad generic map (tech => padtech) port map (rtsn1, u1o.rtsn);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
rts1_pad : outpad generic map (tech => padtech) port map (rtsn2, '0');
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOGEN*CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
wden : if CFG_GPT_WDOGEN /= 0 generate
wdogl <= gpto.wdogn or not rstn;
--wdogn_pad : odpad generic map (tech => padtech) port map (wdogn, wdogl);
wdogn_pad : outpad generic map (tech => padtech) port map (wdogn, wdogl);
end generate;
wddis : if CFG_GPT_WDOGEN = 0 generate
--wdogn_pad : odpad generic map (tech => padtech) port map (wdogn, vcc);
wdogn_pad : outpad generic map (tech => padtech) port map (wdogn, vcc);
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
port map(rstn, clkm, apbi, apbo(4), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate
apbo(4) <= apb_none; mouo <= ps2o_none;
apbo(5) <= apb_none; kbdo <= ps2o_none;
end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(1),kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2data(1), kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(0),mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2data(0), mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, ethclk, apbi, apbo(6), vgao);
video_clk <= not ethclk;
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 20000, clk1 => 0, --1000000000/((BOARD_FREQ * CFG_CLKMUL)/CFG_CLKDIV),
clk2 => 0, clk3 => 0, burstlen => 6)
port map(rstn, clkm, video_clk, apbi, apbo(6), vgao, vahbmi,
vahbmo, clk_sel);
end generate;
--b0 : techbuf generic map (2, fabtech) port map (clk50, video_clk);
video_clk <= clk50;
vgadvi : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) /= 0 generate
dvi0 : entity work.svga2ch7301c generic map (tech => fabtech, dynamic => 1)
port map (clkm, vgao, video_clk, clkvga_p, clkvga_n,
lcd_datal, lcd_hsyncl, lcd_vsyncl, lcd_del);
i2cdvi : i2cmst
generic map (pindex => 9, paddr => 9, pmask => 16#FFF#, pirq => 3)
port map (rstn, clkm, apbi, apbo(9), dvi_i2ci, dvi_i2co);
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
tft_lcd_data_pad : outpadv generic map (width => 12, tech => padtech)
port map (tft_lcd_data, lcd_datal);
tft_lcd_clkp_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_p, clkvga_p);
tft_lcd_clkn_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_n, clkvga_n);
tft_lcd_hsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_hsync, lcd_hsyncl);
tft_lcd_vsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_vsync, lcd_vsyncl);
tft_lcd_de_pad : outpad generic map (tech => padtech)
port map (tft_lcd_de, lcd_del);
tft_lcd_reset_pad : outpad generic map (tech => padtech)
port map (tft_lcd_reset_b, rstn);
dvi_i2c_scl_pad : iopad generic map (tech => padtech)
port map (dvi_iic_scl, dvi_i2co.scl, dvi_i2co.scloen, dvi_i2ci.scl);
dvi_i2c_sda_pad : iopad generic map (tech => padtech)
port map (dvi_iic_sda, dvi_i2co.sda, dvi_i2co.sdaoen, dvi_i2ci.sda);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 10, paddr => 10, imask => CFG_GRGPIO_IMASK, nbits => 16)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(10),
gpioi => gpioi, gpioo => gpioo);
p0 : if (CFG_CAN = 0) or (CFG_CAN_NUM = 1) generate
pio_pads : for i in 1 to 2 generate
pio_pad : iopad generic map (tech => padtech)
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
p1 : if (CFG_CAN = 0) generate
pio_pads : for i in 4 to 5 generate
pio_pad : iopad generic map (tech => padtech)
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
pio_pad0 : iopad generic map (tech => padtech)
port map (pio(0), gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
pio_pad1 : iopad generic map (tech => padtech)
port map (pio(3), gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
pio_pads : for i in 6 to 15 generate
pio_pad : iopad generic map (tech => padtech)
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-- make an additonal 32 bit GPIO port for genio(31..0)
gpio1 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio1: grgpio
generic map(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 32)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(11),
gpioi => gpioi2, gpioo => gpioo2);
pio_pads : for i in 0 to 31 generate
pio_pad : iopad generic map (tech => padtech)
port map (genio(i), gpioo2.dout(i), gpioo2.oen(i), gpioi2.din(i));
end generate;
end generate;
gpio2 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio2: grgpio
generic map(pindex => 12, paddr => 12, imask => CFG_GRGPIO_IMASK, nbits => 28)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(12),
gpioi => gpioi3, gpioo => gpioo3);
pio_pads : for i in 0 to 27 generate
pio_pad : iopad generic map (tech => padtech)
port map (genio(i+32), gpioo3.dout(i), gpioo3.oen(i), gpioi3.din(i));
end generate;
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati <= ahbstat_in_none;
ahbstat0 : ahbstat generic map (pindex => 13, paddr => 13, pirq => 1,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(13));
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 14, paddr => 14, pirq => 6, memtech => memtech,
mdcscaler => CPU_FREQ/1000, rmii => 0, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 2, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, phyrstadr => 1,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(14), ethi => gmiii, etho => gmiio);
end generate;
led(3 downto 2) <= not (gmiio.gbit & gmiio.speed);
noethindelay0 : if (use_eth_input_delay = 0) generate
rgmiii.rx_dv <= rgmiii_buf.rx_dv;
rgmiii.rxd <= rgmiii_buf.rxd;
end generate;
noethoutdelay0 : if (use_eth_output_delay = 0) generate
rgmiio_tx_clk <= rgmiio.tx_clk;
end generate;
noethdataoutdelay0 : if (use_eth_data_output_delay = 0) generate
rgmiio_tx_en <= rgmiio.tx_en;
rgmiio_txd <= rgmiio.txd(3 downto 0);
end generate;
ethindelay0 : if (use_eth_input_delay /= 0) generate
erx_clk0 : if (use_eth_input_delay_clk /= 0) generate
delay_rgmii_rx_clk : IODELAY2 generic map(
DELAY_SRC => "IDATAIN",
IDELAY_TYPE => "FIXED",
DATA_RATE => "DDR",
IDELAY_VALUE => 0 -- (See table 39 in Xilinx ds162.pdf)
)
port map(
IDATAIN => rgmiii_buf.rx_clk,
T => '1',
ODATAIN => '0',
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => rgmiii.rx_clk,
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => OPEN
);
end generate;
delay_rgmii_rx_ctl0 : IODELAY2 generic map(
DELAY_SRC => "IDATAIN",
IDELAY_TYPE => "FIXED",
DATA_RATE => "DDR",
IDELAY_VALUE => 80 -- (See table 39 in Xilinx ds162.pdf)
)
port map(
IDATAIN => rgmiii_buf.rx_dv,
T => '1',
ODATAIN => '0',
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => rgmiii.rx_dv,
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => OPEN
);
rgmii_rxd : for i in 0 to 3 generate
delay_rgmii_rxd0 : IODELAY2 generic map(
DELAY_SRC => "IDATAIN",
IDELAY_TYPE => "FIXED",
DATA_RATE => "DDR",
IDELAY_VALUE => 80 -- (See table 39 in Xilinx ds162.pdf)
)
port map(
IDATAIN => rgmiii_buf.rxd(i),
T => '1',
ODATAIN => '0',
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => rgmiii.rxd(i),
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => OPEN
);
end generate;
end generate;
ethoutdelay0 : if (use_eth_output_delay /= 0) generate
delay_rgmii_tx_clk0 : IODELAY2 generic map(
DELAY_SRC => "ODATAIN",
IDELAY_TYPE => "FIXED",
DATA_RATE => "DDR",
ODELAY_VALUE => 30 -- (See table 39 in Xilinx ds162.pdf)
)
port map(
IDATAIN => '0',
T => '1',
ODATAIN => rgmiio.tx_clk,
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => OPEN,
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => rgmiio_tx_clk
);
end generate;
ethoutdatadelay0 : if (use_eth_data_output_delay /= 0) generate
delay_rgmii_tx_en0 : IODELAY2 generic map(
DELAY_SRC => "ODATAIN",
IDELAY_TYPE => "FIXED",
DATA_RATE => "DDR",
ODELAY_VALUE => 0
)
port map(
IDATAIN => '0',
T => '1',
ODATAIN => rgmiio.tx_en,
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => OPEN,
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => rgmiio_tx_en
);
rgmii_txd : for i in 0 to 3 generate
delay_rgmii_txd0 : IODELAY2 generic map(
DELAY_SRC => "ODATAIN",
IDELAY_TYPE => "FIXED",
DATA_RATE => "DDR",
ODELAY_VALUE => 0
)
port map(
IDATAIN => '0',
T => '1',
ODATAIN => rgmiio.txd(i),
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => OPEN,
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => rgmiio_txd(i)
);
end generate;
end generate;
rgmii0 : rgmii generic map (pindex => 15, paddr => 16#010#, pmask => 16#ff0#, tech => fabtech,
gmii => CFG_GRETH1G, debugmem => 1, abits => 8, no_clk_mux => 0,
pirq => 15, use90degtxclk => 0)
port map (rstn, gmiii, gmiio, rgmiii, rgmiio, clkm, rstn, apbi, apbo(15));
ethpads : if (CFG_GRETH = 1) generate -- eth pads
etxc_pad : outpad generic map (tech => padtech)
port map (etx_clk, rgmiio_tx_clk);
erx_clk1 : if (use_eth_input_delay_clk = 0) generate
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, rgmiii.rx_clk);
end generate;
erx_clk2 : if (use_eth_input_delay_clk /= 0) generate
erxc_pad : inpad generic map (tech => padtech)
port map (erx_clk, rgmii_pad.rx_clk);
erxc_bufg0 : BUFG port map (O => rgmiii_buf.rx_clk, I => rgmii_pad.rx_clk);
end generate;
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, rgmiii_buf.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, rgmiii_buf.rx_dv);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, rgmiio_txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, rgmiio_tx_en);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, rgmiio.mdio_o, rgmiio.mdio_oe, rgmiii.mdio_i);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, rgmiio.mdc);
emdint_pad : inpad generic map (tech => padtech)
port map (emdint, rgmiii.mdint);
gtx_clk0 : if (use_gtx_clk = 0) generate
-- Use MIG PLL
-- Add to UCF (only if there is no BUFG left):
-- PIN "ethpads.gtx_clk0.clk_125_bufg0.O" CLOCK_DEDICATED_ROUTE = FALSE;
clk_125_bufg0 : BUFG port map (O => clk_125_bufg, I => clk_125);
rgmiii.gtx_clk <= clk_125_bufg;
end generate;
gtx_clk1 : if (use_gtx_clk = 1) generate
-- Incoming 125Mhz ref clock
clk125_pad : clkpad generic map (tech => padtech, arch => 3)
port map (clk125, rgmiii.gtx_clk);
end generate;
gtx_clk2 : if (use_gtx_clk = 2) generate
-- Use Separate PLL
-- Add to UCF (only if there is no BUFG left):
-- PIN "ethpads.gtx_clk2.clkgen0/xc3s.v/bufg0.O" CLOCK_DEDICATED_ROUTE =FALSE;
-- PIN "ethpads.gtx_clk2.clk_125_bufg0.O" CLOCK_DEDICATED_ROUTE = FALSE;
cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw;
clkgen0 : clkgen -- clock generator
generic map (clktech, 5, 2, CFG_MCTRL_SDEN,CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (clkm, clkm, clk_125_pll, open, open, open, open, cgi2, cgo2, open, open, open);
clk_125_bufg0 : BUFG port map (O => clk_125_bufg, I => clk_125_pll);
rgmiii.gtx_clk <= clk_125_bufg;
end generate;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- Multi-core CAN ---------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_mc generic map (slvndx => 4, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech,
ncores => CFG_CAN_NUM, sepirq => CFG_CANSEPIRQ)
port map (rstn, clkm, ahbsi, ahbso(4), can_lrx, can_ltx );
can_tx_pad1 : iopad generic map (tech => padtech)
port map (pio(5), can_ltx(0), gnd, gpioi.din(5));
can_rx_pad1 : iopad generic map (tech => padtech)
port map (pio(4), gnd, vcc, can_lrx(0));
canpas : if CFG_CAN_NUM = 2 generate
can_tx_pad2 : iopad generic map (tech => padtech)
port map (pio(2), can_ltx(1), gnd, gpioi.din(2));
can_rx_pad2 : iopad generic map (tech => padtech)
port map (pio(1), gnd, vcc, can_lrx(1));
end generate;
end generate;
-- standby controlled by pio(3) and pio(0)
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
-- temporary, just to make sure the SPW pins are instantiated correctly
no_spw : if CFG_SPW_EN = 0 generate
pad_gen: for i in 0 to CFG_SPW_NUM-1 generate
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x33v)
port map (spw_rxdp(i), spw_rxdn(i), dtmp(i));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x33v)
port map (spw_rxsp(i), spw_rxsn(i), stmp(i));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x33v)
port map (spw_txdp(i), spw_txdn(i), dtmp(i), gnd);
spw_txs_pad : outpad_ds generic map (padtech, lvds, x33v)
port map (spw_txsp(i), spw_txsn(i), stmp(i), gnd);
end generate;
end generate;
spw : if CFG_SPW_EN > 0 generate
core0: if CFG_SPW_GRSPW = 1 generate
spw_rxtxclk <= clkm;
spw_rstn <= rstn;
end generate;
core1 : if CFG_SPW_GRSPW = 2 generate
spw_rxtxclk <= clk100;
spw_rstn_sync_proc : process(rstn,spw_rxtxclk)
begin
if rstn = '0' then
spw_rstn_sync <= '0';
spw_rstn <= '0';
elsif rising_edge(spw_rxtxclk) then
spw_rstn_sync <= '1';
spw_rstn <= spw_rstn_sync;
end if;
end process spw_rstn_sync_proc;
end generate;
spw_rxclkn <= not spw_rxtxclk;
swloop : for i in 0 to CFG_SPW_NUM-1 generate
-- GRSPW2 PHY
spw2_input : if CFG_SPW_GRSPW = 2 generate
spw_inputloop: for j in 0 to CFG_SPW_PORTS-1 generate
spw_phy0 : grspw2_phy
generic map(
scantest => 0,
tech => fabtech,
input_type => CFG_SPW_INPUT,
rxclkbuftype => 2)
port map(
rstn => spw_rstn,
rxclki => spw_rxtxclk,
rxclkin => spw_rxclkn,
nrxclki => spw_rxtxclk,
di => dtmp(i*CFG_SPW_PORTS+j),
si => stmp(i*CFG_SPW_PORTS+j),
do => spwi(i).d(j*2+1 downto j*2),
dov => spwi(i).dv(j*2+1 downto j*2),
dconnect => spwi(i).dconnect(j*2+1 downto j*2),
rxclko => spw_rxclk(i*CFG_SPW_PORTS+j));
end generate;
oneport : if CFG_SPW_PORTS = 1 generate
spwi(i).d(3 downto 2) <= "00"; -- For second port
spwi(i).dv(3 downto 2) <= "00"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
end generate;
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
end generate;
spw1_input: if CFG_SPW_GRSPW = 1 generate
spw_inputloop: for j in 0 to CFG_SPW_PORTS-1 generate
spw_phy0 : grspw_phy
generic map(
tech => fabtech,
rxclkbuftype => 2,
scantest => 0)
port map(
rxrst => spwo(i).rxrst,
di => dtmp(i*CFG_SPW_PORTS+j),
si => stmp(i*CFG_SPW_PORTS+j),
rxclko => spw_rxclk(i*CFG_SPW_PORTS+j),
do => spwi(i).d(j),
ndo => spwi(i).nd(j*5+4 downto j*5),
dconnect => spwi(i).dconnect(j*2+1 downto j*2));
end generate spw_inputloop;
oneport : if CFG_SPW_PORTS = 1 generate
spwi(i).d(1) <= '0'; -- For second port
spwi(i).d(3 downto 2) <= "00"; -- For GRSPW2 second port
spwi(i).nd(9 downto 5) <= "00000"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
end generate;
spwi(i).dv <= (others => '0'); -- Only used in GRSPW2
end generate spw1_input;
sw0 : grspwm generic map(tech => memtech,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+i,
sysfreq => CPU_FREQ, usegen => 1,
pindex => 10+i, paddr => 10+i, pirq => 10+i,
nsync => 1, rmap => CFG_SPW_RMAP, rxunaligned => CFG_SPW_RXUNAL,
rmapcrc => CFG_SPW_RMAPCRC, fifosize1 => CFG_SPW_AHBFIFO,
fifosize2 => CFG_SPW_RXFIFO, rxclkbuftype => 2, dmachan => CFG_SPW_DMACHAN,
rmapbufs => CFG_SPW_RMAPBUF, ft => CFG_SPW_FT, ports => CFG_SPW_PORTS,
spwcore => CFG_SPW_GRSPW, netlist => CFG_SPW_NETLIST,
rxtx_sameclk => CFG_SPW_RTSAME, input_type => CFG_SPW_INPUT,
output_type => CFG_SPW_OUTPUT)
port map(rstn, clkm, spw_rxclk(i*CFG_SPW_PORTS), spw_rxclk(i*CFG_SPW_PORTS+1),
spw_rxtxclk, spw_rxtxclk, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+i),
apbi2, apbo2(10+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '1';
spwi(i).clkdiv10 <= conv_std_logic_vector(CPU_FREQ/10000-1, 8) when CFG_SPW_GRSPW = 1
else conv_std_logic_vector(10-1, 8);
spwi(i).tickinraw <= '0';
spwi(i).timein <= (others => '0');
spwi(i).dcrstval <= (others => '0');
spwi(i).timerrstval <= (others => '0');
swportloop1: for j in 0 to CFG_SPW_PORTS-1 generate
spwlb0 : if SPW_LOOP_BACK = 1 generate
dtmp(i*CFG_SPW_PORTS+j) <= spwo(i).d(j); stmp(i*CFG_SPW_PORTS+j) <= spwo(i).s(j);
end generate;
nospwlb0 : if SPW_LOOP_BACK = 0 generate
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x33v, 1)
port map (spw_rxdp(i*CFG_SPW_PORTS+j), spw_rxdn(i*CFG_SPW_PORTS+j), dtmp(i*CFG_SPW_PORTS+j));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x33v, 1)
port map (spw_rxsp(i*CFG_SPW_PORTS+j), spw_rxsn(i*CFG_SPW_PORTS+j), stmp(i*CFG_SPW_PORTS+j));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x33v)
port map (spw_txdp(i*CFG_SPW_PORTS+j), spw_txdn(i*CFG_SPW_PORTS+j), spwo(i).d(j), gnd);
spw_txs_pad : outpad_ds generic map (padtech, lvds, x33v)
port map (spw_txsp(i*CFG_SPW_PORTS+j), spw_txsn(i*CFG_SPW_PORTS+j), spwo(i).s(j), gnd);
end generate;
end generate;
end generate;
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 GR-XC6S-LX75 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cordic_lib.all;
---use work.float_pkg.all;
--library ieee_proposed;
--use ieee_proposed.float_pkg.all;
library floatfixlib;
use floatfixlib.float_pkg.all;
-- RAM interna que recibe svl's de forma serial y los guarda como posiciones de 3 coordenadas; también lee
---Actualmente debería recibir precisamente (o más) CANT_P puntos. Podría cambiarla para que sepa la cantidad que contiene
entity ram_interna is
generic(
N_BITS : integer := 32; -- Cantidad de bits por coordenada
CANT_P : integer := 100;---1000; -- Cantidad de puntos ---12 MIL
REFR_R : integer := 100 -- Ciclos por dato que saco
);
port(
clk: in std_logic;
rst: in std_logic;
Rx: in std_logic;
Din: in std_logic_vector(15 downto 0);
Dout: out t_pos_mem;
Rdy: out std_logic := '0';
barrido: out std_logic := '0'
);
end entity;
architecture ram_interna_arq of ram_interna is
signal n : integer := 0;
constant ram_size : integer := 3 * CANT_P;
subtype t_ram_elem is std_logic_vector(15 downto 0);---t_coordenada;
type t_ram is array(1 to ram_size) of t_ram_elem;
signal ram : t_ram := (others => (others => '0'));
---shared variable ram: t_ram;
signal Dout_aux : t_pos_mem := (others => (others => '0'));
begin
-- IN
process(Rx, Din, n, rst)
variable j_in : natural := 1;
begin
-- Reseteo
if rst = '1' then
ram <= (others => (others => '0'));
ram(1) <= "0000000000000001";
ram(2) <= "0000000000000001";
ram(3) <= "0000000000000001";
j_in := 1;
elsif Rx = '1' then
---if Rx = '1' then
if j_in > ram_size then
j_in := 1;
end if;
ram(j_in) <= Din;
j_in := j_in + 1;
if n < ram_size then
n <= n + 1;
end if;
end if;
end process;
-- OUT
process(clk)
variable i : natural := 0;
variable j_out : natural := ram_size;
begin
if rising_edge(clk) then
i := i + 1;
if i = REFR_R then
barrido <= '0';
i := 0;
if j_out > n then
j_out := 1;
Dout_aux(1) <= ram(j_out);
Dout_aux(2) <= ram(j_out+1);
Dout_aux(3) <= ram(j_out+2);
else
j_out := j_out + 3;
if j_out > n then
barrido <= '1';
else
Dout_aux(1) <= ram(j_out);
Dout_aux(2) <= ram(j_out+1);
Dout_aux(3) <= ram(j_out+2);
end if;
end if;
Rdy <= '1';
else
Rdy <= '0'; ---Chequear que funcione
end if;
end if;
end process;
Dout <= Dout_aux;
----Analizar problemas con el tiempo intermedio entre fin de lectura y barrido
end;
|
-------------------------------------------------------------------------------
-- $Id: or_muxcy.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- or_muxcy
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_muxcy.vhd
-- Version: v1.02e
-- Description: This file is used to implement an OR function using
-- carry chain muxes.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: Common use module
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 08/28/01 -- Version 1.01a creation to include IPIF v1.22a
-- ALS 10/04/01 -- Version 1.02a creation to include IPIF v1.23a
-- ALS 11/27/01
-- ^^^^^^
-- Version 1.02b created to fix registered grant problem.
-- ~~~~~~
-- ALS 01/26/02
-- ^^^^^^
-- Created version 1.02c to fix problem with registered grants, and buslock when
-- the buslock master is holding request high and performing conversion cycles.
-- ~~~~~~
-- ALS 01/09/03
-- ^^^^^^
-- Created version 1.02d to register OPB_timeout to improve timing
-- ~~~~~~
-- bsbrao 09/27/04
-- ^^^^^^
-- Created version 1.02e to upgrade IPIF from opb_ipif_v1_23_a to
-- opb_ipif_v3_01_a
-- ~~~~~~
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- Unisim library contains Xilinx primitives
library unisim;
use unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_BITS -- number of bits to OR in bus section
--
-- Definition of Ports:
-- input In_Bus -- bus containing bits to be ORd
-- output Or_out -- OR result
--
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity or_muxcy is
generic (
C_NUM_BITS : integer := 8
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end or_muxcy;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of or_muxcy is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Pad the number of bits to OR to the next multiple of 4
constant NUM_BITS_PAD : integer := ((C_NUM_BITS-1)/4+1)*4;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- Carry Chain muxes are used to implement OR of 4 bits or more
component MUXCY
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component;
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- If the number of bits to OR is 4 or less, a simple LUT can be used
LESSTHAN4_GEN: if C_NUM_BITS < 5 generate
-- define output of OR chain
signal or_tmp : std_logic_vector(0 to C_NUM_BITS-1) := (others => '0');
begin
BIT_LOOP: for i in 0 to C_NUM_BITS-1 generate
FIRST: if i = 0 generate
or_tmp(i) <= In_bus(0);
end generate FIRST;
REST: if i /= 0 generate
or_tmp(i) <= or_tmp(i-1) or In_bus(i);
end generate REST;
end generate BIT_LOOP;
Or_out <= or_tmp(C_NUM_BITS-1);
end generate LESSTHAN4_GEN;
-- If the number of bits to OR is 4 or more, then use LUTs and
-- carry chain. Pad the number of bits to the nearest multiple of 4
MORETHAN4_GEN: if C_NUM_BITS >= 5 generate
-- define output of LUTs
signal lut_out : std_logic_vector(0 to NUM_BITS_PAD/4-1) := (others => '0');
-- define padded input bus
signal in_bus_pad : std_logic_vector(0 to NUM_BITS_PAD-1) := (others => '0');
-- define output of OR chain
signal or_tmp : std_logic_vector(0 to NUM_BITS_PAD/4-1) := (others => '0');
begin
-- pad input bus
in_bus_pad(0 to C_NUM_BITS-1) <= In_bus(0 to C_NUM_BITS-1);
OR_GENERATE: for i in 0 to NUM_BITS_PAD/4-1 generate
lut_out(i) <= not( in_bus_pad(i*4) or
in_bus_pad(i*4+1) or
in_bus_pad(i*4+2) or
in_bus_pad(i*4+3) );
FIRST: if i = 0 generate
FIRSTMUX_I: MUXCY
port map (
O => or_tmp(i), --[out]
CI => '0' , --[in]
DI => '1' , --[in]
S => lut_out(i) --[in]
);
end generate FIRST;
REST: if i /= 0 generate
RESTMUX_I: MUXCY
port map (
O => or_tmp(i), --[out]
CI => or_tmp(i-1), --[in]
DI => '1' , --[in]
S => lut_out(i) --[in]
);
end generate REST;
end generate OR_GENERATE;
Or_out <= or_tmp(NUM_BITS_PAD/4-1);
end generate MORETHAN4_GEN;
end implementation;
|
-------------------------------------------------------------------------------
-- $Id: or_muxcy.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- or_muxcy
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
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-- ** code, or information as one possible implementation of **
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-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_muxcy.vhd
-- Version: v1.02e
-- Description: This file is used to implement an OR function using
-- carry chain muxes.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: Common use module
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 08/28/01 -- Version 1.01a creation to include IPIF v1.22a
-- ALS 10/04/01 -- Version 1.02a creation to include IPIF v1.23a
-- ALS 11/27/01
-- ^^^^^^
-- Version 1.02b created to fix registered grant problem.
-- ~~~~~~
-- ALS 01/26/02
-- ^^^^^^
-- Created version 1.02c to fix problem with registered grants, and buslock when
-- the buslock master is holding request high and performing conversion cycles.
-- ~~~~~~
-- ALS 01/09/03
-- ^^^^^^
-- Created version 1.02d to register OPB_timeout to improve timing
-- ~~~~~~
-- bsbrao 09/27/04
-- ^^^^^^
-- Created version 1.02e to upgrade IPIF from opb_ipif_v1_23_a to
-- opb_ipif_v3_01_a
-- ~~~~~~
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- Unisim library contains Xilinx primitives
library unisim;
use unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_BITS -- number of bits to OR in bus section
--
-- Definition of Ports:
-- input In_Bus -- bus containing bits to be ORd
-- output Or_out -- OR result
--
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity or_muxcy is
generic (
C_NUM_BITS : integer := 8
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end or_muxcy;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of or_muxcy is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Pad the number of bits to OR to the next multiple of 4
constant NUM_BITS_PAD : integer := ((C_NUM_BITS-1)/4+1)*4;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- Carry Chain muxes are used to implement OR of 4 bits or more
component MUXCY
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component;
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- If the number of bits to OR is 4 or less, a simple LUT can be used
LESSTHAN4_GEN: if C_NUM_BITS < 5 generate
-- define output of OR chain
signal or_tmp : std_logic_vector(0 to C_NUM_BITS-1) := (others => '0');
begin
BIT_LOOP: for i in 0 to C_NUM_BITS-1 generate
FIRST: if i = 0 generate
or_tmp(i) <= In_bus(0);
end generate FIRST;
REST: if i /= 0 generate
or_tmp(i) <= or_tmp(i-1) or In_bus(i);
end generate REST;
end generate BIT_LOOP;
Or_out <= or_tmp(C_NUM_BITS-1);
end generate LESSTHAN4_GEN;
-- If the number of bits to OR is 4 or more, then use LUTs and
-- carry chain. Pad the number of bits to the nearest multiple of 4
MORETHAN4_GEN: if C_NUM_BITS >= 5 generate
-- define output of LUTs
signal lut_out : std_logic_vector(0 to NUM_BITS_PAD/4-1) := (others => '0');
-- define padded input bus
signal in_bus_pad : std_logic_vector(0 to NUM_BITS_PAD-1) := (others => '0');
-- define output of OR chain
signal or_tmp : std_logic_vector(0 to NUM_BITS_PAD/4-1) := (others => '0');
begin
-- pad input bus
in_bus_pad(0 to C_NUM_BITS-1) <= In_bus(0 to C_NUM_BITS-1);
OR_GENERATE: for i in 0 to NUM_BITS_PAD/4-1 generate
lut_out(i) <= not( in_bus_pad(i*4) or
in_bus_pad(i*4+1) or
in_bus_pad(i*4+2) or
in_bus_pad(i*4+3) );
FIRST: if i = 0 generate
FIRSTMUX_I: MUXCY
port map (
O => or_tmp(i), --[out]
CI => '0' , --[in]
DI => '1' , --[in]
S => lut_out(i) --[in]
);
end generate FIRST;
REST: if i /= 0 generate
RESTMUX_I: MUXCY
port map (
O => or_tmp(i), --[out]
CI => or_tmp(i-1), --[in]
DI => '1' , --[in]
S => lut_out(i) --[in]
);
end generate REST;
end generate OR_GENERATE;
Or_out <= or_tmp(NUM_BITS_PAD/4-1);
end generate MORETHAN4_GEN;
end implementation;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2421.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x01p01n01i02421ent IS
END c07s03b02x01p01n01i02421ent;
ARCHITECTURE c07s03b02x01p01n01i02421arch OF c07s03b02x01p01n01i02421ent IS
BEGIN
TESTING: PROCESS
type rec is record
a: integer;
b: real;
end record;
constant y: rec := (a => 12, b => 12.0);
BEGIN
assert NOT(y.a=12 and y.b=12.0)
report "***PASSED TEST: c07s03b02x01p01n01i02421"
severity NOTE;
assert (y.a=12 and y.b=12.0)
report "***FAILED TEST: c07s03b02x01p01n01i02421 - Element names must denote elments of the record type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x01p01n01i02421arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2421.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x01p01n01i02421ent IS
END c07s03b02x01p01n01i02421ent;
ARCHITECTURE c07s03b02x01p01n01i02421arch OF c07s03b02x01p01n01i02421ent IS
BEGIN
TESTING: PROCESS
type rec is record
a: integer;
b: real;
end record;
constant y: rec := (a => 12, b => 12.0);
BEGIN
assert NOT(y.a=12 and y.b=12.0)
report "***PASSED TEST: c07s03b02x01p01n01i02421"
severity NOTE;
assert (y.a=12 and y.b=12.0)
report "***FAILED TEST: c07s03b02x01p01n01i02421 - Element names must denote elments of the record type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x01p01n01i02421arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2421.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x01p01n01i02421ent IS
END c07s03b02x01p01n01i02421ent;
ARCHITECTURE c07s03b02x01p01n01i02421arch OF c07s03b02x01p01n01i02421ent IS
BEGIN
TESTING: PROCESS
type rec is record
a: integer;
b: real;
end record;
constant y: rec := (a => 12, b => 12.0);
BEGIN
assert NOT(y.a=12 and y.b=12.0)
report "***PASSED TEST: c07s03b02x01p01n01i02421"
severity NOTE;
assert (y.a=12 and y.b=12.0)
report "***FAILED TEST: c07s03b02x01p01n01i02421 - Element names must denote elments of the record type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x01p01n01i02421arch;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_delay is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 0;
BITPATTERN : string := "00000001";
WIDTH : positive := 8
);
port (
input : in std_logic_vector(width-1 downto 0);
clock : in std_logic;
sclr : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(width-1 downto 0);
ena : in std_logic
);
end entity alt_dspbuilder_delay;
architecture rtl of alt_dspbuilder_delay is
component alt_dspbuilder_delay_GNZCCH64DU is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 1;
BITPATTERN : string := "0000000000000000";
WIDTH : positive := 16
);
port (
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector(16-1 downto 0);
output : out std_logic_vector(16-1 downto 0);
sclr : in std_logic
);
end component alt_dspbuilder_delay_GNZCCH64DU;
begin
alt_dspbuilder_delay_GNZCCH64DU_0: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "0000000000000000") and (WIDTH = 16)) generate
inst_alt_dspbuilder_delay_GNZCCH64DU_0: alt_dspbuilder_delay_GNZCCH64DU
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 1, BITPATTERN => "0000000000000000", WIDTH => 16)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
assert not (((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "0000000000000000") and (WIDTH = 16)))
report "Please run generate again" severity error;
end architecture rtl;
|
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 27440)
`protect data_block
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`protect end_protected
|
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.constants.all;
entity sys_toplevel is
Port(
I_clk: in std_logic;
I_en: in std_logic := '1';
I_reset: in std_logic := '0';
I_serial_rx: in std_logic;
O_addr: out std_logic_vector(XLEN-1 downto 0);
O_data: out std_logic_vector(XLEN-1 downto 0);
O_leds: out std_logic_vector(7 downto 0);
O_serial_tx: out std_logic;
O_busy: out std_logic
);
end sys_toplevel;
architecture Behavioral of sys_toplevel is
component arbiter
Port(
I_addr: in std_logic_vector(31 downto 0);
I_busy0, I_busy1, I_busy2, I_busy3: in std_logic;
I_data0, I_data1, I_data2, I_data3: in std_logic_vector(31 downto 0);
I_en: in std_logic;
O_busy: out std_logic;
O_data: out std_logic_vector(31 downto 0);
O_en0, O_en1, O_en2, O_en3: out std_logic
);
end component;
component arbiter_dummy
Port(
I_addr: in std_logic_vector(31 downto 0);
I_clk: in std_logic;
I_data: in std_logic_vector(31 downto 0);
I_en: in std_logic;
I_write: in std_logic;
O_busy: out std_logic;
O_data: out std_logic_vector(31 downto 0)
);
end component;
component cpu_toplevel
Port(
I_clk: in std_logic;
I_en: in std_logic;
I_reset: in std_logic;
I_memdata: in std_logic_vector(XLEN-1 downto 0);
I_membusy: in std_logic;
O_memdata: out std_logic_vector(XLEN-1 downto 0);
O_memaddr: out std_logic_vector(XLEN-1 downto 0);
O_memen: out std_logic := '0';
O_memwrite: out std_logic := '0'
);
end component;
component leds
Port(
I_addr: in std_logic_vector(31 downto 0);
I_clk: in std_logic;
I_data: in std_logic_vector(31 downto 0);
I_en: in std_logic;
I_write: in std_logic;
O_busy: out std_logic;
O_data: out std_logic_vector(31 downto 0);
O_leds: out std_logic_vector(7 downto 0)
);
end component;
component ram
Port(
I_clk: in std_logic;
I_en: in std_logic;
I_write: in std_logic;
I_addr: in std_logic_vector(XLEN-1 downto 0);
I_data: in std_logic_vector(XLEN-1 downto 0);
O_data: out std_logic_vector(XLEN-1 downto 0);
O_busy: out std_logic
);
end component;
component serial
Port(
I_clk: in std_logic;
I_en: in std_logic;
I_addr: in std_logic_vector(31 downto 0);
I_data: in std_logic_vector(31 downto 0);
I_rx: in std_logic;
I_write: in std_logic;
O_tx: out std_logic;
O_busy: out std_logic;
O_data: out std_logic_vector(31 downto 0)
);
end component;
component wizpll
PORT(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC
);
end component;
signal arb_busy, arb_en0, arb_en1, arb_en2, arb_en3: std_logic;
signal arb_data: std_logic_vector(XLEN-1 downto 0);
signal cpu_memdata: std_logic_vector(XLEN-1 downto 0);
signal cpu_memaddr: std_logic_vector(XLEN-1 downto 0);
signal cpu_memen: std_logic := '0';
signal cpu_memwrite: std_logic := '0';
signal dummy3_data: std_logic_vector(XLEN-1 downto 0);
signal dummy3_busy: std_logic;
signal inv_clk: std_logic;
signal inv_reset: std_logic;
signal led_busy: std_logic;
signal led_data: std_logic_vector(XLEN-1 downto 0);
signal pll_clk: std_logic;
signal ram_busy: std_logic := '0';
signal ram_data: std_logic_vector(XLEN-1 downto 0);
signal serial_busy: std_logic;
signal serial_data: std_logic_vector(XLEN-1 downto 0);
begin
arbiter_instance: arbiter port map(
I_addr => cpu_memaddr,
I_busy0 => ram_busy,
I_busy1 => led_busy,
I_busy2 => serial_busy,
I_busy3 => dummy3_busy,
I_data0 => ram_data,
I_data1 => led_data,
I_data2 => serial_data,
I_data3 => dummy3_data,
I_en => cpu_memen,
O_busy => arb_busy,
O_data => arb_data,
O_en0 => arb_en0,
O_en1 => arb_en1,
O_en2 => arb_en2,
O_en3 => arb_en3
);
cpu_instance: cpu_toplevel port map(
I_clk => pll_clk,
I_en => I_en,
I_reset => inv_reset,
I_memdata => arb_data,
I_membusy => arb_busy,
O_memdata => cpu_memdata,
O_memaddr => cpu_memaddr,
O_memen => cpu_memen,
O_memwrite => cpu_memwrite
);
-- I/O device 0
ram_instance: ram port map(
I_clk => inv_clk,
I_en => arb_en0,
I_write => cpu_memwrite,
I_addr => cpu_memaddr,
I_data => cpu_memdata,
O_data => ram_data,
O_busy => ram_busy
);
-- I/O device 1
leds_instance: leds port map(
I_clk => inv_clk,
I_en => arb_en1,
I_write => cpu_memwrite,
I_addr => cpu_memaddr,
I_data => cpu_memdata,
O_data => led_data,
O_busy => led_busy,
O_leds => O_leds
);
-- I/O device 2
serial_instance: serial port map(
I_clk => inv_clk,
I_en => arb_en2,
I_addr => cpu_memaddr,
I_data => cpu_memdata,
I_rx => I_serial_rx,
I_write => cpu_memwrite,
O_tx => O_serial_tx,
O_busy => serial_busy,
O_data => serial_data
);
-- I/O device 3
dummy3: arbiter_dummy port map(
I_addr => cpu_memaddr,
I_clk => inv_clk,
I_data => cpu_memdata,
I_en => arb_en3,
I_write => cpu_memwrite,
O_busy => dummy3_busy,
O_data => dummy3_data
);
pll_instance: wizpll port map(
inclk0 => I_clk,
c0 => pll_clk
);
inv_clk <= not pll_clk;
inv_reset <= not I_reset;
O_addr <= cpu_memaddr;
O_data <= cpu_memdata;
O_busy <= arb_busy;
end Behavioral; |
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.types_pkg.all;
use work.adaptations_pkg.all;
use work.string_methods_pkg.all;
package protected_types_pkg is
type t_protected_alert_attention_counters is protected
procedure increment(
alert_level : t_alert_level;
attention : t_attention := REGARD; -- count, expect, ignore
number : natural := 1
);
impure function get(
alert_level : t_alert_level;
attention : t_attention := REGARD
) return natural;
procedure to_string(
order : t_order
);
end protected t_protected_alert_attention_counters;
type t_protected_semaphore is protected
impure function get_semaphore return boolean;
procedure release_semaphore;
end protected t_protected_semaphore;
type t_protected_acknowledge_cmd_idx is protected
impure function set_index(index : integer) return boolean;
impure function get_index return integer;
procedure release_index;
end protected t_protected_acknowledge_cmd_idx;
type t_protected_check_counters is protected
procedure increment(
check_type : t_check_type;
number : natural := 1
);
procedure decrement(
check_type : t_check_type;
number : integer := 1
);
impure function get(
check_type : t_check_type
) return natural;
procedure to_string(
order : t_order
);
end protected t_protected_check_counters;
type t_protected_covergroup_status is protected
impure function add_coverpoint(constant VOID : t_void) return integer;
procedure remove_coverpoint(constant coverpoint_idx : in integer);
procedure set_name(constant coverpoint_idx : in integer; constant name : in string);
procedure set_num_valid_bins(constant coverpoint_idx : in integer; constant num_bins : in natural);
procedure set_num_covered_bins(constant coverpoint_idx : in integer; constant num_bins : in natural);
procedure set_total_bin_min_hits(constant coverpoint_idx : in integer; constant min_hits : in natural);
procedure set_total_bin_hits(constant coverpoint_idx : in integer; constant hits : in natural);
procedure set_total_coverage_bin_hits(constant coverpoint_idx : in integer; constant hits : in natural);
procedure set_total_goal_bin_hits(constant coverpoint_idx : in integer; constant hits : in natural);
procedure set_coverage_weight(constant coverpoint_idx : in integer; constant weight : in natural);
procedure set_bins_coverage_goal(constant coverpoint_idx : in integer; constant percentage : in positive range 1 to 100);
procedure set_hits_coverage_goal(constant coverpoint_idx : in integer; constant percentage : in positive);
procedure set_covpts_coverage_goal(constant percentage : in positive range 1 to 100);
procedure increment_valid_bin_count(constant coverpoint_idx : in integer);
procedure increment_covered_bin_count(constant coverpoint_idx : in integer);
procedure increment_min_hits_count(constant coverpoint_idx : in integer; constant min_hits : in natural);
procedure increment_hits_count(constant coverpoint_idx : in integer);
procedure increment_coverage_hits_count(constant coverpoint_idx : in integer);
procedure increment_goal_hits_count(constant coverpoint_idx : in integer);
impure function is_initialized(constant coverpoint_idx : integer) return boolean;
impure function get_name(constant coverpoint_idx : integer) return string;
impure function get_num_valid_bins(constant coverpoint_idx : integer) return natural;
impure function get_num_covered_bins(constant coverpoint_idx : integer) return natural;
impure function get_total_bin_min_hits(constant coverpoint_idx : integer) return natural;
impure function get_total_bin_hits(constant coverpoint_idx : integer) return natural;
impure function get_total_coverage_bin_hits(constant coverpoint_idx : integer) return natural;
impure function get_total_goal_bin_hits(constant coverpoint_idx : integer) return natural;
impure function get_coverage_weight(constant coverpoint_idx : integer) return natural;
impure function get_bins_coverage_goal(constant coverpoint_idx : integer) return positive;
impure function get_hits_coverage_goal(constant coverpoint_idx : integer) return positive;
impure function get_covpts_coverage_goal(constant VOID : t_void) return positive;
impure function get_bins_coverage(constant coverpoint_idx : integer; constant cov_representation : t_coverage_representation) return real;
impure function get_hits_coverage(constant coverpoint_idx : integer; constant cov_representation : t_coverage_representation) return real;
impure function get_total_bins_coverage(constant VOID : t_void) return real;
impure function get_total_hits_coverage(constant VOID : t_void) return real;
impure function get_total_covpts_coverage(constant cov_representation : t_coverage_representation) return real;
end protected t_protected_covergroup_status;
end package protected_types_pkg;
--=============================================================================
--=============================================================================
package body protected_types_pkg is
--------------------------------------------------------------------------------
type t_protected_alert_attention_counters is protected body
variable priv_alert_attention_counters : t_alert_attention_counters;
procedure increment(
alert_level : t_alert_level;
attention : t_attention := REGARD;
number : natural := 1
) is
begin
priv_alert_attention_counters(alert_level)(attention) := priv_alert_attention_counters(alert_level)(attention) + number;
end;
impure function get(
alert_level : t_alert_level;
attention : t_attention := REGARD
) return natural is
begin
return priv_alert_attention_counters(alert_level)(attention);
end;
procedure to_string(
order : t_order
) is
begin
to_string(priv_alert_attention_counters, order);
end;
end protected body t_protected_alert_attention_counters;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
type t_protected_semaphore is protected body
variable v_priv_semaphore_taken : boolean := false;
impure function get_semaphore return boolean is
begin
if v_priv_semaphore_taken = false then
-- semaphore was free
v_priv_semaphore_taken := true;
return true;
else
-- semaphore was not free
return false;
end if;
end;
procedure release_semaphore is
begin
v_priv_semaphore_taken := false;
end procedure;
end protected body t_protected_semaphore;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
type t_protected_acknowledge_cmd_idx is protected body
variable v_priv_idx : integer := -1;
impure function set_index(index : integer) return boolean is
begin
-- for broadcast
if v_priv_idx = -1 or v_priv_idx = index then
-- index was now set
v_priv_idx := index;
return true;
else
-- index was set by another vvc
return false;
end if;
end;
impure function get_index return integer is
begin
return v_priv_idx;
end;
procedure release_index is
begin
v_priv_idx := -1;
end procedure;
end protected body t_protected_acknowledge_cmd_idx;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
type t_protected_check_counters is protected body
variable priv_check_counters : t_check_counters_array;
variable priv_counter_limit_alert_raised : boolean := False;
-- Helper method for alerting when the maximum
-- value for check_counter is reached.
impure function priv_check_counter_limit_reached(
check_type : t_check_type;
number : natural := 1
) return boolean is
begin
if priv_check_counters(check_type) = natural'high then
if priv_counter_limit_alert_raised = false then
report "check_counter limit reached" severity warning;
priv_counter_limit_alert_raised := true;
end if;
return True;
else
return False;
end if;
end function priv_check_counter_limit_reached;
procedure increment(
check_type : t_check_type;
number : natural := 1
) is
begin
if C_ENABLE_CHECK_COUNTER then
if priv_check_counter_limit_reached(check_type, number) = false then
priv_check_counters(check_type) := priv_check_counters(check_type) + number;
end if;
end if;
end procedure increment;
procedure decrement(
check_type : t_check_type;
number : integer := 1
) is
begin
if C_ENABLE_CHECK_COUNTER then
if priv_check_counter_limit_reached(check_type, number) = false then
priv_check_counters(check_type) := priv_check_counters(check_type) - number;
end if;
end if;
end procedure decrement;
impure function get(
check_type : t_check_type
) return natural is
begin
return priv_check_counters(check_type);
end function get;
procedure to_string(
order : t_order
) is
begin
to_string(priv_check_counters, order);
end procedure to_string;
end protected body t_protected_check_counters;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
type t_protected_covergroup_status is protected body
type t_coverpoint_status is record
initialized : boolean;
name : string(1 to C_FC_MAX_NAME_LENGTH);
num_valid_bins : natural;
num_covered_bins : natural;
total_bin_min_hits : natural;
total_bin_hits : natural;
total_coverage_bin_hits : natural;
total_goal_bin_hits : natural;
coverage_weight : natural;
bins_coverage_goal : positive;
hits_coverage_goal : positive;
end record;
constant C_COVERPOINT_STATUS_DEFAULT : t_coverpoint_status := (
initialized => false,
name => (others => NUL),
num_valid_bins => 0,
num_covered_bins => 0,
total_bin_min_hits => 0,
total_bin_hits => 0,
total_coverage_bin_hits => 0,
total_goal_bin_hits => 0,
coverage_weight => 1,
bins_coverage_goal => 100,
hits_coverage_goal => 100
);
type t_coverpoint_status_array is array (natural range <>) of t_coverpoint_status;
variable priv_coverpoint_status_list : t_coverpoint_status_array(0 to C_FC_MAX_NUM_COVERPOINTS-1) := (others => C_COVERPOINT_STATUS_DEFAULT);
variable priv_coverpoint_name_idx : natural := 1;
variable priv_covpts_coverage_goal : positive := 100;
impure function add_coverpoint(
constant VOID : t_void)
return integer is
constant C_COVERPOINT_NUM : string := to_string(priv_coverpoint_name_idx);
variable v_next_coverpoint_idx : natural := 0;
begin
for i in 0 to C_FC_MAX_NUM_COVERPOINTS-1 loop
if not(priv_coverpoint_status_list(v_next_coverpoint_idx).initialized) then
exit;
end if;
v_next_coverpoint_idx := v_next_coverpoint_idx + 1;
end loop;
if v_next_coverpoint_idx < C_FC_MAX_NUM_COVERPOINTS then
priv_coverpoint_status_list(v_next_coverpoint_idx).name := "Covpt_" & C_COVERPOINT_NUM & fill_string(NUL, C_FC_MAX_NAME_LENGTH-6-C_COVERPOINT_NUM'length);
priv_coverpoint_status_list(v_next_coverpoint_idx).initialized := true;
priv_coverpoint_name_idx := priv_coverpoint_name_idx + 1;
return v_next_coverpoint_idx;
else
return -1; -- Error: no more space in the list
end if;
end function;
procedure remove_coverpoint(
constant coverpoint_idx : in integer) is
begin
priv_coverpoint_status_list(coverpoint_idx) := C_COVERPOINT_STATUS_DEFAULT;
end procedure;
procedure set_name(
constant coverpoint_idx : in integer;
constant name : in string) is
begin
if name'length > C_FC_MAX_NAME_LENGTH then
priv_coverpoint_status_list(coverpoint_idx).name := name(1 to C_FC_MAX_NAME_LENGTH);
else
priv_coverpoint_status_list(coverpoint_idx).name := name & fill_string(NUL, C_FC_MAX_NAME_LENGTH-name'length);
end if;
end procedure;
procedure set_num_valid_bins(
constant coverpoint_idx : in integer;
constant num_bins : in natural) is
begin
priv_coverpoint_status_list(coverpoint_idx).num_valid_bins := num_bins;
end procedure;
procedure set_num_covered_bins(
constant coverpoint_idx : in integer;
constant num_bins : in natural) is
begin
priv_coverpoint_status_list(coverpoint_idx).num_covered_bins := num_bins;
end procedure;
procedure set_total_bin_min_hits(
constant coverpoint_idx : in integer;
constant min_hits : in natural) is
begin
priv_coverpoint_status_list(coverpoint_idx).total_bin_min_hits := min_hits;
end procedure;
procedure set_total_bin_hits(
constant coverpoint_idx : in integer;
constant hits : in natural) is
begin
priv_coverpoint_status_list(coverpoint_idx).total_bin_hits := hits;
end procedure;
procedure set_total_coverage_bin_hits(
constant coverpoint_idx : in integer;
constant hits : in natural) is
begin
priv_coverpoint_status_list(coverpoint_idx).total_coverage_bin_hits := hits;
end procedure;
procedure set_total_goal_bin_hits(
constant coverpoint_idx : in integer;
constant hits : in natural) is
begin
priv_coverpoint_status_list(coverpoint_idx).total_goal_bin_hits := hits;
end procedure;
procedure set_coverage_weight(
constant coverpoint_idx : in integer;
constant weight : in natural) is
begin
priv_coverpoint_status_list(coverpoint_idx).coverage_weight := weight;
end procedure;
procedure set_bins_coverage_goal(
constant coverpoint_idx : in integer;
constant percentage : in positive range 1 to 100) is
begin
priv_coverpoint_status_list(coverpoint_idx).bins_coverage_goal := percentage;
end procedure;
procedure set_hits_coverage_goal(
constant coverpoint_idx : in integer;
constant percentage : in positive) is
begin
priv_coverpoint_status_list(coverpoint_idx).hits_coverage_goal := percentage;
end procedure;
procedure set_covpts_coverage_goal(
constant percentage : in positive range 1 to 100) is
begin
priv_covpts_coverage_goal := percentage;
end procedure;
procedure increment_valid_bin_count(
constant coverpoint_idx : in integer) is
begin
priv_coverpoint_status_list(coverpoint_idx).num_valid_bins := priv_coverpoint_status_list(coverpoint_idx).num_valid_bins + 1;
end procedure;
procedure increment_covered_bin_count(
constant coverpoint_idx : in integer) is
begin
priv_coverpoint_status_list(coverpoint_idx).num_covered_bins := priv_coverpoint_status_list(coverpoint_idx).num_covered_bins + 1;
end procedure;
procedure increment_min_hits_count(
constant coverpoint_idx : in integer;
constant min_hits : in natural) is
begin
priv_coverpoint_status_list(coverpoint_idx).total_bin_min_hits := priv_coverpoint_status_list(coverpoint_idx).total_bin_min_hits + min_hits;
end procedure;
procedure increment_hits_count(
constant coverpoint_idx : in integer) is
begin
priv_coverpoint_status_list(coverpoint_idx).total_bin_hits := priv_coverpoint_status_list(coverpoint_idx).total_bin_hits + 1;
end procedure;
procedure increment_coverage_hits_count(
constant coverpoint_idx : in integer) is
begin
priv_coverpoint_status_list(coverpoint_idx).total_coverage_bin_hits := priv_coverpoint_status_list(coverpoint_idx).total_coverage_bin_hits + 1;
end procedure;
procedure increment_goal_hits_count(
constant coverpoint_idx : in integer) is
begin
priv_coverpoint_status_list(coverpoint_idx).total_goal_bin_hits := priv_coverpoint_status_list(coverpoint_idx).total_goal_bin_hits + 1;
end procedure;
impure function is_initialized(
constant coverpoint_idx : integer)
return boolean is
begin
return priv_coverpoint_status_list(coverpoint_idx).initialized;
end function;
impure function get_name(
constant coverpoint_idx : integer)
return string is
begin
return to_string(priv_coverpoint_status_list(coverpoint_idx).name);
end function;
impure function get_num_valid_bins(
constant coverpoint_idx : integer)
return natural is
begin
return priv_coverpoint_status_list(coverpoint_idx).num_valid_bins;
end function;
impure function get_num_covered_bins(
constant coverpoint_idx : integer)
return natural is
begin
return priv_coverpoint_status_list(coverpoint_idx).num_covered_bins;
end function;
impure function get_total_bin_min_hits(
constant coverpoint_idx : integer)
return natural is
begin
return priv_coverpoint_status_list(coverpoint_idx).total_bin_min_hits;
end function;
impure function get_total_bin_hits(
constant coverpoint_idx : integer)
return natural is
begin
return priv_coverpoint_status_list(coverpoint_idx).total_bin_hits;
end function;
impure function get_total_coverage_bin_hits(
constant coverpoint_idx : integer)
return natural is
begin
return priv_coverpoint_status_list(coverpoint_idx).total_coverage_bin_hits;
end function;
impure function get_total_goal_bin_hits(
constant coverpoint_idx : integer)
return natural is
begin
return priv_coverpoint_status_list(coverpoint_idx).total_goal_bin_hits;
end function;
impure function get_coverage_weight(
constant coverpoint_idx : integer)
return natural is
begin
return priv_coverpoint_status_list(coverpoint_idx).coverage_weight;
end function;
impure function get_bins_coverage_goal(
constant coverpoint_idx : integer)
return positive is
begin
return priv_coverpoint_status_list(coverpoint_idx).bins_coverage_goal;
end function;
impure function get_hits_coverage_goal(
constant coverpoint_idx : integer)
return positive is
begin
return priv_coverpoint_status_list(coverpoint_idx).hits_coverage_goal;
end function;
impure function get_covpts_coverage_goal(
constant VOID : t_void)
return positive is
begin
return priv_covpts_coverage_goal;
end function;
-- Returns the percentage of covered_bins/valid_bins in the coverpoint
impure function get_bins_coverage(
constant coverpoint_idx : integer;
constant cov_representation : t_coverage_representation)
return real is
variable v_num_covered_bins : natural := priv_coverpoint_status_list(coverpoint_idx).num_covered_bins;
variable v_num_valid_bins : natural := priv_coverpoint_status_list(coverpoint_idx).num_valid_bins;
variable v_coverage : real;
begin
v_coverage := real(v_num_covered_bins)*100.0/real(v_num_valid_bins) when v_num_valid_bins > 0 else 0.0;
if cov_representation = GOAL_CAPPED or cov_representation = GOAL_UNCAPPED then
v_coverage := v_coverage*100.0/real(priv_coverpoint_status_list(coverpoint_idx).bins_coverage_goal);
end if;
if cov_representation = GOAL_CAPPED and v_coverage > 100.0 then
v_coverage := 100.0;
end if;
return v_coverage;
end function;
-- Returns the percentage of total_hits/total_min_hits in the coverpoint
impure function get_hits_coverage(
constant coverpoint_idx : integer;
constant cov_representation : t_coverage_representation)
return real is
variable v_tot_coverage_bin_hits : natural := priv_coverpoint_status_list(coverpoint_idx).total_coverage_bin_hits;
variable v_tot_goal_bin_hits : natural := priv_coverpoint_status_list(coverpoint_idx).total_goal_bin_hits;
variable v_tot_bin_hits : natural := priv_coverpoint_status_list(coverpoint_idx).total_bin_hits;
variable v_tot_bin_min_hits : natural := priv_coverpoint_status_list(coverpoint_idx).total_bin_min_hits;
variable v_tot_goal_bin_min_hits : real := real(priv_coverpoint_status_list(coverpoint_idx).total_bin_min_hits*
priv_coverpoint_status_list(coverpoint_idx).hits_coverage_goal)/100.0;
variable v_coverage : real;
begin
if cov_representation = GOAL_CAPPED then
v_coverage := real(v_tot_goal_bin_hits)*100.0/v_tot_goal_bin_min_hits when v_tot_goal_bin_min_hits > 0.0 else 0.0;
v_coverage := 100.0 when v_coverage > 100.0;
elsif cov_representation = GOAL_UNCAPPED then
v_coverage := real(v_tot_bin_hits)*100.0/v_tot_goal_bin_min_hits when v_tot_goal_bin_min_hits > 0.0 else 0.0;
else -- NO_GOAL
v_coverage := real(v_tot_coverage_bin_hits)*100.0/real(v_tot_bin_min_hits) when v_tot_bin_min_hits > 0 else 0.0;
end if;
return v_coverage;
end function;
-- Returns the percentage of covered_bins/valid_bins for all the coverpoints
impure function get_total_bins_coverage(
constant VOID : t_void)
return real is
variable v_tot_covered_bins : natural := 0;
variable v_tot_valid_bins : natural := 0;
variable v_coverage : real;
begin
for i in 0 to C_FC_MAX_NUM_COVERPOINTS-1 loop
if priv_coverpoint_status_list(i).initialized then
v_tot_covered_bins := v_tot_covered_bins + priv_coverpoint_status_list(i).num_covered_bins * priv_coverpoint_status_list(i).coverage_weight;
v_tot_valid_bins := v_tot_valid_bins + priv_coverpoint_status_list(i).num_valid_bins * priv_coverpoint_status_list(i).coverage_weight;
end if;
end loop;
v_coverage := real(v_tot_covered_bins)*100.0/real(v_tot_valid_bins) when v_tot_valid_bins > 0 else 0.0;
return v_coverage;
end function;
-- Returns the percentage of total_hits/total_min_hits for all the coverpoints
impure function get_total_hits_coverage(
constant VOID : t_void)
return real is
variable v_tot_bin_hits : natural := 0;
variable v_tot_bin_min_hits : natural := 0;
variable v_coverage : real;
begin
for i in 0 to C_FC_MAX_NUM_COVERPOINTS-1 loop
if priv_coverpoint_status_list(i).initialized then
v_tot_bin_hits := v_tot_bin_hits + priv_coverpoint_status_list(i).total_coverage_bin_hits * priv_coverpoint_status_list(i).coverage_weight;
v_tot_bin_min_hits := v_tot_bin_min_hits + priv_coverpoint_status_list(i).total_bin_min_hits * priv_coverpoint_status_list(i).coverage_weight;
end if;
end loop;
v_coverage := real(v_tot_bin_hits)*100.0/real(v_tot_bin_min_hits) when v_tot_bin_min_hits > 0 else 0.0;
return v_coverage;
end function;
-- Returns the percentage of covered_coverpoints/total_coverpoints
impure function get_total_covpts_coverage(
constant cov_representation : t_coverage_representation)
return real is
variable v_tot_covered_covpts : natural := 0;
variable v_tot_covpts : natural := 0;
variable v_coverage : real;
begin
for i in 0 to C_FC_MAX_NUM_COVERPOINTS-1 loop
if priv_coverpoint_status_list(i).initialized then
v_tot_covered_covpts := v_tot_covered_covpts + priv_coverpoint_status_list(i).coverage_weight when
priv_coverpoint_status_list(i).total_coverage_bin_hits >= priv_coverpoint_status_list(i).total_bin_min_hits;
v_tot_covpts := v_tot_covpts + priv_coverpoint_status_list(i).coverage_weight;
end if;
end loop;
v_coverage := real(v_tot_covered_covpts)*100.0/real(v_tot_covpts) when v_tot_covpts > 0 else 0.0;
if cov_representation = GOAL_CAPPED or cov_representation = GOAL_UNCAPPED then
v_coverage := v_coverage*100.0/real(priv_covpts_coverage_goal);
end if;
if cov_representation = GOAL_CAPPED and v_coverage > 100.0 then
v_coverage := 100.0;
end if;
return v_coverage;
end function;
end protected body t_protected_covergroup_status;
--------------------------------------------------------------------------------
end package body protected_types_pkg;
|
-------------------------------------------------------------------------------
-- Title : TIE-50206, Exercise 02
-- Project :
-------------------------------------------------------------------------------
-- File : ripple_carry_adder.vhd
-- Author : Tuomas Huuki, Jonas Nikula
-- Company : TUT
-- Created : 28.10.2015
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Second excercise.
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 28.10.2015 1.0 tuhu, nikulaj Created
-------------------------------------------------------------------------------
-- TODO: Add library called ieee here
-- And use package called std_logic_1164 from the library
library ieee;
use ieee.std_logic_1164.all;
-- TODO: Declare entity here
-- Name: ripple_carry_adder
-- No generics yet
-- Ports: a_in 3-bit std_logic_vector
-- b_in 3-bit std_logic_vector
-- s_out 4-bit std_logic_vector
entity ripple_carry_adder is
PORT (
a_in : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
b_in : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
end ripple_carry_adder;
-------------------------------------------------------------------------------
-- Architecture called 'gate' is already defined. Just fill it.
-- Architecture defines an implementation for an entity
architecture gate of ripple_carry_adder is
-- TODO: Add your internal signal declarations here
SIGNAL carry_ha : STD_LOGIC;
SIGNAL carry_fa : STD_LOGIC;
SIGNAL C, D, E, F, G, H : STD_LOGIC;
begin -- gate
-- Half adder.
s_out(0) <= a_in(0) XOR b_in(0);
carry_ha <= a_in(0) AND b_in(0);
-- Full adder 1.
C <= a_in(1) XOR b_in(1);
D <= carry_ha AND C;
E <= a_in(1) AND b_in(1);
s_out(1) <= carry_ha XOR C;
carry_fa <= D OR E;
-- Full adder 2.
F <= a_in(2) XOR b_in(2);
G <= carry_fa AND F;
H <= a_in(2) AND b_in(2);
s_out(2) <= carry_fa XOR F;
s_out(3) <= G OR H;
end gate;
|
-------------------------------------------------------------------------------
-- Phy Management Interface for OpenMAC
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY OpenMAC_MII IS
PORT( Clk : IN std_logic;
Rst : IN std_logic;
Addr : IN std_logic_vector( 2 DOWNTO 0);
Sel : IN std_logic;
nBe : IN std_logic_vector( 1 DOWNTO 0);
nWr : IN std_logic;
Data_In : IN std_logic_vector(15 DOWNTO 0);
Data_Out : OUT std_logic_vector(15 DOWNTO 0);
Mii_Clk : OUT std_logic;
Mii_Di : IN std_logic;
Mii_Do : out std_logic;
Mii_Doe : out std_logic; --'1' ... Input / '0' ... Output!!!
nResetOut : OUT std_logic
);
END ENTITY OpenMAC_MII;
ARCHITECTURE struct OF OpenMAC_MII IS
SIGNAL ShiftReg : std_logic_vector (31 DOWNTO 0);
SIGNAL iMiiClk : std_logic;
SIGNAL ClkDiv : std_logic_vector (4 DOWNTO 0);
ALIAS Shift : std_logic IS ClkDiv(ClkDiv'high);
SIGNAL BitCnt : std_logic_vector (2 DOWNTO 0);
SIGNAL BytCnt : std_logic_vector (2 DOWNTO 0);
SIGNAL Run, SrBusy, nReset : std_logic;
SIGNAL M_Dout, M_Oe : std_logic;
BEGIN
Data_Out <= x"00" & nReset & x"0" & "00" & SrBusy WHEN Addr(0) = '0' ELSE
ShiftReg(15 DOWNTO 0);
Mii_Clk <= iMiiClk;
Mii_Do <= M_Dout;
Mii_Doe <= not M_Oe;
nresetout <= nReset;
p_Mii: PROCESS (Clk, Rst)
BEGIN
IF Rst = '1' THEN
iMiiClk <= '0'; Run <= '0'; SrBusy <= '0'; M_Oe <= '1'; M_Dout <= '1'; nReset <= '0';
BitCnt <= (OTHERS => '0'); BytCnt <= (OTHERS => '0');
ShiftReg <= x"0000ABCD"; ClkDiv <= (OTHERS => '0');
ELSIF rising_edge( Clk ) THEN
IF Shift = '1' THEN ClkDiv <= conv_std_logic_vector( 8, ClkDiv'high + 1);
iMiiClk <= NOT iMiiClk;
ELSE ClkDiv <= ClkDiv - 1;
END IF;
IF Sel = '1' AND nWr = '0' AND SrBusy = '0' AND Addr(1) = '1' AND nBE(0) = '0' THEN nReset <= Data_In(7);
END IF;
IF Sel = '1' AND nWr = '0' AND SrBusy = '0' AND Addr(1) = '0' THEN
IF Addr(0) = '0' THEN
IF nBE(1) = '0' THEN ShiftReg(31 DOWNTO 24) <= Data_In(15 DOWNTO 8);
END IF;
IF nBE(0) = '0' THEN ShiftReg(23 DOWNTO 16) <= Data_In( 7 DOWNTO 0);
SrBusy <= '1';
END IF;
ELSE
IF nBE(1) = '0' THEN ShiftReg(15 DOWNTO 8) <= Data_In(15 DOWNTO 8);
END IF;
IF nBE(0) = '0' THEN ShiftReg( 7 DOWNTO 0) <= Data_In( 7 DOWNTO 0);
END IF;
END IF;
ELSE
IF Shift = '1' AND iMiiClk = '1' THEN
IF Run = '0' AND SrBusy = '1' THEN
Run <= '1';
BytCnt <= "111";
BitCnt <= "111";
ELSE
IF BytCnt(2) = '0' AND SrBusy = '1' THEN
M_Dout <= ShiftReg(31);
ShiftReg <= ShiftReg(30 DOWNTO 0) & Mii_Di; -- & Mii_Dio;
END IF;
BitCnt <= BitCnt - 1;
IF BitCnt = 0 THEN
BytCnt <= BytCnt - 1;
IF BytCnt = 0 THEN
SrBusy <= '0';
Run <= '0';
END IF;
END IF;
IF BytCnt = 2 AND BitCnt = 1 AND ShiftReg(31) = '0' THEN
M_Oe <= '0';
END IF;
END IF;
IF SrBusy = '0' OR Run = '0' THEN
M_Dout <= '1';
M_Oe <= '1';
END IF;
END IF;
END IF;
END IF;
END PROCESS p_Mii;
END struct; |
-------------------------------------------------------------------------------
-- Phy Management Interface for OpenMAC
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY OpenMAC_MII IS
PORT( Clk : IN std_logic;
Rst : IN std_logic;
Addr : IN std_logic_vector( 2 DOWNTO 0);
Sel : IN std_logic;
nBe : IN std_logic_vector( 1 DOWNTO 0);
nWr : IN std_logic;
Data_In : IN std_logic_vector(15 DOWNTO 0);
Data_Out : OUT std_logic_vector(15 DOWNTO 0);
Mii_Clk : OUT std_logic;
Mii_Di : IN std_logic;
Mii_Do : out std_logic;
Mii_Doe : out std_logic; --'1' ... Input / '0' ... Output!!!
nResetOut : OUT std_logic
);
END ENTITY OpenMAC_MII;
ARCHITECTURE struct OF OpenMAC_MII IS
SIGNAL ShiftReg : std_logic_vector (31 DOWNTO 0);
SIGNAL iMiiClk : std_logic;
SIGNAL ClkDiv : std_logic_vector (4 DOWNTO 0);
ALIAS Shift : std_logic IS ClkDiv(ClkDiv'high);
SIGNAL BitCnt : std_logic_vector (2 DOWNTO 0);
SIGNAL BytCnt : std_logic_vector (2 DOWNTO 0);
SIGNAL Run, SrBusy, nReset : std_logic;
SIGNAL M_Dout, M_Oe : std_logic;
BEGIN
Data_Out <= x"00" & nReset & x"0" & "00" & SrBusy WHEN Addr(0) = '0' ELSE
ShiftReg(15 DOWNTO 0);
Mii_Clk <= iMiiClk;
Mii_Do <= M_Dout;
Mii_Doe <= not M_Oe;
nresetout <= nReset;
p_Mii: PROCESS (Clk, Rst)
BEGIN
IF Rst = '1' THEN
iMiiClk <= '0'; Run <= '0'; SrBusy <= '0'; M_Oe <= '1'; M_Dout <= '1'; nReset <= '0';
BitCnt <= (OTHERS => '0'); BytCnt <= (OTHERS => '0');
ShiftReg <= x"0000ABCD"; ClkDiv <= (OTHERS => '0');
ELSIF rising_edge( Clk ) THEN
IF Shift = '1' THEN ClkDiv <= conv_std_logic_vector( 8, ClkDiv'high + 1);
iMiiClk <= NOT iMiiClk;
ELSE ClkDiv <= ClkDiv - 1;
END IF;
IF Sel = '1' AND nWr = '0' AND SrBusy = '0' AND Addr(1) = '1' AND nBE(0) = '0' THEN nReset <= Data_In(7);
END IF;
IF Sel = '1' AND nWr = '0' AND SrBusy = '0' AND Addr(1) = '0' THEN
IF Addr(0) = '0' THEN
IF nBE(1) = '0' THEN ShiftReg(31 DOWNTO 24) <= Data_In(15 DOWNTO 8);
END IF;
IF nBE(0) = '0' THEN ShiftReg(23 DOWNTO 16) <= Data_In( 7 DOWNTO 0);
SrBusy <= '1';
END IF;
ELSE
IF nBE(1) = '0' THEN ShiftReg(15 DOWNTO 8) <= Data_In(15 DOWNTO 8);
END IF;
IF nBE(0) = '0' THEN ShiftReg( 7 DOWNTO 0) <= Data_In( 7 DOWNTO 0);
END IF;
END IF;
ELSE
IF Shift = '1' AND iMiiClk = '1' THEN
IF Run = '0' AND SrBusy = '1' THEN
Run <= '1';
BytCnt <= "111";
BitCnt <= "111";
ELSE
IF BytCnt(2) = '0' AND SrBusy = '1' THEN
M_Dout <= ShiftReg(31);
ShiftReg <= ShiftReg(30 DOWNTO 0) & Mii_Di; -- & Mii_Dio;
END IF;
BitCnt <= BitCnt - 1;
IF BitCnt = 0 THEN
BytCnt <= BytCnt - 1;
IF BytCnt = 0 THEN
SrBusy <= '0';
Run <= '0';
END IF;
END IF;
IF BytCnt = 2 AND BitCnt = 1 AND ShiftReg(31) = '0' THEN
M_Oe <= '0';
END IF;
END IF;
IF SrBusy = '0' OR Run = '0' THEN
M_Dout <= '1';
M_Oe <= '1';
END IF;
END IF;
END IF;
END IF;
END PROCESS p_Mii;
END struct; |
entity E is
end entity;
architecture A of E is
-- array with unconstrained array element type
type A is array(natural range <>) of bit_vector;
-- partially constrained array -> constrained inner array (element)
subtype P1 is A(open)(7 downto 0);
-- partially constrained array -> constrained outer array (vector)
subtype P2 is A(15 downto 0)(open);
signal S1 : P1(15 downto 0); -- finally constraining the vector size
signal S2 : P2(open)(7 downto 0); -- finally constraining the element size line 14
begin
end architecture;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for ioblock3_e
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:46:40 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ioblock3_e-conf-c.vhd,v 1.2 2005/07/19 07:13:14 wig Exp $
-- $Date: 2005/07/19 07:13:14 $
-- $Log: ioblock3_e-conf-c.vhd,v $
-- Revision 1.2 2005/07/19 07:13:14 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration ioblock3_e_conf / ioblock3_e
--
configuration ioblock3_e_conf of ioblock3_e is
for rtl
-- Generated Configuration
for ioc_g_i_33 : ioc_g_i
use configuration work.ioc_g_i_conf;
end for;
for ioc_g_i_34 : ioc_g_i
use configuration work.ioc_g_i_conf;
end for;
for ioc_g_o_35 : ioc_g_o
use configuration work.ioc_g_o_conf;
end for;
for ioc_g_o_36 : ioc_g_o
use configuration work.ioc_g_o_conf;
end for;
for ioc_r_io3_39 : ioc_r_io3
use configuration work.ioc_r_io3_conf;
end for;
for ioc_r_io3_40 : ioc_r_io3
use configuration work.ioc_r_io3_conf;
end for;
for ioc_r_iou_31 : ioc_r_iou
use configuration work.ioc_r_iou_conf;
end for;
for ioc_r_iou_32 : ioc_r_iou
use configuration work.ioc_r_iou_conf;
end for;
end for;
end ioblock3_e_conf;
--
-- End of Generated Configuration ioblock3_e_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- Title : MIPS Register File
-- Project :
-------------------------------------------------------------------------------
-- File : read_register.vhd
-- Author : Frank Vanbever <frank@neuromancer>
-- Company :
-- Created : 2013-02-27
-- Last update: 2013-04-15
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: This is a MIPS register file implementation in VHDL
-------------------------------------------------------------------------------
-- Copyright (c) 2013
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-02-27 1.0 frank Created
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--! @file
--! @brief Register file for a MIPS processor
--! @details There are 32 registers which can all be read. All registers except
--! for register 0 can be written to. Register 0 contains the constant value 0
--! which is needed for the correct functioning of the MIPS processor.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--! The register file contains all registers for a MIPS processor to function
entity register_file is
port (
clk : in std_logic; --! clock signal
-- input vectors
--! First read register adress input
Read_reg_1 : in std_logic_vector(25 downto 21);
--! Second read register adress input
Read_reg_2 : in std_logic_vector(20 downto 16);
--! Write register adress input
Write_reg : in std_logic_vector(15 downto 11);
--! Data to be written to the write adress
Write_data : in std_logic_vector(31 downto 0);
-- output vectors
--! Data read from read register 1
Read_data_1 : out std_logic_vector(31 downto 0);
--! Data read from read register 2
Read_data_2 : out std_logic_vector(31 downto 0);
-- control signals
--! Togles reading/writing of values to registers
write_enable : in std_logic
);
end register_file;
--! @brief The architecture of this component is based on an array of 32 32-bit words
--! @details There are 32 registers which can all be read. All registers except
--! for register 0 can be written to. Register 0 contains the constant value 0
--! which is needed for the correct functioning of the MIPS processor.
architecture behavioral of register_file is
-- Zero register: constant value 0
subtype word is std_logic_vector(31 downto 0); --! Each register consists of
--! a 32 bit word
type registerFile is array (0 to 31) of word;
shared variable register_file : registerFile :=
(X"00000000", -- 0
X"00000000", -- 1
X"00000000", -- 2
X"00000000", -- 3
X"00000000", -- 4
X"00000000", -- 5
X"00000000", -- 6
X"00000000", -- 7
X"00000000", -- 8
X"00000000", -- 9
X"00000000", -- 10
X"00000000", -- 11
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000"); --! All registers are initialized to 0
begin -- behavioral
read_reg_proc : process ( Read_reg_1 , Read_reg_2 )
begin
Read_data_1 <= register_file(conv_integer(Read_reg_1));
Read_data_2 <= register_file(conv_integer(Read_reg_2));
end process read_reg_proc;
write_reg_proc : process (clk,Write_data)
begin -- process reg_file_proc
if write_enable = '1' then
if Write_reg /= X"00000000" then
register_file(conv_integer(Write_reg)) := Write_data;
end if;
end if;
end process write_reg_proc;
end behavioral;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library gmzpu;
use gmzpu.zwishbone.all;
library zetaio;
use zetaio.pic.all;
use zetaio.tim.all;
entity zwc is
generic (
DATA_WIDTH : natural:=32;
ADR_WIDTH : natural:=16;
CS_WIDTH : natural:=4
);
port (
-- SYSCON
clk_i : in std_logic;
rst_i : in std_logic;
-- zpu interface (non wishbone signal)
busy_o : out std_logic; -- controller busy
ready_o : out std_logic; -- read request ready
adr_i : in unsigned(ADR_WIDTH-1 downto 0);
re_i : in std_logic;
we_i : in std_logic;
dat_i : in unsigned(DATA_WIDTH-1 downto 0);
dat_o : out unsigned(DATA_WIDTH-1 downto 0);
int_i : in std_logic; -- external int
-- interrupts
-- wishbone controller int
irq_o : out std_logic
);
end entity zwc;
architecture rtl of zwc is
-- wishbone bus
signal wb_dat_i : unsigned(DATA_WIDTH-1 downto 0);
signal wb_dat_o : unsigned(DATA_WIDTH-1 downto 0);
signal wb_tgd_i : unsigned(DATA_WIDTH-1 downto 0);
signal wb_tgd_o : unsigned(DATA_WIDTH-1 downto 0);
signal wb_ack_i : std_logic;
signal wb_adr_o : unsigned(ADR_WIDTH-CS_WIDTH-2 downto 0);
signal wb_cyc_o : std_logic;
signal wb_stall_i : std_logic;
signal wb_err_i : std_logic;
signal wb_lock_o : std_logic;
signal wb_rty_i : std_logic;
signal wb_sel_o : std_logic_vector(DATA_WIDTH-1 downto 0);
signal wb_stb_o : std_logic_vector((2**CS_WIDTH)-1 downto 0);
signal wb_tga_o : unsigned(ADR_WIDTH-CS_WIDTH-2 downto 0);
signal wb_tgc_o : unsigned(DATA_WIDTH-1 downto 0); -- size correct?
signal wb_we_o : std_logic;
-- interrupt lines
signal int_ctrl_r : std_logic;
signal int_pic_r : std_logic;
signal int_timer_r : std_logic;
signal int_r : std_logic_vector(DATA_WIDTH-1 downto 0);
-- PIC interrupt mapping
constant PIC_INT_EXT : natural:=0;
constant PIC_INT_ZWC : natural:=1;
constant PIC_INT_TIMER : natural:=2;
constant PIC_INT_UNUSED : natural:=3;
-- devices on the bus
constant WB_CS_PIC : natural:=0;
constant WB_CS_TIM : natural:=1;
begin
-- unused interrupt lines
int_r(DATA_WIDTH-1 downto PIC_INT_UNUSED) <= (others => '0');
-- external interrupt line
int_r(PIC_INT_EXT) <= int_i;
-- master
controller: zwishbone_controller
generic map(
DATA_WIDTH => DATA_WIDTH, ADR_WIDTH => ADR_WIDTH, CS_WIDTH => CS_WIDTH
)
port map(
-- syscon
clk_i => clk_i, rst_i => rst_i, busy_o => busy_o, ready_o => ready_o,
-- interrupt
irq_o => int_r(PIC_INT_ZWC),
adr_i => adr_i, re_i => re_i, we_i => we_i, dat_i => dat_i, dat_o => dat_o,
-- chip select
wb_stb_o => wb_stb_o,
-- wishbone bus (master)
wb_dat_i => wb_dat_i, wb_dat_o => wb_dat_o,
wb_tgd_i => wb_tgd_i, wb_tgd_o => wb_tgd_o,
wb_ack_i => wb_ack_i, wb_adr_o => wb_adr_o,
wb_cyc_o => wb_cyc_o, wb_stall_i => wb_stall_i, wb_err_i => wb_err_i, wb_lock_o => wb_lock_o, wb_rty_i => wb_rty_i,
wb_sel_o => wb_sel_o,
wb_tga_o => wb_tga_o,
wb_tgc_o => wb_tgc_o,
wb_we_o => wb_we_o
);
-- slave 0: PIC
pic: interrupt_controller
generic map(ADR_WIDTH => ADR_WIDTH-CS_WIDTH-1, DATA_WIDTH => DATA_WIDTH, N_BANKS => 1)
port map(
-- syscon
rst_i => rst_i, clk_i => clk_i,
-- interrupt
int_i => int_r,
irq_o => irq_o,
-- chip select
wb_stb_i => wb_stb_o(WB_CS_PIC),
-- wishbone
wb_dat_o => wb_dat_i, wb_dat_i => wb_dat_o, wb_tgd_o => wb_tgd_i, wb_tgd_i => wb_tgd_o,
wb_ack_o => wb_ack_i, wb_adr_i => wb_adr_o, wb_cyc_i => wb_cyc_o,
wb_stall_o => wb_stall_i, wb_err_o => wb_err_i, wb_lock_i => wb_lock_o, wb_rty_o => wb_rty_i,
wb_sel_i => wb_sel_o,
wb_tga_i => wb_tga_o, wb_tgc_i => wb_tgc_o,
wb_we_i => wb_we_o
);
-- slave 1: TIMER
timrs: timers
generic map(DATA_WIDTH => DATA_WIDTH, ADR_WIDTH => ADR_WIDTH-CS_WIDTH-1, N_TIMERS => 4)
port map(
-- syscon
rst_i => rst_i, clk_i => clk_i,
-- interrupt
irq_o => int_r(PIC_INT_TIMER),
-- chip select
wb_stb_i => wb_stb_o(WB_CS_TIM),
-- wishbone
wb_dat_o => wb_dat_i, wb_dat_i => wb_dat_o, wb_tgd_o => wb_tgd_i, wb_tgd_i => wb_tgd_o,
wb_ack_o => wb_ack_i, wb_adr_i => wb_adr_o, wb_cyc_i => wb_cyc_o,
wb_stall_o => wb_stall_i, wb_err_o => wb_err_i, wb_lock_i => wb_lock_o, wb_rty_o => wb_rty_i,
wb_sel_i => wb_sel_o,
wb_tga_i => wb_tga_o, wb_tgc_i => wb_tgc_o,
wb_we_i => wb_we_o
);
end architecture rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc260.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p08n01i00260ent IS
END c03s01b02x00p08n01i00260ent;
ARCHITECTURE c03s01b02x00p08n01i00260arch OF c03s01b02x00p08n01i00260ent IS
BEGIN
TESTING: PROCESS
variable V : INTEGER := INTEGER'LOW;
variable R : REAL := 0.0;
BEGIN
R := 2.0 * REAL(V);
V := INTEGER(R);
assert FALSE
report "***FAILED TEST: c03s01b02x00p08n01i00260 - Number is out of integer bounds."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p08n01i00260arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc260.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p08n01i00260ent IS
END c03s01b02x00p08n01i00260ent;
ARCHITECTURE c03s01b02x00p08n01i00260arch OF c03s01b02x00p08n01i00260ent IS
BEGIN
TESTING: PROCESS
variable V : INTEGER := INTEGER'LOW;
variable R : REAL := 0.0;
BEGIN
R := 2.0 * REAL(V);
V := INTEGER(R);
assert FALSE
report "***FAILED TEST: c03s01b02x00p08n01i00260 - Number is out of integer bounds."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p08n01i00260arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc260.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p08n01i00260ent IS
END c03s01b02x00p08n01i00260ent;
ARCHITECTURE c03s01b02x00p08n01i00260arch OF c03s01b02x00p08n01i00260ent IS
BEGIN
TESTING: PROCESS
variable V : INTEGER := INTEGER'LOW;
variable R : REAL := 0.0;
BEGIN
R := 2.0 * REAL(V);
V := INTEGER(R);
assert FALSE
report "***FAILED TEST: c03s01b02x00p08n01i00260 - Number is out of integer bounds."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p08n01i00260arch;
|
entity func9 is
end entity;
architecture test of func9 is
constant msg0 : string := "zero";
constant msg1 : string := "one";
function get_message(x : in bit) return string is
begin
case x is
when '0' => return msg0;
when '1' => return msg1;
end case;
end function;
begin
process is
variable x : bit;
begin
x := '1';
wait for 1 ns; -- Prevent constant folding
assert get_message(x) = "one";
x := '0';
wait for 1 ns;
assert get_message(x) = "zero";
wait;
end process;
end architecture;
|
-------------------------------------------------------------------------------
--
-- Title : No Title
-- Design :
-- Author : Shadowmaker
-- Company : Home
--
-------------------------------------------------------------------------------
--
-- File : E:\Embedded\Projects\POCP\Lab05\Lab05\src\Task4_TB\Task4_tb3.vhd
-- Generated : 10/18/14 16:15:19
-- From : E:\Embedded\Projects\POCP\Lab05\Lab05\src\Task4.asf
-- By : ASFTEST ver. v.2.1.3 build 56, August 25, 2005
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library IEEE;
use IEEE.STD_LOGIC_TEXTIO.all;
use STD.TEXTIO.all;
entity Task4_ent_tb3 is
end entity Task4_ent_tb3;
architecture Task4_arch_tb3 of Task4_ent_tb3 is
constant delay_wr_in : Time := 5 ns;
constant delay_pos_edge : Time := 5 ns;
constant delay_wr_out : Time := 5 ns;
constant delay_neg_edge : Time := 5 ns;
file RESULTS : Text open WRITE_MODE is "results.txt";
procedure WRITE_RESULTS(
constant CLK : in Std_logic;
constant RST : in Std_logic;
constant IP : in Std_logic_Vector (3 downto 0);
constant OP : in Std_logic_Vector (1 downto 0)
) is
variable l_out : Line;
begin
WRITE(l_out, now, right, 15, ps);
-- write input signals
WRITE(l_out, CLK, right, 8);
WRITE(l_out, RST, right, 8);
WRITE(l_out, IP, right, 11);
-- write output signals
WRITE(l_out, OP, right, 9);
WRITELINE(RESULTS, l_out);
end;
component Task4 is
port(
CLK : in Std_logic;
RST : in Std_logic;
IP : in Std_logic_Vector (3 downto 0);
OP :out Std_logic_Vector (1 downto 0));
end component; -- Task4;
signal CLK : Std_logic;
signal RST : Std_logic;
signal IP : Std_logic_Vector (3 downto 0);
signal OP : Std_logic_Vector (1 downto 0);
signal cycle_num : Integer; -- takt number
-- this signal is added for compare test simulation results only
type test_state_type is (S0, S1, S2, S3, S4, any_state);
signal test_state : test_state_type;
begin
UUT : Task4
port map(
CLK => CLK,
RST => RST,
IP => IP,
OP => OP);
STIMULI : process
begin
-- Test reset - state(i)
CLK <= '0';
cycle_num <= 0;
wait for delay_wr_in;
RST <= '1';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 1;
wait for delay_wr_in;
RST <= '0';
wait for delay_pos_edge;
test_state <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
CLK <= '0';
cycle_num <= 2;
wait for delay_wr_in;
RST <= '0';
IP <= "1101";
wait for delay_pos_edge;
test_state <= S3;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S3
CLK <= '0';
cycle_num <= 3;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S2;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S2
CLK <= '0';
cycle_num <= 4;
wait for delay_wr_in;
RST <= '0';
IP <= "1100";
wait for delay_pos_edge;
test_state <= S1;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S1
CLK <= '0';
cycle_num <= 5;
wait for delay_wr_in;
RST <= '1';
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 6;
wait for delay_wr_in;
RST <= '0';
wait for delay_pos_edge;
test_state <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
CLK <= '0';
cycle_num <= 7;
wait for delay_wr_in;
RST <= '0';
IP <= "1101";
wait for delay_pos_edge;
test_state <= S3;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S3
CLK <= '0';
cycle_num <= 8;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S2;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S2
CLK <= '0';
cycle_num <= 9;
wait for delay_wr_in;
RST <= '1';
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 10;
wait for delay_wr_in;
RST <= '0';
wait for delay_pos_edge;
test_state <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
CLK <= '0';
cycle_num <= 11;
wait for delay_wr_in;
RST <= '0';
IP <= "1101";
wait for delay_pos_edge;
test_state <= S3;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S3
CLK <= '0';
cycle_num <= 12;
wait for delay_wr_in;
RST <= '1';
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 13;
wait for delay_wr_in;
RST <= '0';
wait for delay_pos_edge;
test_state <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
CLK <= '0';
cycle_num <= 14;
wait for delay_wr_in;
RST <= '1';
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
-- Test length 15
wait; -- stop simulation
end process; -- STIMULI;
WRITE_RESULTS(CLK,RST,IP,OP);
end architecture Task4_arch_tb3;
configuration Task4_cfg_tb3 of Task4_ent_tb3 is
for Task4_arch_tb3
for UUT : Task4 use entity work.Task4(Beh);
end for;
end for;
end Task4_cfg_tb3;
|
-------------------------------------------------------------------------------
--
-- Title : No Title
-- Design :
-- Author : Shadowmaker
-- Company : Home
--
-------------------------------------------------------------------------------
--
-- File : E:\Embedded\Projects\POCP\Lab05\Lab05\src\Task4_TB\Task4_tb3.vhd
-- Generated : 10/18/14 16:15:19
-- From : E:\Embedded\Projects\POCP\Lab05\Lab05\src\Task4.asf
-- By : ASFTEST ver. v.2.1.3 build 56, August 25, 2005
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library IEEE;
use IEEE.STD_LOGIC_TEXTIO.all;
use STD.TEXTIO.all;
entity Task4_ent_tb3 is
end entity Task4_ent_tb3;
architecture Task4_arch_tb3 of Task4_ent_tb3 is
constant delay_wr_in : Time := 5 ns;
constant delay_pos_edge : Time := 5 ns;
constant delay_wr_out : Time := 5 ns;
constant delay_neg_edge : Time := 5 ns;
file RESULTS : Text open WRITE_MODE is "results.txt";
procedure WRITE_RESULTS(
constant CLK : in Std_logic;
constant RST : in Std_logic;
constant IP : in Std_logic_Vector (3 downto 0);
constant OP : in Std_logic_Vector (1 downto 0)
) is
variable l_out : Line;
begin
WRITE(l_out, now, right, 15, ps);
-- write input signals
WRITE(l_out, CLK, right, 8);
WRITE(l_out, RST, right, 8);
WRITE(l_out, IP, right, 11);
-- write output signals
WRITE(l_out, OP, right, 9);
WRITELINE(RESULTS, l_out);
end;
component Task4 is
port(
CLK : in Std_logic;
RST : in Std_logic;
IP : in Std_logic_Vector (3 downto 0);
OP :out Std_logic_Vector (1 downto 0));
end component; -- Task4;
signal CLK : Std_logic;
signal RST : Std_logic;
signal IP : Std_logic_Vector (3 downto 0);
signal OP : Std_logic_Vector (1 downto 0);
signal cycle_num : Integer; -- takt number
-- this signal is added for compare test simulation results only
type test_state_type is (S0, S1, S2, S3, S4, any_state);
signal test_state : test_state_type;
begin
UUT : Task4
port map(
CLK => CLK,
RST => RST,
IP => IP,
OP => OP);
STIMULI : process
begin
-- Test reset - state(i)
CLK <= '0';
cycle_num <= 0;
wait for delay_wr_in;
RST <= '1';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 1;
wait for delay_wr_in;
RST <= '0';
wait for delay_pos_edge;
test_state <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
CLK <= '0';
cycle_num <= 2;
wait for delay_wr_in;
RST <= '0';
IP <= "1101";
wait for delay_pos_edge;
test_state <= S3;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S3
CLK <= '0';
cycle_num <= 3;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S2;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S2
CLK <= '0';
cycle_num <= 4;
wait for delay_wr_in;
RST <= '0';
IP <= "1100";
wait for delay_pos_edge;
test_state <= S1;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S1
CLK <= '0';
cycle_num <= 5;
wait for delay_wr_in;
RST <= '1';
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 6;
wait for delay_wr_in;
RST <= '0';
wait for delay_pos_edge;
test_state <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
CLK <= '0';
cycle_num <= 7;
wait for delay_wr_in;
RST <= '0';
IP <= "1101";
wait for delay_pos_edge;
test_state <= S3;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S3
CLK <= '0';
cycle_num <= 8;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S2;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S2
CLK <= '0';
cycle_num <= 9;
wait for delay_wr_in;
RST <= '1';
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 10;
wait for delay_wr_in;
RST <= '0';
wait for delay_pos_edge;
test_state <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
CLK <= '0';
cycle_num <= 11;
wait for delay_wr_in;
RST <= '0';
IP <= "1101";
wait for delay_pos_edge;
test_state <= S3;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S3
CLK <= '0';
cycle_num <= 12;
wait for delay_wr_in;
RST <= '1';
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 13;
wait for delay_wr_in;
RST <= '0';
wait for delay_pos_edge;
test_state <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
CLK <= '0';
cycle_num <= 14;
wait for delay_wr_in;
RST <= '1';
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
-- Test length 15
wait; -- stop simulation
end process; -- STIMULI;
WRITE_RESULTS(CLK,RST,IP,OP);
end architecture Task4_arch_tb3;
configuration Task4_cfg_tb3 of Task4_ent_tb3 is
for Task4_arch_tb3
for UUT : Task4 use entity work.Task4(Beh);
end for;
end for;
end Task4_cfg_tb3;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: constants_mem_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY constants_mem_exdes IS
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END constants_mem_exdes;
ARCHITECTURE xilinx OF constants_mem_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT constants_mem IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : constants_mem
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
-- $Id: $
-- File name: tb_sd_control.vhd
-- Created: 4/21/2012
-- Author: Spencer Julian
-- Lab Section: 337-02
-- Version: 1.0 Initial Test Bench
library ieee;
--library gold_lib; --UNCOMMENT if you're using a GOLD model
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use gold_lib.all; --UNCOMMENT if you're using a GOLD model
entity tb_sd_control is
generic (Period : Time := 10 ns);
end tb_sd_control;
architecture TEST of tb_sd_control is
function UINT_TO_STD_LOGIC( X: INTEGER; NumBits: INTEGER )
return STD_LOGIC_VECTOR is
begin
return std_logic_vector(to_unsigned(X, NumBits));
end;
function STD_LOGIC_TO_UINT( X: std_logic_vector)
return integer is
begin
return to_integer(unsigned(x));
end;
component sd_control
PORT(
clk : in std_logic;
rst : in std_logic;
sd_clock : in std_logic;
fifo_empty : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
clk_mode : out std_logic;
tsr_load : out std_logic;
tsr_enable : out std_logic;
sd_enable : out std_logic;
clk_enable : out std_logic
);
end component;
-- Insert signals Declarations here
signal clk : std_logic;
signal rst : std_logic;
signal sd_clock : std_logic;
signal fifo_empty : std_logic;
signal data_in : std_logic_vector(7 downto 0);
signal data_out : std_logic_vector(7 downto 0);
signal clk_mode : std_logic;
signal tsr_load : std_logic;
signal tsr_enable : std_logic;
signal sd_enable : std_logic;
signal clk_enable : std_logic;
-- signal <name> : <type>;
begin
CLKGEN: process
variable clk_tmp: std_logic := '0';
begin
clk_tmp := not clk_tmp;
clk <= clk_tmp;
wait for Period/2;
end process;
DUT: sd_control port map(
clk => clk,
rst => rst,
sd_clock => sd_clock,
fifo_empty => fifo_empty,
data_in => data_in,
data_out => data_out,
clk_mode => clk_mode,
tsr_load => tsr_load,
tsr_enable => tsr_enable,
sd_enable => sd_enable,
clk_enable => clk_enable
);
-- GOLD: <GOLD_NAME> port map(<put mappings here>);
process --sd clock generator
variable sd_clk_tmp: std_logic := '0';
begin
if (clk_enable = '1') then
sd_clk_tmp := not sd_clock;
sd_clock <= sd_clk_tmp;
if (clk_mode = '0') then
wait for Period*10;
else
wait for Period*2;
end if;
else
sd_clk_tmp := '0';
sd_clock <= sd_clk_tmp;
wait for Period;
end if;
end process;
process
begin
-- Insert TEST BENCH Code Here
fifo_empty <= '1'; --Reset ALL THE THINGS.
data_in <= (others => '0');
rst <= '0';
wait for Period;
rst <= '1'; --Finish reset, insert test data (doesn't matter what it is, just testing output), say fifo is no longer empty
data_in <= "10101010";
fifo_empty <= '0';
wait for Period*10000; --wait for a LOONG time to ensure that we see proper microSD setup, as that's this block's primary challenge.
fifo_empty <= '1'; --at this point we should have written things. Several times. Claim the fifo is empty now.
wait; --If that worked, then this should work as expected. TO THE TOP LEVEL!
end process;
end TEST;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity perm_layer is
port(data_in: in std_logic_vector(63 downto 0);
data_out: out std_logic_vector(63 downto 0)
);
end perm_layer;
architecture structural of perm_layer is
begin
PERM: for i in 63 downto 0 generate
data_out((i mod 4) * 16 + (i / 4)) <= data_in(i);
end generate;
end structural;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "xilinx_block_ram"
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xilinx_block_ram_pkg.all;
-------------------------------------------------------------------------------
entity xilinx_block_ram_tb is
end xilinx_block_ram_tb;
-------------------------------------------------------------------------------
architecture tb of xilinx_block_ram_tb is
-- component generics
constant ADDR_A_WIDTH : positive := 11;
constant ADDR_B_WIDTH : positive := 10;
constant DATA_A_WIDTH : positive := 8;
constant DATA_B_WIDTH : positive := 16;
-- component ports
signal addr_a : std_logic_vector(ADDR_A_WIDTH-1 downto 0) := (others => '0');
signal addr_b : std_logic_vector(ADDR_B_WIDTH-1 downto 0) := (others => '0');
signal din_a : std_logic_vector(DATA_A_WIDTH-1 downto 0) := (others => '0');
signal din_b : std_logic_vector(DATA_B_WIDTH-1 downto 0) := (others => '0');
signal dout_a : std_logic_vector(DATA_A_WIDTH-1 downto 0) := (others => '0');
signal dout_b : std_logic_vector(DATA_B_WIDTH-1 downto 0) := (others => '0');
signal we_a : std_logic := '0';
signal we_b : std_logic := '0';
-- clock
signal clk : std_logic := '1';
begin -- tb
-- component instantiation
DUT : xilinx_block_ram_dual_port
generic map (
ADDR_A_WIDTH => ADDR_A_WIDTH,
ADDR_B_WIDTH => ADDR_B_WIDTH,
DATA_A_WIDTH => DATA_A_WIDTH,
DATA_B_WIDTH => DATA_B_WIDTH)
port map (
addr_a => addr_a,
addr_b => addr_b,
din_a => din_a,
din_b => din_b,
dout_a => dout_a,
dout_b => dout_b,
we_a => we_a,
we_b => we_b,
en_a => '1',
en_b => '1',
ssr_a => '0',
ssr_b => '0',
clk_a => clk,
clk_b => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
begin
wait until clk = '0';
-- write Port A 0xfe at 0x20
addr_a <= std_logic_vector(unsigned'(resize(x"0020", addr_a'length)));
din_a <= std_logic_vector(unsigned'(resize(x"00fe", din_a'length)));
we_a <= '1';
wait until clk = '0';
we_a <= '0';
-- write Port A 0xab at 0x21
addr_a <= std_logic_vector(unsigned'(resize(x"0021", addr_a'length)));
din_a <= std_logic_vector(unsigned'(resize(x"00ab", din_a'length)));
we_a <= '1';
-- read Port B 0x20 / 2
addr_b <= std_logic_vector(unsigned'(resize(x"0010", addr_b'length)));
wait until clk = '0';
we_a <= '0';
-- Remember the effect of "read-first":
-- When 0x21 is addressed the memory cell is read before 0xab is
-- written to that cell. Thus 0x00 will appear at the output of dout_a.
-- 0xab will appear with the next rising clock edge on the output dout_a.
wait until clk = '0';
-- do not repeat
wait for 10 ms;
end process WaveGen_Proc;
end tb;
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "xilinx_block_ram"
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xilinx_block_ram_pkg.all;
-------------------------------------------------------------------------------
entity xilinx_block_ram_tb is
end xilinx_block_ram_tb;
-------------------------------------------------------------------------------
architecture tb of xilinx_block_ram_tb is
-- component generics
constant ADDR_A_WIDTH : positive := 11;
constant ADDR_B_WIDTH : positive := 10;
constant DATA_A_WIDTH : positive := 8;
constant DATA_B_WIDTH : positive := 16;
-- component ports
signal addr_a : std_logic_vector(ADDR_A_WIDTH-1 downto 0) := (others => '0');
signal addr_b : std_logic_vector(ADDR_B_WIDTH-1 downto 0) := (others => '0');
signal din_a : std_logic_vector(DATA_A_WIDTH-1 downto 0) := (others => '0');
signal din_b : std_logic_vector(DATA_B_WIDTH-1 downto 0) := (others => '0');
signal dout_a : std_logic_vector(DATA_A_WIDTH-1 downto 0) := (others => '0');
signal dout_b : std_logic_vector(DATA_B_WIDTH-1 downto 0) := (others => '0');
signal we_a : std_logic := '0';
signal we_b : std_logic := '0';
-- clock
signal clk : std_logic := '1';
begin -- tb
-- component instantiation
DUT : xilinx_block_ram_dual_port
generic map (
ADDR_A_WIDTH => ADDR_A_WIDTH,
ADDR_B_WIDTH => ADDR_B_WIDTH,
DATA_A_WIDTH => DATA_A_WIDTH,
DATA_B_WIDTH => DATA_B_WIDTH)
port map (
addr_a => addr_a,
addr_b => addr_b,
din_a => din_a,
din_b => din_b,
dout_a => dout_a,
dout_b => dout_b,
we_a => we_a,
we_b => we_b,
en_a => '1',
en_b => '1',
ssr_a => '0',
ssr_b => '0',
clk_a => clk,
clk_b => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
begin
wait until clk = '0';
-- write Port A 0xfe at 0x20
addr_a <= std_logic_vector(unsigned'(resize(x"0020", addr_a'length)));
din_a <= std_logic_vector(unsigned'(resize(x"00fe", din_a'length)));
we_a <= '1';
wait until clk = '0';
we_a <= '0';
-- write Port A 0xab at 0x21
addr_a <= std_logic_vector(unsigned'(resize(x"0021", addr_a'length)));
din_a <= std_logic_vector(unsigned'(resize(x"00ab", din_a'length)));
we_a <= '1';
-- read Port B 0x20 / 2
addr_b <= std_logic_vector(unsigned'(resize(x"0010", addr_b'length)));
wait until clk = '0';
we_a <= '0';
-- Remember the effect of "read-first":
-- When 0x21 is addressed the memory cell is read before 0xab is
-- written to that cell. Thus 0x00 will appear at the output of dout_a.
-- 0xab will appear with the next rising clock edge on the output dout_a.
wait until clk = '0';
-- do not repeat
wait for 10 ms;
end process WaveGen_Proc;
end tb;
-------------------------------------------------------------------------------
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library work;
use work.wishbonepkg.all;
entity xtc_wbmux2 is
generic (
select_line: integer;
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_syscon: in wb_syscon_type;
-- Master
m_wbi: in wb_mosi_type;
m_wbo: out wb_miso_type;
-- Slave signals
s0_wbo: out wb_mosi_type;
s0_wbi: in wb_miso_type;
s1_wbo: out wb_mosi_type;
s1_wbi: in wb_miso_type
);
end entity xtc_wbmux2;
architecture behave of xtc_wbmux2 is
component reqcnt is
port (
clk: in std_logic;
rst: in std_logic;
stb: in std_logic;
cyc: in std_logic;
stall:in std_logic;
ack: in std_logic;
req: out std_logic
);
end component;
signal select_zero: std_logic;
--signal trcnt0, trcnt1: unsigned(3 downto 0);
signal t0,t1: std_logic;
signal qdat,qtag: std_logic_vector(31 downto 0);
signal queue, queued, qerr: std_logic;
signal internal_stall:std_logic;
signal req0,req1: std_logic;
signal endt0,endt1: std_logic;
begin
select_zero<='1' when m_wbi.adr(select_line)='0' else '0';
req0<=(select_zero and m_wbi.stb) and not internal_stall;
req1<=((not select_zero) and m_wbi.stb) and not internal_stall;
s0_wbo.dat <= m_wbi.dat;
s0_wbo.adr <= m_wbi.adr;
s0_wbo.stb <= req0;--m_wbi.stb and not internal_stall;
s0_wbo.we <= m_wbi.we;
s0_wbo.sel <= m_wbi.sel;
s0_wbo.tag <= m_wbi.tag;
s0_wbo.cti <= m_wbi.cti;
s0_wbo.bte <= m_wbi.bte;
s1_wbo.dat <= m_wbi.dat;
s1_wbo.adr <= m_wbi.adr;
s1_wbo.stb <= req1;--m_wbi.stb and not internal_stall;
s1_wbo.we <= m_wbi.we;
s1_wbo.sel <= m_wbi.sel;
s1_wbo.tag <= m_wbi.tag;
s1_wbo.cti <= m_wbi.cti;
s1_wbo.bte <= m_wbi.bte;
cnt0: reqcnt port map (
clk => wb_syscon.clk,
rst => wb_syscon.rst,
stb => req0,
cyc => m_wbi.cyc,
stall => s0_wbi.stall,
ack => endt0,
req => t0
);
endt0<=s0_wbi.ack or s0_wbi.err;
cnt1: reqcnt port map (
clk => wb_syscon.clk,
rst => wb_syscon.rst,
stb => req1,
cyc => m_wbi.cyc,
stall => s1_wbi.stall,
ack => endt1,
req => t1
);
endt1 <= s1_wbi.ack or s1_wbi.err;
process(m_wbi.cyc,select_zero,m_wbi.stb,t0,t1)
begin
if m_wbi.cyc='0' then
s0_wbo.cyc<='0';
s1_wbo.cyc<='0';
else
s0_wbo.cyc<=(select_zero and m_wbi.cyc) or t0;
s1_wbo.cyc<=(( not select_zero ) and m_wbi.cyc) or t1;
end if;
end process;
process(t0,t1,m_wbi.stb,m_wbi.cyc,select_zero)
begin
internal_stall<='0';
if m_wbi.stb='1' and m_wbi.cyc='1' then
-- Check if same request
if select_zero='1' and t1='1' then
internal_stall<='1';
elsif select_zero='0' and t0='1' then
internal_stall<='1';
end if;
end if;
end process;
process(select_zero,s1_wbi.stall,s0_wbi.stall,internal_stall)
begin
if select_zero='0' then
m_wbo.stall<=s1_wbi.stall or internal_stall;
else
m_wbo.stall<=s0_wbi.stall or internal_stall;
end if;
end process;
-- synthesis translate_off
process (wb_syscon.clk)
begin
if rising_edge(wb_syscon.clk) then
if is_x(s0_wbi.err) then
--report "Slave0 'err' is X" severity failure;
end if;
if is_x(s1_wbi.err) then
--report "Slave1 'err' is X" severity failure;
end if;
end if;
end process;
-- synthesis translate_on
-- Process responses from both slaves.
-- USE ONLY IN SIMULATION FOR NOW!!!!!
process(s0_wbi,s1_wbi,queued,qdat,qtag)
variable sel: std_logic_vector(1 downto 0);
begin
sel(0) := s0_wbi.ack or s0_wbi.err;
sel(1) := s1_wbi.ack or s1_wbi.err;
queue <= '0';
case sel is
when "00" =>
if queued='0' then
m_wbo.ack<='0';
m_wbo.err<='0';
m_wbo.dat<=(others => 'X');
m_wbo.tag<=(others => 'X');
else
m_wbo.ack<='1';
m_wbo.dat<=qdat;
m_wbo.err<=qerr;
m_wbo.tag<=qtag;
end if;
when "01" =>
m_wbo.ack<='1';
m_wbo.dat<=s0_wbi.dat;
m_wbo.err<=s0_wbi.err;
m_wbo.tag<=s0_wbi.tag;
when "10" =>
m_wbo.ack<='1';
m_wbo.dat<=s1_wbi.dat;
m_wbo.err<=s1_wbi.err;
m_wbo.tag<=s1_wbi.tag;
when "11" =>
queue <= '1'; -- Queue S1 request.
m_wbo.ack<='1';
m_wbo.dat<=s0_wbi.dat;
m_wbo.err<=s0_wbi.err;
m_wbo.tag<=s0_wbi.tag;
when others => null;
end case;
end process;
process(wb_syscon.clk)
begin
if rising_edge(wb_syscon.clk) then
if wb_syscon.rst='1' then
queued<='0';
else
queued<='0';
if queue='1' and queued='0' then
queued<='1';
qdat <= s1_wbi.dat;
qtag <= s1_wbi.tag;
qerr <= s1_wbi.err;
end if;
end if;
end if;
end process;
end behave;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: iodrp_mcb_controller.vhd
-- /___/ /\ Date Last Modified: $Date: 2010/03/21 17:21:17 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design for IODRP controller for v0.9 device
--
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 03/19/09: Initial version for IODRP_MCB read operations.
-- 1.1: 04/03/09: SLH - Added left shift for certain IOI's
-- End Revision
--*******************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity iodrp_mcb_controller is
--output to IODRP SDI pin
--input from IODRP SDO pin
-- Register where memcell_address is captured during the READY state
-- Register which stores the write data until it is ready to be shifted out
-- The shift register which shifts out SDO and shifts in SDI.
-- This register is loaded before the address or data phase, but continues to shift for a writeback of read data
-- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO
-- The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg
-- The counter for which bit is being shifted during address or data phase
-- This is set after the first address phase has executed
-- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg
--added so that DRP_SDI output is only active when DRP_CS is active
port (
memcell_address : in std_logic_vector(7 downto 0);
write_data : in std_logic_vector(7 downto 0);
read_data : out std_logic_vector(7 downto 0);
rd_not_write : in std_logic;
cmd_valid : in std_logic;
rdy_busy_n : out std_logic;
use_broadcast : in std_logic;
drp_ioi_addr : in std_logic_vector(4 downto 0);
sync_rst : in std_logic;
DRP_CLK : in std_logic;
DRP_CS : out std_logic;
DRP_SDI : out std_logic;
DRP_ADD : out std_logic;
DRP_BKST : out std_logic;
DRP_SDO : in std_logic;
MCB_UIREAD : out std_logic
);
end entity iodrp_mcb_controller;
architecture trans of iodrp_mcb_controller is
constant READY : std_logic_vector(3 downto 0) := "0000";
constant DECIDE : std_logic_vector(3 downto 0) := "0001";
constant ADDR_PHASE : std_logic_vector(3 downto 0) := "0010";
constant ADDR_TO_DATA_GAP : std_logic_vector(3 downto 0) := "0011";
constant ADDR_TO_DATA_GAP2 : std_logic_vector(3 downto 0) := "0100";
constant ADDR_TO_DATA_GAP3 : std_logic_vector(3 downto 0) := "0101";
constant DATA_PHASE : std_logic_vector(3 downto 0) := "0110";
constant ALMOST_READY : std_logic_vector(3 downto 0) := "0111";
constant ALMOST_READY2 : std_logic_vector(3 downto 0) := "1001";
constant ALMOST_READY3 : std_logic_vector(3 downto 0) := "1010";
constant IOI_DQ0 : std_logic_vector(4 downto 0) := "00001";
constant IOI_DQ1 : std_logic_vector(4 downto 0) := "00000";
constant IOI_DQ2 : std_logic_vector(4 downto 0) := "00011";
constant IOI_DQ3 : std_logic_vector(4 downto 0) := "00010";
constant IOI_DQ4 : std_logic_vector(4 downto 0) := "00101";
constant IOI_DQ5 : std_logic_vector(4 downto 0) := "00100";
constant IOI_DQ6 : std_logic_vector(4 downto 0) := "00111";
constant IOI_DQ7 : std_logic_vector(4 downto 0) := "00110";
constant IOI_DQ8 : std_logic_vector(4 downto 0) := "01001";
constant IOI_DQ9 : std_logic_vector(4 downto 0) := "01000";
constant IOI_DQ10 : std_logic_vector(4 downto 0) := "01011";
constant IOI_DQ11 : std_logic_vector(4 downto 0) := "01010";
constant IOI_DQ12 : std_logic_vector(4 downto 0) := "01101";
constant IOI_DQ13 : std_logic_vector(4 downto 0) := "01100";
constant IOI_DQ14 : std_logic_vector(4 downto 0) := "01111";
constant IOI_DQ15 : std_logic_vector(4 downto 0) := "01110";
constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := "11101";
constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := "11100";
constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := "11111";
constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := "11110";
signal memcell_addr_reg : std_logic_vector(7 downto 0);
signal data_reg : std_logic_vector(7 downto 0);
signal shift_through_reg : std_logic_vector(8 downto 0);
signal load_shift_n : std_logic;
signal addr_data_sel_n : std_logic;
signal bit_cnt : std_logic_vector(2 downto 0);
signal rd_not_write_reg : std_logic;
signal AddressPhase : std_logic;
signal DRP_CS_pre : std_logic;
signal extra_cs : std_logic;
signal state : std_logic_vector(3 downto 0);
signal nextstate : std_logic_vector(3 downto 0);
signal data_out : std_logic_vector(8 downto 0);
signal data_out_mux : std_logic_vector(8 downto 0);
signal DRP_SDI_pre : std_logic;
--synthesis translate_off
signal state_ascii : std_logic_vector(32 * 8 - 1 downto 0);
-- case(state)
--synthesis translate_on
-- The changes below are to compensate for an issue with 1.0 silicon.
-- It may still be necessary to add a clock cycle to the ADD and CS signals
--`define DRP_v1_0_FIX // Uncomment out this line for synthesis
procedure shift_n_expand(
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(8 downto 0)) is
variable data_out_xilinx2 : std_logic_vector(8 downto 0);
begin
if ((data_in(0)) = '1') then
data_out_xilinx2(1 downto 0) := "11";
else
data_out_xilinx2(1 downto 0) := "00";
end if;
if (data_in(1 downto 0) = "10") then
data_out_xilinx2(2 downto 1) := "11";
else
data_out_xilinx2(2 downto 1) := (data_in(1) & data_out_xilinx2(1));
end if;
if (data_in(2 downto 1) = "10") then
data_out_xilinx2(3 downto 2) := "11";
else
data_out_xilinx2(3 downto 2) := (data_in(2) & data_out_xilinx2(2));
end if;
if (data_in(3 downto 2) = "10") then
data_out_xilinx2(4 downto 3) := "11";
else
data_out_xilinx2(4 downto 3) := (data_in(3) & data_out_xilinx2(3));
end if;
if (data_in(4 downto 3) = "10") then
data_out_xilinx2(5 downto 4) := "11";
else
data_out_xilinx2(5 downto 4) := (data_in(4) & data_out_xilinx2(4));
end if;
if (data_in(5 downto 4) = "10") then
data_out_xilinx2(6 downto 5) := "11";
else
data_out_xilinx2(6 downto 5) := (data_in(5) & data_out_xilinx2(5));
end if;
if (data_in(6 downto 5) = "10") then
data_out_xilinx2(7 downto 6) := "11";
else
data_out_xilinx2(7 downto 6) := (data_in(6) & data_out_xilinx2(6));
end if;
if (data_in(7 downto 6) = "10") then
data_out_xilinx2(8 downto 7) := "11";
else
data_out_xilinx2(8 downto 7) := (data_in(7) & data_out_xilinx2(7));
end if;
end shift_n_expand;
-- Declare intermediate signals for referenced outputs
signal DRP_CS_xilinx1 : std_logic;
signal DRP_ADD_xilinx0 : std_logic;
signal ALMOST_READY2_ST : std_logic;
signal ADDR_PHASE_ST : std_logic;
signal BIT_CNT7 : std_logic;
signal ADDR_PHASE_ST1 : std_logic;
signal DATA_PHASE_ST : std_logic;
begin
-- Drive referenced outputs
DRP_CS <= DRP_CS_xilinx1;
DRP_ADD <= DRP_ADD_xilinx0;
-- process (state)
-- begin
-- case state is
-- when READY =>
-- state_ascii <= "READY";
-- when DECIDE =>
-- state_ascii <= "DECIDE";
-- when ADDR_PHASE =>
-- state_ascii <= "ADDR_PHASE";
-- when ADDR_TO_DATA_GAP =>
-- state_ascii <= "ADDR_TO_DATA_GAP";
-- when ADDR_TO_DATA_GAP2 =>
-- state_ascii <= "ADDR_TO_DATA_GAP2";
-- when ADDR_TO_DATA_GAP3 =>
-- state_ascii <= "ADDR_TO_DATA_GAP3";
-- when DATA_PHASE =>
-- state_ascii <= "DATA_PHASE";
-- when ALMOST_READY =>
-- state_ascii <= "ALMOST_READY";
-- when ALMOST_READY2 =>
-- state_ascii <= "ALMOST_READY2";
-- when ALMOST_READY3 =>
-- state_ascii <= "ALMOST_READY3";
-- when others =>
-- null;
-- end case;
-- end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (state = READY) then
memcell_addr_reg <= memcell_address;
data_reg <= write_data;
rd_not_write_reg <= rd_not_write;
end if;
end if;
end process;
rdy_busy_n <= '1' when state = READY else '0';
process (drp_ioi_addr, data_out)
begin
case drp_ioi_addr is
when IOI_DQ0 =>
data_out_mux <= data_out;
when IOI_DQ1 =>
data_out_mux <= data_out;
when IOI_DQ2 =>
data_out_mux <= data_out;
when IOI_DQ3 =>
data_out_mux <= data_out;
when IOI_DQ4 =>
data_out_mux <= data_out;
when IOI_DQ5 =>
data_out_mux <= data_out;
when IOI_DQ6 =>
data_out_mux <= data_out;
when IOI_DQ7 =>
data_out_mux <= data_out;
when IOI_DQ8 =>
data_out_mux <= data_out;
when IOI_DQ9 =>
data_out_mux <= data_out;
when IOI_DQ10 =>
data_out_mux <= data_out;
when IOI_DQ11 =>
data_out_mux <= data_out;
when IOI_DQ12 =>
data_out_mux <= data_out;
when IOI_DQ13 =>
data_out_mux <= data_out;
when IOI_DQ14 =>
data_out_mux <= data_out;
when IOI_DQ15 =>
data_out_mux <= data_out;
when IOI_UDQS_CLK =>
data_out_mux <= data_out;
when IOI_UDQS_PIN =>
data_out_mux <= data_out;
when IOI_LDQS_CLK =>
data_out_mux <= data_out;
when IOI_LDQS_PIN =>
data_out_mux <= data_out;
when others =>
data_out_mux <= data_out;
end case;
end process;
data_out <= ('0' & memcell_addr_reg) when (addr_data_sel_n = '1') else
('0' & data_reg);
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
shift_through_reg <= "000000000";
else
if (load_shift_n = '1') then --Assume the shifter is either loading or shifting, bit 0 is shifted out first
shift_through_reg <= data_out_mux;
else
shift_through_reg <= ('0' & DRP_SDO & shift_through_reg(7 downto 1));
end if;
end if;
end if;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (not(sync_rst)) = '1') then
bit_cnt <= bit_cnt + "001";
else
bit_cnt <= "000";
end if;
end if;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
read_data <= "00000000";
else
if (state = ALMOST_READY3) then
read_data <= shift_through_reg(7 downto 0);
end if;
end if;
end if;
end process;
ALMOST_READY2_ST <= '1' when state = ALMOST_READY2 else '0';
ADDR_PHASE_ST <= '1' when state = ADDR_PHASE else '0';
BIT_CNT7 <= '1' when bit_cnt = "111" else '0';
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
AddressPhase <= '0';
else
if (AddressPhase = '1') then
-- Keep it set until we finish the cycle
AddressPhase <= AddressPhase and (not ALMOST_READY2_ST);
else
-- set the address phase when ever we finish the address phase
AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7);
end if;
end if;
end if;
end process;
ADDR_PHASE_ST1 <= '1' when nextstate = ADDR_PHASE else '0';
DATA_PHASE_ST <= '1' when nextstate = DATA_PHASE else '0';
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
DRP_ADD_xilinx0 <= ADDR_PHASE_ST1;
-- DRP_CS <= (drp_ioi_addr != IOI_DQ0) ? (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE) : (bit_cnt != 3'b111) && (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE);
DRP_CS_xilinx1 <= ADDR_PHASE_ST1 or DATA_PHASE_ST;
MCB_UIREAD <= DATA_PHASE_ST and rd_not_write_reg;
if (state = READY) then
DRP_BKST <= use_broadcast;
end if;
end if;
end process;
DRP_SDI_pre <= shift_through_reg(0) when (DRP_CS_xilinx1 = '1') else --if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance
'0';
DRP_SDI <= DRP_SDO when ((rd_not_write_reg and DRP_CS_xilinx1 and not(DRP_ADD_xilinx0)) = '1') else --If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance
DRP_SDI_pre;
process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase)
begin
addr_data_sel_n <= '0';
load_shift_n <= '0';
case state is
when READY =>
load_shift_n <= '0';
if (cmd_valid = '1') then
nextstate <= DECIDE;
else
nextstate <= READY;
end if;
when DECIDE =>
load_shift_n <= '1';
addr_data_sel_n <= '1';
nextstate <= ADDR_PHASE;
-- After the second pass go to end of statemachine
-- execute a second address phase for the alternative access method.
when ADDR_PHASE =>
load_shift_n <= '0';
if (BIT_CNT7 = '1') then
if (('1' and rd_not_write_reg) = '1') then
if (AddressPhase = '1') then
nextstate <= ALMOST_READY;
else
nextstate <= DECIDE;
end if;
else
nextstate <= ADDR_TO_DATA_GAP;
end if;
else
nextstate <= ADDR_PHASE;
end if;
when ADDR_TO_DATA_GAP =>
load_shift_n <= '1';
nextstate <= ADDR_TO_DATA_GAP2;
when ADDR_TO_DATA_GAP2 =>
load_shift_n <= '1';
nextstate <= ADDR_TO_DATA_GAP3;
when ADDR_TO_DATA_GAP3 =>
load_shift_n <= '1';
nextstate <= DATA_PHASE;
when DATA_PHASE =>
load_shift_n <= '0';
if (BIT_CNT7 = '1') then
nextstate <= ALMOST_READY;
else
nextstate <= DATA_PHASE;
end if;
when ALMOST_READY =>
load_shift_n <= '0';
nextstate <= ALMOST_READY2;
when ALMOST_READY2 =>
load_shift_n <= '0';
nextstate <= ALMOST_READY3;
when ALMOST_READY3 =>
load_shift_n <= '0';
nextstate <= READY;
when others =>
load_shift_n <= '0';
nextstate <= READY;
end case;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
state <= READY;
else
state <= nextstate;
end if;
end if;
end process;
end architecture trans;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: toutpad_ds
-- File: toutpad_ds.vhd
-- Author: Jonas Ekergarn - Aeroflex Gaisler
-- Description: tri-state differential output pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity toutpad_ds is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (padp, padn : out std_ulogic; i, en : in std_ulogic);
end;
architecture rtl of toutpad_ds is
signal oen : std_ulogic;
signal padx, gnd : std_ulogic;
begin
gnd <= '0';
oen <= not en when oepol /= padoen_polarity(tech) else en;
gen0 : if has_ds_pads(tech) = 0 or (is_unisim(tech) = 1) or
tech = axcel or tech = axdsp or tech = rhlib18t or
tech = ut25 or tech = ut130
generate
padp <= i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(en)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
;
padn <= not i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(en)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
;
end generate;
pa3 : if (tech = apa3) generate
u0 : apa3_toutpad_ds generic map (level)
port map (padp, padn, i, oen);
end generate;
pa3e : if (tech = apa3e) generate
u0 : apa3e_toutpad_ds generic map (level)
port map (padp, padn, i, oen);
end generate;
igl2 : if (tech = igloo2) or (tech = rtg4) generate
u0 : igloo2_toutpad_ds port map (padp, padn, i, oen);
end generate;
pa3l : if (tech = apa3l) generate
u0 : apa3l_toutpad_ds generic map (level)
port map (padp, padn, i, oen);
end generate;
fus : if (tech = actfus) generate
u0 : fusion_toutpad_ds generic map (level)
port map (padp, padn, i, oen);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity toutpad_dsv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp : out std_logic_vector(width-1 downto 0);
padn : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic);
end;
architecture rtl of toutpad_dsv is
begin
v : for j in width-1 downto 0 generate
u0 : toutpad_ds generic map (tech, level, slew, voltage, strength, oepol)
port map (padp(j), padn(j), i(j), en);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity toutpad_dsvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp : out std_logic_vector(width-1 downto 0);
padn : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0));
end;
architecture rtl of toutpad_dsvv is
begin
v : for j in width-1 downto 0 generate
u0 : toutpad_ds generic map (tech, level, slew, voltage, strength, oepol)
port map (padp(j), padn(j), i(j), en(j));
end generate;
end;
|
-------------------------------------------------------------------------------
-- reset_sync_module.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: reset_sync_module.vhd
-- Version: v3.0
-- Description: This is the reset sync module.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_misc.all;
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.axi_lite_ipif;
use axi_lite_ipif_v3_0.ipif_pkg.all;
library axi_quad_spi_v3_2;
use axi_quad_spi_v3_2.all;
library unisim;
use unisim.vcomponents.FDR;
-------------------------------------------------------------------------------
entity reset_sync_module is
--generic();
port(EXT_SPI_CLK : in std_logic;
Soft_Reset_frm_axi: in std_logic;
Rst_to_spi : out std_logic
);
end entity reset_sync_module;
architecture imp of reset_sync_module is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- signal declaration
signal Soft_Reset_frm_axi_d1 : std_logic;
signal Soft_Reset_frm_axi_d2 : std_logic;
signal Soft_Reset_frm_axi_d3 : std_logic;
attribute ASYNC_REG : string;
attribute ASYNC_REG of RESET_SYNC_AX2S_1 : label is "TRUE";
-----
begin
-----
--RESET_SYNC_FROM_AXI_TO_SPI: process(EXT_SPI_CLK)is
-------
--begin
-------
-- if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
-- Soft_Reset_frm_axi_d1 <= Soft_Reset_frm_axi;
-- Soft_Reset_frm_axi_d2 <= Soft_Reset_frm_axi_d1;
-- Soft_Reset_frm_axi_d3 <= Soft_Reset_frm_axi_d2;
-- end if;
--end process RESET_SYNC_FROM_AXI_TO_SPI;
-----------------------------------------
RESET_SYNC_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => Soft_Reset_frm_axi_d1,
C => EXT_SPI_CLK,
D => Soft_Reset_frm_axi,
R => '0'
);
RESET_SYNC_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => Soft_Reset_frm_axi_d2,
C => EXT_SPI_CLK,
D => Soft_Reset_frm_axi_d1,
R => '0'
);
Rst_to_spi <= Soft_Reset_frm_axi_d2;
---------------------------------------
end architecture imp;
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
--
-- Title : fourbit_submodule
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\ESE345_PROJECT\ALU\src\fourbit_submodule.vhd
-- Generated : Thu Nov 17 11:48:45 2016
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {fourbit_submodule} architecture {structural}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity fourbit_submodule is
port(
a: in std_logic_vector (3 downto 0);
b: in std_logic_vector (3 downto 0);
c0: in std_logic;
s: out std_logic_vector (3 downto 0);
Pi: out std_logic;
Gi: out std_logic
);
end fourbit_submodule;
--}} End of automatically maintained section
architecture structural of fourbit_submodule is
signal p0, p1, p2, p3, g0, g1, g2, g3, c1, c2, c3: std_logic;
begin
u1: entity xor_2_structural port map(i1 => a(0), i2 => b(0), o1 => p0);
u2: entity xor_2_structural port map(i1 => a(1), i2 => b(1), o1 => p1);
u3: entity xor_2_structural port map(i1 => a(2), i2 => b(2), o1 => p2);
u4: entity xor_2_structural port map(i1 => a(3), i2 => b(3), o1 => p3);
Pi <= p0 and p1 and p2 and p3;
u5: entity and_2 port map(i1 => a(0), i2 => b(0), o1 => g0);
u6: entity and_2 port map(i1 => a(1), i2 => b(1), o1 => g1);
u7: entity and_2 port map(i1 => a(2), i2 => b(2), o1 => g2);
u8: entity and_2 port map(i1 => a(3), i2 => b(3), o1 => g3);
Gi <= g3 or (p3 and g2) or (p3 and p2 and g1) or (p3 and p2 and p1 and g0);
c1 <= g0 or (p0 and c0);
c2 <= g1 or (p1 and g0) or (p1 and p0 and c0);
c3 <= g2 or (p2 and g1) or (p2 and p1 and g0) or (p2 and p1 and p0 and c0);
u13: entity xor_2_structural port map(i1 => p0, i2 => c0, o1 => s(0));
u14: entity xor_2_structural port map(i1 => p1, i2 => c1, o1 => s(1));
u15: entity xor_2_structural port map(i1 => p2, i2 => c2, o1 => s(2));
u16: entity xor_2_structural port map(i1 => p3, i2 => c3, o1 => s(3));
end structural;
|
-- $Id: pdp11.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: pdp11
-- Description: Definitions for pdp11 components
--
-- Dependencies: -
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.4.8 now numeric_std clean
-- 2010-12-30 351 1.4.7 rename pdp11_core_rri->pdp11_core_rbus; use rblib
-- 2010-10-23 335 1.4.6 rename RRI_LAM->RB_LAM;
-- 2010-10-16 332 1.4.5 renames of pdp11_du_drv port names
-- 2010-09-18 330 1.4.4 rename (adlm)box->(oalm)unit
-- 2010-06-20 308 1.4.3 add c_ibrb_ibf_ def's
-- 2010-06-20 307 1.4.2 rename cpacc to cacc in vm_cntl_type, mmu_cntl_type
-- 2010-06-18 306 1.4.1 add racc, be to cp_addr_type; rm pdp11_ibdr_rri
-- 2010-06-13 305 1.4 add rnum to cp_cntl_type, cprnum to cpustat_type;
-- reassign cp command codes and rename: c_cp_func_...
-- -> c_cpfunc_...; remove cpaddr_(lal|lah|inc) from
-- dpath_cntl_type; add cpdout_we to dpath_cntl_type;
-- reassign rbus adresses and rename: c_rb_addr_...
-- -> c_rbaddr_...; rename rbus fields: c_rb_statf_...
-- -> c_stat_rbf_...
-- 2010-06-12 304 1.3.3 add cpuwait to cp_stat_type and cpustat_type
-- 2010-06-11 303 1.3.2 use IB_MREQ.racc instead of RRI_REQ
-- 2010-05-02 287 1.3.1 rename RP_STAT->RB_STAT
-- 2010-05-01 285 1.3 port to rri V2 interface; drop pdp11_rri_2rp;
-- rename c_rp_addr_* -> c_rb_addr_*
-- 2010-03-21 270 1.2.6 add pdp11_du_drv
-- 2009-05-30 220 1.2.5 final removal of snoopers (were already commented)
-- 2009-05-10 214 1.2.4 add ENA (trace enable) for _tmu; add _pdp11_tmu_sb
-- 2009-05-09 213 1.2.3 BUGFIX: default for inst_compl now '0'
-- 2008-12-14 177 1.2.2 add gpr_* fields to DM_STAT_DP
-- 2008-11-30 174 1.2.1 BUGFIX: add updt_dstadsrc;
-- 2008-08-22 161 1.2 move slvnn_m subtypes to slvtypes;
-- move (and rename) intbus defs to iblib package;
-- move intbus devices to ibdlib package;
-- rename ubf_ --> ibf_;
-- 2008-05-09 144 1.1.17 use EI_ACK with _kw11l, _dl11
-- 2008-05-03 143 1.1.16 rename _cpursta->_cpurust
-- 2008-04-27 140 1.1.15 add c_cpursta_xxx defs; cpufail->cpursta in cp_stat
-- 2008-04-25 138 1.1.14 add BRESET port to _mmu, _vmbox, use in _irq
-- 2008-04-19 137 1.1.13 add _tmu,_sys70 entity, dm_stat_** types and ports
-- 2008-04-18 136 1.1.12 ibdr_sdreg: use RESET; ibdr_minisys: add RESET
-- 2008-03-02 121 1.1.11 remove snoopers; add waitsusp in cpustat_type
-- 2008-02-24 119 1.1.10 add lah,rps,wps commands, cp_addr_type.
-- _vmbox,_mmu interface changed
-- 2008-02-17 117 1.1.9 add em_(mreq|sres)_type, pdp11_cache, pdp11_bram
-- 2008-01-27 115 1.1.8 add pdp11_ubmap, pdp11_mem70
-- 2008-01-26 114 1.1.7 add c_rp_addr_ibr(b) defs (for ibr addresses)
-- 2008-01-20 113 1.1.6 _core_rri: use RRI_LAM; _minisys: RRI_LAM vector
-- 2008-01-20 112 1.1.5 added ibdr_minisys; _ibdr_rri
-- 2008-01-06 111 1.1.4 rename ibdr_kw11l->ibd_kw11l; add ibdr_(dl11|rk11)
-- mod pdp11_intmap;
-- 2008-01-05 110 1.1.3 delete _mmu_regfile; rename _mmu_regs->_mmu_sadr
-- rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- add ibdr_kw11l.
-- 2008-01-01 109 1.1.2 _vmbox w/ IB_SRES_(CPU|EXT); remove vm_regs_type
-- 2007-12-30 108 1.1.1 add ibdr_sdreg, ubf_byte[01]
-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now; remove DMA port
-- 2007-08-16 74 1.0.6 add AP_LAM interface to pdp11_core_rri
-- 2007-08-12 73 1.0.5 add c_rp_addr_xxx and c_rp_statf_xxx def's
-- 2007-08-10 72 1.0.4 added c_cp_func_xxx constant def's for commands
-- 2007-07-15 66 1.0.3 rename pdp11_top -> pdp11_core
-- 2007-07-02 63 1.0.2 reordered ports on pdp11_top (by function, not i/o)
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.rblib.all;
package pdp11 is
type psw_type is record -- processor status
cmode : slv2; -- current mode
pmode : slv2; -- previous mode
rset : slbit; -- register set
pri : slv3; -- processor priority
tflag : slbit; -- trace flag
cc : slv4; -- condition codes (NZVC).
end record psw_type;
constant psw_init : psw_type := (
"00","00", -- cmode, pmode (=kernel)
'0',"111",'0', -- rset, pri (=7), tflag
"0000" -- cc NZVC=0
);
constant c_psw_kmode : slv2 := "00"; -- processor mode: kernel
constant c_psw_smode : slv2 := "01"; -- processor mode: supervisor
constant c_psw_umode : slv2 := "11"; -- processor mode: user
subtype psw_ibf_cmode is integer range 15 downto 14;
subtype psw_ibf_pmode is integer range 13 downto 12;
constant psw_ibf_rset: integer := 11;
subtype psw_ibf_pri is integer range 7 downto 5;
constant psw_ibf_tflag: integer := 4;
subtype psw_ibf_cc is integer range 3 downto 0;
type sarsdr_type is record -- combined SAR/SDR MMU status
saf : slv16; -- segment address field
slf : slv7; -- segment length field
ed : slbit; -- expansion direction
acf : slv3; -- access control field
end record sarsdr_type;
constant sarsdr_init : sarsdr_type := (
(others=>'0'), -- saf
"0000000",'0',"000" -- slf, ed, acf
);
type dpath_cntl_type is record -- data path control
gpr_asrc : slv3; -- src register address
gpr_adst : slv3; -- dst register address
gpr_mode : slv2; -- psw mode for gpr access
gpr_rset : slbit; -- register set
gpr_we : slbit; -- gpr write enable
gpr_bytop : slbit; -- gpr high byte enable
gpr_pcinc : slbit; -- pc increment enable
psr_ccwe : slbit; -- enable update cc
psr_we: slbit; -- write enable psw (from DIN)
psr_func : slv3; -- write function psw (from DIN)
dsrc_sel : slbit; -- src data register source select
dsrc_we : slbit; -- src data register write enable
ddst_sel : slbit; -- dst data register source select
ddst_we : slbit; -- dst data register write enable
dtmp_sel : slv2; -- tmp data register source select
dtmp_we : slbit; -- tmp data register write enable
ounit_asel : slv2; -- ounit a port selector
ounit_azero : slbit; -- ounit a port force zero
ounit_const : slv9; -- ounit b port const
ounit_bsel : slv2; -- ounit b port selector
ounit_opsub : slbit; -- ounit operation
aunit_srcmod : slv2; -- aunit src port modifier
aunit_dstmod : slv2; -- aunit dst port modifier
aunit_cimod : slv2; -- aunit ci port modifier
aunit_cc1op : slbit; -- aunit use cc modes (1 op instruction)
aunit_ccmode : slv3; -- aunit cc port mode
aunit_bytop : slbit; -- aunit byte operation
lunit_func : slv4; -- lunit function
lunit_bytop : slbit; -- lunit byte operation
munit_func : slv2; -- munit function
munit_s_div : slbit; -- munit s_opg_div state
munit_s_div_cn : slbit; -- munit s_opg_div_cn state
munit_s_div_cr : slbit; -- munit s_opg_div_cr state
munit_s_ash : slbit; -- munit s_opg_ash state
munit_s_ash_cn : slbit; -- munit s_opg_ash_cn state
munit_s_ashc : slbit; -- munit s_opg_ashc state
munit_s_ashc_cn : slbit; -- munit s_opg_ashc_cn state
ireg_we : slbit; -- ireg register write enable
cres_sel : slv3; -- result bus (cres) select
dres_sel : slv3; -- result bus (dres) select
vmaddr_sel : slv2; -- virtual address select
cpdout_we : slbit; -- capture dres for cpdout
end record dpath_cntl_type;
constant dpath_cntl_init : dpath_cntl_type := (
"000","000","00",'0','0','0','0', -- gpr
'0','0',"000", -- psr
'0','0','0','0',"00",'0', -- dsrc,..,dtmp
"00",'0',"000000000","00",'0', -- ounit
"00","00","00",'0',"000",'0', -- aunit
"0000",'0', -- lunit
"00",'0','0','0','0','0','0','0', -- munit
'0',"000","000","00",'0' -- rest
);
constant c_dpath_dsrc_src : slbit := '0'; -- DSRC = R(SRC)
constant c_dpath_dsrc_res : slbit := '1'; -- DSRC = DRES
constant c_dpath_ddst_dst : slbit := '0'; -- DDST = R(DST)
constant c_dpath_ddst_res : slbit := '1'; -- DDST = DRES
constant c_dpath_dtmp_dsrc : slv2 := "00"; -- DTMP = DSRC
constant c_dpath_dtmp_psw : slv2 := "01"; -- DTMP = PSW
constant c_dpath_dtmp_dres : slv2 := "10"; -- DTMP = DRES
constant c_dpath_dtmp_drese : slv2 := "11"; -- DTMP = DRESE
constant c_dpath_res_ounit : slv3 := "000"; -- D/CRES = OUNIT
constant c_dpath_res_aunit : slv3 := "001"; -- D/CRES = AUNIT
constant c_dpath_res_lunit : slv3 := "010"; -- D/CRES = LUNIT
constant c_dpath_res_munit : slv3 := "011"; -- D/CRES = MUNIT
constant c_dpath_res_vmdout : slv3 := "100"; -- D/CRES = VMDOUT
constant c_dpath_res_fpdout : slv3 := "101"; -- D/CRES = FPDOUT
constant c_dpath_res_ireg : slv3 := "110"; -- D/CRES = IREG
constant c_dpath_res_cpdin : slv3 := "111"; -- D/CRES = CPDIN
constant c_dpath_vmaddr_dsrc : slv2 := "00"; -- VMADDR = DSRC
constant c_dpath_vmaddr_ddst : slv2 := "01"; -- VMADDR = DDST
constant c_dpath_vmaddr_pc : slv2 := "10"; -- VMADDR = PC
constant c_dpath_vmaddr_dtmp : slv2 := "11"; -- VMADDR = DTMP
type dpath_stat_type is record -- data path status
ccout_z : slbit; -- current effective Z cc flag
shc_tc : slbit; -- last shc cycle (shc==0)
div_cr : slbit; -- division: reminder correction needed
div_cq : slbit; -- division: quotient correction needed
div_zero : slbit; -- division: divident or divisor zero
div_ovfl : slbit; -- division: overflow
end record dpath_stat_type;
constant dpath_stat_init : dpath_stat_type := (others=>'0');
type decode_stat_type is record -- decode status
is_dstmode0 : slbit; -- dest. is register mode
is_srcpc : slbit; -- source is pc
is_srcpcmode1 : slbit; -- source is pc and mode=1
is_dstpc : slbit; -- dest. is pc
is_dstw_reg : slbit; -- dest. register to be written
is_dstw_pc : slbit; -- pc register to be written
is_rmwop : slbit; -- read-modify-write operation
is_bytop : slbit; -- byte operation
is_res : slbit; -- reserved operation code
op_rtt : slbit; -- RTT instruction
op_mov : slbit; -- MOV instruction
trap_vec : slv3; -- trap vector addr bits 4:2
force_srcsp : slbit; -- force src register to be sp
updt_dstadsrc : slbit; -- update dsrc in dsta flow
aunit_srcmod : slv2; -- aunit src port modifier
aunit_dstmod : slv2; -- aunit dst port modifier
aunit_cimod : slv2; -- aunit ci port modifier
aunit_cc1op : slbit; -- aunit use cc modes (1 op instruction)
aunit_ccmode : slv3; -- aunit cc port mode
lunit_func : slv4; -- lunit function
munit_func : slv2; -- munit function
res_sel : slv3; -- result bus (cres/dres) select
fork_op : slv4; -- op fork after idecode state
fork_srcr : slv2; -- src-read fork after idecode state
fork_dstr : slv2; -- dst-read fork after src read state
fork_dsta : slv2; -- dst-addr fork after idecode state
fork_opg : slv4; -- opg fork
fork_opa : slv3; -- opa fork
do_fork_op : slbit; -- execute fork_op
do_fork_srcr : slbit; -- execute fork_srcr
do_fork_dstr : slbit; -- execute fork_dstr
do_fork_dsta : slbit; -- execute fork_dsta
do_fork_opg : slbit; -- execute fork_opg
do_pref_dec : slbit; -- can do prefetch at decode phase
end record decode_stat_type;
constant decode_stat_init : decode_stat_type := (
'0','0','0','0','0','0','0','0','0', -- is_
'0','0',"000",'0','0', -- op_, trap_, force_, updt_
"00","00","00",'0',"000", -- aunit_
"0000","00","000", -- lunit_, munit_, res_
"0000","00","00","00","0000","000", -- fork_
'0','0','0','0','0', -- do_fork_
'0' -- do_pref_
);
constant c_fork_op_halt : slv4 := "0000";
constant c_fork_op_wait : slv4 := "0001";
constant c_fork_op_rtti : slv4 := "0010";
constant c_fork_op_trap : slv4 := "0011";
constant c_fork_op_reset: slv4 := "0100";
constant c_fork_op_rts : slv4 := "0101";
constant c_fork_op_spl : slv4 := "0110";
constant c_fork_op_mcc : slv4 := "0111";
constant c_fork_op_br : slv4 := "1000";
constant c_fork_op_mark : slv4 := "1001";
constant c_fork_op_sob : slv4 := "1010";
constant c_fork_op_mtp : slv4 := "1011";
constant c_fork_srcr_def : slv2:= "00";
constant c_fork_srcr_inc : slv2:= "01";
constant c_fork_srcr_dec : slv2:= "10";
constant c_fork_srcr_ind : slv2:= "11";
constant c_fork_dstr_def : slv2:= "00";
constant c_fork_dstr_inc : slv2:= "01";
constant c_fork_dstr_dec : slv2:= "10";
constant c_fork_dstr_ind : slv2:= "11";
constant c_fork_dsta_def : slv2:= "00";
constant c_fork_dsta_inc : slv2:= "01";
constant c_fork_dsta_dec : slv2:= "10";
constant c_fork_dsta_ind : slv2:= "11";
constant c_fork_opg_gen : slv4 := "0000";
constant c_fork_opg_wdef : slv4 := "0001";
constant c_fork_opg_winc : slv4 := "0010";
constant c_fork_opg_wdec : slv4 := "0011";
constant c_fork_opg_wind : slv4 := "0100";
constant c_fork_opg_mul : slv4 := "0101";
constant c_fork_opg_div : slv4 := "0110";
constant c_fork_opg_ash : slv4 := "0111";
constant c_fork_opg_ashc : slv4 := "1000";
constant c_fork_opa_jsr : slv3 := "000";
constant c_fork_opa_jmp : slv3 := "001";
constant c_fork_opa_mtp : slv3 := "010";
constant c_fork_opa_mfp_reg : slv3 := "011";
constant c_fork_opa_mfp_mem : slv3 := "100";
-- Note: MSB=0 are 'normal' states, MSB=1 are fatal errors
constant c_cpurust_init : slv4 := "0000"; -- cpu in init state
constant c_cpurust_halt : slv4 := "0001"; -- cpu executed HALT
constant c_cpurust_reset : slv4 := "0010"; -- cpu was reset
constant c_cpurust_stop : slv4 := "0011"; -- cpu was stopped
constant c_cpurust_step : slv4 := "0100"; -- cpu was stepped
constant c_cpurust_susp : slv4 := "0101"; -- cpu was suspended
constant c_cpurust_runs : slv4 := "0111"; -- cpu running
constant c_cpurust_vecfet : slv4 := "1000"; -- vector fetch error halt
constant c_cpurust_recrsv : slv4 := "1001"; -- recursive red-stack halt
constant c_cpurust_sfail : slv4 := "1100"; -- sequencer failure
constant c_cpurust_vfail : slv4 := "1101"; -- vmbox failure
type cpustat_type is record -- CPU status
cmdbusy : slbit; -- command busy
cmdack : slbit; -- command acknowledge
cmderr : slbit; -- command error
cmdmerr : slbit; -- command memory access error
cpugo : slbit; -- CPU go state
cpustep : slbit; -- CPU step flag
cpuhalt : slbit; -- CPU halt flag
cpuwait : slbit; -- CPU wait flag
cpurust : slv4; -- CPU run status
cpfunc : slv5; -- current control port function
cprnum : slv3; -- current control port register number
waitsusp : slbit; -- WAIT instruction suspended
intvect : slv9_2; -- current interrupt vector
trap_mmu : slbit; -- mmu trace trap pending
trap_ysv : slbit; -- ysv trap pending
prefdone : slbit; -- prefetch done
do_gprwe : slbit; -- pending gpr_we
do_intrsv : slbit; -- active rsv interrupt sequence
end record cpustat_type;
constant cpustat_init : cpustat_type := (
'0','0','0','0', -- cmd..
'0','0','0','0', -- cpu..
c_cpurust_init, -- cpurust
"00000","000", -- cpfunc, cprnum
'0', -- waitsusp
(others=>'0'), -- intvect
'0','0','0', -- trap_(mmu|ysv), prefdone
'0','0' -- do_gprwe, do_intrsv
);
type cpuerr_type is record -- CPU error register
illhlt : slbit; -- illegal halt (in non-kernel mode)
adderr : slbit; -- address error (odd, jmp/jsr reg)
nxm : slbit; -- non-existent memory
iobto : slbit; -- I/O bus timeout (non-exist UB)
ysv : slbit; -- yellow stack violation
rsv : slbit; -- red stack violation
end record cpuerr_type;
constant cpuerr_init : cpuerr_type := (others=>'0');
type vm_cntl_type is record -- virt memory control port
req : slbit; -- request
wacc : slbit; -- write access
macc : slbit; -- modify access (r-m-w sequence)
cacc : slbit; -- console access
bytop : slbit; -- byte operation
dspace : slbit; -- dspace operation
kstack : slbit; -- access through kernel stack
intrsv : slbit; -- active rsv interrupt sequence
mode : slv2; -- mode
trap_done : slbit; -- mmu trap taken (to set ssr0 bit)
end record vm_cntl_type;
constant vm_cntl_init : vm_cntl_type := (
'0','0','0','0', -- req, wacc, macc,cacc
'0','0','0', -- bytop, dspace, kstack
'0',"00",'0' -- intrsv, mode, trap_done
);
type vm_stat_type is record -- virt memory status port
ack : slbit; -- acknowledge
err : slbit; -- error (see err_xxx for reason)
fail : slbit; -- failure (machine check)
err_odd : slbit; -- abort: odd address error
err_mmu : slbit; -- abort: mmu reject
err_nxm : slbit; -- abort: non-existing memory
err_iobto : slbit; -- abort: non-existing I/O resource
err_rsv : slbit; -- abort: red stack violation
trap_ysv : slbit; -- trap: yellow stack violation
trap_mmu : slbit; -- trap: mmu trace trap
end record vm_stat_type;
constant vm_stat_init : vm_stat_type := (others=>'0');
type em_mreq_type is record -- external memory - master request
req : slbit; -- request
we : slbit; -- write enable
be : slv2; -- byte enables
cancel : slbit; -- cancel request
addr : slv22_1; -- address
din : slv16; -- data in (input to memory)
end record em_mreq_type;
constant em_mreq_init : em_mreq_type := (
'0','0',"00",'0', -- req, we, be, cancel
(others=>'0'),(others=>'0') -- addr, din
);
type em_sres_type is record -- external memory - slave response
ack_r : slbit; -- acknowledge read
ack_w : slbit; -- acknowledge write
dout : slv16; -- data out (output from memory)
end record em_sres_type;
constant em_sres_init : em_sres_type := (
'0','0', -- ack_r, ack_w
(others=>'0') -- dout
);
type mmu_cntl_type is record -- mmu control port
req : slbit; -- translate request
wacc : slbit; -- write access
macc : slbit; -- modify access (r-m-w sequence)
cacc : slbit; -- console access (bypass mmu)
dspace : slbit; -- dspace access
mode : slv2; -- processor mode
trap_done : slbit; -- mmu trap taken (set ssr0 bit)
end record mmu_cntl_type;
constant mmu_cntl_init : mmu_cntl_type := (
'0','0','0','0', -- req, wacc, macc, cacc
'0',"00",'0' -- dspace, mode, trap_done
);
type mmu_stat_type is record -- mmu status port
vaok : slbit; -- virtual address valid
trap : slbit; -- mmu trap request
ena_mmu : slbit; -- mmu enable (ssr0 bit 0)
ena_22bit : slbit; -- mmu in 22 bit mode (ssr3 bit 4)
ena_ubmap : slbit; -- ubmap enable (ssr3 bit 5)
end record mmu_stat_type;
constant mmu_stat_init : mmu_stat_type := (others=>'0');
type mmu_moni_type is record -- mmu monitor port
istart : slbit; -- instruction start
idone : slbit; -- instruction done
pc : slv16; -- PC of new instruction
regmod : slbit; -- register modified
regnum : slv3; -- register number
delta : slv4; -- register offset
isdec : slbit; -- offset to be subtracted
trace_prev : slbit; -- use ssr12 trace state of prev. state
end record mmu_moni_type;
constant mmu_moni_init : mmu_moni_type := (
'0','0',(others=>'0'), -- istart, idone, pc
'0',"000","0000", -- regmod, regnum, delta
'0','0' -- isdec, trace_prev
);
type mmu_ssr0_type is record -- MMU ssr0
abo_nonres : slbit; -- abort non resident
abo_length : slbit; -- abort segment length
abo_rdonly : slbit; -- abort read-only
trap_mmu : slbit; -- trap management
ena_trap : slbit; -- enable traps
inst_compl : slbit; -- instruction complete
seg_mode : slv2; -- segement mode
dspace : slbit; -- address space (D=1, I=0)
seg_num : slv3; -- segment number
ena_mmu : slbit; -- enable memory management
trace_prev : slbit; -- ssr12 trace status in prev. state
end record mmu_ssr0_type;
constant mmu_ssr0_init : mmu_ssr0_type := (
inst_compl=>'0', seg_mode=>"00", seg_num=>"000",
others=>'0'
);
type mmu_ssr1_type is record -- MMU ssr1
rb_delta : slv5; -- RB: amount change
rb_num : slv3; -- RB: register number
ra_delta : slv5; -- RA: amount change
ra_num : slv3; -- RA: register number
end record mmu_ssr1_type;
constant mmu_ssr1_init : mmu_ssr1_type := (
"00000","000", -- rb_...
"00000","000" -- ra_...
);
type mmu_ssr3_type is record -- MMU ssr3
ena_ubmap : slbit; -- enable unibus mapping
ena_22bit : slbit; -- enable 22 bit mapping
dspace_km : slbit; -- enable dspace kernel
dspace_sm : slbit; -- enable dspace supervisor
dspace_um : slbit; -- enable dspace user
end record mmu_ssr3_type;
constant mmu_ssr3_init : mmu_ssr3_type := (others=>'0');
-- control port definitions --------------------------------------------------
type cp_cntl_type is record -- control port control
req : slbit; -- request
func : slv5; -- function
rnum : slv3; -- register number
end record cp_cntl_type;
constant c_cpfunc_noop : slv5 := "00000"; -- noop : no operation
constant c_cpfunc_sta : slv5 := "00001"; -- sta : cpu start
constant c_cpfunc_sto : slv5 := "00010"; -- sto : cpu stop
constant c_cpfunc_cont : slv5 := "00011"; -- cont : cpu continue
constant c_cpfunc_step : slv5 := "00100"; -- step : cpu step
constant c_cpfunc_rst : slv5 := "01111"; -- rst : cpu reset (soft)
constant c_cpfunc_rreg : slv5 := "10000"; -- rreg : read register
constant c_cpfunc_wreg : slv5 := "10001"; -- wreg : write register
constant c_cpfunc_rpsw : slv5 := "10010"; -- rpsw : read psw
constant c_cpfunc_wpsw : slv5 := "10011"; -- wpsw : write psw
constant c_cpfunc_rmem : slv5 := "10100"; -- rmem : read memory
constant c_cpfunc_wmem : slv5 := "10101"; -- wmem : write memory
constant cp_cntl_init : cp_cntl_type := ('0',c_cpfunc_noop,"000");
type cp_stat_type is record -- control port status
cmdbusy : slbit; -- command busy
cmdack : slbit; -- command acknowledge
cmderr : slbit; -- command error
cmdmerr : slbit; -- command memory access error
cpugo : slbit; -- CPU go state
cpustep : slbit; -- CPU step flag
cpuhalt : slbit; -- CPU halt flag
cpuwait : slbit; -- CPU wait flag
cpurust : slv4; -- CPU run status
end record cp_stat_type;
constant cp_stat_init : cp_stat_type := (
'0','0','0','0', -- cmd...
'0','0','0','0', -- cpu...
(others=>'0') -- cpurust
);
type cp_addr_type is record -- control port address
addr : slv22_1; -- address
racc : slbit; -- ibr access
be : slv2; -- byte enables
ena_22bit : slbit; -- enable 22 bit mode
ena_ubmap : slbit; -- enable unibus mapper
end record cp_addr_type;
constant cp_addr_init : cp_addr_type := (
(others=>'0'), -- addr
'0',"00", -- racc, be
'0','0' -- ena_...
);
-- debug and monitoring port definitions -------------------------------------
type dm_cntl_type is record -- debug and monitor control
dum1 : slbit; -- dummy 1
dum2 : slbit; -- dummy 2
end record dm_cntl_type;
constant dm_cntl_init : dm_cntl_type := (others=>'0');
type dm_stat_dp_type is record -- debug and monitor status - dpath
pc : slv16; -- pc
psw : psw_type; -- psw
ireg : slv16; -- ireg
ireg_we : slbit; -- ireg we
dsrc : slv16; -- dsrc register
ddst : slv16; -- ddst register
dtmp : slv16; -- dtmp register
dres : slv16; -- dres bus
gpr_adst : slv3; -- gpr dst regsiter
gpr_mode : slv2; -- gpr mode
gpr_bytop : slbit; -- gpr bytop
gpr_we : slbit; -- gpr we
end record dm_stat_dp_type;
constant dm_stat_dp_init : dm_stat_dp_type := (
(others=>'0'), -- pc
psw_init, -- psw
(others=>'0'),'0', -- ireg, ireg_we
(others=>'0'),(others=>'0'), -- dsrc, ddst
(others=>'0'),(others=>'0'), -- dtmp, dres
(others=>'0'),(others=>'0'), -- gpr_adst, gpr_mode
'0','0' -- gpr_bytop, gpr_we
);
type dm_stat_vm_type is record -- debug and monitor status - vmbox
ibmreq : ib_mreq_type; -- ibus master request
ibsres : ib_sres_type; -- ibus slave response
end record dm_stat_vm_type;
constant dm_stat_vm_init : dm_stat_vm_type := (ib_mreq_init,ib_sres_init);
type dm_stat_co_type is record -- debug and monitor status - core
cpugo : slbit; -- cpugo state flag
cpuhalt : slbit; -- cpuhalt state flag
end record dm_stat_co_type;
constant dm_stat_co_init : dm_stat_co_type := ('0','0');
type dm_stat_sy_type is record -- debug and monitor status - system
emmreq : em_mreq_type; -- external memory: request
emsres : em_sres_type; -- external memory: response
chit : slbit; -- cache hit
end record dm_stat_sy_type;
constant dm_stat_sy_init : dm_stat_sy_type := (em_mreq_init,em_sres_init,'0');
-- rbus interface definitions ------------------------------------------------
constant c_rbaddr_conf : slv5 := "00000"; -- R/W configuration reg
constant c_rbaddr_cntl : slv5 := "00001"; -- -/F control reg
constant c_rbaddr_stat : slv5 := "00010"; -- R/- status reg
constant c_rbaddr_psw : slv5 := "00011"; -- R/W psw access
constant c_rbaddr_al : slv5 := "00100"; -- R/W address low reg
constant c_rbaddr_ah : slv5 := "00101"; -- R/W address high reg
constant c_rbaddr_mem : slv5 := "00110"; -- R/W memory access
constant c_rbaddr_memi : slv5 := "00111"; -- R/W memory access; inc addr
constant c_rbaddr_r0 : slv5 := "01000"; -- R/W gpr 0
constant c_rbaddr_r1 : slv5 := "01001"; -- R/W gpr 1
constant c_rbaddr_r2 : slv5 := "01010"; -- R/W gpr 2
constant c_rbaddr_r3 : slv5 := "01011"; -- R/W gpr 3
constant c_rbaddr_r4 : slv5 := "01100"; -- R/W gpr 4
constant c_rbaddr_r5 : slv5 := "01101"; -- R/W gpr 5
constant c_rbaddr_sp : slv5 := "01110"; -- R/W gpr 6 (sp)
constant c_rbaddr_pc : slv5 := "01111"; -- R/W gpr 7 (pc)
constant c_rbaddr_ibrb : slv5 := "10000"; -- R/W ibr base address
subtype c_al_rbf_addr is integer range 15 downto 1; -- al: address
constant c_ah_rbf_ena_ubmap: integer := 7; -- ah: ubmap
constant c_ah_rbf_ena_22bit: integer := 6; -- ah: 22bit
subtype c_ah_rbf_addr is integer range 5 downto 0; -- ah: address
constant c_stat_rbf_cmderr: integer := 0; -- stat field: cmderr
constant c_stat_rbf_cmdmerr: integer := 1; -- stat field: cmdmerr
constant c_stat_rbf_cpugo: integer := 2; -- stat field: cpugo
constant c_stat_rbf_cpuhalt: integer := 3; -- stat field: cpuhalt
subtype c_stat_rbf_cpurust is integer range 7 downto 4; -- cpurust
subtype c_ibrb_ibf_base is integer range 12 downto 6; -- ibrb: base addr
subtype c_ibrb_ibf_be is integer range 1 downto 0; -- ibrb: be's
-- -------------------------------------
component pdp11_gpr is -- general purpose registers
port (
CLK : in slbit; -- clock
DIN : in slv16; -- input data
ASRC : in slv3; -- source register number
ADST : in slv3; -- destination register number
MODE : in slv2; -- processor mode (k=>00,s=>01,u=>11)
RSET : in slbit; -- register set
WE : in slbit; -- write enable
BYTOP : in slbit; -- byte operation (write low byte only)
PCINC : in slbit; -- increment PC
DSRC : out slv16; -- source register data
DDST : out slv16; -- destination register data
PC : out slv16 -- current PC value
);
end component;
constant c_gpr_r5 : slv3 := "101"; -- register number of r5
constant c_gpr_sp : slv3 := "110"; -- register number of SP
constant c_gpr_pc : slv3 := "111"; -- register number of PC
component pdp11_psr is -- processor status word register
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- console reset
DIN : in slv16; -- input data
CCIN : in slv4; -- cc input
CCWE : in slbit; -- enable update cc
WE : in slbit; -- write enable (from DIN)
FUNC : in slv3; -- write function (from DIN)
PSW : out psw_type; -- current psw
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
constant c_psr_func_wspl : slv3 := "000"; -- SPL mode: set pri
constant c_psr_func_wcc : slv3 := "001"; -- CC mode: set/clear cc
constant c_psr_func_wint : slv3 := "010"; -- interupt mode: pmode=cmode
constant c_psr_func_wrti : slv3 := "011"; -- rti mode: protect modes
constant c_psr_func_wall : slv3 := "100"; -- write all fields
component pdp11_ounit is -- offset adder for addresses (ounit)
port (
DSRC : in slv16; -- 'src' data for port A
DDST : in slv16; -- 'dst' data for port A
DTMP : in slv16; -- 'tmp' data for port A
PC : in slv16; -- PC data for port A
ASEL : in slv2; -- selector for port A
AZERO : in slbit; -- force zero for port A
IREG8 : in slv8; -- 'ireg' data for port B
VMDOUT : in slv16; -- virt. memory data for port B
CONST : in slv9; -- sequencer const data for port B
BSEL : in slv2; -- selector for port B
OPSUB : in slbit; -- operation: 0 add, 1 sub
DOUT : out slv16; -- data output
NZOUT : out slv2 -- NZ condition codes out
);
end component;
constant c_ounit_asel_ddst : slv2 := "00"; -- A = DDST
constant c_ounit_asel_dsrc : slv2 := "01"; -- A = DSRC
constant c_ounit_asel_pc : slv2 := "10"; -- A = PC
constant c_ounit_asel_dtmp : slv2 := "11"; -- A = DTMP
constant c_ounit_bsel_const : slv2 := "00"; -- B = CONST
constant c_ounit_bsel_vmdout : slv2 := "01"; -- B = VMDOUT
constant c_ounit_bsel_ireg6 : slv2 := "10"; -- B = 2*IREG(6bit)
constant c_ounit_bsel_ireg8 : slv2 := "11"; -- B = 2*IREG(8bit,sign-extend)
component pdp11_aunit is -- arithmetic unit for data (aunit)
port (
DSRC : in slv16; -- 'src' data in
DDST : in slv16; -- 'dst' data in
CI : in slbit; -- carry flag in
SRCMOD : in slv2; -- src modifier mode
DSTMOD : in slv2; -- dst modifier mode
CIMOD : in slv2; -- ci modifier mode
CC1OP : in slbit; -- use cc modes (1 op instruction)
CCMODE : in slv3; -- cc mode
BYTOP : in slbit; -- byte operation
DOUT : out slv16; -- data output
CCOUT : out slv4 -- condition codes out
);
end component;
constant c_aunit_mod_pass : slv2 := "00"; -- pass data
constant c_aunit_mod_inv : slv2 := "01"; -- invert data
constant c_aunit_mod_zero : slv2 := "10"; -- set to 0
constant c_aunit_mod_one : slv2 := "11"; -- set to 1
-- the c_aunit_ccmode codes follow exactly the opcode format (bit 8:6)
constant c_aunit_ccmode_clr : slv3 := "000"; -- do clr instruction
constant c_aunit_ccmode_com : slv3 := "001"; -- do com instruction
constant c_aunit_ccmode_inc : slv3 := "010"; -- do inc instruction
constant c_aunit_ccmode_dec : slv3 := "011"; -- do dec instruction
constant c_aunit_ccmode_neg : slv3 := "100"; -- do neg instruction
constant c_aunit_ccmode_adc : slv3 := "101"; -- do adc instruction
constant c_aunit_ccmode_sbc : slv3 := "110"; -- do sbc instruction
constant c_aunit_ccmode_tst : slv3 := "111"; -- do tst instruction
component pdp11_lunit is -- logic unit for data (lunit)
port (
DSRC : in slv16; -- 'src' data in
DDST : in slv16; -- 'dst' data in
CCIN : in slv4; -- condition codes in
FUNC : in slv4; -- function
BYTOP : in slbit; -- byte operation
DOUT : out slv16; -- data output
CCOUT : out slv4 -- condition codes out
);
end component;
constant c_lunit_func_asr : slv4 := "0000"; -- ASR/ASRB ??? recheck coding !!
constant c_lunit_func_asl : slv4 := "0001"; -- ASL/ASLB
constant c_lunit_func_ror : slv4 := "0010"; -- ROR/RORB
constant c_lunit_func_rol : slv4 := "0011"; -- ROL/ROLB
constant c_lunit_func_bis : slv4 := "0100"; -- BIS/BISB
constant c_lunit_func_bic : slv4 := "0101"; -- BIC/BICB
constant c_lunit_func_bit : slv4 := "0110"; -- BIT/BITB
constant c_lunit_func_mov : slv4 := "0111"; -- MOV/MOVB
constant c_lunit_func_sxt : slv4 := "1000"; -- SXT
constant c_lunit_func_swap : slv4 := "1001"; -- SWAB
constant c_lunit_func_xor : slv4 := "1010"; -- XOR
component pdp11_munit is -- mul/div unit for data (munit)
port (
CLK : in slbit; -- clock
DSRC : in slv16; -- 'src' data in
DDST : in slv16; -- 'dst' data in
DTMP : in slv16; -- 'tmp' data in
GPR_DSRC : in slv16; -- 'src' data from GPR
FUNC : in slv2; -- function
S_DIV : in slbit; -- s_opg_div state
S_DIV_CN : in slbit; -- s_opg_div_cn state
S_DIV_CR : in slbit; -- s_opg_div_cr state
S_ASH : in slbit; -- s_opg_ash state
S_ASH_CN : in slbit; -- s_opg_ash_cn state
S_ASHC : in slbit; -- s_opg_ashc state
S_ASHC_CN : in slbit; -- s_opg_ashc_cn state
SHC_TC : out slbit; -- last shc cycle (shc==0)
DIV_CR : out slbit; -- division: reminder correction needed
DIV_CQ : out slbit; -- division: quotient correction needed
DIV_ZERO : out slbit; -- division: divident or divisor zero
DIV_OVFL : out slbit; -- division: overflow
DOUT : out slv16; -- data output
DOUTE : out slv16; -- data output extra
CCOUT : out slv4 -- condition codes out
);
end component;
constant c_munit_func_mul : slv2 := "00"; -- MUL
constant c_munit_func_div : slv2 := "01"; -- DIV
constant c_munit_func_ash : slv2 := "10"; -- ASH
constant c_munit_func_ashc : slv2 := "11"; -- ASHC
component pdp11_mmu_sadr is -- mmu SAR/SDR register set
port (
CLK : in slbit; -- clock
MODE : in slv2; -- mode
ASN : in slv4; -- augmented segment number (1+3 bit)
AIB_WE : in slbit; -- update AIB
AIB_SETA : in slbit; -- set access AIB
AIB_SETW : in slbit; -- set write AIB
SARSDR : out sarsdr_type; -- combined SAR/SDR
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_mmu_ssr12 is -- mmu register ssr1 and ssr2
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- console reset
TRACE : in slbit; -- trace enable
MONI : in mmu_moni_type; -- MMU monitor port data
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_mmu is -- mmu - memory management unit
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- console reset
BRESET : in slbit; -- ibus reset
CNTL : in mmu_cntl_type; -- control port
VADDR : in slv16; -- virtual address
MONI : in mmu_moni_type; -- monitor port
STAT : out mmu_stat_type; -- status port
PADDRH : out slv16; -- physical address (upper 16 bit)
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_vmbox is -- virtual memory
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- global reset
CRESET : in slbit; -- console reset
BRESET : in slbit; -- ibus reset
CP_ADDR : in cp_addr_type; -- console port address
VM_CNTL : in vm_cntl_type; -- vm control port
VM_ADDR : in slv16; -- vm address
VM_DIN : in slv16; -- vm data in
VM_STAT : out vm_stat_type; -- vm status port
VM_DOUT : out slv16; -- vm data out
EM_MREQ : out em_mreq_type; -- external memory: request
EM_SRES : in em_sres_type; -- external memory: response
MMU_MONI : in mmu_moni_type; -- mmu monitor port
IB_MREQ_M : out ib_mreq_type; -- ibus request (master)
IB_SRES_CPU : in ib_sres_type; -- ibus response (CPU registers)
IB_SRES_EXT : in ib_sres_type; -- ibus response (external devices)
DM_STAT_VM : out dm_stat_vm_type -- debug and monitor status
);
end component;
component pdp11_dpath is -- CPU datapath
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- console reset
CNTL : in dpath_cntl_type; -- control interface
STAT : out dpath_stat_type; -- status interface
CP_DIN : in slv16; -- console port data in
CP_DOUT : out slv16; -- console port data out
PSWOUT : out psw_type; -- current psw
PCOUT : out slv16; -- current pc
IREG : out slv16; -- ireg out
VM_ADDR : out slv16; -- virt. memory address
VM_DOUT : in slv16; -- virt. memory data out
VM_DIN : out slv16; -- virt. memory data in
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
DM_STAT_DP : out dm_stat_dp_type -- debug and monitor status
);
end component;
component pdp11_decode is -- instruction decoder
port (
IREG : in slv16; -- input instruction word
STAT : out decode_stat_type -- status output
);
end component;
component pdp11_sequencer is -- cpu sequencer
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- global reset
PSW : in psw_type; -- processor status
PC : in slv16; -- program counter
IREG : in slv16; -- IREG
ID_STAT : in decode_stat_type; -- instr. decoder status
DP_STAT : in dpath_stat_type; -- data path status
CP_CNTL : in cp_cntl_type; -- console port control
VM_STAT : in vm_stat_type; -- virtual memory status port
INT_PRI : in slv3; -- interrupt priority
INT_VECT : in slv9_2; -- interrupt vector
CRESET : out slbit; -- console reset
BRESET : out slbit; -- ibus reset
MMU_MONI : out mmu_moni_type; -- mmu monitor port
DP_CNTL : out dpath_cntl_type; -- data path control
VM_CNTL : out vm_cntl_type; -- virtual memory control port
CP_STAT : out cp_stat_type; -- console port status
INT_ACK : out slbit; -- interrupt acknowledge
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_irq is -- interrupt requester
port (
CLK : in slbit; -- clock
BRESET : in slbit; -- ibus reset
INT_ACK : in slbit; -- interrupt acknowledge from CPU
EI_PRI : in slv3; -- external interrupt priority
EI_VECT : in slv9_2; -- external interrupt vector
EI_ACKM : out slbit; -- external interrupt acknowledge
PRI : out slv3; -- interrupt priority
VECT : out slv9_2; -- interrupt vector
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_ubmap is -- 11/70 unibus mapper
port (
CLK : in slbit; -- clock
MREQ : in slbit; -- request mapping
ADDR_UB : in slv18_1; -- UNIBUS address (in)
ADDR_PM : out slv22_1; -- physical memory address (out)
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_sys70 is -- 11/70 memory system registers
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- console reset
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_mem70 is -- 11/70 memory system registers
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- console reset
HM_ENA : in slbit; -- hit/miss enable
HM_VAL : in slbit; -- hit/miss value
CACHE_FMISS : out slbit; -- cache force miss
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_cache is -- cache
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- global reset
EM_MREQ : in em_mreq_type; -- em request
EM_SRES : out em_sres_type; -- em response
FMISS : in slbit; -- force miss
CHIT : out slbit; -- cache hit flag
MEM_REQ : out slbit; -- memory: request
MEM_WE : out slbit; -- memory: write enable
MEM_BUSY : in slbit; -- memory: controller busy
MEM_ACK_R : in slbit; -- memory: acknowledge read
MEM_ADDR : out slv20; -- memory: address
MEM_BE : out slv4; -- memory: byte enable
MEM_DI : out slv32; -- memory: data in (memory view)
MEM_DO : in slv32 -- memory: data out (memory view)
);
end component;
component pdp11_core is -- full processor core
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CP_CNTL : in cp_cntl_type; -- console control port
CP_ADDR : in cp_addr_type; -- console address port
CP_DIN : in slv16; -- console data in
CP_STAT : out cp_stat_type; -- console status port
CP_DOUT : out slv16; -- console data out
EI_PRI : in slv3; -- external interrupt priority
EI_VECT : in slv9_2; -- external interrupt vector
EI_ACKM : out slbit; -- external interrupt acknowledge
EM_MREQ : out em_mreq_type; -- external memory: request
EM_SRES : in em_sres_type; -- external memory: response
BRESET : out slbit; -- ibus reset
IB_MREQ_M : out ib_mreq_type; -- ibus master request (master)
IB_SRES_M : in ib_sres_type; -- ibus slave response (master)
DM_STAT_DP : out dm_stat_dp_type; -- debug and monitor status - dpath
DM_STAT_VM : out dm_stat_vm_type; -- debug and monitor status - vmbox
DM_STAT_CO : out dm_stat_co_type -- debug and monitor status - core
);
end component;
component pdp11_tmu is -- trace and monitor unit
port (
CLK : in slbit; -- clock
ENA : in slbit := '0'; -- enable trace output
DM_STAT_DP : in dm_stat_dp_type; -- DM dpath
DM_STAT_VM : in dm_stat_vm_type; -- DM vmbox
DM_STAT_CO : in dm_stat_co_type; -- DM core
DM_STAT_SY : in dm_stat_sy_type -- DM system
);
end component;
component pdp11_tmu_sb is -- trace and mon. unit; simbus wrapper
generic (
ENAPIN : integer := 13); -- SB_CNTL signal to use for enable
port (
CLK : in slbit; -- clock
DM_STAT_DP : in dm_stat_dp_type; -- DM dpath
DM_STAT_VM : in dm_stat_vm_type; -- DM vmbox
DM_STAT_CO : in dm_stat_co_type; -- DM core
DM_STAT_SY : in dm_stat_sy_type -- DM system
);
end component;
component pdp11_du_drv is -- display unit low level driver
generic (
CDWIDTH : positive := 3); -- clock divider width
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- global reset
ROW0 : in slv22; -- led row 0 (22 leds, top)
ROW1 : in slv16; -- led row 1 (16 leds)
ROW2 : in slv16; -- led row 2 (16 leds)
ROW3 : in slv10; -- led row 3 (10 leds, bottom)
SWOPT : out slv8; -- option pattern from du
SWOPT_RDY : out slbit; -- marks update of swopt
DU_SCLK : out slbit; -- DU: sclk
DU_SS_N : out slbit; -- DU: ss_n
DU_MOSI : out slbit; -- DU: mosi (master out, slave in)
DU_MISO : in slbit -- DU: miso (master in, slave out)
);
end component;
component pdp11_bram is -- BRAM based ext. memory dummy
generic (
AWIDTH : positive := 14); -- address width
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- global reset
EM_MREQ : in em_mreq_type; -- em request
EM_SRES : out em_sres_type -- em response
);
end component;
component pdp11_core_rbus is -- core to rbus interface
generic (
RB_ADDR_CORE : slv8 := slv(to_unsigned(2#00000000#,8));
RB_ADDR_IBUS : slv8 := slv(to_unsigned(2#10000000#,8)));
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RB_STAT : out slv3; -- rbus: status flags
RB_LAM : out slbit; -- remote attention
CPU_RESET : out slbit; -- cpu master reset
CP_CNTL : out cp_cntl_type; -- console control port
CP_ADDR : out cp_addr_type; -- console address port
CP_DIN : out slv16; -- console data in
CP_STAT : in cp_stat_type; -- console status port
CP_DOUT : in slv16 -- console data out
);
end component;
-- ----- move later to pdp11_conf --------------------------------------------
constant conf_vect_pirq : integer := 8#240#;
constant conf_pri_pirq_1 : integer := 1;
constant conf_pri_pirq_2 : integer := 2;
constant conf_pri_pirq_3 : integer := 3;
constant conf_pri_pirq_4 : integer := 4;
constant conf_pri_pirq_5 : integer := 5;
constant conf_pri_pirq_6 : integer := 6;
constant conf_pri_pirq_7 : integer := 7;
end package pdp11;
|
-- $Id: pdp11.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: pdp11
-- Description: Definitions for pdp11 components
--
-- Dependencies: -
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.4.8 now numeric_std clean
-- 2010-12-30 351 1.4.7 rename pdp11_core_rri->pdp11_core_rbus; use rblib
-- 2010-10-23 335 1.4.6 rename RRI_LAM->RB_LAM;
-- 2010-10-16 332 1.4.5 renames of pdp11_du_drv port names
-- 2010-09-18 330 1.4.4 rename (adlm)box->(oalm)unit
-- 2010-06-20 308 1.4.3 add c_ibrb_ibf_ def's
-- 2010-06-20 307 1.4.2 rename cpacc to cacc in vm_cntl_type, mmu_cntl_type
-- 2010-06-18 306 1.4.1 add racc, be to cp_addr_type; rm pdp11_ibdr_rri
-- 2010-06-13 305 1.4 add rnum to cp_cntl_type, cprnum to cpustat_type;
-- reassign cp command codes and rename: c_cp_func_...
-- -> c_cpfunc_...; remove cpaddr_(lal|lah|inc) from
-- dpath_cntl_type; add cpdout_we to dpath_cntl_type;
-- reassign rbus adresses and rename: c_rb_addr_...
-- -> c_rbaddr_...; rename rbus fields: c_rb_statf_...
-- -> c_stat_rbf_...
-- 2010-06-12 304 1.3.3 add cpuwait to cp_stat_type and cpustat_type
-- 2010-06-11 303 1.3.2 use IB_MREQ.racc instead of RRI_REQ
-- 2010-05-02 287 1.3.1 rename RP_STAT->RB_STAT
-- 2010-05-01 285 1.3 port to rri V2 interface; drop pdp11_rri_2rp;
-- rename c_rp_addr_* -> c_rb_addr_*
-- 2010-03-21 270 1.2.6 add pdp11_du_drv
-- 2009-05-30 220 1.2.5 final removal of snoopers (were already commented)
-- 2009-05-10 214 1.2.4 add ENA (trace enable) for _tmu; add _pdp11_tmu_sb
-- 2009-05-09 213 1.2.3 BUGFIX: default for inst_compl now '0'
-- 2008-12-14 177 1.2.2 add gpr_* fields to DM_STAT_DP
-- 2008-11-30 174 1.2.1 BUGFIX: add updt_dstadsrc;
-- 2008-08-22 161 1.2 move slvnn_m subtypes to slvtypes;
-- move (and rename) intbus defs to iblib package;
-- move intbus devices to ibdlib package;
-- rename ubf_ --> ibf_;
-- 2008-05-09 144 1.1.17 use EI_ACK with _kw11l, _dl11
-- 2008-05-03 143 1.1.16 rename _cpursta->_cpurust
-- 2008-04-27 140 1.1.15 add c_cpursta_xxx defs; cpufail->cpursta in cp_stat
-- 2008-04-25 138 1.1.14 add BRESET port to _mmu, _vmbox, use in _irq
-- 2008-04-19 137 1.1.13 add _tmu,_sys70 entity, dm_stat_** types and ports
-- 2008-04-18 136 1.1.12 ibdr_sdreg: use RESET; ibdr_minisys: add RESET
-- 2008-03-02 121 1.1.11 remove snoopers; add waitsusp in cpustat_type
-- 2008-02-24 119 1.1.10 add lah,rps,wps commands, cp_addr_type.
-- _vmbox,_mmu interface changed
-- 2008-02-17 117 1.1.9 add em_(mreq|sres)_type, pdp11_cache, pdp11_bram
-- 2008-01-27 115 1.1.8 add pdp11_ubmap, pdp11_mem70
-- 2008-01-26 114 1.1.7 add c_rp_addr_ibr(b) defs (for ibr addresses)
-- 2008-01-20 113 1.1.6 _core_rri: use RRI_LAM; _minisys: RRI_LAM vector
-- 2008-01-20 112 1.1.5 added ibdr_minisys; _ibdr_rri
-- 2008-01-06 111 1.1.4 rename ibdr_kw11l->ibd_kw11l; add ibdr_(dl11|rk11)
-- mod pdp11_intmap;
-- 2008-01-05 110 1.1.3 delete _mmu_regfile; rename _mmu_regs->_mmu_sadr
-- rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- add ibdr_kw11l.
-- 2008-01-01 109 1.1.2 _vmbox w/ IB_SRES_(CPU|EXT); remove vm_regs_type
-- 2007-12-30 108 1.1.1 add ibdr_sdreg, ubf_byte[01]
-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now; remove DMA port
-- 2007-08-16 74 1.0.6 add AP_LAM interface to pdp11_core_rri
-- 2007-08-12 73 1.0.5 add c_rp_addr_xxx and c_rp_statf_xxx def's
-- 2007-08-10 72 1.0.4 added c_cp_func_xxx constant def's for commands
-- 2007-07-15 66 1.0.3 rename pdp11_top -> pdp11_core
-- 2007-07-02 63 1.0.2 reordered ports on pdp11_top (by function, not i/o)
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.rblib.all;
package pdp11 is
type psw_type is record -- processor status
cmode : slv2; -- current mode
pmode : slv2; -- previous mode
rset : slbit; -- register set
pri : slv3; -- processor priority
tflag : slbit; -- trace flag
cc : slv4; -- condition codes (NZVC).
end record psw_type;
constant psw_init : psw_type := (
"00","00", -- cmode, pmode (=kernel)
'0',"111",'0', -- rset, pri (=7), tflag
"0000" -- cc NZVC=0
);
constant c_psw_kmode : slv2 := "00"; -- processor mode: kernel
constant c_psw_smode : slv2 := "01"; -- processor mode: supervisor
constant c_psw_umode : slv2 := "11"; -- processor mode: user
subtype psw_ibf_cmode is integer range 15 downto 14;
subtype psw_ibf_pmode is integer range 13 downto 12;
constant psw_ibf_rset: integer := 11;
subtype psw_ibf_pri is integer range 7 downto 5;
constant psw_ibf_tflag: integer := 4;
subtype psw_ibf_cc is integer range 3 downto 0;
type sarsdr_type is record -- combined SAR/SDR MMU status
saf : slv16; -- segment address field
slf : slv7; -- segment length field
ed : slbit; -- expansion direction
acf : slv3; -- access control field
end record sarsdr_type;
constant sarsdr_init : sarsdr_type := (
(others=>'0'), -- saf
"0000000",'0',"000" -- slf, ed, acf
);
type dpath_cntl_type is record -- data path control
gpr_asrc : slv3; -- src register address
gpr_adst : slv3; -- dst register address
gpr_mode : slv2; -- psw mode for gpr access
gpr_rset : slbit; -- register set
gpr_we : slbit; -- gpr write enable
gpr_bytop : slbit; -- gpr high byte enable
gpr_pcinc : slbit; -- pc increment enable
psr_ccwe : slbit; -- enable update cc
psr_we: slbit; -- write enable psw (from DIN)
psr_func : slv3; -- write function psw (from DIN)
dsrc_sel : slbit; -- src data register source select
dsrc_we : slbit; -- src data register write enable
ddst_sel : slbit; -- dst data register source select
ddst_we : slbit; -- dst data register write enable
dtmp_sel : slv2; -- tmp data register source select
dtmp_we : slbit; -- tmp data register write enable
ounit_asel : slv2; -- ounit a port selector
ounit_azero : slbit; -- ounit a port force zero
ounit_const : slv9; -- ounit b port const
ounit_bsel : slv2; -- ounit b port selector
ounit_opsub : slbit; -- ounit operation
aunit_srcmod : slv2; -- aunit src port modifier
aunit_dstmod : slv2; -- aunit dst port modifier
aunit_cimod : slv2; -- aunit ci port modifier
aunit_cc1op : slbit; -- aunit use cc modes (1 op instruction)
aunit_ccmode : slv3; -- aunit cc port mode
aunit_bytop : slbit; -- aunit byte operation
lunit_func : slv4; -- lunit function
lunit_bytop : slbit; -- lunit byte operation
munit_func : slv2; -- munit function
munit_s_div : slbit; -- munit s_opg_div state
munit_s_div_cn : slbit; -- munit s_opg_div_cn state
munit_s_div_cr : slbit; -- munit s_opg_div_cr state
munit_s_ash : slbit; -- munit s_opg_ash state
munit_s_ash_cn : slbit; -- munit s_opg_ash_cn state
munit_s_ashc : slbit; -- munit s_opg_ashc state
munit_s_ashc_cn : slbit; -- munit s_opg_ashc_cn state
ireg_we : slbit; -- ireg register write enable
cres_sel : slv3; -- result bus (cres) select
dres_sel : slv3; -- result bus (dres) select
vmaddr_sel : slv2; -- virtual address select
cpdout_we : slbit; -- capture dres for cpdout
end record dpath_cntl_type;
constant dpath_cntl_init : dpath_cntl_type := (
"000","000","00",'0','0','0','0', -- gpr
'0','0',"000", -- psr
'0','0','0','0',"00",'0', -- dsrc,..,dtmp
"00",'0',"000000000","00",'0', -- ounit
"00","00","00",'0',"000",'0', -- aunit
"0000",'0', -- lunit
"00",'0','0','0','0','0','0','0', -- munit
'0',"000","000","00",'0' -- rest
);
constant c_dpath_dsrc_src : slbit := '0'; -- DSRC = R(SRC)
constant c_dpath_dsrc_res : slbit := '1'; -- DSRC = DRES
constant c_dpath_ddst_dst : slbit := '0'; -- DDST = R(DST)
constant c_dpath_ddst_res : slbit := '1'; -- DDST = DRES
constant c_dpath_dtmp_dsrc : slv2 := "00"; -- DTMP = DSRC
constant c_dpath_dtmp_psw : slv2 := "01"; -- DTMP = PSW
constant c_dpath_dtmp_dres : slv2 := "10"; -- DTMP = DRES
constant c_dpath_dtmp_drese : slv2 := "11"; -- DTMP = DRESE
constant c_dpath_res_ounit : slv3 := "000"; -- D/CRES = OUNIT
constant c_dpath_res_aunit : slv3 := "001"; -- D/CRES = AUNIT
constant c_dpath_res_lunit : slv3 := "010"; -- D/CRES = LUNIT
constant c_dpath_res_munit : slv3 := "011"; -- D/CRES = MUNIT
constant c_dpath_res_vmdout : slv3 := "100"; -- D/CRES = VMDOUT
constant c_dpath_res_fpdout : slv3 := "101"; -- D/CRES = FPDOUT
constant c_dpath_res_ireg : slv3 := "110"; -- D/CRES = IREG
constant c_dpath_res_cpdin : slv3 := "111"; -- D/CRES = CPDIN
constant c_dpath_vmaddr_dsrc : slv2 := "00"; -- VMADDR = DSRC
constant c_dpath_vmaddr_ddst : slv2 := "01"; -- VMADDR = DDST
constant c_dpath_vmaddr_pc : slv2 := "10"; -- VMADDR = PC
constant c_dpath_vmaddr_dtmp : slv2 := "11"; -- VMADDR = DTMP
type dpath_stat_type is record -- data path status
ccout_z : slbit; -- current effective Z cc flag
shc_tc : slbit; -- last shc cycle (shc==0)
div_cr : slbit; -- division: reminder correction needed
div_cq : slbit; -- division: quotient correction needed
div_zero : slbit; -- division: divident or divisor zero
div_ovfl : slbit; -- division: overflow
end record dpath_stat_type;
constant dpath_stat_init : dpath_stat_type := (others=>'0');
type decode_stat_type is record -- decode status
is_dstmode0 : slbit; -- dest. is register mode
is_srcpc : slbit; -- source is pc
is_srcpcmode1 : slbit; -- source is pc and mode=1
is_dstpc : slbit; -- dest. is pc
is_dstw_reg : slbit; -- dest. register to be written
is_dstw_pc : slbit; -- pc register to be written
is_rmwop : slbit; -- read-modify-write operation
is_bytop : slbit; -- byte operation
is_res : slbit; -- reserved operation code
op_rtt : slbit; -- RTT instruction
op_mov : slbit; -- MOV instruction
trap_vec : slv3; -- trap vector addr bits 4:2
force_srcsp : slbit; -- force src register to be sp
updt_dstadsrc : slbit; -- update dsrc in dsta flow
aunit_srcmod : slv2; -- aunit src port modifier
aunit_dstmod : slv2; -- aunit dst port modifier
aunit_cimod : slv2; -- aunit ci port modifier
aunit_cc1op : slbit; -- aunit use cc modes (1 op instruction)
aunit_ccmode : slv3; -- aunit cc port mode
lunit_func : slv4; -- lunit function
munit_func : slv2; -- munit function
res_sel : slv3; -- result bus (cres/dres) select
fork_op : slv4; -- op fork after idecode state
fork_srcr : slv2; -- src-read fork after idecode state
fork_dstr : slv2; -- dst-read fork after src read state
fork_dsta : slv2; -- dst-addr fork after idecode state
fork_opg : slv4; -- opg fork
fork_opa : slv3; -- opa fork
do_fork_op : slbit; -- execute fork_op
do_fork_srcr : slbit; -- execute fork_srcr
do_fork_dstr : slbit; -- execute fork_dstr
do_fork_dsta : slbit; -- execute fork_dsta
do_fork_opg : slbit; -- execute fork_opg
do_pref_dec : slbit; -- can do prefetch at decode phase
end record decode_stat_type;
constant decode_stat_init : decode_stat_type := (
'0','0','0','0','0','0','0','0','0', -- is_
'0','0',"000",'0','0', -- op_, trap_, force_, updt_
"00","00","00",'0',"000", -- aunit_
"0000","00","000", -- lunit_, munit_, res_
"0000","00","00","00","0000","000", -- fork_
'0','0','0','0','0', -- do_fork_
'0' -- do_pref_
);
constant c_fork_op_halt : slv4 := "0000";
constant c_fork_op_wait : slv4 := "0001";
constant c_fork_op_rtti : slv4 := "0010";
constant c_fork_op_trap : slv4 := "0011";
constant c_fork_op_reset: slv4 := "0100";
constant c_fork_op_rts : slv4 := "0101";
constant c_fork_op_spl : slv4 := "0110";
constant c_fork_op_mcc : slv4 := "0111";
constant c_fork_op_br : slv4 := "1000";
constant c_fork_op_mark : slv4 := "1001";
constant c_fork_op_sob : slv4 := "1010";
constant c_fork_op_mtp : slv4 := "1011";
constant c_fork_srcr_def : slv2:= "00";
constant c_fork_srcr_inc : slv2:= "01";
constant c_fork_srcr_dec : slv2:= "10";
constant c_fork_srcr_ind : slv2:= "11";
constant c_fork_dstr_def : slv2:= "00";
constant c_fork_dstr_inc : slv2:= "01";
constant c_fork_dstr_dec : slv2:= "10";
constant c_fork_dstr_ind : slv2:= "11";
constant c_fork_dsta_def : slv2:= "00";
constant c_fork_dsta_inc : slv2:= "01";
constant c_fork_dsta_dec : slv2:= "10";
constant c_fork_dsta_ind : slv2:= "11";
constant c_fork_opg_gen : slv4 := "0000";
constant c_fork_opg_wdef : slv4 := "0001";
constant c_fork_opg_winc : slv4 := "0010";
constant c_fork_opg_wdec : slv4 := "0011";
constant c_fork_opg_wind : slv4 := "0100";
constant c_fork_opg_mul : slv4 := "0101";
constant c_fork_opg_div : slv4 := "0110";
constant c_fork_opg_ash : slv4 := "0111";
constant c_fork_opg_ashc : slv4 := "1000";
constant c_fork_opa_jsr : slv3 := "000";
constant c_fork_opa_jmp : slv3 := "001";
constant c_fork_opa_mtp : slv3 := "010";
constant c_fork_opa_mfp_reg : slv3 := "011";
constant c_fork_opa_mfp_mem : slv3 := "100";
-- Note: MSB=0 are 'normal' states, MSB=1 are fatal errors
constant c_cpurust_init : slv4 := "0000"; -- cpu in init state
constant c_cpurust_halt : slv4 := "0001"; -- cpu executed HALT
constant c_cpurust_reset : slv4 := "0010"; -- cpu was reset
constant c_cpurust_stop : slv4 := "0011"; -- cpu was stopped
constant c_cpurust_step : slv4 := "0100"; -- cpu was stepped
constant c_cpurust_susp : slv4 := "0101"; -- cpu was suspended
constant c_cpurust_runs : slv4 := "0111"; -- cpu running
constant c_cpurust_vecfet : slv4 := "1000"; -- vector fetch error halt
constant c_cpurust_recrsv : slv4 := "1001"; -- recursive red-stack halt
constant c_cpurust_sfail : slv4 := "1100"; -- sequencer failure
constant c_cpurust_vfail : slv4 := "1101"; -- vmbox failure
type cpustat_type is record -- CPU status
cmdbusy : slbit; -- command busy
cmdack : slbit; -- command acknowledge
cmderr : slbit; -- command error
cmdmerr : slbit; -- command memory access error
cpugo : slbit; -- CPU go state
cpustep : slbit; -- CPU step flag
cpuhalt : slbit; -- CPU halt flag
cpuwait : slbit; -- CPU wait flag
cpurust : slv4; -- CPU run status
cpfunc : slv5; -- current control port function
cprnum : slv3; -- current control port register number
waitsusp : slbit; -- WAIT instruction suspended
intvect : slv9_2; -- current interrupt vector
trap_mmu : slbit; -- mmu trace trap pending
trap_ysv : slbit; -- ysv trap pending
prefdone : slbit; -- prefetch done
do_gprwe : slbit; -- pending gpr_we
do_intrsv : slbit; -- active rsv interrupt sequence
end record cpustat_type;
constant cpustat_init : cpustat_type := (
'0','0','0','0', -- cmd..
'0','0','0','0', -- cpu..
c_cpurust_init, -- cpurust
"00000","000", -- cpfunc, cprnum
'0', -- waitsusp
(others=>'0'), -- intvect
'0','0','0', -- trap_(mmu|ysv), prefdone
'0','0' -- do_gprwe, do_intrsv
);
type cpuerr_type is record -- CPU error register
illhlt : slbit; -- illegal halt (in non-kernel mode)
adderr : slbit; -- address error (odd, jmp/jsr reg)
nxm : slbit; -- non-existent memory
iobto : slbit; -- I/O bus timeout (non-exist UB)
ysv : slbit; -- yellow stack violation
rsv : slbit; -- red stack violation
end record cpuerr_type;
constant cpuerr_init : cpuerr_type := (others=>'0');
type vm_cntl_type is record -- virt memory control port
req : slbit; -- request
wacc : slbit; -- write access
macc : slbit; -- modify access (r-m-w sequence)
cacc : slbit; -- console access
bytop : slbit; -- byte operation
dspace : slbit; -- dspace operation
kstack : slbit; -- access through kernel stack
intrsv : slbit; -- active rsv interrupt sequence
mode : slv2; -- mode
trap_done : slbit; -- mmu trap taken (to set ssr0 bit)
end record vm_cntl_type;
constant vm_cntl_init : vm_cntl_type := (
'0','0','0','0', -- req, wacc, macc,cacc
'0','0','0', -- bytop, dspace, kstack
'0',"00",'0' -- intrsv, mode, trap_done
);
type vm_stat_type is record -- virt memory status port
ack : slbit; -- acknowledge
err : slbit; -- error (see err_xxx for reason)
fail : slbit; -- failure (machine check)
err_odd : slbit; -- abort: odd address error
err_mmu : slbit; -- abort: mmu reject
err_nxm : slbit; -- abort: non-existing memory
err_iobto : slbit; -- abort: non-existing I/O resource
err_rsv : slbit; -- abort: red stack violation
trap_ysv : slbit; -- trap: yellow stack violation
trap_mmu : slbit; -- trap: mmu trace trap
end record vm_stat_type;
constant vm_stat_init : vm_stat_type := (others=>'0');
type em_mreq_type is record -- external memory - master request
req : slbit; -- request
we : slbit; -- write enable
be : slv2; -- byte enables
cancel : slbit; -- cancel request
addr : slv22_1; -- address
din : slv16; -- data in (input to memory)
end record em_mreq_type;
constant em_mreq_init : em_mreq_type := (
'0','0',"00",'0', -- req, we, be, cancel
(others=>'0'),(others=>'0') -- addr, din
);
type em_sres_type is record -- external memory - slave response
ack_r : slbit; -- acknowledge read
ack_w : slbit; -- acknowledge write
dout : slv16; -- data out (output from memory)
end record em_sres_type;
constant em_sres_init : em_sres_type := (
'0','0', -- ack_r, ack_w
(others=>'0') -- dout
);
type mmu_cntl_type is record -- mmu control port
req : slbit; -- translate request
wacc : slbit; -- write access
macc : slbit; -- modify access (r-m-w sequence)
cacc : slbit; -- console access (bypass mmu)
dspace : slbit; -- dspace access
mode : slv2; -- processor mode
trap_done : slbit; -- mmu trap taken (set ssr0 bit)
end record mmu_cntl_type;
constant mmu_cntl_init : mmu_cntl_type := (
'0','0','0','0', -- req, wacc, macc, cacc
'0',"00",'0' -- dspace, mode, trap_done
);
type mmu_stat_type is record -- mmu status port
vaok : slbit; -- virtual address valid
trap : slbit; -- mmu trap request
ena_mmu : slbit; -- mmu enable (ssr0 bit 0)
ena_22bit : slbit; -- mmu in 22 bit mode (ssr3 bit 4)
ena_ubmap : slbit; -- ubmap enable (ssr3 bit 5)
end record mmu_stat_type;
constant mmu_stat_init : mmu_stat_type := (others=>'0');
type mmu_moni_type is record -- mmu monitor port
istart : slbit; -- instruction start
idone : slbit; -- instruction done
pc : slv16; -- PC of new instruction
regmod : slbit; -- register modified
regnum : slv3; -- register number
delta : slv4; -- register offset
isdec : slbit; -- offset to be subtracted
trace_prev : slbit; -- use ssr12 trace state of prev. state
end record mmu_moni_type;
constant mmu_moni_init : mmu_moni_type := (
'0','0',(others=>'0'), -- istart, idone, pc
'0',"000","0000", -- regmod, regnum, delta
'0','0' -- isdec, trace_prev
);
type mmu_ssr0_type is record -- MMU ssr0
abo_nonres : slbit; -- abort non resident
abo_length : slbit; -- abort segment length
abo_rdonly : slbit; -- abort read-only
trap_mmu : slbit; -- trap management
ena_trap : slbit; -- enable traps
inst_compl : slbit; -- instruction complete
seg_mode : slv2; -- segement mode
dspace : slbit; -- address space (D=1, I=0)
seg_num : slv3; -- segment number
ena_mmu : slbit; -- enable memory management
trace_prev : slbit; -- ssr12 trace status in prev. state
end record mmu_ssr0_type;
constant mmu_ssr0_init : mmu_ssr0_type := (
inst_compl=>'0', seg_mode=>"00", seg_num=>"000",
others=>'0'
);
type mmu_ssr1_type is record -- MMU ssr1
rb_delta : slv5; -- RB: amount change
rb_num : slv3; -- RB: register number
ra_delta : slv5; -- RA: amount change
ra_num : slv3; -- RA: register number
end record mmu_ssr1_type;
constant mmu_ssr1_init : mmu_ssr1_type := (
"00000","000", -- rb_...
"00000","000" -- ra_...
);
type mmu_ssr3_type is record -- MMU ssr3
ena_ubmap : slbit; -- enable unibus mapping
ena_22bit : slbit; -- enable 22 bit mapping
dspace_km : slbit; -- enable dspace kernel
dspace_sm : slbit; -- enable dspace supervisor
dspace_um : slbit; -- enable dspace user
end record mmu_ssr3_type;
constant mmu_ssr3_init : mmu_ssr3_type := (others=>'0');
-- control port definitions --------------------------------------------------
type cp_cntl_type is record -- control port control
req : slbit; -- request
func : slv5; -- function
rnum : slv3; -- register number
end record cp_cntl_type;
constant c_cpfunc_noop : slv5 := "00000"; -- noop : no operation
constant c_cpfunc_sta : slv5 := "00001"; -- sta : cpu start
constant c_cpfunc_sto : slv5 := "00010"; -- sto : cpu stop
constant c_cpfunc_cont : slv5 := "00011"; -- cont : cpu continue
constant c_cpfunc_step : slv5 := "00100"; -- step : cpu step
constant c_cpfunc_rst : slv5 := "01111"; -- rst : cpu reset (soft)
constant c_cpfunc_rreg : slv5 := "10000"; -- rreg : read register
constant c_cpfunc_wreg : slv5 := "10001"; -- wreg : write register
constant c_cpfunc_rpsw : slv5 := "10010"; -- rpsw : read psw
constant c_cpfunc_wpsw : slv5 := "10011"; -- wpsw : write psw
constant c_cpfunc_rmem : slv5 := "10100"; -- rmem : read memory
constant c_cpfunc_wmem : slv5 := "10101"; -- wmem : write memory
constant cp_cntl_init : cp_cntl_type := ('0',c_cpfunc_noop,"000");
type cp_stat_type is record -- control port status
cmdbusy : slbit; -- command busy
cmdack : slbit; -- command acknowledge
cmderr : slbit; -- command error
cmdmerr : slbit; -- command memory access error
cpugo : slbit; -- CPU go state
cpustep : slbit; -- CPU step flag
cpuhalt : slbit; -- CPU halt flag
cpuwait : slbit; -- CPU wait flag
cpurust : slv4; -- CPU run status
end record cp_stat_type;
constant cp_stat_init : cp_stat_type := (
'0','0','0','0', -- cmd...
'0','0','0','0', -- cpu...
(others=>'0') -- cpurust
);
type cp_addr_type is record -- control port address
addr : slv22_1; -- address
racc : slbit; -- ibr access
be : slv2; -- byte enables
ena_22bit : slbit; -- enable 22 bit mode
ena_ubmap : slbit; -- enable unibus mapper
end record cp_addr_type;
constant cp_addr_init : cp_addr_type := (
(others=>'0'), -- addr
'0',"00", -- racc, be
'0','0' -- ena_...
);
-- debug and monitoring port definitions -------------------------------------
type dm_cntl_type is record -- debug and monitor control
dum1 : slbit; -- dummy 1
dum2 : slbit; -- dummy 2
end record dm_cntl_type;
constant dm_cntl_init : dm_cntl_type := (others=>'0');
type dm_stat_dp_type is record -- debug and monitor status - dpath
pc : slv16; -- pc
psw : psw_type; -- psw
ireg : slv16; -- ireg
ireg_we : slbit; -- ireg we
dsrc : slv16; -- dsrc register
ddst : slv16; -- ddst register
dtmp : slv16; -- dtmp register
dres : slv16; -- dres bus
gpr_adst : slv3; -- gpr dst regsiter
gpr_mode : slv2; -- gpr mode
gpr_bytop : slbit; -- gpr bytop
gpr_we : slbit; -- gpr we
end record dm_stat_dp_type;
constant dm_stat_dp_init : dm_stat_dp_type := (
(others=>'0'), -- pc
psw_init, -- psw
(others=>'0'),'0', -- ireg, ireg_we
(others=>'0'),(others=>'0'), -- dsrc, ddst
(others=>'0'),(others=>'0'), -- dtmp, dres
(others=>'0'),(others=>'0'), -- gpr_adst, gpr_mode
'0','0' -- gpr_bytop, gpr_we
);
type dm_stat_vm_type is record -- debug and monitor status - vmbox
ibmreq : ib_mreq_type; -- ibus master request
ibsres : ib_sres_type; -- ibus slave response
end record dm_stat_vm_type;
constant dm_stat_vm_init : dm_stat_vm_type := (ib_mreq_init,ib_sres_init);
type dm_stat_co_type is record -- debug and monitor status - core
cpugo : slbit; -- cpugo state flag
cpuhalt : slbit; -- cpuhalt state flag
end record dm_stat_co_type;
constant dm_stat_co_init : dm_stat_co_type := ('0','0');
type dm_stat_sy_type is record -- debug and monitor status - system
emmreq : em_mreq_type; -- external memory: request
emsres : em_sres_type; -- external memory: response
chit : slbit; -- cache hit
end record dm_stat_sy_type;
constant dm_stat_sy_init : dm_stat_sy_type := (em_mreq_init,em_sres_init,'0');
-- rbus interface definitions ------------------------------------------------
constant c_rbaddr_conf : slv5 := "00000"; -- R/W configuration reg
constant c_rbaddr_cntl : slv5 := "00001"; -- -/F control reg
constant c_rbaddr_stat : slv5 := "00010"; -- R/- status reg
constant c_rbaddr_psw : slv5 := "00011"; -- R/W psw access
constant c_rbaddr_al : slv5 := "00100"; -- R/W address low reg
constant c_rbaddr_ah : slv5 := "00101"; -- R/W address high reg
constant c_rbaddr_mem : slv5 := "00110"; -- R/W memory access
constant c_rbaddr_memi : slv5 := "00111"; -- R/W memory access; inc addr
constant c_rbaddr_r0 : slv5 := "01000"; -- R/W gpr 0
constant c_rbaddr_r1 : slv5 := "01001"; -- R/W gpr 1
constant c_rbaddr_r2 : slv5 := "01010"; -- R/W gpr 2
constant c_rbaddr_r3 : slv5 := "01011"; -- R/W gpr 3
constant c_rbaddr_r4 : slv5 := "01100"; -- R/W gpr 4
constant c_rbaddr_r5 : slv5 := "01101"; -- R/W gpr 5
constant c_rbaddr_sp : slv5 := "01110"; -- R/W gpr 6 (sp)
constant c_rbaddr_pc : slv5 := "01111"; -- R/W gpr 7 (pc)
constant c_rbaddr_ibrb : slv5 := "10000"; -- R/W ibr base address
subtype c_al_rbf_addr is integer range 15 downto 1; -- al: address
constant c_ah_rbf_ena_ubmap: integer := 7; -- ah: ubmap
constant c_ah_rbf_ena_22bit: integer := 6; -- ah: 22bit
subtype c_ah_rbf_addr is integer range 5 downto 0; -- ah: address
constant c_stat_rbf_cmderr: integer := 0; -- stat field: cmderr
constant c_stat_rbf_cmdmerr: integer := 1; -- stat field: cmdmerr
constant c_stat_rbf_cpugo: integer := 2; -- stat field: cpugo
constant c_stat_rbf_cpuhalt: integer := 3; -- stat field: cpuhalt
subtype c_stat_rbf_cpurust is integer range 7 downto 4; -- cpurust
subtype c_ibrb_ibf_base is integer range 12 downto 6; -- ibrb: base addr
subtype c_ibrb_ibf_be is integer range 1 downto 0; -- ibrb: be's
-- -------------------------------------
component pdp11_gpr is -- general purpose registers
port (
CLK : in slbit; -- clock
DIN : in slv16; -- input data
ASRC : in slv3; -- source register number
ADST : in slv3; -- destination register number
MODE : in slv2; -- processor mode (k=>00,s=>01,u=>11)
RSET : in slbit; -- register set
WE : in slbit; -- write enable
BYTOP : in slbit; -- byte operation (write low byte only)
PCINC : in slbit; -- increment PC
DSRC : out slv16; -- source register data
DDST : out slv16; -- destination register data
PC : out slv16 -- current PC value
);
end component;
constant c_gpr_r5 : slv3 := "101"; -- register number of r5
constant c_gpr_sp : slv3 := "110"; -- register number of SP
constant c_gpr_pc : slv3 := "111"; -- register number of PC
component pdp11_psr is -- processor status word register
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- console reset
DIN : in slv16; -- input data
CCIN : in slv4; -- cc input
CCWE : in slbit; -- enable update cc
WE : in slbit; -- write enable (from DIN)
FUNC : in slv3; -- write function (from DIN)
PSW : out psw_type; -- current psw
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
constant c_psr_func_wspl : slv3 := "000"; -- SPL mode: set pri
constant c_psr_func_wcc : slv3 := "001"; -- CC mode: set/clear cc
constant c_psr_func_wint : slv3 := "010"; -- interupt mode: pmode=cmode
constant c_psr_func_wrti : slv3 := "011"; -- rti mode: protect modes
constant c_psr_func_wall : slv3 := "100"; -- write all fields
component pdp11_ounit is -- offset adder for addresses (ounit)
port (
DSRC : in slv16; -- 'src' data for port A
DDST : in slv16; -- 'dst' data for port A
DTMP : in slv16; -- 'tmp' data for port A
PC : in slv16; -- PC data for port A
ASEL : in slv2; -- selector for port A
AZERO : in slbit; -- force zero for port A
IREG8 : in slv8; -- 'ireg' data for port B
VMDOUT : in slv16; -- virt. memory data for port B
CONST : in slv9; -- sequencer const data for port B
BSEL : in slv2; -- selector for port B
OPSUB : in slbit; -- operation: 0 add, 1 sub
DOUT : out slv16; -- data output
NZOUT : out slv2 -- NZ condition codes out
);
end component;
constant c_ounit_asel_ddst : slv2 := "00"; -- A = DDST
constant c_ounit_asel_dsrc : slv2 := "01"; -- A = DSRC
constant c_ounit_asel_pc : slv2 := "10"; -- A = PC
constant c_ounit_asel_dtmp : slv2 := "11"; -- A = DTMP
constant c_ounit_bsel_const : slv2 := "00"; -- B = CONST
constant c_ounit_bsel_vmdout : slv2 := "01"; -- B = VMDOUT
constant c_ounit_bsel_ireg6 : slv2 := "10"; -- B = 2*IREG(6bit)
constant c_ounit_bsel_ireg8 : slv2 := "11"; -- B = 2*IREG(8bit,sign-extend)
component pdp11_aunit is -- arithmetic unit for data (aunit)
port (
DSRC : in slv16; -- 'src' data in
DDST : in slv16; -- 'dst' data in
CI : in slbit; -- carry flag in
SRCMOD : in slv2; -- src modifier mode
DSTMOD : in slv2; -- dst modifier mode
CIMOD : in slv2; -- ci modifier mode
CC1OP : in slbit; -- use cc modes (1 op instruction)
CCMODE : in slv3; -- cc mode
BYTOP : in slbit; -- byte operation
DOUT : out slv16; -- data output
CCOUT : out slv4 -- condition codes out
);
end component;
constant c_aunit_mod_pass : slv2 := "00"; -- pass data
constant c_aunit_mod_inv : slv2 := "01"; -- invert data
constant c_aunit_mod_zero : slv2 := "10"; -- set to 0
constant c_aunit_mod_one : slv2 := "11"; -- set to 1
-- the c_aunit_ccmode codes follow exactly the opcode format (bit 8:6)
constant c_aunit_ccmode_clr : slv3 := "000"; -- do clr instruction
constant c_aunit_ccmode_com : slv3 := "001"; -- do com instruction
constant c_aunit_ccmode_inc : slv3 := "010"; -- do inc instruction
constant c_aunit_ccmode_dec : slv3 := "011"; -- do dec instruction
constant c_aunit_ccmode_neg : slv3 := "100"; -- do neg instruction
constant c_aunit_ccmode_adc : slv3 := "101"; -- do adc instruction
constant c_aunit_ccmode_sbc : slv3 := "110"; -- do sbc instruction
constant c_aunit_ccmode_tst : slv3 := "111"; -- do tst instruction
component pdp11_lunit is -- logic unit for data (lunit)
port (
DSRC : in slv16; -- 'src' data in
DDST : in slv16; -- 'dst' data in
CCIN : in slv4; -- condition codes in
FUNC : in slv4; -- function
BYTOP : in slbit; -- byte operation
DOUT : out slv16; -- data output
CCOUT : out slv4 -- condition codes out
);
end component;
constant c_lunit_func_asr : slv4 := "0000"; -- ASR/ASRB ??? recheck coding !!
constant c_lunit_func_asl : slv4 := "0001"; -- ASL/ASLB
constant c_lunit_func_ror : slv4 := "0010"; -- ROR/RORB
constant c_lunit_func_rol : slv4 := "0011"; -- ROL/ROLB
constant c_lunit_func_bis : slv4 := "0100"; -- BIS/BISB
constant c_lunit_func_bic : slv4 := "0101"; -- BIC/BICB
constant c_lunit_func_bit : slv4 := "0110"; -- BIT/BITB
constant c_lunit_func_mov : slv4 := "0111"; -- MOV/MOVB
constant c_lunit_func_sxt : slv4 := "1000"; -- SXT
constant c_lunit_func_swap : slv4 := "1001"; -- SWAB
constant c_lunit_func_xor : slv4 := "1010"; -- XOR
component pdp11_munit is -- mul/div unit for data (munit)
port (
CLK : in slbit; -- clock
DSRC : in slv16; -- 'src' data in
DDST : in slv16; -- 'dst' data in
DTMP : in slv16; -- 'tmp' data in
GPR_DSRC : in slv16; -- 'src' data from GPR
FUNC : in slv2; -- function
S_DIV : in slbit; -- s_opg_div state
S_DIV_CN : in slbit; -- s_opg_div_cn state
S_DIV_CR : in slbit; -- s_opg_div_cr state
S_ASH : in slbit; -- s_opg_ash state
S_ASH_CN : in slbit; -- s_opg_ash_cn state
S_ASHC : in slbit; -- s_opg_ashc state
S_ASHC_CN : in slbit; -- s_opg_ashc_cn state
SHC_TC : out slbit; -- last shc cycle (shc==0)
DIV_CR : out slbit; -- division: reminder correction needed
DIV_CQ : out slbit; -- division: quotient correction needed
DIV_ZERO : out slbit; -- division: divident or divisor zero
DIV_OVFL : out slbit; -- division: overflow
DOUT : out slv16; -- data output
DOUTE : out slv16; -- data output extra
CCOUT : out slv4 -- condition codes out
);
end component;
constant c_munit_func_mul : slv2 := "00"; -- MUL
constant c_munit_func_div : slv2 := "01"; -- DIV
constant c_munit_func_ash : slv2 := "10"; -- ASH
constant c_munit_func_ashc : slv2 := "11"; -- ASHC
component pdp11_mmu_sadr is -- mmu SAR/SDR register set
port (
CLK : in slbit; -- clock
MODE : in slv2; -- mode
ASN : in slv4; -- augmented segment number (1+3 bit)
AIB_WE : in slbit; -- update AIB
AIB_SETA : in slbit; -- set access AIB
AIB_SETW : in slbit; -- set write AIB
SARSDR : out sarsdr_type; -- combined SAR/SDR
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_mmu_ssr12 is -- mmu register ssr1 and ssr2
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- console reset
TRACE : in slbit; -- trace enable
MONI : in mmu_moni_type; -- MMU monitor port data
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_mmu is -- mmu - memory management unit
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- console reset
BRESET : in slbit; -- ibus reset
CNTL : in mmu_cntl_type; -- control port
VADDR : in slv16; -- virtual address
MONI : in mmu_moni_type; -- monitor port
STAT : out mmu_stat_type; -- status port
PADDRH : out slv16; -- physical address (upper 16 bit)
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_vmbox is -- virtual memory
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- global reset
CRESET : in slbit; -- console reset
BRESET : in slbit; -- ibus reset
CP_ADDR : in cp_addr_type; -- console port address
VM_CNTL : in vm_cntl_type; -- vm control port
VM_ADDR : in slv16; -- vm address
VM_DIN : in slv16; -- vm data in
VM_STAT : out vm_stat_type; -- vm status port
VM_DOUT : out slv16; -- vm data out
EM_MREQ : out em_mreq_type; -- external memory: request
EM_SRES : in em_sres_type; -- external memory: response
MMU_MONI : in mmu_moni_type; -- mmu monitor port
IB_MREQ_M : out ib_mreq_type; -- ibus request (master)
IB_SRES_CPU : in ib_sres_type; -- ibus response (CPU registers)
IB_SRES_EXT : in ib_sres_type; -- ibus response (external devices)
DM_STAT_VM : out dm_stat_vm_type -- debug and monitor status
);
end component;
component pdp11_dpath is -- CPU datapath
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- console reset
CNTL : in dpath_cntl_type; -- control interface
STAT : out dpath_stat_type; -- status interface
CP_DIN : in slv16; -- console port data in
CP_DOUT : out slv16; -- console port data out
PSWOUT : out psw_type; -- current psw
PCOUT : out slv16; -- current pc
IREG : out slv16; -- ireg out
VM_ADDR : out slv16; -- virt. memory address
VM_DOUT : in slv16; -- virt. memory data out
VM_DIN : out slv16; -- virt. memory data in
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
DM_STAT_DP : out dm_stat_dp_type -- debug and monitor status
);
end component;
component pdp11_decode is -- instruction decoder
port (
IREG : in slv16; -- input instruction word
STAT : out decode_stat_type -- status output
);
end component;
component pdp11_sequencer is -- cpu sequencer
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- global reset
PSW : in psw_type; -- processor status
PC : in slv16; -- program counter
IREG : in slv16; -- IREG
ID_STAT : in decode_stat_type; -- instr. decoder status
DP_STAT : in dpath_stat_type; -- data path status
CP_CNTL : in cp_cntl_type; -- console port control
VM_STAT : in vm_stat_type; -- virtual memory status port
INT_PRI : in slv3; -- interrupt priority
INT_VECT : in slv9_2; -- interrupt vector
CRESET : out slbit; -- console reset
BRESET : out slbit; -- ibus reset
MMU_MONI : out mmu_moni_type; -- mmu monitor port
DP_CNTL : out dpath_cntl_type; -- data path control
VM_CNTL : out vm_cntl_type; -- virtual memory control port
CP_STAT : out cp_stat_type; -- console port status
INT_ACK : out slbit; -- interrupt acknowledge
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_irq is -- interrupt requester
port (
CLK : in slbit; -- clock
BRESET : in slbit; -- ibus reset
INT_ACK : in slbit; -- interrupt acknowledge from CPU
EI_PRI : in slv3; -- external interrupt priority
EI_VECT : in slv9_2; -- external interrupt vector
EI_ACKM : out slbit; -- external interrupt acknowledge
PRI : out slv3; -- interrupt priority
VECT : out slv9_2; -- interrupt vector
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_ubmap is -- 11/70 unibus mapper
port (
CLK : in slbit; -- clock
MREQ : in slbit; -- request mapping
ADDR_UB : in slv18_1; -- UNIBUS address (in)
ADDR_PM : out slv22_1; -- physical memory address (out)
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_sys70 is -- 11/70 memory system registers
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- console reset
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_mem70 is -- 11/70 memory system registers
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- console reset
HM_ENA : in slbit; -- hit/miss enable
HM_VAL : in slbit; -- hit/miss value
CACHE_FMISS : out slbit; -- cache force miss
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_cache is -- cache
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- global reset
EM_MREQ : in em_mreq_type; -- em request
EM_SRES : out em_sres_type; -- em response
FMISS : in slbit; -- force miss
CHIT : out slbit; -- cache hit flag
MEM_REQ : out slbit; -- memory: request
MEM_WE : out slbit; -- memory: write enable
MEM_BUSY : in slbit; -- memory: controller busy
MEM_ACK_R : in slbit; -- memory: acknowledge read
MEM_ADDR : out slv20; -- memory: address
MEM_BE : out slv4; -- memory: byte enable
MEM_DI : out slv32; -- memory: data in (memory view)
MEM_DO : in slv32 -- memory: data out (memory view)
);
end component;
component pdp11_core is -- full processor core
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CP_CNTL : in cp_cntl_type; -- console control port
CP_ADDR : in cp_addr_type; -- console address port
CP_DIN : in slv16; -- console data in
CP_STAT : out cp_stat_type; -- console status port
CP_DOUT : out slv16; -- console data out
EI_PRI : in slv3; -- external interrupt priority
EI_VECT : in slv9_2; -- external interrupt vector
EI_ACKM : out slbit; -- external interrupt acknowledge
EM_MREQ : out em_mreq_type; -- external memory: request
EM_SRES : in em_sres_type; -- external memory: response
BRESET : out slbit; -- ibus reset
IB_MREQ_M : out ib_mreq_type; -- ibus master request (master)
IB_SRES_M : in ib_sres_type; -- ibus slave response (master)
DM_STAT_DP : out dm_stat_dp_type; -- debug and monitor status - dpath
DM_STAT_VM : out dm_stat_vm_type; -- debug and monitor status - vmbox
DM_STAT_CO : out dm_stat_co_type -- debug and monitor status - core
);
end component;
component pdp11_tmu is -- trace and monitor unit
port (
CLK : in slbit; -- clock
ENA : in slbit := '0'; -- enable trace output
DM_STAT_DP : in dm_stat_dp_type; -- DM dpath
DM_STAT_VM : in dm_stat_vm_type; -- DM vmbox
DM_STAT_CO : in dm_stat_co_type; -- DM core
DM_STAT_SY : in dm_stat_sy_type -- DM system
);
end component;
component pdp11_tmu_sb is -- trace and mon. unit; simbus wrapper
generic (
ENAPIN : integer := 13); -- SB_CNTL signal to use for enable
port (
CLK : in slbit; -- clock
DM_STAT_DP : in dm_stat_dp_type; -- DM dpath
DM_STAT_VM : in dm_stat_vm_type; -- DM vmbox
DM_STAT_CO : in dm_stat_co_type; -- DM core
DM_STAT_SY : in dm_stat_sy_type -- DM system
);
end component;
component pdp11_du_drv is -- display unit low level driver
generic (
CDWIDTH : positive := 3); -- clock divider width
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- global reset
ROW0 : in slv22; -- led row 0 (22 leds, top)
ROW1 : in slv16; -- led row 1 (16 leds)
ROW2 : in slv16; -- led row 2 (16 leds)
ROW3 : in slv10; -- led row 3 (10 leds, bottom)
SWOPT : out slv8; -- option pattern from du
SWOPT_RDY : out slbit; -- marks update of swopt
DU_SCLK : out slbit; -- DU: sclk
DU_SS_N : out slbit; -- DU: ss_n
DU_MOSI : out slbit; -- DU: mosi (master out, slave in)
DU_MISO : in slbit -- DU: miso (master in, slave out)
);
end component;
component pdp11_bram is -- BRAM based ext. memory dummy
generic (
AWIDTH : positive := 14); -- address width
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- global reset
EM_MREQ : in em_mreq_type; -- em request
EM_SRES : out em_sres_type -- em response
);
end component;
component pdp11_core_rbus is -- core to rbus interface
generic (
RB_ADDR_CORE : slv8 := slv(to_unsigned(2#00000000#,8));
RB_ADDR_IBUS : slv8 := slv(to_unsigned(2#10000000#,8)));
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RB_STAT : out slv3; -- rbus: status flags
RB_LAM : out slbit; -- remote attention
CPU_RESET : out slbit; -- cpu master reset
CP_CNTL : out cp_cntl_type; -- console control port
CP_ADDR : out cp_addr_type; -- console address port
CP_DIN : out slv16; -- console data in
CP_STAT : in cp_stat_type; -- console status port
CP_DOUT : in slv16 -- console data out
);
end component;
-- ----- move later to pdp11_conf --------------------------------------------
constant conf_vect_pirq : integer := 8#240#;
constant conf_pri_pirq_1 : integer := 1;
constant conf_pri_pirq_2 : integer := 2;
constant conf_pri_pirq_3 : integer := 3;
constant conf_pri_pirq_4 : integer := 4;
constant conf_pri_pirq_5 : integer := 5;
constant conf_pri_pirq_6 : integer := 6;
constant conf_pri_pirq_7 : integer := 7;
end package pdp11;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_pas.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity product_adder_subtracter is
port ( mode : in std_ulogic;
a, b : in std_ulogic_vector(31 downto 0);
s : out std_ulogic_vector(32 downto 0) );
end entity product_adder_subtracter;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_pas.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity product_adder_subtracter is
port ( mode : in std_ulogic;
a, b : in std_ulogic_vector(31 downto 0);
s : out std_ulogic_vector(32 downto 0) );
end entity product_adder_subtracter;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_pas.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity product_adder_subtracter is
port ( mode : in std_ulogic;
a, b : in std_ulogic_vector(31 downto 0);
s : out std_ulogic_vector(32 downto 0) );
end entity product_adder_subtracter;
|
--------------------------------------------------------------------------------
-- Title : internal Wishbone master module
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : wb_master.vhd
-- Author : Susanne Reinfelder
-- Email : [email protected]
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 16.11.2010
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6a / ModelSim AE 6.5e sp1
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- handles Wishbone accesses, writes data from rx_module and returns read
-- data to tx_module
--------------------------------------------------------------------------------
-- Hierarchy :
-- ip_16z091_01
-- rx_module
-- rx_ctrl
-- rx_get_data
-- rx_fifo
-- rx_len_cntr
-- * wb_master
-- wb_slave
-- tx_module
-- tx_ctrl
-- tx_put_data
-- tx_compl_timeout
-- tx_fifo_data
-- tx_fifo_header
-- error
-- err_fifo
-- init
-- interrupt_core
-- interrupt_wb
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.math_real.all;
library work;
use work.src_utils_pkg.all;
entity z091_01_wb_master is
generic(
NR_OF_WB_SLAVES : natural range 63 DOWNTO 1 := 12;
SUSPEND_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111111011"; -- = 1019 DW
RESUME_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111110111" -- = 1015 DW
);
port(
wb_clk : in std_logic;
wb_rst : in std_logic;
-- Rx Module
rx_fifo_wr_out : in std_logic_vector(31 downto 0);
rx_fifo_wr_empty : in std_logic;
rx_fifo_wr_rd_enable : out std_logic;
-- Tx Module
tx_fifo_c_head_full : in std_logic;
tx_fifo_c_data_full : in std_logic;
tx_fifo_c_data_usedw : in std_logic_vector(9 downto 0);
tx_fifo_c_head_enable : out std_logic;
tx_fifo_c_data_enable : out std_logic;
tx_fifo_c_head_in : out std_logic_vector(31 downto 0);
tx_fifo_c_data_in : out std_logic_vector(31 downto 0);
tx_fifo_c_data_clr : out std_logic;
tx_fifo_c_head_clr : out std_logic;
-- Wishbone
wbm_ack : in std_logic;
wbm_dat_i : in std_logic_vector(31 downto 0);
wbm_stb : out std_logic;
--wbm_cyc : out std_logic;
wbm_cyc_o : out std_logic_vector(NR_OF_WB_SLAVES - 1 downto 0); --new
wbm_we : out std_logic;
wbm_sel : out std_logic_vector(3 downto 0);
wbm_adr : out std_logic_vector(31 downto 0);
wbm_dat_o : out std_logic_vector(31 downto 0);
wbm_cti : out std_logic_vector(2 downto 0);
wbm_tga : out std_logic; -- wbm_tga(0)=1 if ECRC error occured
--wb_bar_dec : out std_logic_vector(6 downto 0); -- decoded BAR for wb_adr_dec.vhd mwawrik: no longer necessary
-- error
ecrc_err_in : in std_logic; -- input from error module
err_tag_id : in std_logic_vector(7 downto 0);
ecrc_err_out : out std_logic -- output of 16z091-01
);
end entity z091_01_wb_master;
-- ****************************************************************************
architecture z091_01_wb_master_arch of z091_01_wb_master is
component z091_01_wb_adr_dec
generic(
NR_OF_WB_SLAVES : integer range 63 downto 1 := 1
);
port (
pci_cyc_i : in std_logic_vector(6 downto 0);
wbm_adr_o_q : in std_logic_vector(31 downto 2);
wbm_cyc_o : out std_logic_vector(NR_OF_WB_SLAVES -1 downto 0)
);
end component;
-- FSM state encoding ---------------------------------------------------------
type fsm_state is (
PREPARE_FIFO, IDLE, GET_HEADER_0, GET_HEADER_1, GET_HEADER_2, GET_WR_DATA, START_TRANS,
TRANSMIT, WAIT_ON_FIFO, PUT_HEADER_0, PUT_HEADER_1, PUT_HEADER_2, GET_Z
);
signal state : fsm_state;
-------------------------------------------------------------------------------
-- constants ------------------------------------------------------------------
constant ADDR_INCR : std_logic_vector(13 downto 0) := "00000000000100"; -- address increment for burst access
-------------------------------------------------------------------------------
-- internal signals -----------------------------------------------------------
signal get_data : std_logic;
signal decode_header : std_logic_vector(1 downto 0); -- 00 = idle, 01 = H0, 10 = H1, 11 = H3
signal data_to_wb : std_logic;
signal data_to_fifo : std_logic;
signal listen_to_ack : std_logic;
signal write_header : std_logic_vector(1 downto 0); -- 00 = idle, 01 = H0, 10 = H1, 11 = H3
signal wr_en_int : std_logic; -- write flag, 0 = read, 1 = write
signal attr_int : std_logic_vector(2 downto 0);
signal tc_int : std_logic_vector(2 downto 0);
signal req_id_int : std_logic_vector(15 downto 0);
signal addr_int : std_logic_vector(31 downto 0);
signal tag_id_int : std_logic_vector(7 downto 0);
signal first_dw_int : std_logic_vector(3 downto 0);
signal last_dw_int : std_logic_vector(3 downto 0);
signal length_int : std_logic_vector(9 downto 0);
signal data_q : std_logic_vector(31 downto 0);
signal data_qq : std_logic_vector(31 downto 0);
signal cnt_len_wb : std_logic_vector(10 downto 0); -- count amount of data tranfered through wishbone
signal cnt_len_fifo : std_logic_vector(10 downto 0); -- count amount of data taken from fifo
signal addr_offset : std_logic_vector(13 downto 0);
signal wait_clk : integer range 2 downto 0 := 0;
signal q_to_wbm : std_logic_vector(1 downto 0);
signal wbm_ack_int : std_logic;
signal err_tag_id_int : std_logic_vector(7 downto 0);
signal byte_count_int : std_logic_vector(11 downto 0);
signal suspend : std_logic;
signal goto_start : std_logic;
signal bar_dec_int : std_logic_vector(6 downto 0); -- decode which BAR was hit, only one bit may be set at a time
signal aligned_int : std_logic;
signal transmission : std_logic;
signal io_wr_int : std_logic;
signal wb_bar_dec_int : std_logic_vector(6 downto 0);
signal wb_bar_dec_int_d : std_logic_vector(6 downto 0);
signal ecrc_err_int : std_logic;
signal wbm_cyc_o_int : std_logic_vector(NR_OF_WB_SLAVES -1 downto 0);
-------------------------------------------------------------------------------
begin
z091_01_wb_adr_dec_comp : z091_01_wb_adr_dec
generic map(
NR_OF_WB_SLAVES => NR_OF_WB_SLAVES
)
port map(
pci_cyc_i => wb_bar_dec_int,
wbm_adr_o_q => addr_int(31 downto 2),
wbm_cyc_o => wbm_cyc_o_int
);
wb_bar_dec_int <= bar_dec_int when (state = START_TRANS) or
(state = WAIT_ON_FIFO and tx_fifo_c_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_c_data_usedw /= ZERO_10B
and tx_fifo_c_data_full = '0' and goto_start = '0') else
(OTHERS => '0') when (state = IDLE) or
(state = START_TRANS and wbm_ack = '1' and wr_en_int = '1' and cnt_len_wb = ZERO_11B) or
state = GET_Z or state = PUT_HEADER_0
else
wb_bar_dec_int_d;
--wb_bar_dec <= wb_bar_dec_int_d; --mwawrik: no longer necessary because out-pin wb_bar_dec removed
ecrc_err_int <= '0' when wb_rst = '1' else
'0' when state = TRANSMIT else
'1' when state /= TRANSMIT and ecrc_err_in = '1';
-------------------------------------------------------------------------------
fsm_trans : process(wb_rst, wb_clk)
begin
if(wb_rst = '1') then
state <= IDLE;
elsif(wb_clk'event and wb_clk = '1') then
case state is
when IDLE =>
if(rx_fifo_wr_empty = '0') then
state <= PREPARE_FIFO;
else
state <= IDLE;
end if;
when PREPARE_FIFO =>
state <= GET_HEADER_0;
when GET_HEADER_0 =>
state <= GET_HEADER_1;
when GET_HEADER_1 =>
state <= GET_HEADER_2;
when GET_HEADER_2 =>
if((tx_fifo_c_data_usedw > SUSPEND_FIFO_ACCESS or tx_fifo_c_data_full = '1') and wr_en_int = '0') then
state <= WAIT_ON_FIFO;
elsif(rx_fifo_wr_out(2) = '0') then
------------------------
-- transfer is aligned
------------------------
state <= GET_Z;
elsif(rx_fifo_wr_out(2) = '1' and wr_en_int = '1') then
state <= GET_WR_DATA;
elsif(rx_fifo_wr_out(2) = '1' and wr_en_int = '0') then
state <= START_TRANS;
end if;
when GET_WR_DATA =>
if(length_int = ONE_10B or ((length_int > ONE_10B or length_int = ZERO_10B) and wait_clk = 1)) then
state <= START_TRANS;
else
state <= GET_WR_DATA;
end if;
when START_TRANS =>
if(cnt_len_wb > ZERO_11B) then
state <= TRANSMIT;
elsif(cnt_len_wb <= ZERO_11B and wbm_ack = '1' and wr_en_int = '1') then
state <= IDLE;
elsif(cnt_len_wb <= ZERO_11B and (wbm_ack = '1' or wr_en_int = '0')) then
state <= START_TRANS;
end if;
when TRANSMIT =>
if(wbm_ack = '1' and (wr_en_int = '0' or (io_wr_int = '1' and aligned_int = '0')) and ((tx_fifo_c_data_usedw > SUSPEND_FIFO_ACCESS and cnt_len_wb /= ZERO_11B) or cnt_len_wb = ZERO_11B)) then
state <= PUT_HEADER_0;
elsif(wbm_ack = '1' and cnt_len_wb = ZERO_11B and wr_en_int = '1' and ((addr_int(2) = '0' and length_int(0) = '0') or
(addr_int(2) = '1' and length_int(0) = '1'))) then
state <= IDLE;
elsif(wbm_ack = '1' and cnt_len_wb = ZERO_11B and wr_en_int = '1' and ((addr_int(2) = '0' and length_int(0) = '1') or
(addr_int(2) = '1' and length_int(0) = '0') or (io_wr_int = '1' and aligned_int = '1'))) then
state <= GET_Z;
else
state <= TRANSMIT;
end if;
when WAIT_ON_FIFO =>
if(tx_fifo_c_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_c_data_usedw /= ZERO_10B and tx_fifo_c_data_full = '0' and goto_start = '1') then
state <= START_TRANS;
elsif(tx_fifo_c_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_c_data_usedw /= ZERO_10B and tx_fifo_c_data_full = '0' and goto_start = '0') then
state <= TRANSMIT;
else
state <= WAIT_ON_FIFO;
end if;
when PUT_HEADER_0 =>
state <= PUT_HEADER_1;
when PUT_HEADER_1 =>
if(wr_en_int = '0' or io_wr_int = '1') then
state <= PUT_HEADER_2;
else
state <= IDLE;
end if;
when PUT_HEADER_2 =>
if(wait_clk = 1 and suspend = '0') then
state <= IDLE;
elsif(suspend = '1') then
state <= WAIT_ON_FIFO;
else
state <= PUT_HEADER_2;
end if;
when GET_Z =>
if(io_wr_int = '1' and aligned_int = '1' and transmission = '0') then
state <= PUT_HEADER_0;
elsif(transmission = '1' and wr_en_int = '1') then
state <= GET_WR_DATA;
elsif(transmission = '1' and wr_en_int = '0') then
state <= START_TRANS;
else
state <= IDLE;
end if;
-- coverage off
when others =>
-- synthesis translate_off
report "reached unknown FSM state in process fsm_trans of z091_01_wb_master.vhd" severity error;
-- synthesis translate_on
state <= IDLE;
-- coverage on
end case;
end if;
end process fsm_trans;
-------------------------------------------------------------------------------
fsm_out : process(wb_rst, wb_clk)
begin
if(wb_rst = '1') then
rx_fifo_wr_rd_enable <= '0';
tx_fifo_c_head_enable <= '0';
tx_fifo_c_data_enable <= '0';
tx_fifo_c_data_clr <= '1';
tx_fifo_c_head_clr <= '1';
wbm_stb <= '0';
wbm_cyc_o <= (others => '0');
wbm_we <= '0';
wbm_sel <= (others => '0');
wbm_adr <= (others => '0');
wbm_cti <= (others => '0');
wbm_tga <= '0';
ecrc_err_out <= '0';
get_data <= '0';
decode_header <= (others => '0');
data_to_wb <= '0';
data_to_fifo <= '0';
listen_to_ack <= '0';
write_header <= (others => '0');
cnt_len_wb <= (others => '0');
cnt_len_fifo <= (others => '0');
addr_offset <= (others => '0');
wait_clk <= 0;
q_to_wbm <= (others => '0');
wbm_ack_int <= '0';
err_tag_id_int <= x"FF"; -- init with a value greater than allowed 32 tags
byte_count_int <= (others => '0');
suspend <= '0';
goto_start <= '0';
aligned_int <= '0';
transmission <= '0';
elsif(wb_clk'event and wb_clk = '1') then
wb_bar_dec_int_d <= wb_bar_dec_int;
if(state = PREPARE_FIFO) then
transmission <= '1';
elsif(state = TRANSMIT) then
transmission <= '0';
end if;
-- determine data alignment which decides whether first packet after header2 is empty or contains first data packet
if(state = GET_HEADER_2 and rx_fifo_wr_out(2) = '0') then
aligned_int <= '1';
elsif(state = IDLE) then
aligned_int <= '0';
end if;
if((state = IDLE and rx_fifo_wr_empty = '1') or state = START_TRANS or state = WAIT_ON_FIFO or
(state = GET_Z and (transmission = '0' or wr_en_int = '0' or (wr_en_int = '1' and aligned_int = '1' and length_int = ONE_10B))) or
(state = GET_HEADER_2 and (wr_en_int = '0' or (wr_en_int = '1' and length_int = ONE_10B and rx_fifo_wr_out(2) = '1'))) or
(state = TRANSMIT and wbm_ack = '1' and cnt_len_fifo = ONE_11B) or
(state = GET_WR_DATA and ((length_int = TWO_10B and wait_clk = 0) or (length_int = THREE_10B and wait_clk = 1))) or
(state = TRANSMIT and wbm_ack = '0')
) then
rx_fifo_wr_rd_enable <= '0';
elsif((state = IDLE and rx_fifo_wr_empty = '0') or
(state = GET_Z and transmission = '1' and wr_en_int = '1') or
(state = TRANSMIT and wbm_ack = '1' and wr_en_int = '1' and ((cnt_len_wb = ZERO_11B and ((addr_int(2) = '0' and length_int(0) = '1') or
(addr_int(2) = '1' and length_int(0) = '0'))) or cnt_len_fifo > ONE_11B))) then
rx_fifo_wr_rd_enable <= '1';
end if;
if(state = IDLE or state = GET_Z or (state = WAIT_ON_FIFO and wait_clk = 1)) then
tx_fifo_c_head_enable <= '0';
elsif(state = PUT_HEADER_0) then
tx_fifo_c_head_enable <= '1';
end if;
if(state = IDLE or (state = PUT_HEADER_2 and length_int(0) = '1')) then
tx_fifo_c_data_enable <= '0';
elsif(state = TRANSMIT or state = PUT_HEADER_0 or (state = PUT_HEADER_1 and length_int(0) = '0') ) then
tx_fifo_c_data_enable <= wbm_ack_int;
end if;
if(state = IDLE or (state = START_TRANS and wbm_ack = '1' and wr_en_int = '1' and cnt_len_wb = ZERO_11B) or
(state = TRANSMIT and wbm_ack = '1' and (cnt_len_wb = ZERO_11B or (tx_fifo_c_data_usedw > SUSPEND_FIFO_ACCESS and
cnt_len_wb /= ZERO_11B and wr_en_int = '0'))) ) then
wbm_stb <= '0';
elsif(state = START_TRANS or
(state = WAIT_ON_FIFO and tx_fifo_c_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_c_data_usedw /= ZERO_10B and
tx_fifo_c_data_full = '0' and goto_start = '0') ) then
wbm_stb <= '1';
end if;
--wbm_cyc never used before and now it is removed
--if(state = IDLE or (state = START_TRANS and wbm_ack = '1' and wr_en_int = '1' and cnt_len_wb = ZERO_11B) or
-- (state = TRANSMIT and wbm_ack = '1' and (cnt_len_wb = ZERO_11B or (tx_fifo_c_data_usedw > SUSPEND_FIFO_ACCESS and
-- cnt_len_wb /= ZERO_11B and wr_en_int = '0'))) ) then
-- wbm_cyc <= '0';
--elsif(state = START_TRANS or
-- (state = WAIT_ON_FIFO and tx_fifo_c_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_c_data_usedw /= ZERO_10B and
-- tx_fifo_c_data_full = '0' and goto_start = '0') ) then
-- wbm_cyc <= '1';
--end if;
if(state = IDLE or (cnt_len_wb = ZERO_11B and wbm_ack = '1' and (state = TRANSMIT or (state = START_TRANS and wr_en_int = '1')))) then
wbm_we <= '0';
elsif(state = START_TRANS and wr_en_int = '1') then
wbm_we <= '1';
end if;
if(state = IDLE or (cnt_len_wb = ZERO_11B and wbm_ack = '1' and (state = TRANSMIT or (state = START_TRANS and wr_en_int = '1')))) then
wbm_sel <= (others => '0');
elsif(state = START_TRANS) then
wbm_sel <= first_dw_int;
elsif(state = TRANSMIT and wbm_ack = '1' and cnt_len_wb > ONE_11B) then
wbm_sel <= x"F";
elsif(state = TRANSMIT and wbm_ack = '1' and cnt_len_wb = ONE_11B) then
wbm_sel <= last_dw_int;
end if;
----------------------------------------
-- manage Wishbone address
-- add addr_offset during transmission
----------------------------------------
if(state = START_TRANS or (state = TRANSMIT and wbm_ack = '1')) then
wbm_adr <= addr_int + addr_offset;
--else
--wbm_adr <= addr_int;
end if;
-- calculate address offset
if(state = IDLE) then
addr_offset <= (others => '0');
elsif(state = START_TRANS or (state = TRANSMIT and wbm_ack = '1')) then
addr_offset <= addr_offset + ADDR_INCR;
end if;
-- add wbm_cyc_o to be registered
if((state = START_TRANS and suspend = '0' and length_int /= ONE_10B) or
(state = WAIT_ON_FIFO and tx_fifo_c_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_c_data_usedw /= ZERO_10B and
tx_fifo_c_data_full = '0' and goto_start = '0' and cnt_len_wb > ZERO_11B) ) then
wbm_cti <= "010";
wbm_cyc_o <= wbm_cyc_o_int;
elsif((state = START_TRANS and suspend = '0' and length_int = ONE_10B) or
(state = TRANSMIT and wbm_ack = '1' and (cnt_len_wb = ONE_11B or (tx_fifo_c_data_usedw = SUSPEND_FIFO_ACCESS and
wr_en_int = '0'))) or
(state = WAIT_ON_FIFO and tx_fifo_c_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_c_data_usedw /= ZERO_10B and
tx_fifo_c_data_full = '0' and goto_start = '0' and cnt_len_wb <= ZERO_11B) ) then
wbm_cti <= "111";
wbm_cyc_o <= wbm_cyc_o_int;
elsif(wbm_ack = '1' and cnt_len_wb = ZERO_11B and (state = TRANSMIT or (state = START_TRANS and wr_en_int = '1')) ) then
wbm_cti <= "000";
wbm_cyc_o <= (OTHERS=>'0');
end if;
if(state = IDLE or (state = TRANSMIT and wbm_ack = '1' and cnt_len_wb = ZERO_11B)) then
wbm_tga <= '0';
elsif(state = START_TRANS and err_tag_id_int = tag_id_int) then
wbm_tga <= '1';
end if;
if(state = IDLE or (state = TRANSMIT and wbm_ack = '1' and cnt_len_wb = ZERO_11B)) then
ecrc_err_out <= '0';
elsif(state = START_TRANS and ecrc_err_int = '1' and err_tag_id_int = tag_id_int) then
ecrc_err_out <= '1';
end if;
if(state = IDLE or state = START_TRANS or (state = GET_HEADER_2 and wr_en_int = '0') or (state = GET_WR_DATA and length_int = ONE_10B) or
(state = TRANSMIT and ((wbm_ack = '0' or wr_en_int = '0' or cnt_len_wb = ZERO_11B) or (wbm_ack = '1' and cnt_len_wb = ZERO_11B))) ) then
get_data <= '0';
elsif((state = GET_HEADER_2 and rx_fifo_wr_out(2) = '1' and wr_en_int = '1') or (state = GET_WR_DATA and length_int /= ONE_10B) or
(state = TRANSMIT and wbm_ack = '1' and wr_en_int = '1' and cnt_len_wb > ZERO_11B) or
(state = GET_Z and aligned_int = '1' and wr_en_int = '1')
) then
get_data <= '1';
end if;
if(state = IDLE or state = GET_WR_DATA or state = START_TRANS or state = GET_HEADER_2) then
decode_header <= (others => '0');
elsif(state = PREPARE_FIFO) then
decode_header <= "01";
elsif(state = GET_HEADER_0) then
decode_header <= "10";
elsif(state = GET_HEADER_1) then
decode_header <= "11";
end if;
if(state = IDLE or state = START_TRANS or (state = TRANSMIT and wbm_ack = '1' and cnt_len_wb = ZERO_11B)) then
data_to_wb <= '0';
elsif(state = GET_WR_DATA and wr_en_int = '1' and (length_int = ONE_10B or wait_clk = 1)) then
data_to_wb <= '1';
end if;
if(state = IDLE or (state = START_TRANS and wbm_ack = '1' and wr_en_int = '1' and cnt_len_wb = ZERO_11B)) then
data_to_fifo <= '0';
elsif(wr_en_int = '0' and (state = START_TRANS or state = TRANSMIT)) then
data_to_fifo <= '1';
end if;
if(state = IDLE or
(wbm_ack = '1' and cnt_len_wb = ZERO_11B and ((state = START_TRANS and wr_en_int = '1') or state = TRANSMIT)) ) then
listen_to_ack <= '0';
elsif(state = START_TRANS and wr_en_int = '1') then
listen_to_ack <= '1';
end if;
if(state = IDLE) then
write_header <= (others => '0');
elsif(state = TRANSMIT and wbm_ack = '1' and (wr_en_int = '0' or io_wr_int = '1') and (cnt_len_wb = ZERO_11B or
(tx_fifo_c_data_usedw > SUSPEND_FIFO_ACCESS and cnt_len_wb /= ZERO_11B)) ) then
write_header <= "01";
elsif(state = PUT_HEADER_0) then
write_header <= "10";
elsif(state = PUT_HEADER_1 and (wr_en_int = '0' or io_wr_int = '1')) then
write_header <= "11";
end if;
-- calculate length counters for Wishbone transactions and decrement when necessary
if(state = IDLE) then
cnt_len_wb <= (others => '0');
elsif(state = GET_HEADER_1 and length_int = ZERO_10B) then
cnt_len_wb <= '1' & length_int;
elsif(state = GET_HEADER_1 and length_int /= ZERO_10B) then
cnt_len_wb <= '0' & length_int;
elsif(cnt_len_wb > ZERO_11B and (state = START_TRANS or (state = TRANSMIT and wbm_ack = '1')) ) then
cnt_len_wb <= cnt_len_wb - ONE_11B;
end if;
-- calculate length counters for FIFO transactions and decrement when necessary
if(state = IDLE) then
cnt_len_fifo <= (others => '0');
elsif(state = GET_HEADER_1 and length_int = ZERO_10B) then
cnt_len_fifo <= '1' & length_int;
elsif(state = GET_HEADER_1 and length_int /= ZERO_10B) then
cnt_len_fifo <= '0' & length_int;
elsif(wr_en_int = '1' and cnt_len_fifo > ZERO_11B and (state = GET_WR_DATA or state = START_TRANS or
(state = TRANSMIT and wbm_ack = '1')) ) then
cnt_len_fifo <= cnt_len_fifo - ONE_11B;
end if;
if(state = IDLE or state = GET_HEADER_1 or state = PUT_HEADER_1 or (state = PUT_HEADER_2 and suspend = '1') or
(state = WAIT_ON_FIFO and tx_fifo_c_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_c_data_usedw /= ZERO_10B and
tx_fifo_c_data_full = '0' and goto_start = '0') ) then
wait_clk <= 0;
elsif(state = GET_WR_DATA or (state = WAIT_ON_FIFO and wait_clk < 1) or (state = PUT_HEADER_2 and suspend = '0')) then
wait_clk <= wait_clk + 1;
end if;
if(state = IDLE) then
q_to_wbm <= (others => '0');
elsif((state = GET_HEADER_1 and length_int = ONE_10B) or (state = TRANSMIT and wbm_ack = '1')) then
q_to_wbm <= "01";
elsif((state = GET_HEADER_1 and length_int /= ONE_10B) or (state = TRANSMIT and wbm_ack = '0')) then
q_to_wbm <= "10";
end if;
if(state = IDLE or (wbm_ack = '0' and wr_en_int = '0' and (state = TRANSMIT or state = PUT_HEADER_0 or state = PUT_HEADER_1))) then
wbm_ack_int <= '0';
elsif(wbm_ack = '1' and wr_en_int = '0' and (state = TRANSMIT or state = PUT_HEADER_0 or state = PUT_HEADER_1)) then
wbm_ack_int <= '1';
end if;
-- capture ecrc error
if(state = IDLE and ecrc_err_in = '0') then
err_tag_id_int <= (others => '0');
elsif(ecrc_err_in = '1' and (state = IDLE or state = GET_HEADER_0 or state = GET_HEADER_1 or state = GET_HEADER_2 or
state = GET_WR_DATA)) then
err_tag_id_int <= err_tag_id;
end if;
-- calculate byte count
-- correct byte count value according to first_dw_int value as defined in PCIe base specification in state PUT_HEADER_0
if(state = IDLE) then
byte_count_int <= (others => '0');
elsif(wbm_ack = '1' and (state = TRANSMIT or (state = START_TRANS and wr_en_int = '1' and cnt_len_wb = 0))) then
byte_count_int <= byte_count_int + FOUR_12B;
elsif(state = PUT_HEADER_0 and length_int = ONE_10B and (first_dw_int = ZERO_04B or first_dw_int = EIGHT_04B or first_dw_int = FOUR_04B or first_dw_int = TWO_04B or first_dw_int = ONE_04B)) then
byte_count_int <= ONE_12B;
elsif(state = PUT_HEADER_0 and length_int = ONE_10B and (first_dw_int = C_04B or first_dw_int = SIX_04B or first_dw_int = THREE_04B)) then
byte_count_int <= TWO_12B;
elsif(state = PUT_HEADER_0 and length_int = ONE_10B and ((first_dw_int(3) = '1' and first_dw_int(1 downto 0) = TWO_02B) or (first_dw_int(3 downto 2) = ONE_02B and first_dw_int(0) = '1'))) then
byte_count_int <= THREE_12B;
elsif(state = PUT_HEADER_0 and length_int = ONE_10B and first_dw_int(3) = '1' and first_dw_int(0) = '1') then
byte_count_int <= FOUR_12B;
elsif(state = PUT_HEADER_0 and length_int /= ONE_10B and ((first_dw_int(0) = '1' and last_dw_int(3 downto 2) = ONE_02B) or (first_dw_int(1 downto 0) = TWO_02B and last_dw_int(3) = '1'))) then
byte_count_int <= byte_count_int - ONE_12B;
elsif(state = PUT_HEADER_0 and length_int /= ONE_10B and ((first_dw_int(0) = '1' and last_dw_int(3 downto 1) = ONE_03B) or (first_dw_int(1 downto 0) = TWO_02B and last_dw_int(3 downto 2) = ONE_02B) or (first_dw_int(2 downto 0) = FOUR_03B and last_dw_int(3) = '1'))) then
byte_count_int <= byte_count_int - TWO_12B;
elsif(state = PUT_HEADER_0 and length_int /= ONE_10B and ((first_dw_int(0) = '1' and last_dw_int = ONE_04B) or (first_dw_int(1 downto 0) = ONE_02B and last_dw_int(3 downto 1) = ONE_03B) or (first_dw_int(2 downto 0) = FOUR_03B and last_dw_int(3 downto 2) = ONE_02B) or (first_dw_int = EIGHT_04B and last_dw_int(3) = '1'))) then
byte_count_int <= byte_count_int - THREE_12B;
elsif(state = PUT_HEADER_0 and length_int /= ONE_10B and ((first_dw_int(1 downto 0) = TWO_02B and last_dw_int = ONE_04B) or (first_dw_int(2 downto 0) = FOUR_03B and last_dw_int(3 downto 1) = ONE_03B) or (first_dw_int = EIGHT_04B and last_dw_int(3 downto 2) = ONE_02B))) then
byte_count_int <= byte_count_int - FOUR_12B;
elsif(state = PUT_HEADER_0 and length_int /= ONE_10B and ((first_dw_int = EIGHT_04B and last_dw_int(3 downto 1) = ONE_03B) or (first_dw_int(2 downto 0) = FOUR_03B and last_dw_int = ONE_04B))) then
byte_count_int <= byte_count_int - FIVE_12B;
elsif(state = PUT_HEADER_0 and length_int /= ONE_10B and first_dw_int = EIGHT_04B and last_dw_int = ONE_04B) then
byte_count_int <= byte_count_int - SIX_12B;
end if;
-- suspend all actions when FIFO is full until there is space in FIFO again
if(state = IDLE or
(state = WAIT_ON_FIFO and tx_fifo_c_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_c_data_usedw /= ZERO_10B and
tx_fifo_c_data_full = '0')) then
suspend <= '0';
elsif((state = GET_HEADER_2 and (tx_fifo_c_data_usedw > SUSPEND_FIFO_ACCESS or tx_fifo_c_data_full = '1') and wr_en_int = '0') or
(state = TRANSMIT and wbm_ack = '1' and tx_fifo_c_data_usedw > SUSPEND_FIFO_ACCESS and cnt_len_wb /= ZERO_11B and
wr_en_int = '0')) then
suspend <= '1';
end if;
if(state = IDLE or
(state = WAIT_ON_FIFO and tx_fifo_c_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_c_data_usedw /= ZERO_10B and
tx_fifo_c_data_full = '0' and goto_start = '1')) then
goto_start <= '0';
elsif(state = GET_HEADER_2 and (tx_fifo_c_data_usedw > SUSPEND_FIFO_ACCESS or tx_fifo_c_data_full = '1')) then
goto_start <= '1';
end if;
if(state = IDLE) then
tx_fifo_c_data_clr <= '0';
tx_fifo_c_head_clr <= '0';
end if;
end if;
end process fsm_out;
-------------------------------------------------------------------------------
data_path : process(wb_clk, wb_rst, wbm_ack)
begin
if(wb_rst = '1') then
-- ports:
tx_fifo_c_head_in <= (others => '0');
tx_fifo_c_data_in <= (others => '0');
wbm_dat_o <= (others => '0');
-- signals:
data_q <= (others => '0');
data_qq <= (others => '0');
wr_en_int <= '0';
attr_int <= (others => '0');
tc_int <= (others => '0');
req_id_int <= (others => '0');
addr_int <= (others => '0');
tag_id_int <= (others => '0');
first_dw_int <= (others => '0');
last_dw_int <= (others => '0');
length_int <= (others => '0');
bar_dec_int <= (others => '0');
io_wr_int <= '0';
else
if(wb_clk'event and wb_clk = '1') then
if(decode_header = "01") then
-- decode which BAR was hit
case rx_fifo_wr_out(28 downto 26) is
when "000" =>
bar_dec_int(0) <= '1';
bar_dec_int(6 downto 1) <= (others => '0');
when "001" =>
bar_dec_int(0) <= '0';
bar_dec_int(1) <= '1';
bar_dec_int(6 downto 2) <= (others => '0');
when "010" =>
bar_dec_int(1 downto 0) <= (others => '0');
bar_dec_int(2) <= '1';
bar_dec_int(6 downto 3) <= (others => '0');
when "011" =>
bar_dec_int(2 downto 0) <= (others => '0');
bar_dec_int(3) <= '1';
bar_dec_int(6 downto 4) <= (others => '0');
when "100" =>
bar_dec_int(3 downto 0) <= (others => '0');
bar_dec_int(4) <= '1';
bar_dec_int(6 downto 5) <= (others => '0');
when "101" =>
bar_dec_int(4 downto 0) <= (others => '0');
bar_dec_int(5) <= '1';
bar_dec_int(6) <= '0';
when "110" =>
bar_dec_int(5 downto 0) <= (others => '0');
bar_dec_int(6) <= '1';
-- coverage off
when others =>
bar_dec_int <= (0 => '1', others => '0');
-- synthesis translate_off
report "Error while decoding BAR" severity error;
-- synthesis translate_on
-- coverage on
end case;
-- split value of data bus into its components
wr_en_int <= rx_fifo_wr_out(31);
io_wr_int <= rx_fifo_wr_out(30) and rx_fifo_wr_out(31);
first_dw_int <= rx_fifo_wr_out(17 downto 14);
last_dw_int <= rx_fifo_wr_out(13 downto 10);
length_int <= rx_fifo_wr_out(9 downto 0);
tag_id_int <= rx_fifo_wr_out(25 downto 18);
elsif(decode_header = "10") then
attr_int <= rx_fifo_wr_out(21 downto 19);
tc_int <= rx_fifo_wr_out(18 downto 16);
req_id_int <= rx_fifo_wr_out(15 downto 0);
elsif(decode_header = "11") then
addr_int <= rx_fifo_wr_out;
end if;
-- manage data registering pipeline
if(get_data = '1' and wr_en_int = '1') then
data_q <= rx_fifo_wr_out;
data_qq <= data_q;
elsif(get_data = '1' and wr_en_int = '0') then
data_q <= wbm_dat_i;
end if;
-- route registered data signals to output port
if(listen_to_ack = '1' and wbm_ack = '1') then
case q_to_wbm is
when "01" =>
wbm_dat_o <= data_q;
when "10" =>
wbm_dat_o <= data_qq;
when "11" =>
-- coverage off
when others =>
-- synthesis translate_off
report "Reached undecoded state of signal q_to_wbm" severity error;
-- synthesis translate_on
-- coverage on
end case;
elsif(data_to_wb = '1') then
case q_to_wbm is
when "01" =>
wbm_dat_o <= data_q;
when "10" =>
wbm_dat_o <= data_qq;
when "11" =>
-- coverage off
when others =>
-- synthesis translate_off
report "Reached undecoded state of signal q_to_wbm" severity error;
-- synthesis translate_on
-- coverage on
end case;
elsif(data_to_fifo = '1') then
data_q <= wbm_dat_i;
tx_fifo_c_data_in <= data_q;
end if;
-- asseble tx data packet
if(write_header = "01") then
tx_fifo_c_head_in(31 downto 29) <= attr_int;
tx_fifo_c_head_in(28 downto 26) <= tc_int;
tx_fifo_c_head_in(25 downto 18) <= tag_id_int;
tx_fifo_c_head_in(17 downto 14) <= first_dw_int;
tx_fifo_c_head_in(13 downto 10) <= last_dw_int;
tx_fifo_c_head_in(9 downto 0) <= length_int;
elsif(write_header = "10") then
tx_fifo_c_head_in <= addr_int;
elsif(write_header = "11") then
tx_fifo_c_head_in(31 downto 29) <= (others => '0');
tx_fifo_c_head_in(28) <= io_wr_int;
if(io_wr_int = '1') then
tx_fifo_c_head_in(27 downto 16) <= "000000000100";
else
tx_fifo_c_head_in(27 downto 16) <= byte_count_int;
end if;
tx_fifo_c_head_in(15 downto 0) <= req_id_int;
else
tx_fifo_c_head_in <= (others => '0');
end if;
end if;
end if;
end process data_path;
-------------------------------------------------------------------------------
end architecture z091_01_wb_master_arch;
|
-------------------------------------------------------------------------------
-- Copyright (c) 2015 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application: XILINX CORE Generator
-- / / Filename : CSP_PB_Tracer_ILA.vhd
-- /___/ /\ Timestamp : Tue May 26 23:06:57 Mitteleuropäische Sommerzeit 2015
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY CSP_PB_Tracer_ILA IS
port (
CONTROL: inout std_logic_vector(35 downto 0);
CLK: in std_logic;
DATA: in std_logic_vector(62 downto 0);
TRIG0: in std_logic_vector(14 downto 0);
TRIG1: in std_logic_vector(7 downto 0);
TRIG2: in std_logic_vector(5 downto 0);
TRIG3: in std_logic_vector(15 downto 0);
TRIG_OUT: out std_logic);
END CSP_PB_Tracer_ILA;
ARCHITECTURE CSP_PB_Tracer_ILA_a OF CSP_PB_Tracer_ILA IS
BEGIN
END CSP_PB_Tracer_ILA_a;
|
---------------------------------------------------------------------------------------------------
--
-- Title : zcpsmProgRom
-- Design : eth_new
-- Author : a4a881d4
-- Company : a4a881d4
--
---------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
entity zcpsmProgRom is
generic (
AWIDTH : natural := 10;
PROG : string := "program.bit"
);
port (
clk : in std_logic;
addr : in std_logic_vector( AWIDTH-1 downto 0 );
dout : out std_logic_vector( 17 downto 0 )
);
end zcpsmProgRom;
architecture syn of zcpsmProgRom is
type RamType is array( 0 to (2**AWIDTH-1) ) of bit_vector( 17 downto 0 );
impure function InitRamFromFile (RamFileName : in string) return RamType is
FILE RamFile : text is in RamFileName;
variable RamFileLine : line;
variable RAM : RamType;
begin
for I in RamType'range loop
readline (RamFile, RamFileLine);
read (RamFileLine, RAM(I));
end loop;
return RAM;
end function;
signal RAM : RamType := InitRamFromFile(PROG);
begin
process (clk)
begin
if clk'event and clk = '1' then
dout <= to_stdlogicvector(RAM(conv_integer(addr)));
end if;
end process;
end syn;
|
-- NEED RESULT: ARCH00061.P1: Body of 'for' loop is executed once for each value in the discrete range passed
-- NEED RESULT: ARCH00061.P2: Body of 'for' loop is executed once for each value in the discrete range passed
-- NEED RESULT: ARCH00061.P3: Body of 'for' loop is executed once for each value in the discrete range passed
-- NEED RESULT: ARCH00061.P4: Body of 'for' loop is executed once for each value in the discrete range passed
-- NEED RESULT: ARCH00061.P5: Body of 'for' loop is executed once for each value in the discrete range passed
-- NEED RESULT: ARCH00061.P6: Body of 'for' loop is executed once for each value in the discrete range passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00061
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.8 (6)
-- 8.8 (8)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00061)
-- ENT00061_Test_Bench(ARCH00061_Test_Bench)
--
-- REVISION HISTORY:
--
-- 06-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00061 of E00000 is
signal Dummy : Boolean := false ;
begin
P1 :
process ( Dummy )
variable correct : boolean ;
variable count : integer := 0 ;
--
procedure Proc1 (
lowb, highb : boolean ;
counter : inout integer
) is
begin
L1 :
for i in lowb to highb loop
counter := counter + 1 ;
end loop L1 ;
end Proc1 ;
--
begin
Proc1 (boolean'Low, boolean'High, count) ;
correct := count =
(boolean'Pos (boolean'High) -
boolean'Pos (boolean'Low) + 1) ;
test_report ( "ARCH00061.P1" ,
"Body of 'for' loop is executed once " &
"for each value in the discrete range",
correct ) ;
--
end process P1 ;
--
P2 :
process ( Dummy )
variable correct : boolean ;
variable count : integer := 0 ;
--
procedure Proc1 (
lowb, highb : bit ;
counter : inout integer
) is
begin
L1 :
for i in lowb to highb loop
counter := counter + 1 ;
end loop L1 ;
end Proc1 ;
--
begin
Proc1 (bit'Low, bit'High, count) ;
correct := count =
(bit'Pos (bit'High) -
bit'Pos (bit'Low) + 1) ;
test_report ( "ARCH00061.P2" ,
"Body of 'for' loop is executed once " &
"for each value in the discrete range",
correct ) ;
--
end process P2 ;
--
P3 :
process ( Dummy )
variable correct : boolean ;
variable count : integer := 0 ;
--
procedure Proc1 (
lowb, highb : severity_level ;
counter : inout integer
) is
begin
L1 :
for i in lowb to highb loop
counter := counter + 1 ;
end loop L1 ;
end Proc1 ;
--
begin
Proc1 (severity_level'Low, severity_level'High, count) ;
correct := count =
(severity_level'Pos (severity_level'High) -
severity_level'Pos (severity_level'Low) + 1) ;
test_report ( "ARCH00061.P3" ,
"Body of 'for' loop is executed once " &
"for each value in the discrete range",
correct ) ;
--
end process P3 ;
--
P4 :
process ( Dummy )
variable correct : boolean ;
variable count : integer := 0 ;
--
procedure Proc1 (
lowb, highb : character ;
counter : inout integer
) is
begin
L1 :
for i in lowb to highb loop
counter := counter + 1 ;
end loop L1 ;
end Proc1 ;
--
begin
Proc1 (character'Low, character'High, count) ;
correct := count =
(character'Pos (character'High) -
character'Pos (character'Low) + 1) ;
test_report ( "ARCH00061.P4" ,
"Body of 'for' loop is executed once " &
"for each value in the discrete range",
correct ) ;
--
end process P4 ;
--
P5 :
process ( Dummy )
variable correct : boolean ;
variable count : integer := 0 ;
--
procedure Proc1 (
lowb, highb : st_enum1 ;
counter : inout integer
) is
begin
L1 :
for i in lowb to highb loop
counter := counter + 1 ;
end loop L1 ;
end Proc1 ;
--
begin
Proc1 (st_enum1'Low, st_enum1'High, count) ;
correct := count =
(st_enum1'Pos (st_enum1'High) -
st_enum1'Pos (st_enum1'Low) + 1) ;
test_report ( "ARCH00061.P5" ,
"Body of 'for' loop is executed once " &
"for each value in the discrete range",
correct ) ;
--
end process P5 ;
--
P6 :
process ( Dummy )
variable correct : boolean ;
variable count : integer := 0 ;
--
procedure Proc1 (
lowb, highb : st_int1 ;
counter : inout integer
) is
begin
L1 :
for i in lowb to highb loop
counter := counter + 1 ;
end loop L1 ;
end Proc1 ;
--
begin
Proc1 (st_int1'Low, st_int1'High, count) ;
correct := count =
(st_int1'Pos (st_int1'High) -
st_int1'Pos (st_int1'Low) + 1) ;
test_report ( "ARCH00061.P6" ,
"Body of 'for' loop is executed once " &
"for each value in the discrete range",
correct ) ;
--
end process P6 ;
--
--
end ARCH00061 ;
--
entity ENT00061_Test_Bench is
end ENT00061_Test_Bench ;
--
architecture ARCH00061_Test_Bench of ENT00061_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00061 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00061_Test_Bench ;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:22:16 01/07/2014
-- Design Name:
-- Module Name: C:/Users/Ruy/Desktop/LCSE_lab/dma/tb_dma.vhd
-- Project Name: dma
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: dma
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_dma IS
END tb_dma;
ARCHITECTURE behavior OF tb_dma IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT dma
PORT(
Clk : IN std_logic;
Reset : IN std_logic;
Databus : INOUT std_logic_vector(7 downto 0);
Address : OUT std_logic_vector(7 downto 0);
ChipSelect : OUT std_logic;
WriteEnable : OUT std_logic;
OutputEnable : OUT std_logic;
Send : IN std_logic;
Ready : OUT std_logic;
DMA_RQ : OUT std_logic;
DMA_ACK : IN std_logic;
TX_data : OUT std_logic_vector(7 downto 0);
Valid_D : OUT std_logic;
Ack_out : IN std_logic;
TX_RDY : IN std_logic;
RCVD_data : IN std_logic_vector(7 downto 0);
Data_read : OUT std_logic;
RX_Full : IN std_logic;
RX_empty : IN std_logic
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Reset : std_logic := '0';
signal Send : std_logic := '0';
signal DMA_ACK : std_logic := '0';
signal Ack_out : std_logic := '0';
signal TX_RDY : std_logic := '0';
signal RCVD_data : std_logic_vector(7 downto 0) := (others => '0');
signal RX_Full : std_logic := '1';
signal RX_empty : std_logic := '1';
--BiDirs
signal Databus : std_logic_vector(7 downto 0);
--Outputs
signal Address : std_logic_vector(7 downto 0);
signal ChipSelect : std_logic;
signal WriteEnable : std_logic;
signal OutputEnable : std_logic;
signal Ready : std_logic;
signal DMA_RQ : std_logic;
signal TX_data : std_logic_vector(7 downto 0);
signal Valid_D : std_logic;
signal Data_read : std_logic;
-- Clock period definitions
constant Clk_period : time := 25 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: dma PORT MAP (
Clk => Clk,
Reset => Reset,
Databus => Databus,
Address => Address,
ChipSelect => ChipSelect,
WriteEnable => WriteEnable,
OutputEnable => OutputEnable,
Send => Send,
Ready => Ready,
DMA_RQ => DMA_RQ,
DMA_ACK => DMA_ACK,
TX_data => TX_data,
Valid_D => Valid_D,
Ack_out => Ack_out,
TX_RDY => TX_RDY,
RCVD_data => RCVD_data,
Data_read => Data_read,
RX_Full => RX_Full,
RX_empty => RX_empty
);
-- Clock process definitions
Clk <= not Clk after Clk_period;
-- Stimulus
Reset <= '1' after 100 ns;
Databus <= X"00", (others => 'Z') after 326 ns, X"22" after 576 ns, X"AA" after 676 ns, (others => 'Z') after 776 ns, X"22" after 826 ns,
(others => 'Z') after 976 ns;
Address <= X"00", (others => 'Z') after 326 ns, X"88" after 576 ns, (others => 'Z') after 676 ns, X"88" after 826 ns,
(others => 'Z') after 976 ns;
ChipSelect <= '0', 'Z' after 326 ns, '1' after 576 ns, 'Z' after 676 ns, '1' after 826 ns, 'Z' after 976 ns;
WriteEnable <= '0', 'Z' after 326 ns, '1' after 576 ns, 'Z' after 676 ns, '1' after 826 ns, 'Z' after 976 ns;
OutputEnable <= '0', 'Z' after 326 ns, '0' after 576 ns, 'Z' after 676 ns, '1' after 826 ns, 'Z' after 976 ns;
Send <= '1' after 626 ns, '0' after 776 ns;
DMA_ACK <= '1' after 276 ns, '0' after 526 ns, '1' after 926 ns, '0' after 1076 ns, '1' after 1226 ns;
RCVD_data <= X"55" after 250 ns;
RX_empty <= '0' after 250 ns, '1' after 1026 ns, '0' after 1201 ns, '1' after 1376 ns;
process
begin
wait;
end process;
END;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Thu Sep 28 11:37:19 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_rx_inst_stub.vhdl
-- Design : fifo_generator_rx_inst
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,rst,din[63:0],wr_en,rd_en,dout[63:0],full,empty";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fifo_generator_v13_1_2,Vivado 2016.3";
begin
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tlc_sim is
Port (
-- The crystal:
CLK : in STD_LOGIC;
-- VGA Connector
R0 : out STD_LOGIC;
R1 : out STD_LOGIC;
R2 : out STD_LOGIC;
G0 : out STD_LOGIC;
G1 : out STD_LOGIC;
G2 : out STD_LOGIC;
B0 : out STD_LOGIC;
B1 : out STD_LOGIC;
HS : out STD_LOGIC;
VS : out STD_LOGIC;
-- Memory Bus:
ADDR0 : out STD_LOGIC;
ADDR1 : out STD_LOGIC;
ADDR2 : out STD_LOGIC;
ADDR3 : out STD_LOGIC;
ADDR4 : out STD_LOGIC;
ADDR5 : out STD_LOGIC;
ADDR6 : out STD_LOGIC;
ADDR7 : out STD_LOGIC;
ADDR8 : out STD_LOGIC;
ADDR9 : out STD_LOGIC;
ADDR10 : out STD_LOGIC;
ADDR11 : out STD_LOGIC;
ADDR12 : out STD_LOGIC;
ADDR13 : out STD_LOGIC;
ADDR14 : out STD_LOGIC;
ADDR15 : out STD_LOGIC;
ADDR16 : out STD_LOGIC;
ADDR17 : out STD_LOGIC;
ADDR18 : out STD_LOGIC;
ADDR19 : out STD_LOGIC;
ADDR20 : out STD_LOGIC;
ADDR21 : out STD_LOGIC;
ADDR22 : out STD_LOGIC;
ADDR23 : out STD_LOGIC;
DataIn0 : in STD_LOGIC;
DataIn1 : in STD_LOGIC;
DataIn2 : in STD_LOGIC;
DataIn3 : in STD_LOGIC;
DataIn4 : in STD_LOGIC;
DataIn5 : in STD_LOGIC;
DataIn6 : in STD_LOGIC;
DataIn7 : in STD_LOGIC;
DataIn8 : in STD_LOGIC;
DataIn9 : in STD_LOGIC;
DataIn10 : in STD_LOGIC;
DataIn11 : in STD_LOGIC;
DataIn12 : in STD_LOGIC;
DataIn13 : in STD_LOGIC;
DataIn14 : in STD_LOGIC;
DataIn15 : in STD_LOGIC;
DataOut0 : out STD_LOGIC;
DataOut1 : out STD_LOGIC;
DataOut2 : out STD_LOGIC;
DataOut3 : out STD_LOGIC;
DataOut4 : out STD_LOGIC;
DataOut5 : out STD_LOGIC;
DataOut6 : out STD_LOGIC;
DataOut7 : out STD_LOGIC;
DataOut8 : out STD_LOGIC;
DataOut9 : out STD_LOGIC;
DataOut10 : out STD_LOGIC;
DataOut11 : out STD_LOGIC;
DataOut12 : out STD_LOGIC;
DataOut13 : out STD_LOGIC;
DataOut14 : out STD_LOGIC;
DataOut15 : out STD_LOGIC;
OE : out STD_LOGIC := '1';
WE : out STD_LOGIC := '1';
MT_ADV : out STD_LOGIC := '0';
MT_CLK : out STD_LOGIC := '0';
MT_UB : out STD_LOGIC := '1';
MT_LB : out STD_LOGIC := '1';
MT_CE : out STD_LOGIC := '1';
MT_CRE : out STD_LOGIC := '0';
MT_WAIT : in STD_LOGIC;
ST_STS : in STD_LOGIC;
RP : out STD_LOGIC := '1';
ST_CE : out STD_LOGIC := '1';
-- PS/2 port:
PS2CLK : in STD_LOGIC;
PS2DATA : in STD_LOGIC
);
end entity;
architecture Structural of tlc_sim is
component TLC is
Port (
-- The crystal:
CLK : in STD_LOGIC;
-- LED:
LED : out STD_LOGIC_VECTOR ( 7 downto 0);
-- VGA Connector
R : out STD_LOGIC_VECTOR ( 2 downto 0);
G : out STD_LOGIC_VECTOR ( 2 downto 0);
B : out STD_LOGIC_VECTOR ( 1 downto 0);
HS : out STD_LOGIC;
VS : out STD_LOGIC;
-- Memory Bus:
ADDR : out STD_LOGIC_VECTOR (23 downto 0);
DATA : inout STD_LOGIC_VECTOR (15 downto 0);
OE : out STD_LOGIC := '1';
WE : out STD_LOGIC := '1';
MT_ADV : out STD_LOGIC := '0';
MT_CLK : out STD_LOGIC := '0';
MT_UB : out STD_LOGIC := '1';
MT_LB : out STD_LOGIC := '1';
MT_CE : out STD_LOGIC := '1';
MT_CRE : out STD_LOGIC := '0';
MT_WAIT : in STD_LOGIC;
ST_STS : in STD_LOGIC;
RP : out STD_LOGIC := '1';
ST_CE : out STD_LOGIC := '1';
-- PS/2 port:
PS2CLK : in STD_LOGIC;
PS2DATA : in STD_LOGIC
);
end component;
signal LED : STD_LOGIC_VECTOR ( 7 downto 0);
signal R : STD_LOGIC_VECTOR ( 2 downto 0);
signal G : STD_LOGIC_VECTOR ( 2 downto 0);
signal B : STD_LOGIC_VECTOR ( 1 downto 0);
signal ADDR : STD_LOGIC_VECTOR (23 downto 0);
signal DATA : STD_LOGIC_VECTOR (15 downto 0);
signal DataIn : STD_LOGIC_VECTOR (15 downto 0);
signal DataOut : STD_LOGIC_VECTOR (15 downto 0);
signal myCLK : STD_LOGIC;
begin
-- array work around
R0 <= R(0);
R1 <= R(1);
R2 <= R(2);
G0 <= G(0);
G1 <= G(1);
G2 <= G(2);
B0 <= B(0);
B1 <= B(1);
ADDR0 <= ADDR( 0);
ADDR1 <= ADDR( 1);
ADDR2 <= ADDR( 2);
ADDR3 <= ADDR( 3);
ADDR4 <= ADDR( 4);
ADDR5 <= ADDR( 5);
ADDR6 <= ADDR( 6);
ADDR7 <= ADDR( 7);
ADDR8 <= ADDR( 8);
ADDR9 <= ADDR( 9);
ADDR10 <= ADDR(10);
ADDR11 <= ADDR(11);
ADDR12 <= ADDR(12);
ADDR13 <= ADDR(13);
ADDR14 <= ADDR(14);
ADDR15 <= ADDR(15);
ADDR16 <= ADDR(16);
ADDR17 <= ADDR(17);
ADDR18 <= ADDR(18);
ADDR19 <= ADDR(19);
ADDR20 <= ADDR(20);
ADDR21 <= ADDR(21);
ADDR22 <= ADDR(22);
ADDR23 <= ADDR(23);
DataIn( 0) <= DataIn0;
DataIn( 1) <= DataIn1;
DataIn( 2) <= DataIn2;
DataIn( 3) <= DataIn3;
DataIn( 4) <= DataIn4;
DataIn( 5) <= DataIn5;
DataIn( 6) <= DataIn6;
DataIn( 7) <= DataIn7;
DataIn( 8) <= DataIn8;
DataIn( 9) <= DataIn9;
DataIn(10) <= DataIn10;
DataIn(11) <= DataIn11;
DataIn(12) <= DataIn12;
DataIn(13) <= DataIn13;
DataIn(14) <= DataIn14;
DataIn(15) <= DataIn15;
DataOut0 <= DataOut( 0);
DataOut1 <= DataOut( 1);
DataOut2 <= DataOut( 2);
DataOut3 <= DataOut( 3);
DataOut4 <= DataOut( 4);
DataOut5 <= DataOut( 5);
DataOut6 <= DataOut( 6);
DataOut7 <= DataOut( 7);
DataOut8 <= DataOut( 8);
DataOut9 <= DataOut( 9);
DataOut10 <= DataOut(10);
DataOut11 <= DataOut(11);
DataOut12 <= DataOut(12);
DataOut13 <= DataOut(13);
DataOut14 <= DataOut(14);
DataOut15 <= DataOut(15);
-- memory data bus
DATA <= DataIn;
DataOut <= DATA;
U: TLC port map (myCLK, LED, R, G, B, HS, VS,
ADDR, DATA, OE, WE,
MT_ADV, MT_CLK, MT_UB, MT_LB, MT_CE, MT_CRE, MT_WAIT,
ST_STS, RP, ST_CE,
PS2CLK, PS2DATA);
process
begin
while true loop
myCLK <= '1';
wait for 10 ns;
myCLK <= '0';
wait for 10 ns;
end loop;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use work.AuxPkg.all;
use work.ComponentsPkg.all;
entity tb_Pull is
end tb_Pull;
architecture arch of tb_Pull is
constant WIDTH : integer := 8;
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (rst, idle, pull_up, pull_down, partbus);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- data/control signals
signal ModexS : std_logic;
signal BusxZ : std_logic_vector(WIDTH-1 downto 0) := (others => 'Z');
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : PullBus
generic map (
WIDTH => WIDTH)
port map (
ModexSI => ModexS,
BusxZO => BusxZ);
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
begin -- process stimuliTb
tbStatus <= rst;
ModexS <= '0';
BusxZ <= (others => 'Z');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= pull_up;
ModexS <= '1';
wait for CLK_PERIOD;
tbStatus <= pull_down;
ModexS <= '0';
wait for CLK_PERIOD;
tbStatus <= partbus;
BusxZ <= (5 downto 4 => '1', 2 downto 1 => '0', others => 'Z');
wait for CLK_PERIOD;
tbStatus <= idle;
ModexS <= '0';
BusxZ <= (others => 'Z');
wait for CLK_PERIOD*2;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY CAPACITOR IS
GENERIC ( v_init : REAL := 0.0;
c : REAL := 10.0e-12 );
PORT ( terminal RT : electrical;
terminal LT : electrical );
END ENTITY CAPACITOR;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY CAPACITOR IS
GENERIC ( v_init : REAL := 0.0;
c : REAL := 10.0e-12 );
PORT ( terminal RT : electrical;
terminal LT : electrical );
END ENTITY CAPACITOR;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY CAPACITOR IS
GENERIC ( v_init : REAL := 0.0;
c : REAL := 10.0e-12 );
PORT ( terminal RT : electrical;
terminal LT : electrical );
END ENTITY CAPACITOR;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY CAPACITOR IS
GENERIC ( v_init : REAL := 0.0;
c : REAL := 10.0e-12 );
PORT ( terminal RT : electrical;
terminal LT : electrical );
END ENTITY CAPACITOR;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY CAPACITOR IS
GENERIC ( v_init : REAL := 0.0;
c : REAL := 10.0e-12 );
PORT ( terminal RT : electrical;
terminal LT : electrical );
END ENTITY CAPACITOR;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY CAPACITOR IS
GENERIC ( v_init : REAL := 0.0;
c : REAL := 10.0e-12 );
PORT ( terminal RT : electrical;
terminal LT : electrical );
END ENTITY CAPACITOR;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY CAPACITOR IS
GENERIC ( v_init : REAL := 0.0;
c : REAL := 10.0e-12 );
PORT ( terminal RT : electrical;
terminal LT : electrical );
END ENTITY CAPACITOR;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY CAPACITOR IS
GENERIC ( v_init : REAL := 0.0;
c : REAL := 10.0e-12 );
PORT ( terminal RT : electrical;
terminal LT : electrical );
END ENTITY CAPACITOR;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY CAPACITOR IS
GENERIC ( v_init : REAL := 0.0;
c : REAL := 10.0e-12 );
PORT ( terminal RT : electrical;
terminal LT : electrical );
END ENTITY CAPACITOR;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY CAPACITOR IS
GENERIC ( v_init : REAL := 0.0;
c : REAL := 10.0e-12 );
PORT ( terminal RT : electrical;
terminal LT : electrical );
END ENTITY CAPACITOR;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY CAPACITOR IS
GENERIC ( v_init : REAL := 0.0;
c : REAL := 10.0e-12 );
PORT ( terminal RT : electrical;
terminal LT : electrical );
END ENTITY CAPACITOR;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY CAPACITOR IS
GENERIC ( v_init : REAL := 0.0;
c : REAL := 10.0e-12 );
PORT ( terminal RT : electrical;
terminal LT : electrical );
END ENTITY CAPACITOR;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY CAPACITOR IS
GENERIC ( v_init : REAL := 0.0;
c : REAL := 10.0e-12 );
PORT ( terminal RT : electrical;
terminal LT : electrical );
END ENTITY CAPACITOR;
|
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