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-- Copyright (C) 2016 by Spallina Ind.
library ieee;
use ieee.std_logic_1164.all;
entity TESTONE is
end TESTONE;
architecture beh of TESTONE is
component sedici_bit is
port (
din : in std_logic_vector(15 downto 0);
start, clk : in std_logic;
res : out std_logic_vector(15 downto 0);
fine : out std_logic
);
end component;
signal start, clk, fine : std_logic;
signal din, res : std_logic_vector(15 downto 0);
begin
DUT: sedici_bit port map (din, start, clk, res, fine);
process
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end process;
start <= '1' after 1 ns, '0' after 11 ns,
'1' after 51 ns, '0' after 61 ns,
'1' after 111 ns, '0' after 121 ns,
'1' after 181 ns, '0' after 191 ns;
din <= "00000000000000"&"00" after 11 ns, "0000000000000000" after 21 ns, -- NOT
"00000000000000"&"01" after 61 ns, "0000000000000001" after 71 ns, "0000000000000010" after 81 ns, -- OR
"00000000000000"&"10" after 121 ns, "0000000000000011" after 131 ns, "0000000000000101" after 141 ns, -- ADD
"00000000000000"&"11" after 191 ns, "0000000000000110" after 201 ns, "0000000000011111" after 211 ns; -- MAC
end beh;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:43:17 02/10/2014
-- Design Name:
-- Module Name: C:/SoundboxProject/Source/soundbox-vhdl/Source/AudioIO/DAPwm_tb.vhd
-- Project Name: SoundboxProject
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: DAPwm
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all ;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY DAPwm_tb IS
END DAPwm_tb;
ARCHITECTURE behavior OF DAPwm_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT DAPwm
PORT(
input : IN std_logic_vector(11 downto 0);
output : OUT std_logic;
clk : IN std_logic;
reset : IN std_logic
);
END COMPONENT;
--Inputs
signal input : std_logic_vector(11 downto 0) := (others => '0');
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal inputNumber : natural := 0;
--Outputs
signal output : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
constant sample_period : time := 40960 ns;
BEGIN
input <= std_logic_vector(to_unsigned(inputNumber, input'high+1));
-- Instantiate the Unit Under Test (UUT)
uut: DAPwm PORT MAP (
input => input,
output => output,
clk => clk,
reset => reset
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
wait for 100 ns;
reset <= '0';
wait for clk_period*10;
wait for 20000 ns;
inputNumber <= 5;
wait for sample_period;
inputNumber <= 4095;
wait for sample_period;
inputNumber <= 4094;
wait for sample_period;
inputNumber <= 4095;
wait for sample_period;
inputNumber <= 5;
wait for sample_period;
-- insert stimulus here
wait;
end process;
END;
|
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Standard multivalue logic package
-- : (STD_LOGIC_1164 package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE model standards group (PAR 1164),
-- : Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This packages defines a standard for designers
-- : to use in describing the interconnection data types
-- : used in vhdl modeling.
-- :
-- Limitation: The logic system defined in this package may
-- : be insufficient for modeling switched transistors,
-- : since such a requirement is out of the scope of this
-- : effort. Furthermore, mathematics, primitives,
-- : timing standards, etc. are considered orthogonal
-- : issues as it relates to this package and are therefore
-- : beyond the scope of this effort.
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1228 $
-- $Date: 2008-04-30 10:04:53 +0930 (Wed, 30 Apr 2008) $
-- --------------------------------------------------------------------
use STD.TEXTIO.all;
package std_logic_1164 is
-------------------------------------------------------------------
-- logic state system (unresolved)
-------------------------------------------------------------------
type STD_ULOGIC is ( 'U', -- Uninitialized
'X', -- Forcing Unknown
'0', -- Forcing 0
'1', -- Forcing 1
'Z', -- High Impedance
'W', -- Weak Unknown
'L', -- Weak 0
'H', -- Weak 1
'-' -- Don't care
);
-------------------------------------------------------------------
-- unconstrained array of std_ulogic for use with the resolution function
-- and for use in declaring signal arrays of unresolved elements
-------------------------------------------------------------------
type STD_ULOGIC_VECTOR is array (NATURAL range <>) of STD_ULOGIC;
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
function resolved (s : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-------------------------------------------------------------------
-- logic state system (resolved)
-------------------------------------------------------------------
subtype STD_LOGIC is resolved STD_ULOGIC;
-------------------------------------------------------------------
-- unconstrained array of resolved std_ulogic for use in declaring
-- signal arrays of resolved elements
-------------------------------------------------------------------
subtype STD_LOGIC_VECTOR is (resolved) STD_ULOGIC_VECTOR;
-------------------------------------------------------------------
-- common subtypes
-------------------------------------------------------------------
subtype X01 is resolved STD_ULOGIC range 'X' to '1'; -- ('X','0','1')
subtype X01Z is resolved STD_ULOGIC range 'X' to 'Z'; -- ('X','0','1','Z')
subtype UX01 is resolved STD_ULOGIC range 'U' to '1'; -- ('U','X','0','1')
subtype UX01Z is resolved STD_ULOGIC range 'U' to 'Z'; -- ('U','X','0','1','Z')
-------------------------------------------------------------------
-- overloaded logical operators
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
function "or" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
function "not" (l : STD_ULOGIC) return UX01;
-------------------------------------------------------------------
-- vectorized overloaded logical operators
-------------------------------------------------------------------
function "and" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nand" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "or" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xnor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "not" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "and" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function "nand" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function "or" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function "nor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function "xor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function "xnor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-------------------------------------------------------------------
-- shift operators
-------------------------------------------------------------------
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
-------------------------------------------------------------------
-- conversion functions
-------------------------------------------------------------------
function To_bit (s : STD_ULOGIC; xmap : BIT := '0') return BIT;
function To_bitvector (s : STD_ULOGIC_VECTOR; xmap : BIT := '0') return BIT_VECTOR;
function To_StdULogic (b : BIT) return STD_ULOGIC;
function To_StdLogicVector (b : BIT_VECTOR) return STD_LOGIC_VECTOR;
function To_StdLogicVector (s : STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR;
function To_StdULogicVector (b : BIT_VECTOR) return STD_ULOGIC_VECTOR;
function To_StdULogicVector (s : STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR;
alias To_Bit_Vector is
To_bitvector[STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
alias To_BV is
To_bitvector[STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
alias To_Std_Logic_Vector is
To_StdLogicVector[BIT_VECTOR return STD_LOGIC_VECTOR];
alias To_SLV is
To_StdLogicVector[BIT_VECTOR return STD_LOGIC_VECTOR];
alias To_Std_Logic_Vector is
To_StdLogicVector[STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias To_SLV is
To_StdLogicVector[STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias To_Std_ULogic_Vector is
To_StdULogicVector[BIT_VECTOR return STD_ULOGIC_VECTOR];
alias To_SULV is
To_StdULogicVector[BIT_VECTOR return STD_ULOGIC_VECTOR];
alias To_Std_ULogic_Vector is
To_StdULogicVector[STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
alias To_SULV is
To_StdULogicVector[STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
-------------------------------------------------------------------
-- strength strippers and type convertors
-------------------------------------------------------------------
function TO_01 (s : STD_ULOGIC_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR;
function TO_01 (s : STD_ULOGIC; xmap : STD_ULOGIC := '0')
return STD_ULOGIC;
function TO_01 (s : BIT_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR;
function TO_01 (s : BIT; xmap : STD_ULOGIC := '0')
return STD_ULOGIC;
function To_X01 (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function To_X01 (s : STD_ULOGIC) return X01;
function To_X01 (b : BIT_VECTOR) return STD_ULOGIC_VECTOR;
function To_X01 (b : BIT) return X01;
function To_X01Z (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function To_X01Z (s : STD_ULOGIC) return X01Z;
function To_X01Z (b : BIT_VECTOR) return STD_ULOGIC_VECTOR;
function To_X01Z (b : BIT) return X01Z;
function To_UX01 (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function To_UX01 (s : STD_ULOGIC) return UX01;
function To_UX01 (b : BIT_VECTOR) return STD_ULOGIC_VECTOR;
function To_UX01 (b : BIT) return UX01;
function "??" (l : STD_ULOGIC) return BOOLEAN;
-------------------------------------------------------------------
-- edge detection
-------------------------------------------------------------------
function rising_edge (signal s : STD_ULOGIC) return BOOLEAN;
function falling_edge (signal s : STD_ULOGIC) return BOOLEAN;
-------------------------------------------------------------------
-- object contains an unknown
-------------------------------------------------------------------
function Is_X (s : STD_ULOGIC_VECTOR) return BOOLEAN;
function Is_X (s : STD_ULOGIC) return BOOLEAN;
-------------------------------------------------------------------
-- matching relational operators
-------------------------------------------------------------------
-- the following operations are predefined
-- function "?=" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function "?=" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- function "?/=" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function "?/=" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- function "?<" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function "?<=" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function "?>" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function "?>=" (l, r : STD_ULOGIC) return STD_ULOGIC;
-------------------------------------------------------------------
-- string conversion and write operations
-------------------------------------------------------------------
-- the following operations are predefined
-- function TO_STRING (value : STD_ULOGIC) return STRING;
-- function TO_STRING (value : STD_ULOGIC_VECTOR) return STRING;
-- explicitly defined operations
alias TO_BSTRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
function TO_OSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [STD_ULOGIC_VECTOR return STRING];
function TO_HSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [STD_ULOGIC_VECTOR return STRING];
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, STD_ULOGIC_VECTOR];
alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR];
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR];
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR];
alias BWRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
end package std_logic_1164;
|
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Standard multivalue logic package
-- : (STD_LOGIC_1164 package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE model standards group (PAR 1164),
-- : Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This packages defines a standard for designers
-- : to use in describing the interconnection data types
-- : used in vhdl modeling.
-- :
-- Limitation: The logic system defined in this package may
-- : be insufficient for modeling switched transistors,
-- : since such a requirement is out of the scope of this
-- : effort. Furthermore, mathematics, primitives,
-- : timing standards, etc. are considered orthogonal
-- : issues as it relates to this package and are therefore
-- : beyond the scope of this effort.
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1228 $
-- $Date: 2008-04-30 10:04:53 +0930 (Wed, 30 Apr 2008) $
-- --------------------------------------------------------------------
use STD.TEXTIO.all;
package std_logic_1164 is
-------------------------------------------------------------------
-- logic state system (unresolved)
-------------------------------------------------------------------
type STD_ULOGIC is ( 'U', -- Uninitialized
'X', -- Forcing Unknown
'0', -- Forcing 0
'1', -- Forcing 1
'Z', -- High Impedance
'W', -- Weak Unknown
'L', -- Weak 0
'H', -- Weak 1
'-' -- Don't care
);
-------------------------------------------------------------------
-- unconstrained array of std_ulogic for use with the resolution function
-- and for use in declaring signal arrays of unresolved elements
-------------------------------------------------------------------
type STD_ULOGIC_VECTOR is array (NATURAL range <>) of STD_ULOGIC;
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
function resolved (s : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-------------------------------------------------------------------
-- logic state system (resolved)
-------------------------------------------------------------------
subtype STD_LOGIC is resolved STD_ULOGIC;
-------------------------------------------------------------------
-- unconstrained array of resolved std_ulogic for use in declaring
-- signal arrays of resolved elements
-------------------------------------------------------------------
subtype STD_LOGIC_VECTOR is (resolved) STD_ULOGIC_VECTOR;
-------------------------------------------------------------------
-- common subtypes
-------------------------------------------------------------------
subtype X01 is resolved STD_ULOGIC range 'X' to '1'; -- ('X','0','1')
subtype X01Z is resolved STD_ULOGIC range 'X' to 'Z'; -- ('X','0','1','Z')
subtype UX01 is resolved STD_ULOGIC range 'U' to '1'; -- ('U','X','0','1')
subtype UX01Z is resolved STD_ULOGIC range 'U' to 'Z'; -- ('U','X','0','1','Z')
-------------------------------------------------------------------
-- overloaded logical operators
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
function "or" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
function "not" (l : STD_ULOGIC) return UX01;
-------------------------------------------------------------------
-- vectorized overloaded logical operators
-------------------------------------------------------------------
function "and" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nand" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "or" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xnor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "not" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "and" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function "nand" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function "or" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function "nor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function "xor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function "xnor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-------------------------------------------------------------------
-- shift operators
-------------------------------------------------------------------
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
-------------------------------------------------------------------
-- conversion functions
-------------------------------------------------------------------
function To_bit (s : STD_ULOGIC; xmap : BIT := '0') return BIT;
function To_bitvector (s : STD_ULOGIC_VECTOR; xmap : BIT := '0') return BIT_VECTOR;
function To_StdULogic (b : BIT) return STD_ULOGIC;
function To_StdLogicVector (b : BIT_VECTOR) return STD_LOGIC_VECTOR;
function To_StdLogicVector (s : STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR;
function To_StdULogicVector (b : BIT_VECTOR) return STD_ULOGIC_VECTOR;
function To_StdULogicVector (s : STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR;
alias To_Bit_Vector is
To_bitvector[STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
alias To_BV is
To_bitvector[STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
alias To_Std_Logic_Vector is
To_StdLogicVector[BIT_VECTOR return STD_LOGIC_VECTOR];
alias To_SLV is
To_StdLogicVector[BIT_VECTOR return STD_LOGIC_VECTOR];
alias To_Std_Logic_Vector is
To_StdLogicVector[STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias To_SLV is
To_StdLogicVector[STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias To_Std_ULogic_Vector is
To_StdULogicVector[BIT_VECTOR return STD_ULOGIC_VECTOR];
alias To_SULV is
To_StdULogicVector[BIT_VECTOR return STD_ULOGIC_VECTOR];
alias To_Std_ULogic_Vector is
To_StdULogicVector[STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
alias To_SULV is
To_StdULogicVector[STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
-------------------------------------------------------------------
-- strength strippers and type convertors
-------------------------------------------------------------------
function TO_01 (s : STD_ULOGIC_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR;
function TO_01 (s : STD_ULOGIC; xmap : STD_ULOGIC := '0')
return STD_ULOGIC;
function TO_01 (s : BIT_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR;
function TO_01 (s : BIT; xmap : STD_ULOGIC := '0')
return STD_ULOGIC;
function To_X01 (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function To_X01 (s : STD_ULOGIC) return X01;
function To_X01 (b : BIT_VECTOR) return STD_ULOGIC_VECTOR;
function To_X01 (b : BIT) return X01;
function To_X01Z (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function To_X01Z (s : STD_ULOGIC) return X01Z;
function To_X01Z (b : BIT_VECTOR) return STD_ULOGIC_VECTOR;
function To_X01Z (b : BIT) return X01Z;
function To_UX01 (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function To_UX01 (s : STD_ULOGIC) return UX01;
function To_UX01 (b : BIT_VECTOR) return STD_ULOGIC_VECTOR;
function To_UX01 (b : BIT) return UX01;
function "??" (l : STD_ULOGIC) return BOOLEAN;
-------------------------------------------------------------------
-- edge detection
-------------------------------------------------------------------
function rising_edge (signal s : STD_ULOGIC) return BOOLEAN;
function falling_edge (signal s : STD_ULOGIC) return BOOLEAN;
-------------------------------------------------------------------
-- object contains an unknown
-------------------------------------------------------------------
function Is_X (s : STD_ULOGIC_VECTOR) return BOOLEAN;
function Is_X (s : STD_ULOGIC) return BOOLEAN;
-------------------------------------------------------------------
-- matching relational operators
-------------------------------------------------------------------
-- the following operations are predefined
-- function "?=" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function "?=" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- function "?/=" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function "?/=" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- function "?<" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function "?<=" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function "?>" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function "?>=" (l, r : STD_ULOGIC) return STD_ULOGIC;
-------------------------------------------------------------------
-- string conversion and write operations
-------------------------------------------------------------------
-- the following operations are predefined
-- function TO_STRING (value : STD_ULOGIC) return STRING;
-- function TO_STRING (value : STD_ULOGIC_VECTOR) return STRING;
-- explicitly defined operations
alias TO_BSTRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
function TO_OSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [STD_ULOGIC_VECTOR return STRING];
function TO_HSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [STD_ULOGIC_VECTOR return STRING];
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, STD_ULOGIC_VECTOR];
alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR];
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR];
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR];
alias BWRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
end package std_logic_1164;
|
library ieee;
use ieee.std_logic_1164.all;
entity sequencer is
generic (
seq : string
);
port (
clk : in std_logic;
data : out std_logic
);
end entity sequencer;
architecture rtl of sequencer is
signal index : natural := seq'low;
signal ch : character;
function to_bit (a : in character) return std_logic is
variable ret : std_logic;
begin
case a is
when '0' | '_' => ret := '0';
when '1' | '-' => ret := '1';
when others => ret := 'X';
end case;
return ret;
end function to_bit;
begin
process (clk) is
begin
if rising_edge(clk) then
if (index < seq'high) then
index <= index + 1;
end if;
end if;
end process;
ch <= seq(index);
data <= to_bit(ch);
end architecture rtl;
library ieee;
use ieee.std_logic_1164.all;
entity psl_next_event_e is
end entity psl_next_event_e;
architecture psl of psl_next_event_e is
signal clk : std_logic := '0';
component sequencer is
generic (
seq : string
);
port (
clk : in std_logic;
data : out std_logic
);
end component sequencer;
signal a, b, c : std_logic;
begin
-- 012345678901234
SEQ_A : sequencer generic map ("_-______-______") port map (clk, a);
SEQ_B : sequencer generic map ("___-__-___-__-_") port map (clk, b);
SEQ_C : sequencer generic map ("______-___-____") port map (clk, c);
-- All is sensitive to rising edge of clk
default clock is rising_edge(clk);
-- This assertion holds
assert_NEXT_EVENT_a : assert always (a -> next_event_e(b)[1 to 2](c));
process
begin
for i in 1 to 2*20 loop
wait for 1 ns;
clk <= not clk;
end loop;
wait;
end process;
end architecture psl;
|
architecture RTL of FIFO is
begin
process
begin
for x in (0 to 30) loop
end loop;
loop
end loop;
-- Violations below
for x in (0 to 30) loop
end loop;
for x in (0 to 30) loop
end loop;
end process;
end;
|
-- lib2
package pkg2 is
constant const2 : integer := 1;
end package;
package body pkg2 is
end package body;
use work.pkg2.all;
package pkg is
constant const : integer := const2 + 1;
end package;
package body pkg is
end package body;
-------------------------------------------------------------------------------
-- lib
library lib2;
use lib2.pkg.all;
entity ent is
end entity;
architecture a of ent is
begin
main : process
begin
assert const = 2;
wait;
end process;
end architecture;
|
-- lib2
package pkg2 is
constant const2 : integer := 1;
end package;
package body pkg2 is
end package body;
use work.pkg2.all;
package pkg is
constant const : integer := const2 + 1;
end package;
package body pkg is
end package body;
-------------------------------------------------------------------------------
-- lib
library lib2;
use lib2.pkg.all;
entity ent is
end entity;
architecture a of ent is
begin
main : process
begin
assert const = 2;
wait;
end process;
end architecture;
|
-- lib2
package pkg2 is
constant const2 : integer := 1;
end package;
package body pkg2 is
end package body;
use work.pkg2.all;
package pkg is
constant const : integer := const2 + 1;
end package;
package body pkg is
end package body;
-------------------------------------------------------------------------------
-- lib
library lib2;
use lib2.pkg.all;
entity ent is
end entity;
architecture a of ent is
begin
main : process
begin
assert const = 2;
wait;
end process;
end architecture;
|
-- lib2
package pkg2 is
constant const2 : integer := 1;
end package;
package body pkg2 is
end package body;
use work.pkg2.all;
package pkg is
constant const : integer := const2 + 1;
end package;
package body pkg is
end package body;
-------------------------------------------------------------------------------
-- lib
library lib2;
use lib2.pkg.all;
entity ent is
end entity;
architecture a of ent is
begin
main : process
begin
assert const = 2;
wait;
end process;
end architecture;
|
-- lib2
package pkg2 is
constant const2 : integer := 1;
end package;
package body pkg2 is
end package body;
use work.pkg2.all;
package pkg is
constant const : integer := const2 + 1;
end package;
package body pkg is
end package body;
-------------------------------------------------------------------------------
-- lib
library lib2;
use lib2.pkg.all;
entity ent is
end entity;
architecture a of ent is
begin
main : process
begin
assert const = 2;
wait;
end process;
end architecture;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
architecture rtl of encoder_inferred is
begin
input_bits_1 : if input_bits = 1 generate
mux : block
signal sel : std_ulogic_vector(0 downto 0);
begin
sel <= datain(0 downto 0);
with sel select
dataout <= "1" when "1",
(others => 'X') when others;
end block;
end generate;
input_bits_2 : if input_bits = 2 generate
mux : block
signal sel : std_ulogic_vector(1 downto 0);
begin
sel <= datain(1 downto 0);
with sel select
dataout <= "0" when "01",
"1" when "10",
(others => 'X') when others;
end block;
end generate;
input_bits_3 : if input_bits = 3 generate
mux : block
signal sel : std_ulogic_vector(2 downto 0);
begin
sel <= datain(2 downto 0);
with sel select
dataout <= "00" when "001",
"01" when "010",
"10" when "100",
(others => 'X') when others;
end block;
end generate;
input_bits_4 : if input_bits = 4 generate
mux : block
signal sel : std_ulogic_vector(3 downto 0);
begin
sel <= datain(3 downto 0);
with sel select
dataout <= "00" when "0001",
"01" when "0010",
"10" when "0100",
"11" when "1000",
(others => 'X') when others;
end block;
end generate;
input_bits_5 : if input_bits = 5 generate
mux : block
signal sel : std_ulogic_vector(4 downto 0);
begin
sel <= datain(4 downto 0);
with sel select
dataout <= "000" when "00001",
"001" when "00010",
"010" when "00100",
"011" when "01000",
"100" when "10000",
(others => 'X') when others;
end block;
end generate;
input_bits_6 : if input_bits = 6 generate
mux : block
signal sel : std_ulogic_vector(5 downto 0);
begin
sel <= datain(5 downto 0);
with sel select
dataout <= "000" when "000001",
"001" when "000010",
"010" when "000100",
"011" when "001000",
"100" when "010000",
"101" when "100000",
(others => 'X') when others;
end block;
end generate;
input_bits_7 : if input_bits = 7 generate
mux : block
signal sel : std_ulogic_vector(6 downto 0);
begin
sel <= datain(6 downto 0);
with sel select
dataout <= "000" when "0000001",
"001" when "0000010",
"010" when "0000100",
"011" when "0001000",
"100" when "0010000",
"101" when "0100000",
"110" when "1000000",
(others => 'X') when others;
end block;
end generate;
input_bits_8 : if input_bits = 8 generate
mux : block
signal sel : std_ulogic_vector(7 downto 0);
begin
sel <= datain(7 downto 0);
with sel select
dataout <= "000" when "00000001",
"001" when "00000010",
"010" when "00000100",
"011" when "00001000",
"100" when "00010000",
"101" when "00100000",
"110" when "01000000",
"111" when "10000000",
(others => 'X') when others;
end block;
end generate;
input_bits_9 : if input_bits = 9 generate
mux : block
signal sel : std_ulogic_vector(8 downto 0);
begin
sel <= datain(8 downto 0);
with sel select
dataout <= "0000" when "000000001",
"0001" when "000000010",
"0010" when "000000100",
"0011" when "000001000",
"0100" when "000010000",
"0101" when "000100000",
"0110" when "001000000",
"0111" when "010000000",
"1000" when "100000000",
(others => 'X') when others;
end block;
end generate;
input_bits_10 : if input_bits = 10 generate
mux : block
signal sel : std_ulogic_vector(9 downto 0);
begin
sel <= datain(9 downto 0);
with sel select
dataout <= "0000" when "0000000001",
"0001" when "0000000010",
"0010" when "0000000100",
"0011" when "0000001000",
"0100" when "0000010000",
"0101" when "0000100000",
"0110" when "0001000000",
"0111" when "0010000000",
"1000" when "0100000000",
"1001" when "1000000000",
(others => 'X') when others;
end block;
end generate;
input_bits_11 : if input_bits = 11 generate
mux : block
signal sel : std_ulogic_vector(10 downto 0);
begin
sel <= datain(10 downto 0);
with sel select
dataout <= "0000" when "00000000001",
"0001" when "00000000010",
"0010" when "00000000100",
"0011" when "00000001000",
"0100" when "00000010000",
"0101" when "00000100000",
"0110" when "00001000000",
"0111" when "00010000000",
"1000" when "00100000000",
"1001" when "01000000000",
"1010" when "10000000000",
(others => 'X') when others;
end block;
end generate;
input_bits_12 : if input_bits = 12 generate
mux : block
signal sel : std_ulogic_vector(11 downto 0);
begin
sel <= datain(11 downto 0);
with sel select
dataout <= "0000" when "000000000001",
"0001" when "000000000010",
"0010" when "000000000100",
"0011" when "000000001000",
"0100" when "000000010000",
"0101" when "000000100000",
"0110" when "000001000000",
"0111" when "000010000000",
"1000" when "000100000000",
"1001" when "001000000000",
"1010" when "010000000000",
"1011" when "100000000000",
(others => 'X') when others;
end block;
end generate;
input_bits_13 : if input_bits = 13 generate
mux : block
signal sel : std_ulogic_vector(12 downto 0);
begin
sel <= datain(12 downto 0);
with sel select
dataout <= "0000" when "0000000000001",
"0001" when "0000000000010",
"0010" when "0000000000100",
"0011" when "0000000001000",
"0100" when "0000000010000",
"0101" when "0000000100000",
"0110" when "0000001000000",
"0111" when "0000010000000",
"1000" when "0000100000000",
"1001" when "0001000000000",
"1010" when "0010000000000",
"1011" when "0100000000000",
"1100" when "1000000000000",
(others => 'X') when others;
end block;
end generate;
input_bits_14 : if input_bits = 14 generate
mux : block
signal sel : std_ulogic_vector(13 downto 0);
begin
sel <= datain(13 downto 0);
with sel select
dataout <= "0000" when "00000000000001",
"0001" when "00000000000010",
"0010" when "00000000000100",
"0011" when "00000000001000",
"0100" when "00000000010000",
"0101" when "00000000100000",
"0110" when "00000001000000",
"0111" when "00000010000000",
"1000" when "00000100000000",
"1001" when "00001000000000",
"1010" when "00010000000000",
"1011" when "00100000000000",
"1100" when "01000000000000",
"1101" when "10000000000000",
(others => 'X') when others;
end block;
end generate;
input_bits_15 : if input_bits = 15 generate
mux : block
signal sel : std_ulogic_vector(14 downto 0);
begin
sel <= datain(14 downto 0);
with sel select
dataout <= "0000" when "000000000000001",
"0001" when "000000000000010",
"0010" when "000000000000100",
"0011" when "000000000001000",
"0100" when "000000000010000",
"0101" when "000000000100000",
"0110" when "000000001000000",
"0111" when "000000010000000",
"1000" when "000000100000000",
"1001" when "000001000000000",
"1010" when "000010000000000",
"1011" when "000100000000000",
"1100" when "001000000000000",
"1101" when "010000000000000",
"1110" when "100000000000000",
(others => 'X') when others;
end block;
end generate;
input_bits_16 : if input_bits = 16 generate
mux : block
signal sel : std_ulogic_vector(15 downto 0);
begin
sel <= datain(15 downto 0);
with sel select
dataout <= "0000" when "0000000000000001",
"0001" when "0000000000000010",
"0010" when "0000000000000100",
"0011" when "0000000000001000",
"0100" when "0000000000010000",
"0101" when "0000000000100000",
"0110" when "0000000001000000",
"0111" when "0000000010000000",
"1000" when "0000000100000000",
"1001" when "0000001000000000",
"1010" when "0000010000000000",
"1011" when "0000100000000000",
"1100" when "0001000000000000",
"1101" when "0010000000000000",
"1110" when "0100000000000000",
"1111" when "1000000000000000",
(others => 'X') when others;
end block;
end generate;
input_bits_out_of_range : if input_bits > 16 generate
input_bits_out_of_rance_proc : process is
begin
assert input_bits > 16 report "input_bits is out of range" severity failure;
wait;
end process;
end generate;
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux32b is
PORT( A : in STD_LOGIC_VECTOR (31 downto 0);
B : in STD_LOGIC_VECTOR (31 downto 0);
Sel: in STD_LOGIC;
O : out STD_LOGIC_VECTOR (31 downto 0));
end mux32b;
architecture arqMux32b of mux32b is
begin
process(A, B, Sel)
begin
if (Sel = '1') then
O <= B;
else
if(Sel = '0') then
O <= A;
end if;
end if;
end process;
end arqMux32b;
|
-----------------------------------------------------------
--------- AUTOGENERATED FILE, DO NOT EDIT -----------------
-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.desilog.all;
entity Example0 is port(
clk_clk, clk_reset_n: in std_ulogic;
doAdd: in std_ulogic; -- reg
xx: in u8; -- reg
yy: in u8; -- reg
zz: out u8; -- reg
and_result_reg: out u8; -- reg
xor_result_wire: out u8; -- WIRE
or_result_latch: out u8 -- Latch
);
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.desilog.all;
--#------- Example0 ------------------------------------
architecture rtl of Example0 is
----- internal regs/wires/etc --------
signal dg_c_doAdd: std_ulogic;
signal dg_c_xx: u8;
signal dg_c_yy: u8;
signal dg_c_zz: u8;
signal dg_o_zz: u8;
signal dg_c_and_result_reg: u8;
signal dg_o_and_result_reg: u8;
signal dg_w_xor_result_wire: u8;
signal dg_l_or_result_latch: u8;
begin
dg_comb_proc1: process (all)
begin
dg_l_or_result_latch <= dg_l_or_result_latch; -- latch preload
dg_l_or_result_latch <= (xx or yy);
if (dg_o_and_result_reg(4) = '1') then
dg_l_or_result_latch <= xx;
end if;
if (dg_boolToBit(dg_o_zz(2 downto 0) = "101") = '1') then
dg_l_or_result_latch <= (not yy);
end if;
end process;
myProcess: process (all)
begin
dg_c_zz <= dg_o_zz; -- reg preload
dg_c_and_result_reg <= dg_o_and_result_reg; -- reg preload
dg_w_xor_result_wire <= X"00"; -- wire pre-zero-init
dg_c_and_result_reg <= (xx and yy);
dg_w_xor_result_wire <= (xx xor yy);
if (doAdd = '1') then
dg_c_zz <= (xx + yy);
else
dg_c_zz <= (xx - yy);
end if;
end process;
----[ sync clock pump for clk ]------
process begin
wait until rising_edge(clk_clk);
dg_o_zz <= dg_c_zz;
dg_o_and_result_reg <= dg_c_and_result_reg;
if clk_reset_n = '0' then
dg_o_and_result_reg <= X"55";
end if;
end process;
------[ output registers/wires/latches ] --------------
zz <= dg_o_zz;
and_result_reg <= dg_o_and_result_reg;
xor_result_wire <= dg_w_xor_result_wire;
or_result_latch <= dg_l_or_result_latch;
end;
|
--------------------------------------------------------------------
-- Package: MultiIO
-- File: MultiIO.vhd
-- Author: Thomas Ameseder, Gleichmann Electronics
-- Based on an orginal version by [email protected]
--
-- Description: APB Multiple digital I/O Types and Components
--------------------------------------------------------------------
-- Functionality:
-- 8 LEDs, active low or high, r/w
-- dual 7Segment, active low or high, w only
-- 8 DIL Switches, active low or high, r only
-- 8 Buttons, active low or high, r only, with IRQ enables
--------------------------------------------------------------------
library ieee;
use IEEE.STD_LOGIC_1164.all;
library grlib;
use grlib.amba.all;
package MultiIO is
-- maximum number of switches and LEDs
-- specific number that is used can be defined via a generic
constant N_SWITCHMAX : integer := 8;
constant N_LEDMAX : integer := 8;
constant N_BUTTONS : integer := 12; -- number of push-buttons
-- data width of the words for the codec configuration interface
constant N_CODECBITS : integer := 16;
-- data width of the words for the i2s digital samples
constant N_CODECI2SBITS : integer := 16;
-- the number of register bits that are assigned to the LCD
-- the enable control bit is set automatically
-- this constant should comprise the number of data bits as well
-- as the RW and RS control bits
constant N_LCDBITS : integer := 10;
-- number of bits to hold information for the (single/dual)
-- seven segment display;
constant N_SEVSEGBITS : integer := 16;
-- number of expansion connector i/o bits
constant N_EXPBITS : integer := 40;
-- number of high-speed connector bits per connector
constant N_HSCBITS : integer := 4;
-- number of childboard3 connector i/o bits
constant N_CB3 : integer := 32;
type asciichar_vect is array (16#30# to 16#46#) of character;
-- excerpt of the ASCII chart
constant ascii2char : asciichar_vect :=
-- -------------------------------------------
-- | 30 31 32 33 34 35 36 37 |
-- -------------------------------------------
('0', '1', '2', '3', '4', '5', '6', '7',
-- -------------------------------------------
-- | 38 39 3A 3B 3C 3D 3E 3F |
-- -------------------------------------------
'8', '9', ':', ';', '<', '=', '>', '?',
-- -------------------------------------------
-- | 40 41 42 43 44 45 46 |
-- -------------------------------------------
'@', 'A', 'B', 'C', 'D', 'E', 'F');
---------------------------------------------------------------------------------------
-- AUDIO CODEC
---------------------------------------------------------------------------------------
subtype tReg is std_ulogic_vector(N_CODECBITS-1 downto 0);
type tRegMap is array(10 downto 0) of tReg;
subtype tRegData is std_ulogic_vector(8 downto 0);
subtype tRegAddr is std_ulogic_vector(6 downto 0);
-- ADDRESS
constant cAddrLLI : tRegAddr := "0000000"; -- Left line input channel volume control
constant cAddrRLI : tRegAddr := "0000001"; -- Right line input channel volume control
constant cAddrLCH : tRegAddr := "0000010"; -- Left channel headphone volume control
constant cAddrRCH : tRegAddr := "0000011"; -- Right channel headphone volume control
constant cAddrAAP : tRegAddr := "0000100"; -- Analog audio path control
constant cAddrDAP : tRegAddr := "0000101"; -- Digital audio path control
constant cAddrPDC : tRegAddr := "0000110"; -- Power down control
constant cAddrDAI : tRegAddr := "0000111"; -- Digital audio interface format
constant cAddrSRC : tRegAddr := "0001000"; -- Sample rate control
constant cAddrDIA : tRegAddr := "0001001"; -- Digital interface activation
constant cAddrReset : tRegAddr := "0001111"; -- Reset register
-- Data
constant cDataLLI : tRegData := "100011111";
constant cDataRLI : tRegData := "100011111";
constant cDataLCH : tRegData := "011111111";
constant cDataRCH : tRegData := "011111111";
constant cDataAAP : tRegData := "000011010";
constant cDataDAP : tRegData := "000000000";
constant cDataPDC : tRegData := "000001010";
constant cDataDAI : tRegData := "000000010";
constant cDataSRC : tRegData := "010000000";
constant cDataDIA : tRegData := "000000001";
constant cdataInit : tRegData := "000000000";
-- Register
constant cRegLLI : tReg := cAddrLLI & cDataLLI;
constant cRegRLI : tReg := cAddrRLI & cDataRLI;
constant cRegLCH : tReg := cAddrLCH & cDataLCH;
constant cRegRCH : tReg := cAddrRCH & cDataRCH;
constant cRegAAP : tReg := cAddrAAP & cDataAAP;
constant cRegDAP : tReg := cAddrDAP & cDataDAP;
constant cRegPDC : tReg := cAddrPDC & cDataPDC;
constant cRegDAI : tReg := cAddrDAI & cDataDAI;
constant cRegSRC : tReg := cAddrSRC & cDataSRC;
constant cRegDIA : tReg := cAddrDIA & cDataDIA;
constant cRegReset : tReg := CAddrReset & cdataInit;
-- Register Map
constant cregmap : tRegMap := (
0 => cRegLLI,
1 => cRegRLI,
2 => cRegLCH,
3 => cRegRCH,
4 => cRegAAP,
5 => cRegDAP,
6 => cRegPDC,
7 => cRegDAI,
8 => cRegSRC,
9 => cRegDIA,
10 => cRegReset
);
---------------------------------------------------------------------------------------
type MultiIO_in_type is
record
switch_in : std_logic_vector(N_SWITCHMAX-1 downto 0); -- 8 DIL Switches
-- row input from the key matrix
row_in : std_logic_vector(3 downto 0);
-- expansion connector input bits
exp_in : std_logic_vector(N_EXPBITS/2-1 downto 0);
hsc_in : std_logic_vector(N_HSCBITS-1 downto 0);
-- childboard3 connector input bits
cb3_in : std_logic_vector(N_CB3-1 downto 0);
end record;
type MultiIO_out_type is
record
-- signals for the 7 segment display
-- data bits 0 to 7 of the LCD
-- LED signals for the Hpe_midi
led_a_out : std_logic;
led_b_out : std_logic;
led_c_out : std_logic;
led_d_out : std_logic;
led_e_out : std_logic;
led_f_out : std_logic;
led_g_out : std_logic;
led_dp_out : std_logic;
-- common anode for enabling left and/or right digit
-- data bit 7 for the LCD
led_ca_out : std_logic_vector(1 downto 0);
-- enable output to LED's for the Hpe_midi
led_enable : std_logic;
-- LCD-only control signals
lcd_regsel : std_logic;
lcd_rw : std_logic;
lcd_enable : std_logic;
-- LED register for all boards except the Hpe_midi
led_out : std_logic_vector(N_LEDMAX-1 downto 0); -- 8 LEDs
-- column output to the key matrix
column_out : std_logic_vector(2 downto 0);
-- signals for the SPI audio codec
codec_mode : std_ulogic;
codec_mclk : std_ulogic;
codec_sclk : std_ulogic;
codec_sdin : std_ulogic;
codec_cs : std_ulogic;
codec_din : std_ulogic; -- I2S format serial data input to the sigma-delta stereo DAC
codec_bclk : std_ulogic; -- I2S serial-bit clock
-- codec_dout : in std_ulogic; -- I2S format serial data output from the sigma-delta stereo ADC
codec_lrcin : std_ulogic; -- I2S DAC-word clock signal
codec_lrcout : std_ulogic; -- I2S ADC-word clock signal
-- expansion connector output bits
exp_out : std_logic_vector(N_EXPBITS/2-1 downto 0);
hsc_out : std_logic_vector(N_HSCBITS-1 downto 0);
-- childboard3 connector output bits
-- cb3_out : std_logic_vector(N_CB3-1 downto 0);
end record;
component MultiIO_APB
generic
(
hpe_version : integer := 0; -- adapt multiplexing for different boards
pindex : integer := 0; -- Leon-Index
paddr : integer := 0; -- Leon-Address
pmask : integer := 16#FFF#; -- Leon-Mask
pirq : integer := 0; -- Leon-IRQ
clk_freq_in : integer; -- Leons clock to calculate timings
led7act : std_logic := '0'; -- active level for 7Segment
ledact : std_logic := '0'; -- active level for LED's
switchact : std_logic := '1'; -- active level for LED's
buttonact : std_logic := '1'; -- active level for LED's
n_switches : integer := 8; -- number of switches
n_leds : integer := 8 -- number of LEDs
);
port (
rst_n : in std_ulogic; -- global Reset, active low
clk : in std_ulogic; -- global Clock
apbi : in apb_slv_in_type; -- APB-Input
apbo : out apb_slv_out_type; -- APB-Output
MultiIO_in : in MultiIO_in_type; -- MultIO-Inputs
MultiIO_out : out MultiIO_out_type -- MultiIO-Outputs
);
end component;
end package;
|
--------------------------------------------------------------------
-- Package: MultiIO
-- File: MultiIO.vhd
-- Author: Thomas Ameseder, Gleichmann Electronics
-- Based on an orginal version by [email protected]
--
-- Description: APB Multiple digital I/O Types and Components
--------------------------------------------------------------------
-- Functionality:
-- 8 LEDs, active low or high, r/w
-- dual 7Segment, active low or high, w only
-- 8 DIL Switches, active low or high, r only
-- 8 Buttons, active low or high, r only, with IRQ enables
--------------------------------------------------------------------
library ieee;
use IEEE.STD_LOGIC_1164.all;
library grlib;
use grlib.amba.all;
package MultiIO is
-- maximum number of switches and LEDs
-- specific number that is used can be defined via a generic
constant N_SWITCHMAX : integer := 8;
constant N_LEDMAX : integer := 8;
constant N_BUTTONS : integer := 12; -- number of push-buttons
-- data width of the words for the codec configuration interface
constant N_CODECBITS : integer := 16;
-- data width of the words for the i2s digital samples
constant N_CODECI2SBITS : integer := 16;
-- the number of register bits that are assigned to the LCD
-- the enable control bit is set automatically
-- this constant should comprise the number of data bits as well
-- as the RW and RS control bits
constant N_LCDBITS : integer := 10;
-- number of bits to hold information for the (single/dual)
-- seven segment display;
constant N_SEVSEGBITS : integer := 16;
-- number of expansion connector i/o bits
constant N_EXPBITS : integer := 40;
-- number of high-speed connector bits per connector
constant N_HSCBITS : integer := 4;
-- number of childboard3 connector i/o bits
constant N_CB3 : integer := 32;
type asciichar_vect is array (16#30# to 16#46#) of character;
-- excerpt of the ASCII chart
constant ascii2char : asciichar_vect :=
-- -------------------------------------------
-- | 30 31 32 33 34 35 36 37 |
-- -------------------------------------------
('0', '1', '2', '3', '4', '5', '6', '7',
-- -------------------------------------------
-- | 38 39 3A 3B 3C 3D 3E 3F |
-- -------------------------------------------
'8', '9', ':', ';', '<', '=', '>', '?',
-- -------------------------------------------
-- | 40 41 42 43 44 45 46 |
-- -------------------------------------------
'@', 'A', 'B', 'C', 'D', 'E', 'F');
---------------------------------------------------------------------------------------
-- AUDIO CODEC
---------------------------------------------------------------------------------------
subtype tReg is std_ulogic_vector(N_CODECBITS-1 downto 0);
type tRegMap is array(10 downto 0) of tReg;
subtype tRegData is std_ulogic_vector(8 downto 0);
subtype tRegAddr is std_ulogic_vector(6 downto 0);
-- ADDRESS
constant cAddrLLI : tRegAddr := "0000000"; -- Left line input channel volume control
constant cAddrRLI : tRegAddr := "0000001"; -- Right line input channel volume control
constant cAddrLCH : tRegAddr := "0000010"; -- Left channel headphone volume control
constant cAddrRCH : tRegAddr := "0000011"; -- Right channel headphone volume control
constant cAddrAAP : tRegAddr := "0000100"; -- Analog audio path control
constant cAddrDAP : tRegAddr := "0000101"; -- Digital audio path control
constant cAddrPDC : tRegAddr := "0000110"; -- Power down control
constant cAddrDAI : tRegAddr := "0000111"; -- Digital audio interface format
constant cAddrSRC : tRegAddr := "0001000"; -- Sample rate control
constant cAddrDIA : tRegAddr := "0001001"; -- Digital interface activation
constant cAddrReset : tRegAddr := "0001111"; -- Reset register
-- Data
constant cDataLLI : tRegData := "100011111";
constant cDataRLI : tRegData := "100011111";
constant cDataLCH : tRegData := "011111111";
constant cDataRCH : tRegData := "011111111";
constant cDataAAP : tRegData := "000011010";
constant cDataDAP : tRegData := "000000000";
constant cDataPDC : tRegData := "000001010";
constant cDataDAI : tRegData := "000000010";
constant cDataSRC : tRegData := "010000000";
constant cDataDIA : tRegData := "000000001";
constant cdataInit : tRegData := "000000000";
-- Register
constant cRegLLI : tReg := cAddrLLI & cDataLLI;
constant cRegRLI : tReg := cAddrRLI & cDataRLI;
constant cRegLCH : tReg := cAddrLCH & cDataLCH;
constant cRegRCH : tReg := cAddrRCH & cDataRCH;
constant cRegAAP : tReg := cAddrAAP & cDataAAP;
constant cRegDAP : tReg := cAddrDAP & cDataDAP;
constant cRegPDC : tReg := cAddrPDC & cDataPDC;
constant cRegDAI : tReg := cAddrDAI & cDataDAI;
constant cRegSRC : tReg := cAddrSRC & cDataSRC;
constant cRegDIA : tReg := cAddrDIA & cDataDIA;
constant cRegReset : tReg := CAddrReset & cdataInit;
-- Register Map
constant cregmap : tRegMap := (
0 => cRegLLI,
1 => cRegRLI,
2 => cRegLCH,
3 => cRegRCH,
4 => cRegAAP,
5 => cRegDAP,
6 => cRegPDC,
7 => cRegDAI,
8 => cRegSRC,
9 => cRegDIA,
10 => cRegReset
);
---------------------------------------------------------------------------------------
type MultiIO_in_type is
record
switch_in : std_logic_vector(N_SWITCHMAX-1 downto 0); -- 8 DIL Switches
-- row input from the key matrix
row_in : std_logic_vector(3 downto 0);
-- expansion connector input bits
exp_in : std_logic_vector(N_EXPBITS/2-1 downto 0);
hsc_in : std_logic_vector(N_HSCBITS-1 downto 0);
-- childboard3 connector input bits
cb3_in : std_logic_vector(N_CB3-1 downto 0);
end record;
type MultiIO_out_type is
record
-- signals for the 7 segment display
-- data bits 0 to 7 of the LCD
-- LED signals for the Hpe_midi
led_a_out : std_logic;
led_b_out : std_logic;
led_c_out : std_logic;
led_d_out : std_logic;
led_e_out : std_logic;
led_f_out : std_logic;
led_g_out : std_logic;
led_dp_out : std_logic;
-- common anode for enabling left and/or right digit
-- data bit 7 for the LCD
led_ca_out : std_logic_vector(1 downto 0);
-- enable output to LED's for the Hpe_midi
led_enable : std_logic;
-- LCD-only control signals
lcd_regsel : std_logic;
lcd_rw : std_logic;
lcd_enable : std_logic;
-- LED register for all boards except the Hpe_midi
led_out : std_logic_vector(N_LEDMAX-1 downto 0); -- 8 LEDs
-- column output to the key matrix
column_out : std_logic_vector(2 downto 0);
-- signals for the SPI audio codec
codec_mode : std_ulogic;
codec_mclk : std_ulogic;
codec_sclk : std_ulogic;
codec_sdin : std_ulogic;
codec_cs : std_ulogic;
codec_din : std_ulogic; -- I2S format serial data input to the sigma-delta stereo DAC
codec_bclk : std_ulogic; -- I2S serial-bit clock
-- codec_dout : in std_ulogic; -- I2S format serial data output from the sigma-delta stereo ADC
codec_lrcin : std_ulogic; -- I2S DAC-word clock signal
codec_lrcout : std_ulogic; -- I2S ADC-word clock signal
-- expansion connector output bits
exp_out : std_logic_vector(N_EXPBITS/2-1 downto 0);
hsc_out : std_logic_vector(N_HSCBITS-1 downto 0);
-- childboard3 connector output bits
-- cb3_out : std_logic_vector(N_CB3-1 downto 0);
end record;
component MultiIO_APB
generic
(
hpe_version : integer := 0; -- adapt multiplexing for different boards
pindex : integer := 0; -- Leon-Index
paddr : integer := 0; -- Leon-Address
pmask : integer := 16#FFF#; -- Leon-Mask
pirq : integer := 0; -- Leon-IRQ
clk_freq_in : integer; -- Leons clock to calculate timings
led7act : std_logic := '0'; -- active level for 7Segment
ledact : std_logic := '0'; -- active level for LED's
switchact : std_logic := '1'; -- active level for LED's
buttonact : std_logic := '1'; -- active level for LED's
n_switches : integer := 8; -- number of switches
n_leds : integer := 8 -- number of LEDs
);
port (
rst_n : in std_ulogic; -- global Reset, active low
clk : in std_ulogic; -- global Clock
apbi : in apb_slv_in_type; -- APB-Input
apbo : out apb_slv_out_type; -- APB-Output
MultiIO_in : in MultiIO_in_type; -- MultIO-Inputs
MultiIO_out : out MultiIO_out_type -- MultiIO-Outputs
);
end component;
end package;
|
----------------------------------------------------------------------------------
-- Company: ZITI
-- Engineer: wgao
--
-- Create Date: 16:38:03 06 Oct 2008
-- Design Name:
-- Module Name: DDR_Blink - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library work;
use work.abb64Package.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DDR_Blink is
port (
DDR_blinker : out std_logic;
DDR_Write : in std_logic;
DDR_Read : in std_logic;
DDR_Both : in std_logic;
ddr_Clock : in std_logic;
DDr_Rst_n : in std_logic
);
end entity DDR_Blink;
architecture Behavioral of DDR_Blink is
-- Blinking -_-_-_-_
constant C_BLINKER_MSB : integer := 15; -- 4; -- 15;
constant CBIT_SLOW_BLINKER : integer := 11; -- 2; -- 11;
signal DDR_blinker_i : std_logic;
signal Fast_blinker : std_logic_vector(C_BLINKER_MSB downto 0);
signal Fast_blinker_MSB_r1 : std_logic;
signal Blink_Pulse : std_logic;
signal Slow_blinker : std_logic_vector(CBIT_SLOW_BLINKER downto 0);
signal DDR_write_extension : std_logic;
signal DDR_write_extension_Cnt : std_logic_vector(1 downto 0);
signal DDR_read_extension : std_logic;
signal DDR_read_extension_Cnt : std_logic_vector(1 downto 0);
begin
--
Syn_DDR_Fast_blinker :
process (ddr_Clock, DDr_Rst_n)
begin
if DDr_Rst_n = '0' then
Fast_blinker <= (others => '0');
Fast_blinker_MSB_r1 <= '0';
Blink_Pulse <= '0';
Slow_blinker <= (others => '0');
elsif ddr_Clock'event and ddr_Clock = '1' then
Fast_blinker <= Fast_blinker + '1';
Fast_blinker_MSB_r1 <= Fast_blinker(C_BLINKER_MSB);
Blink_Pulse <= Fast_blinker(C_BLINKER_MSB) and not Fast_blinker_MSB_r1;
Slow_blinker <= Slow_blinker + Blink_Pulse;
end if;
end process;
--
Syn_DDR_Write_Extenstion :
process (ddr_Clock, DDr_Rst_n)
begin
if DDr_Rst_n = '0' then
DDR_write_extension_Cnt <= (others => '0');
DDR_write_extension <= '0';
elsif ddr_Clock'event and ddr_Clock = '1' then
case DDR_write_extension_Cnt is
when "00" =>
if DDR_Write = '1' then
DDR_write_extension_Cnt <= "01";
DDR_write_extension <= '1';
else
DDR_write_extension_Cnt <= DDR_write_extension_Cnt;
DDR_write_extension <= DDR_write_extension;
end if;
when "01" =>
if Slow_blinker(CBIT_SLOW_BLINKER) = '1' then
DDR_write_extension_Cnt <= "11";
DDR_write_extension <= '1';
else
DDR_write_extension_Cnt <= DDR_write_extension_Cnt;
DDR_write_extension <= DDR_write_extension;
end if;
when "11" =>
if Slow_blinker(CBIT_SLOW_BLINKER) = '0' then
DDR_write_extension_Cnt <= "10";
DDR_write_extension <= '1';
else
DDR_write_extension_Cnt <= DDR_write_extension_Cnt;
DDR_write_extension <= DDR_write_extension;
end if;
when others =>
if Slow_blinker(CBIT_SLOW_BLINKER) = '1' then
DDR_write_extension_Cnt <= "00";
DDR_write_extension <= '0';
else
DDR_write_extension_Cnt <= DDR_write_extension_Cnt;
DDR_write_extension <= DDR_write_extension;
end if;
end case;
end if;
end process;
--
Syn_DDR_Read_Extenstion :
process (ddr_Clock, DDr_Rst_n)
begin
if DDr_Rst_n = '0' then
DDR_read_extension_Cnt <= (others => '0');
DDR_read_extension <= '1';
elsif ddr_Clock'event and ddr_Clock = '1' then
case DDR_read_extension_Cnt is
when "00" =>
if DDR_Read = '1' then
DDR_read_extension_Cnt <= "01";
DDR_read_extension <= '0';
else
DDR_read_extension_Cnt <= DDR_read_extension_Cnt;
DDR_read_extension <= DDR_read_extension;
end if;
when "01" =>
if Slow_blinker(CBIT_SLOW_BLINKER) = '1' then
DDR_read_extension_Cnt <= "11";
DDR_read_extension <= '0';
else
DDR_read_extension_Cnt <= DDR_read_extension_Cnt;
DDR_read_extension <= DDR_read_extension;
end if;
when "11" =>
if Slow_blinker(CBIT_SLOW_BLINKER) = '0' then
DDR_read_extension_Cnt <= "10";
DDR_read_extension <= '0';
else
DDR_read_extension_Cnt <= DDR_read_extension_Cnt;
DDR_read_extension <= DDR_read_extension;
end if;
when others =>
if Slow_blinker(CBIT_SLOW_BLINKER) = '1' then
DDR_read_extension_Cnt <= "00";
DDR_read_extension <= '1';
else
DDR_read_extension_Cnt <= DDR_read_extension_Cnt;
DDR_read_extension <= DDR_read_extension;
end if;
end case;
end if;
end process;
--
Syn_DDR_Working_blinker :
process (ddr_Clock, DDr_Rst_n)
begin
if DDr_Rst_n = '0' then
DDR_Blinker_i <= '0';
elsif ddr_Clock'event and ddr_Clock = '1' then
DDR_Blinker_i <= (Slow_blinker(CBIT_SLOW_BLINKER-2) or DDR_write_extension) and DDR_read_extension;
-- DDR_Blinker_i <= Slow_blinker(CBIT_SLOW_BLINKER-2);
end if;
end process;
DDR_blinker <= DDR_blinker_i;
end architecture Behavioral;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for vor
--
-- Generated
-- by: wig
-- on: Thu Nov 6 15:56:34 2003
-- cmd: H:\work\mix\mix_0.pl -nodelta ..\nreset2.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: vor-rtl-conf-c.vhd,v 1.1 2004/04/06 10:46:48 wig Exp $
-- $Date: 2004/04/06 10:46:48 $
-- $Log: vor-rtl-conf-c.vhd,v $
-- Revision 1.1 2004/04/06 10:46:48 wig
-- Adding result/nreset2
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.31 2003/10/23 12:13:17 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.17 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration vor_rtl_conf / vor
--
configuration vor_rtl_conf of vor is
for rtl
-- Generated Configuration
end for;
end vor_rtl_conf;
--
-- End of Generated Configuration vor_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
library verilog;
use verilog.vl_types.all;
entity altparallel_flash_loader is
generic(
EXTRA_ADDR_BYTE : integer := 0;
FEATURES_CFG : integer := 1;
PAGE_CLK_DIVISOR: integer := 1;
BURST_MODE_SPANSION: integer := 0;
ENHANCED_FLASH_PROGRAMMING: integer := 0;
FLASH_ECC_CHECKBOX: integer := 0;
FLASH_NRESET_COUNTER: integer := 1;
PAGE_MODE : integer := 0;
NRB_ADDR : integer := 65667072;
BURST_MODE : integer := 0;
SAFE_MODE_REVERT_ADDR: integer := 0;
US_UNIT_COUNTER : integer := 1;
FIFO_SIZE : integer := 16;
CONF_DATA_WIDTH : integer := 1;
CONF_WAIT_TIMER_WIDTH: integer := 14;
NFLASH_MFC : string := "NUMONYX";
OPTION_BITS_START_ADDRESS: integer := 0;
SAFE_MODE_RETRY : integer := 1;
DCLK_DIVISOR : integer := 1;
FLASH_TYPE : string := "CFI_FLASH";
N_FLASH : integer := 1;
FLASH_BURST_EXTRA_CYCLE: integer := 0;
TRISTATE_CHECKBOX: integer := 0;
QFLASH_MFC : string := "ALTERA";
FEATURES_PGM : integer := 1;
DISABLE_CRC_CHECKBOX: integer := 0;
FLASH_DATA_WIDTH: integer := 16;
RSU_WATCHDOG_COUNTER: integer := 100000000;
PFL_RSU_WATCHDOG_ENABLED: integer := 0;
SAFE_MODE_HALT : integer := 0;
ADDR_WIDTH : integer := 20;
NAND_SIZE : integer := 67108864;
NORMAL_MODE : integer := 1;
FLASH_NRESET_CHECKBOX: integer := 0;
SAFE_MODE_REVERT: integer := 0;
LPM_TYPE : string := "ALTPARALLEL_FLASH_LOADER";
AUTO_RESTART : string := "OFF";
CLK_DIVISOR : integer := 1;
BURST_MODE_INTEL: integer := 0;
BURST_MODE_NUMONYX: integer := 0;
DECOMPRESSOR_MODE: string := "NONE";
PFL_QUAD_IO_FLASH_IR_BITS: integer := 8;
PFL_CFI_FLASH_IR_BITS: integer := 5;
PFL_NAND_FLASH_IR_BITS: integer := 4;
N_FLASH_BITS : integer := 4
);
port(
flash_nce : out vl_logic_vector;
fpga_data : out vl_logic_vector;
fpga_dclk : out vl_logic;
fpga_nstatus : in vl_logic;
flash_ale : out vl_logic;
pfl_clk : in vl_logic;
fpga_nconfig : out vl_logic;
flash_io2 : inout vl_logic_vector;
flash_sck : out vl_logic_vector;
flash_noe : out vl_logic;
flash_nwe : out vl_logic;
pfl_watchdog_error: out vl_logic;
pfl_reset_watchdog: in vl_logic;
fpga_conf_done : in vl_logic;
flash_rdy : in vl_logic;
pfl_flash_access_granted: in vl_logic;
pfl_nreconfigure: in vl_logic;
flash_cle : out vl_logic;
flash_nreset : out vl_logic;
flash_io0 : inout vl_logic_vector;
pfl_nreset : in vl_logic;
flash_data : inout vl_logic_vector;
flash_io1 : inout vl_logic_vector;
flash_nadv : out vl_logic;
flash_clk : out vl_logic;
flash_io3 : inout vl_logic_vector;
flash_io : inout vl_logic_vector(7 downto 0);
flash_addr : out vl_logic_vector;
pfl_flash_access_request: out vl_logic;
flash_ncs : out vl_logic_vector;
fpga_pgm : in vl_logic_vector(2 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of EXTRA_ADDR_BYTE : constant is 1;
attribute mti_svvh_generic_type of FEATURES_CFG : constant is 1;
attribute mti_svvh_generic_type of PAGE_CLK_DIVISOR : constant is 1;
attribute mti_svvh_generic_type of BURST_MODE_SPANSION : constant is 1;
attribute mti_svvh_generic_type of ENHANCED_FLASH_PROGRAMMING : constant is 1;
attribute mti_svvh_generic_type of FLASH_ECC_CHECKBOX : constant is 1;
attribute mti_svvh_generic_type of FLASH_NRESET_COUNTER : constant is 1;
attribute mti_svvh_generic_type of PAGE_MODE : constant is 1;
attribute mti_svvh_generic_type of NRB_ADDR : constant is 1;
attribute mti_svvh_generic_type of BURST_MODE : constant is 1;
attribute mti_svvh_generic_type of SAFE_MODE_REVERT_ADDR : constant is 1;
attribute mti_svvh_generic_type of US_UNIT_COUNTER : constant is 1;
attribute mti_svvh_generic_type of FIFO_SIZE : constant is 1;
attribute mti_svvh_generic_type of CONF_DATA_WIDTH : constant is 1;
attribute mti_svvh_generic_type of CONF_WAIT_TIMER_WIDTH : constant is 1;
attribute mti_svvh_generic_type of NFLASH_MFC : constant is 1;
attribute mti_svvh_generic_type of OPTION_BITS_START_ADDRESS : constant is 1;
attribute mti_svvh_generic_type of SAFE_MODE_RETRY : constant is 1;
attribute mti_svvh_generic_type of DCLK_DIVISOR : constant is 1;
attribute mti_svvh_generic_type of FLASH_TYPE : constant is 1;
attribute mti_svvh_generic_type of N_FLASH : constant is 1;
attribute mti_svvh_generic_type of FLASH_BURST_EXTRA_CYCLE : constant is 1;
attribute mti_svvh_generic_type of TRISTATE_CHECKBOX : constant is 1;
attribute mti_svvh_generic_type of QFLASH_MFC : constant is 1;
attribute mti_svvh_generic_type of FEATURES_PGM : constant is 1;
attribute mti_svvh_generic_type of DISABLE_CRC_CHECKBOX : constant is 1;
attribute mti_svvh_generic_type of FLASH_DATA_WIDTH : constant is 1;
attribute mti_svvh_generic_type of RSU_WATCHDOG_COUNTER : constant is 1;
attribute mti_svvh_generic_type of PFL_RSU_WATCHDOG_ENABLED : constant is 1;
attribute mti_svvh_generic_type of SAFE_MODE_HALT : constant is 1;
attribute mti_svvh_generic_type of ADDR_WIDTH : constant is 1;
attribute mti_svvh_generic_type of NAND_SIZE : constant is 1;
attribute mti_svvh_generic_type of NORMAL_MODE : constant is 1;
attribute mti_svvh_generic_type of FLASH_NRESET_CHECKBOX : constant is 1;
attribute mti_svvh_generic_type of SAFE_MODE_REVERT : constant is 1;
attribute mti_svvh_generic_type of LPM_TYPE : constant is 1;
attribute mti_svvh_generic_type of AUTO_RESTART : constant is 1;
attribute mti_svvh_generic_type of CLK_DIVISOR : constant is 1;
attribute mti_svvh_generic_type of BURST_MODE_INTEL : constant is 1;
attribute mti_svvh_generic_type of BURST_MODE_NUMONYX : constant is 1;
attribute mti_svvh_generic_type of DECOMPRESSOR_MODE : constant is 1;
attribute mti_svvh_generic_type of PFL_QUAD_IO_FLASH_IR_BITS : constant is 1;
attribute mti_svvh_generic_type of PFL_CFI_FLASH_IR_BITS : constant is 1;
attribute mti_svvh_generic_type of PFL_NAND_FLASH_IR_BITS : constant is 1;
attribute mti_svvh_generic_type of N_FLASH_BITS : constant is 1;
end altparallel_flash_loader;
|
library ieee;
library ieee;
library ieee;
library ieee;
library ieee;
-- Comment with tab
-- Comment with tab
-- Comment with tab
-- Comment with tab
-- Comment with tab
-- Comment with tab
-- Comment with tab
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:08:51 10/04/2009
-- Design Name:
-- Module Name: C:/Users/Ben/Desktop/Folders/FPGA/Projects/Current Projects/Systems/TestCPU1/TestCPU1_RegFile_TB.vhd
-- Project Name: TestCPU1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: TestCPU1_RegFile
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY TestCPU1_RegFile_TB IS
END TestCPU1_RegFile_TB;
ARCHITECTURE behavior OF TestCPU1_RegFile_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT TestCPU1_RegFile
PORT(
clock : IN std_logic;
reset : IN std_logic;
ld_val : IN std_logic;
ALUB_out : IN std_logic;
src1_addr : IN std_logic_vector(2 downto 0);
src2_addr : IN std_logic_vector(2 downto 0);
dest_addr : IN std_logic_vector(2 downto 0);
data_to_load : IN std_logic_vector(15 downto 0);
to_ALUA_out : OUT std_logic_vector(15 downto 0);
to_ALUB_out : OUT std_logic_vector(15 downto 0);
data_collection_1 : out STD_LOGIC_VECTOR(15 downto 0); --for simulation purposes only
data_collection_2 : out STD_LOGIC_VECTOR(15 downto 0); --
data_collection_3 : out STD_LOGIC_VECTOR(15 downto 0)); --
END COMPONENT;
--Inputs
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal ld_val : std_logic := '0';
signal ALUB_out : std_logic := '0';
signal src1_addr : std_logic_vector(2 downto 0) := (others => '0');
signal src2_addr : std_logic_vector(2 downto 0) := (others => '0');
signal dest_addr : std_logic_vector(2 downto 0) := (others => '0');
signal data_to_load : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal to_ALUA_out : std_logic_vector(15 downto 0);
signal to_ALUB_out : std_logic_vector(15 downto 0);
signal data_collection_1 : STD_LOGIC_VECTOR(15 downto 0); --for simulation purposes only
signal data_collection_2 : STD_LOGIC_VECTOR(15 downto 0); --
signal data_collection_3 : STD_LOGIC_VECTOR(15 downto 0); --
-- Clock period definitions
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: TestCPU1_RegFile PORT MAP (
clock => clock,
reset => reset,
ld_val => ld_val,
ALUB_out => ALUB_out,
src1_addr => src1_addr,
src2_addr => src2_addr,
dest_addr => dest_addr,
data_to_load => data_to_load,
to_ALUA_out => to_ALUA_out,
to_ALUB_out => to_ALUB_out,
data_collection_1 => data_collection_1,
data_collection_2 => data_collection_2,
data_collection_3 => data_collection_3
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for 15 ns;
ld_val <= '1';
dest_addr <= b"001";
data_to_load <= x"0001";
wait for 10 ns;
dest_addr <= b"010";
data_to_load <= x"0002";
wait for 10 ns;
dest_addr <= b"011";
data_to_load <= x"0003";
wait for 10 ns;
ld_val <= '0';
ALUB_out <= '1';
src1_addr <= b"001";
wait for 10 ns;
src1_addr <= b"010";
src2_addr <= b"011";
wait for 10 ns;
ALUB_out <= '0';
wait for 10 ns;
reset <= '1';
wait;
end process;
END;
|
package body fifo_pkg is
end package body;
package body fifo_pkg --comment
is
end package body;
|
-------------------------------------------------------------------------------
-- counter_f - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_f.vhd
--
-- Description: Implements a parameterizable N-bit counter_f
-- Up/Down Counter
-- Count Enable
-- Parallel Load
-- Synchronous Reset
-- The structural implementation has incremental cost
-- of one LUT per bit.
-- Precedence of operations when simultaneous:
-- reset, load, count
--
-- A default inferred-RTL implementation is provided and
-- is used if the user explicitly specifies C_FAMILY=nofamily
-- or ommits C_FAMILY (allowing it to default to nofamily).
-- The default implementation is also used
-- if needed primitives are not available in FPGAs of the
-- type given by C_FAMILY.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- Author: FLO & Nitin 06/06/2006 First Version, functional equivalent
-- of counter.vhd.
-- History:
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.unsigned;
use IEEE.numeric_std."+";
use IEEE.numeric_std."-";
library unisim;
use unisim.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_f is
generic(
C_NUM_BITS : integer := 9;
C_FAMILY : string := "nofamily"
);
port(
Clk : in std_logic;
Rst : in std_logic;
Load_In : in std_logic_vector(C_NUM_BITS - 1 downto 0);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(C_NUM_BITS - 1 downto 0);
Carry_Out : out std_logic
);
end entity counter_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_f is
---------------------------------------------------------------------
-- Component declarations
---------------------------------------------------------------------
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
---------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------
constant USE_STRUCTURAL_A : boolean :=
supported(C_FAMILY, (u_MUXCY_L, u_XORCY, u_FDRE));
constant USE_INFERRED : boolean := not USE_STRUCTURAL_A;
---------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Generate structural code
---------------------------------------------------------------------
STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate
signal alu_cy : std_logic_vector(C_NUM_BITS+1 downto 0);
signal alu_cy_init : std_logic;
signal icount_out : std_logic_vector(C_NUM_BITS downto 0);
signal icount_out_x : std_logic_vector(C_NUM_BITS downto 0);
signal load_in_x : std_logic_vector(C_NUM_BITS downto 0);
signal count_AddSub : std_logic_vector(C_NUM_BITS downto 0);
signal count_Result : std_logic_vector(C_NUM_BITS downto 0);
signal count_clock_en : std_logic;
begin
alu_cy_init <= (Count_Down and Count_Load) or
(not Count_Down and not Count_load);
I_MUXCY_I : component MUXCY_L
port map (
DI => '0',
CI => '1',
S => alu_cy_init,
LO => alu_cy(0));
count_clock_en <= Count_Enable or Count_Load;
load_in_x <= ('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0));
-----------------------------------------------------------------
-- Generate counter using MUXCY_L, XORCY and FDRE
-----------------------------------------------------------------
I_ADDSUB_GEN : for i in 0 to C_NUM_BITS generate
count_AddSub(i) <= load_in_x(i) xor Count_Down
when Count_Load ='1' else
icount_out_x(i) xor Count_Down ; -- LUT
MUXCY_I : component MUXCY_L
port map (
DI => Count_Down,
CI => alu_cy(i),
S => count_AddSub(i),
LO => alu_cy(i+1));
XOR_I : component XORCY
port map (
LI => count_AddSub(i),
CI => alu_cy(i),
O => count_Result(i));
FDRE_I: component FDRE
port map (
Q => iCount_Out(i),
C => Clk,
CE => count_clock_en,
D => count_Result(i),
R => Rst);
end generate I_ADDSUB_GEN;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= icount_out(C_NUM_BITS-1 downto 0);
end generate STRUCTURAL_A_GEN;
---------------------------------------------------------------------
-- Generate Inferred code
---------------------------------------------------------------------
--INFERRED_GEN : if USE_INFERRED generate
INFERRED_GEN : if (not USE_STRUCTURAL_A) generate
signal icount_out : unsigned(C_NUM_BITS downto 0);
signal icount_out_x : unsigned(C_NUM_BITS downto 0);
signal load_in_x : unsigned(C_NUM_BITS downto 0);
begin
load_in_x <= unsigned('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
-- icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0)); -- Echeck WA
icount_out_x <= unsigned('0' & std_logic_vector(icount_out(C_NUM_BITS-1 downto 0)));
-----------------------------------------------------------------
-- Process to generate counter with - synchronous reset, load,
-- counter enable, count down / up features.
-----------------------------------------------------------------
CNTR_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
icount_out <= (others => '0');
elsif Count_Load = '1' then
icount_out <= load_in_x;
elsif Count_Down = '1' and Count_Enable = '1' then
icount_out <= icount_out_x - 1;
elsif Count_Enable = '1' then
icount_out <= icount_out_x + 1;
end if;
end if;
end process CNTR_PROC;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= std_logic_vector(icount_out(C_NUM_BITS-1 downto 0));
end generate INFERRED_GEN;
end architecture imp;
---------------------------------------------------------------
-- End of file counter_f.vhd
---------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- counter_f - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_f.vhd
--
-- Description: Implements a parameterizable N-bit counter_f
-- Up/Down Counter
-- Count Enable
-- Parallel Load
-- Synchronous Reset
-- The structural implementation has incremental cost
-- of one LUT per bit.
-- Precedence of operations when simultaneous:
-- reset, load, count
--
-- A default inferred-RTL implementation is provided and
-- is used if the user explicitly specifies C_FAMILY=nofamily
-- or ommits C_FAMILY (allowing it to default to nofamily).
-- The default implementation is also used
-- if needed primitives are not available in FPGAs of the
-- type given by C_FAMILY.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- Author: FLO & Nitin 06/06/2006 First Version, functional equivalent
-- of counter.vhd.
-- History:
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.unsigned;
use IEEE.numeric_std."+";
use IEEE.numeric_std."-";
library unisim;
use unisim.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_f is
generic(
C_NUM_BITS : integer := 9;
C_FAMILY : string := "nofamily"
);
port(
Clk : in std_logic;
Rst : in std_logic;
Load_In : in std_logic_vector(C_NUM_BITS - 1 downto 0);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(C_NUM_BITS - 1 downto 0);
Carry_Out : out std_logic
);
end entity counter_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_f is
---------------------------------------------------------------------
-- Component declarations
---------------------------------------------------------------------
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
---------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------
constant USE_STRUCTURAL_A : boolean :=
supported(C_FAMILY, (u_MUXCY_L, u_XORCY, u_FDRE));
constant USE_INFERRED : boolean := not USE_STRUCTURAL_A;
---------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Generate structural code
---------------------------------------------------------------------
STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate
signal alu_cy : std_logic_vector(C_NUM_BITS+1 downto 0);
signal alu_cy_init : std_logic;
signal icount_out : std_logic_vector(C_NUM_BITS downto 0);
signal icount_out_x : std_logic_vector(C_NUM_BITS downto 0);
signal load_in_x : std_logic_vector(C_NUM_BITS downto 0);
signal count_AddSub : std_logic_vector(C_NUM_BITS downto 0);
signal count_Result : std_logic_vector(C_NUM_BITS downto 0);
signal count_clock_en : std_logic;
begin
alu_cy_init <= (Count_Down and Count_Load) or
(not Count_Down and not Count_load);
I_MUXCY_I : component MUXCY_L
port map (
DI => '0',
CI => '1',
S => alu_cy_init,
LO => alu_cy(0));
count_clock_en <= Count_Enable or Count_Load;
load_in_x <= ('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0));
-----------------------------------------------------------------
-- Generate counter using MUXCY_L, XORCY and FDRE
-----------------------------------------------------------------
I_ADDSUB_GEN : for i in 0 to C_NUM_BITS generate
count_AddSub(i) <= load_in_x(i) xor Count_Down
when Count_Load ='1' else
icount_out_x(i) xor Count_Down ; -- LUT
MUXCY_I : component MUXCY_L
port map (
DI => Count_Down,
CI => alu_cy(i),
S => count_AddSub(i),
LO => alu_cy(i+1));
XOR_I : component XORCY
port map (
LI => count_AddSub(i),
CI => alu_cy(i),
O => count_Result(i));
FDRE_I: component FDRE
port map (
Q => iCount_Out(i),
C => Clk,
CE => count_clock_en,
D => count_Result(i),
R => Rst);
end generate I_ADDSUB_GEN;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= icount_out(C_NUM_BITS-1 downto 0);
end generate STRUCTURAL_A_GEN;
---------------------------------------------------------------------
-- Generate Inferred code
---------------------------------------------------------------------
--INFERRED_GEN : if USE_INFERRED generate
INFERRED_GEN : if (not USE_STRUCTURAL_A) generate
signal icount_out : unsigned(C_NUM_BITS downto 0);
signal icount_out_x : unsigned(C_NUM_BITS downto 0);
signal load_in_x : unsigned(C_NUM_BITS downto 0);
begin
load_in_x <= unsigned('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
-- icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0)); -- Echeck WA
icount_out_x <= unsigned('0' & std_logic_vector(icount_out(C_NUM_BITS-1 downto 0)));
-----------------------------------------------------------------
-- Process to generate counter with - synchronous reset, load,
-- counter enable, count down / up features.
-----------------------------------------------------------------
CNTR_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
icount_out <= (others => '0');
elsif Count_Load = '1' then
icount_out <= load_in_x;
elsif Count_Down = '1' and Count_Enable = '1' then
icount_out <= icount_out_x - 1;
elsif Count_Enable = '1' then
icount_out <= icount_out_x + 1;
end if;
end if;
end process CNTR_PROC;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= std_logic_vector(icount_out(C_NUM_BITS-1 downto 0));
end generate INFERRED_GEN;
end architecture imp;
---------------------------------------------------------------
-- End of file counter_f.vhd
---------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- counter_f - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_f.vhd
--
-- Description: Implements a parameterizable N-bit counter_f
-- Up/Down Counter
-- Count Enable
-- Parallel Load
-- Synchronous Reset
-- The structural implementation has incremental cost
-- of one LUT per bit.
-- Precedence of operations when simultaneous:
-- reset, load, count
--
-- A default inferred-RTL implementation is provided and
-- is used if the user explicitly specifies C_FAMILY=nofamily
-- or ommits C_FAMILY (allowing it to default to nofamily).
-- The default implementation is also used
-- if needed primitives are not available in FPGAs of the
-- type given by C_FAMILY.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- Author: FLO & Nitin 06/06/2006 First Version, functional equivalent
-- of counter.vhd.
-- History:
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.unsigned;
use IEEE.numeric_std."+";
use IEEE.numeric_std."-";
library unisim;
use unisim.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_f is
generic(
C_NUM_BITS : integer := 9;
C_FAMILY : string := "nofamily"
);
port(
Clk : in std_logic;
Rst : in std_logic;
Load_In : in std_logic_vector(C_NUM_BITS - 1 downto 0);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(C_NUM_BITS - 1 downto 0);
Carry_Out : out std_logic
);
end entity counter_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_f is
---------------------------------------------------------------------
-- Component declarations
---------------------------------------------------------------------
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
---------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------
constant USE_STRUCTURAL_A : boolean :=
supported(C_FAMILY, (u_MUXCY_L, u_XORCY, u_FDRE));
constant USE_INFERRED : boolean := not USE_STRUCTURAL_A;
---------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Generate structural code
---------------------------------------------------------------------
STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate
signal alu_cy : std_logic_vector(C_NUM_BITS+1 downto 0);
signal alu_cy_init : std_logic;
signal icount_out : std_logic_vector(C_NUM_BITS downto 0);
signal icount_out_x : std_logic_vector(C_NUM_BITS downto 0);
signal load_in_x : std_logic_vector(C_NUM_BITS downto 0);
signal count_AddSub : std_logic_vector(C_NUM_BITS downto 0);
signal count_Result : std_logic_vector(C_NUM_BITS downto 0);
signal count_clock_en : std_logic;
begin
alu_cy_init <= (Count_Down and Count_Load) or
(not Count_Down and not Count_load);
I_MUXCY_I : component MUXCY_L
port map (
DI => '0',
CI => '1',
S => alu_cy_init,
LO => alu_cy(0));
count_clock_en <= Count_Enable or Count_Load;
load_in_x <= ('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0));
-----------------------------------------------------------------
-- Generate counter using MUXCY_L, XORCY and FDRE
-----------------------------------------------------------------
I_ADDSUB_GEN : for i in 0 to C_NUM_BITS generate
count_AddSub(i) <= load_in_x(i) xor Count_Down
when Count_Load ='1' else
icount_out_x(i) xor Count_Down ; -- LUT
MUXCY_I : component MUXCY_L
port map (
DI => Count_Down,
CI => alu_cy(i),
S => count_AddSub(i),
LO => alu_cy(i+1));
XOR_I : component XORCY
port map (
LI => count_AddSub(i),
CI => alu_cy(i),
O => count_Result(i));
FDRE_I: component FDRE
port map (
Q => iCount_Out(i),
C => Clk,
CE => count_clock_en,
D => count_Result(i),
R => Rst);
end generate I_ADDSUB_GEN;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= icount_out(C_NUM_BITS-1 downto 0);
end generate STRUCTURAL_A_GEN;
---------------------------------------------------------------------
-- Generate Inferred code
---------------------------------------------------------------------
--INFERRED_GEN : if USE_INFERRED generate
INFERRED_GEN : if (not USE_STRUCTURAL_A) generate
signal icount_out : unsigned(C_NUM_BITS downto 0);
signal icount_out_x : unsigned(C_NUM_BITS downto 0);
signal load_in_x : unsigned(C_NUM_BITS downto 0);
begin
load_in_x <= unsigned('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
-- icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0)); -- Echeck WA
icount_out_x <= unsigned('0' & std_logic_vector(icount_out(C_NUM_BITS-1 downto 0)));
-----------------------------------------------------------------
-- Process to generate counter with - synchronous reset, load,
-- counter enable, count down / up features.
-----------------------------------------------------------------
CNTR_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
icount_out <= (others => '0');
elsif Count_Load = '1' then
icount_out <= load_in_x;
elsif Count_Down = '1' and Count_Enable = '1' then
icount_out <= icount_out_x - 1;
elsif Count_Enable = '1' then
icount_out <= icount_out_x + 1;
end if;
end if;
end process CNTR_PROC;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= std_logic_vector(icount_out(C_NUM_BITS-1 downto 0));
end generate INFERRED_GEN;
end architecture imp;
---------------------------------------------------------------
-- End of file counter_f.vhd
---------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- counter_f - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_f.vhd
--
-- Description: Implements a parameterizable N-bit counter_f
-- Up/Down Counter
-- Count Enable
-- Parallel Load
-- Synchronous Reset
-- The structural implementation has incremental cost
-- of one LUT per bit.
-- Precedence of operations when simultaneous:
-- reset, load, count
--
-- A default inferred-RTL implementation is provided and
-- is used if the user explicitly specifies C_FAMILY=nofamily
-- or ommits C_FAMILY (allowing it to default to nofamily).
-- The default implementation is also used
-- if needed primitives are not available in FPGAs of the
-- type given by C_FAMILY.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- Author: FLO & Nitin 06/06/2006 First Version, functional equivalent
-- of counter.vhd.
-- History:
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.unsigned;
use IEEE.numeric_std."+";
use IEEE.numeric_std."-";
library unisim;
use unisim.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_f is
generic(
C_NUM_BITS : integer := 9;
C_FAMILY : string := "nofamily"
);
port(
Clk : in std_logic;
Rst : in std_logic;
Load_In : in std_logic_vector(C_NUM_BITS - 1 downto 0);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(C_NUM_BITS - 1 downto 0);
Carry_Out : out std_logic
);
end entity counter_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_f is
---------------------------------------------------------------------
-- Component declarations
---------------------------------------------------------------------
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
---------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------
constant USE_STRUCTURAL_A : boolean :=
supported(C_FAMILY, (u_MUXCY_L, u_XORCY, u_FDRE));
constant USE_INFERRED : boolean := not USE_STRUCTURAL_A;
---------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Generate structural code
---------------------------------------------------------------------
STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate
signal alu_cy : std_logic_vector(C_NUM_BITS+1 downto 0);
signal alu_cy_init : std_logic;
signal icount_out : std_logic_vector(C_NUM_BITS downto 0);
signal icount_out_x : std_logic_vector(C_NUM_BITS downto 0);
signal load_in_x : std_logic_vector(C_NUM_BITS downto 0);
signal count_AddSub : std_logic_vector(C_NUM_BITS downto 0);
signal count_Result : std_logic_vector(C_NUM_BITS downto 0);
signal count_clock_en : std_logic;
begin
alu_cy_init <= (Count_Down and Count_Load) or
(not Count_Down and not Count_load);
I_MUXCY_I : component MUXCY_L
port map (
DI => '0',
CI => '1',
S => alu_cy_init,
LO => alu_cy(0));
count_clock_en <= Count_Enable or Count_Load;
load_in_x <= ('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0));
-----------------------------------------------------------------
-- Generate counter using MUXCY_L, XORCY and FDRE
-----------------------------------------------------------------
I_ADDSUB_GEN : for i in 0 to C_NUM_BITS generate
count_AddSub(i) <= load_in_x(i) xor Count_Down
when Count_Load ='1' else
icount_out_x(i) xor Count_Down ; -- LUT
MUXCY_I : component MUXCY_L
port map (
DI => Count_Down,
CI => alu_cy(i),
S => count_AddSub(i),
LO => alu_cy(i+1));
XOR_I : component XORCY
port map (
LI => count_AddSub(i),
CI => alu_cy(i),
O => count_Result(i));
FDRE_I: component FDRE
port map (
Q => iCount_Out(i),
C => Clk,
CE => count_clock_en,
D => count_Result(i),
R => Rst);
end generate I_ADDSUB_GEN;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= icount_out(C_NUM_BITS-1 downto 0);
end generate STRUCTURAL_A_GEN;
---------------------------------------------------------------------
-- Generate Inferred code
---------------------------------------------------------------------
--INFERRED_GEN : if USE_INFERRED generate
INFERRED_GEN : if (not USE_STRUCTURAL_A) generate
signal icount_out : unsigned(C_NUM_BITS downto 0);
signal icount_out_x : unsigned(C_NUM_BITS downto 0);
signal load_in_x : unsigned(C_NUM_BITS downto 0);
begin
load_in_x <= unsigned('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
-- icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0)); -- Echeck WA
icount_out_x <= unsigned('0' & std_logic_vector(icount_out(C_NUM_BITS-1 downto 0)));
-----------------------------------------------------------------
-- Process to generate counter with - synchronous reset, load,
-- counter enable, count down / up features.
-----------------------------------------------------------------
CNTR_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
icount_out <= (others => '0');
elsif Count_Load = '1' then
icount_out <= load_in_x;
elsif Count_Down = '1' and Count_Enable = '1' then
icount_out <= icount_out_x - 1;
elsif Count_Enable = '1' then
icount_out <= icount_out_x + 1;
end if;
end if;
end process CNTR_PROC;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= std_logic_vector(icount_out(C_NUM_BITS-1 downto 0));
end generate INFERRED_GEN;
end architecture imp;
---------------------------------------------------------------
-- End of file counter_f.vhd
---------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- counter_f - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_f.vhd
--
-- Description: Implements a parameterizable N-bit counter_f
-- Up/Down Counter
-- Count Enable
-- Parallel Load
-- Synchronous Reset
-- The structural implementation has incremental cost
-- of one LUT per bit.
-- Precedence of operations when simultaneous:
-- reset, load, count
--
-- A default inferred-RTL implementation is provided and
-- is used if the user explicitly specifies C_FAMILY=nofamily
-- or ommits C_FAMILY (allowing it to default to nofamily).
-- The default implementation is also used
-- if needed primitives are not available in FPGAs of the
-- type given by C_FAMILY.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- Author: FLO & Nitin 06/06/2006 First Version, functional equivalent
-- of counter.vhd.
-- History:
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.unsigned;
use IEEE.numeric_std."+";
use IEEE.numeric_std."-";
library unisim;
use unisim.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_f is
generic(
C_NUM_BITS : integer := 9;
C_FAMILY : string := "nofamily"
);
port(
Clk : in std_logic;
Rst : in std_logic;
Load_In : in std_logic_vector(C_NUM_BITS - 1 downto 0);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(C_NUM_BITS - 1 downto 0);
Carry_Out : out std_logic
);
end entity counter_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_f is
---------------------------------------------------------------------
-- Component declarations
---------------------------------------------------------------------
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
---------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------
constant USE_STRUCTURAL_A : boolean :=
supported(C_FAMILY, (u_MUXCY_L, u_XORCY, u_FDRE));
constant USE_INFERRED : boolean := not USE_STRUCTURAL_A;
---------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Generate structural code
---------------------------------------------------------------------
STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate
signal alu_cy : std_logic_vector(C_NUM_BITS+1 downto 0);
signal alu_cy_init : std_logic;
signal icount_out : std_logic_vector(C_NUM_BITS downto 0);
signal icount_out_x : std_logic_vector(C_NUM_BITS downto 0);
signal load_in_x : std_logic_vector(C_NUM_BITS downto 0);
signal count_AddSub : std_logic_vector(C_NUM_BITS downto 0);
signal count_Result : std_logic_vector(C_NUM_BITS downto 0);
signal count_clock_en : std_logic;
begin
alu_cy_init <= (Count_Down and Count_Load) or
(not Count_Down and not Count_load);
I_MUXCY_I : component MUXCY_L
port map (
DI => '0',
CI => '1',
S => alu_cy_init,
LO => alu_cy(0));
count_clock_en <= Count_Enable or Count_Load;
load_in_x <= ('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0));
-----------------------------------------------------------------
-- Generate counter using MUXCY_L, XORCY and FDRE
-----------------------------------------------------------------
I_ADDSUB_GEN : for i in 0 to C_NUM_BITS generate
count_AddSub(i) <= load_in_x(i) xor Count_Down
when Count_Load ='1' else
icount_out_x(i) xor Count_Down ; -- LUT
MUXCY_I : component MUXCY_L
port map (
DI => Count_Down,
CI => alu_cy(i),
S => count_AddSub(i),
LO => alu_cy(i+1));
XOR_I : component XORCY
port map (
LI => count_AddSub(i),
CI => alu_cy(i),
O => count_Result(i));
FDRE_I: component FDRE
port map (
Q => iCount_Out(i),
C => Clk,
CE => count_clock_en,
D => count_Result(i),
R => Rst);
end generate I_ADDSUB_GEN;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= icount_out(C_NUM_BITS-1 downto 0);
end generate STRUCTURAL_A_GEN;
---------------------------------------------------------------------
-- Generate Inferred code
---------------------------------------------------------------------
--INFERRED_GEN : if USE_INFERRED generate
INFERRED_GEN : if (not USE_STRUCTURAL_A) generate
signal icount_out : unsigned(C_NUM_BITS downto 0);
signal icount_out_x : unsigned(C_NUM_BITS downto 0);
signal load_in_x : unsigned(C_NUM_BITS downto 0);
begin
load_in_x <= unsigned('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
-- icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0)); -- Echeck WA
icount_out_x <= unsigned('0' & std_logic_vector(icount_out(C_NUM_BITS-1 downto 0)));
-----------------------------------------------------------------
-- Process to generate counter with - synchronous reset, load,
-- counter enable, count down / up features.
-----------------------------------------------------------------
CNTR_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
icount_out <= (others => '0');
elsif Count_Load = '1' then
icount_out <= load_in_x;
elsif Count_Down = '1' and Count_Enable = '1' then
icount_out <= icount_out_x - 1;
elsif Count_Enable = '1' then
icount_out <= icount_out_x + 1;
end if;
end if;
end process CNTR_PROC;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= std_logic_vector(icount_out(C_NUM_BITS-1 downto 0));
end generate INFERRED_GEN;
end architecture imp;
---------------------------------------------------------------
-- End of file counter_f.vhd
---------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- counter_f - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_f.vhd
--
-- Description: Implements a parameterizable N-bit counter_f
-- Up/Down Counter
-- Count Enable
-- Parallel Load
-- Synchronous Reset
-- The structural implementation has incremental cost
-- of one LUT per bit.
-- Precedence of operations when simultaneous:
-- reset, load, count
--
-- A default inferred-RTL implementation is provided and
-- is used if the user explicitly specifies C_FAMILY=nofamily
-- or ommits C_FAMILY (allowing it to default to nofamily).
-- The default implementation is also used
-- if needed primitives are not available in FPGAs of the
-- type given by C_FAMILY.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- Author: FLO & Nitin 06/06/2006 First Version, functional equivalent
-- of counter.vhd.
-- History:
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.unsigned;
use IEEE.numeric_std."+";
use IEEE.numeric_std."-";
library unisim;
use unisim.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_f is
generic(
C_NUM_BITS : integer := 9;
C_FAMILY : string := "nofamily"
);
port(
Clk : in std_logic;
Rst : in std_logic;
Load_In : in std_logic_vector(C_NUM_BITS - 1 downto 0);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(C_NUM_BITS - 1 downto 0);
Carry_Out : out std_logic
);
end entity counter_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_f is
---------------------------------------------------------------------
-- Component declarations
---------------------------------------------------------------------
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
---------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------
constant USE_STRUCTURAL_A : boolean :=
supported(C_FAMILY, (u_MUXCY_L, u_XORCY, u_FDRE));
constant USE_INFERRED : boolean := not USE_STRUCTURAL_A;
---------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Generate structural code
---------------------------------------------------------------------
STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate
signal alu_cy : std_logic_vector(C_NUM_BITS+1 downto 0);
signal alu_cy_init : std_logic;
signal icount_out : std_logic_vector(C_NUM_BITS downto 0);
signal icount_out_x : std_logic_vector(C_NUM_BITS downto 0);
signal load_in_x : std_logic_vector(C_NUM_BITS downto 0);
signal count_AddSub : std_logic_vector(C_NUM_BITS downto 0);
signal count_Result : std_logic_vector(C_NUM_BITS downto 0);
signal count_clock_en : std_logic;
begin
alu_cy_init <= (Count_Down and Count_Load) or
(not Count_Down and not Count_load);
I_MUXCY_I : component MUXCY_L
port map (
DI => '0',
CI => '1',
S => alu_cy_init,
LO => alu_cy(0));
count_clock_en <= Count_Enable or Count_Load;
load_in_x <= ('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0));
-----------------------------------------------------------------
-- Generate counter using MUXCY_L, XORCY and FDRE
-----------------------------------------------------------------
I_ADDSUB_GEN : for i in 0 to C_NUM_BITS generate
count_AddSub(i) <= load_in_x(i) xor Count_Down
when Count_Load ='1' else
icount_out_x(i) xor Count_Down ; -- LUT
MUXCY_I : component MUXCY_L
port map (
DI => Count_Down,
CI => alu_cy(i),
S => count_AddSub(i),
LO => alu_cy(i+1));
XOR_I : component XORCY
port map (
LI => count_AddSub(i),
CI => alu_cy(i),
O => count_Result(i));
FDRE_I: component FDRE
port map (
Q => iCount_Out(i),
C => Clk,
CE => count_clock_en,
D => count_Result(i),
R => Rst);
end generate I_ADDSUB_GEN;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= icount_out(C_NUM_BITS-1 downto 0);
end generate STRUCTURAL_A_GEN;
---------------------------------------------------------------------
-- Generate Inferred code
---------------------------------------------------------------------
--INFERRED_GEN : if USE_INFERRED generate
INFERRED_GEN : if (not USE_STRUCTURAL_A) generate
signal icount_out : unsigned(C_NUM_BITS downto 0);
signal icount_out_x : unsigned(C_NUM_BITS downto 0);
signal load_in_x : unsigned(C_NUM_BITS downto 0);
begin
load_in_x <= unsigned('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
-- icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0)); -- Echeck WA
icount_out_x <= unsigned('0' & std_logic_vector(icount_out(C_NUM_BITS-1 downto 0)));
-----------------------------------------------------------------
-- Process to generate counter with - synchronous reset, load,
-- counter enable, count down / up features.
-----------------------------------------------------------------
CNTR_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
icount_out <= (others => '0');
elsif Count_Load = '1' then
icount_out <= load_in_x;
elsif Count_Down = '1' and Count_Enable = '1' then
icount_out <= icount_out_x - 1;
elsif Count_Enable = '1' then
icount_out <= icount_out_x + 1;
end if;
end if;
end process CNTR_PROC;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= std_logic_vector(icount_out(C_NUM_BITS-1 downto 0));
end generate INFERRED_GEN;
end architecture imp;
---------------------------------------------------------------
-- End of file counter_f.vhd
---------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- counter_f - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_f.vhd
--
-- Description: Implements a parameterizable N-bit counter_f
-- Up/Down Counter
-- Count Enable
-- Parallel Load
-- Synchronous Reset
-- The structural implementation has incremental cost
-- of one LUT per bit.
-- Precedence of operations when simultaneous:
-- reset, load, count
--
-- A default inferred-RTL implementation is provided and
-- is used if the user explicitly specifies C_FAMILY=nofamily
-- or ommits C_FAMILY (allowing it to default to nofamily).
-- The default implementation is also used
-- if needed primitives are not available in FPGAs of the
-- type given by C_FAMILY.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- Author: FLO & Nitin 06/06/2006 First Version, functional equivalent
-- of counter.vhd.
-- History:
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.unsigned;
use IEEE.numeric_std."+";
use IEEE.numeric_std."-";
library unisim;
use unisim.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_f is
generic(
C_NUM_BITS : integer := 9;
C_FAMILY : string := "nofamily"
);
port(
Clk : in std_logic;
Rst : in std_logic;
Load_In : in std_logic_vector(C_NUM_BITS - 1 downto 0);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(C_NUM_BITS - 1 downto 0);
Carry_Out : out std_logic
);
end entity counter_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_f is
---------------------------------------------------------------------
-- Component declarations
---------------------------------------------------------------------
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
---------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------
constant USE_STRUCTURAL_A : boolean :=
supported(C_FAMILY, (u_MUXCY_L, u_XORCY, u_FDRE));
constant USE_INFERRED : boolean := not USE_STRUCTURAL_A;
---------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Generate structural code
---------------------------------------------------------------------
STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate
signal alu_cy : std_logic_vector(C_NUM_BITS+1 downto 0);
signal alu_cy_init : std_logic;
signal icount_out : std_logic_vector(C_NUM_BITS downto 0);
signal icount_out_x : std_logic_vector(C_NUM_BITS downto 0);
signal load_in_x : std_logic_vector(C_NUM_BITS downto 0);
signal count_AddSub : std_logic_vector(C_NUM_BITS downto 0);
signal count_Result : std_logic_vector(C_NUM_BITS downto 0);
signal count_clock_en : std_logic;
begin
alu_cy_init <= (Count_Down and Count_Load) or
(not Count_Down and not Count_load);
I_MUXCY_I : component MUXCY_L
port map (
DI => '0',
CI => '1',
S => alu_cy_init,
LO => alu_cy(0));
count_clock_en <= Count_Enable or Count_Load;
load_in_x <= ('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0));
-----------------------------------------------------------------
-- Generate counter using MUXCY_L, XORCY and FDRE
-----------------------------------------------------------------
I_ADDSUB_GEN : for i in 0 to C_NUM_BITS generate
count_AddSub(i) <= load_in_x(i) xor Count_Down
when Count_Load ='1' else
icount_out_x(i) xor Count_Down ; -- LUT
MUXCY_I : component MUXCY_L
port map (
DI => Count_Down,
CI => alu_cy(i),
S => count_AddSub(i),
LO => alu_cy(i+1));
XOR_I : component XORCY
port map (
LI => count_AddSub(i),
CI => alu_cy(i),
O => count_Result(i));
FDRE_I: component FDRE
port map (
Q => iCount_Out(i),
C => Clk,
CE => count_clock_en,
D => count_Result(i),
R => Rst);
end generate I_ADDSUB_GEN;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= icount_out(C_NUM_BITS-1 downto 0);
end generate STRUCTURAL_A_GEN;
---------------------------------------------------------------------
-- Generate Inferred code
---------------------------------------------------------------------
--INFERRED_GEN : if USE_INFERRED generate
INFERRED_GEN : if (not USE_STRUCTURAL_A) generate
signal icount_out : unsigned(C_NUM_BITS downto 0);
signal icount_out_x : unsigned(C_NUM_BITS downto 0);
signal load_in_x : unsigned(C_NUM_BITS downto 0);
begin
load_in_x <= unsigned('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
-- icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0)); -- Echeck WA
icount_out_x <= unsigned('0' & std_logic_vector(icount_out(C_NUM_BITS-1 downto 0)));
-----------------------------------------------------------------
-- Process to generate counter with - synchronous reset, load,
-- counter enable, count down / up features.
-----------------------------------------------------------------
CNTR_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
icount_out <= (others => '0');
elsif Count_Load = '1' then
icount_out <= load_in_x;
elsif Count_Down = '1' and Count_Enable = '1' then
icount_out <= icount_out_x - 1;
elsif Count_Enable = '1' then
icount_out <= icount_out_x + 1;
end if;
end if;
end process CNTR_PROC;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= std_logic_vector(icount_out(C_NUM_BITS-1 downto 0));
end generate INFERRED_GEN;
end architecture imp;
---------------------------------------------------------------
-- End of file counter_f.vhd
---------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- counter_f - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_f.vhd
--
-- Description: Implements a parameterizable N-bit counter_f
-- Up/Down Counter
-- Count Enable
-- Parallel Load
-- Synchronous Reset
-- The structural implementation has incremental cost
-- of one LUT per bit.
-- Precedence of operations when simultaneous:
-- reset, load, count
--
-- A default inferred-RTL implementation is provided and
-- is used if the user explicitly specifies C_FAMILY=nofamily
-- or ommits C_FAMILY (allowing it to default to nofamily).
-- The default implementation is also used
-- if needed primitives are not available in FPGAs of the
-- type given by C_FAMILY.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- Author: FLO & Nitin 06/06/2006 First Version, functional equivalent
-- of counter.vhd.
-- History:
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.unsigned;
use IEEE.numeric_std."+";
use IEEE.numeric_std."-";
library unisim;
use unisim.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_f is
generic(
C_NUM_BITS : integer := 9;
C_FAMILY : string := "nofamily"
);
port(
Clk : in std_logic;
Rst : in std_logic;
Load_In : in std_logic_vector(C_NUM_BITS - 1 downto 0);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(C_NUM_BITS - 1 downto 0);
Carry_Out : out std_logic
);
end entity counter_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_f is
---------------------------------------------------------------------
-- Component declarations
---------------------------------------------------------------------
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
---------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------
constant USE_STRUCTURAL_A : boolean :=
supported(C_FAMILY, (u_MUXCY_L, u_XORCY, u_FDRE));
constant USE_INFERRED : boolean := not USE_STRUCTURAL_A;
---------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Generate structural code
---------------------------------------------------------------------
STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate
signal alu_cy : std_logic_vector(C_NUM_BITS+1 downto 0);
signal alu_cy_init : std_logic;
signal icount_out : std_logic_vector(C_NUM_BITS downto 0);
signal icount_out_x : std_logic_vector(C_NUM_BITS downto 0);
signal load_in_x : std_logic_vector(C_NUM_BITS downto 0);
signal count_AddSub : std_logic_vector(C_NUM_BITS downto 0);
signal count_Result : std_logic_vector(C_NUM_BITS downto 0);
signal count_clock_en : std_logic;
begin
alu_cy_init <= (Count_Down and Count_Load) or
(not Count_Down and not Count_load);
I_MUXCY_I : component MUXCY_L
port map (
DI => '0',
CI => '1',
S => alu_cy_init,
LO => alu_cy(0));
count_clock_en <= Count_Enable or Count_Load;
load_in_x <= ('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0));
-----------------------------------------------------------------
-- Generate counter using MUXCY_L, XORCY and FDRE
-----------------------------------------------------------------
I_ADDSUB_GEN : for i in 0 to C_NUM_BITS generate
count_AddSub(i) <= load_in_x(i) xor Count_Down
when Count_Load ='1' else
icount_out_x(i) xor Count_Down ; -- LUT
MUXCY_I : component MUXCY_L
port map (
DI => Count_Down,
CI => alu_cy(i),
S => count_AddSub(i),
LO => alu_cy(i+1));
XOR_I : component XORCY
port map (
LI => count_AddSub(i),
CI => alu_cy(i),
O => count_Result(i));
FDRE_I: component FDRE
port map (
Q => iCount_Out(i),
C => Clk,
CE => count_clock_en,
D => count_Result(i),
R => Rst);
end generate I_ADDSUB_GEN;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= icount_out(C_NUM_BITS-1 downto 0);
end generate STRUCTURAL_A_GEN;
---------------------------------------------------------------------
-- Generate Inferred code
---------------------------------------------------------------------
--INFERRED_GEN : if USE_INFERRED generate
INFERRED_GEN : if (not USE_STRUCTURAL_A) generate
signal icount_out : unsigned(C_NUM_BITS downto 0);
signal icount_out_x : unsigned(C_NUM_BITS downto 0);
signal load_in_x : unsigned(C_NUM_BITS downto 0);
begin
load_in_x <= unsigned('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
-- icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0)); -- Echeck WA
icount_out_x <= unsigned('0' & std_logic_vector(icount_out(C_NUM_BITS-1 downto 0)));
-----------------------------------------------------------------
-- Process to generate counter with - synchronous reset, load,
-- counter enable, count down / up features.
-----------------------------------------------------------------
CNTR_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
icount_out <= (others => '0');
elsif Count_Load = '1' then
icount_out <= load_in_x;
elsif Count_Down = '1' and Count_Enable = '1' then
icount_out <= icount_out_x - 1;
elsif Count_Enable = '1' then
icount_out <= icount_out_x + 1;
end if;
end if;
end process CNTR_PROC;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= std_logic_vector(icount_out(C_NUM_BITS-1 downto 0));
end generate INFERRED_GEN;
end architecture imp;
---------------------------------------------------------------
-- End of file counter_f.vhd
---------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- counter_f - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_f.vhd
--
-- Description: Implements a parameterizable N-bit counter_f
-- Up/Down Counter
-- Count Enable
-- Parallel Load
-- Synchronous Reset
-- The structural implementation has incremental cost
-- of one LUT per bit.
-- Precedence of operations when simultaneous:
-- reset, load, count
--
-- A default inferred-RTL implementation is provided and
-- is used if the user explicitly specifies C_FAMILY=nofamily
-- or ommits C_FAMILY (allowing it to default to nofamily).
-- The default implementation is also used
-- if needed primitives are not available in FPGAs of the
-- type given by C_FAMILY.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- Author: FLO & Nitin 06/06/2006 First Version, functional equivalent
-- of counter.vhd.
-- History:
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.unsigned;
use IEEE.numeric_std."+";
use IEEE.numeric_std."-";
library unisim;
use unisim.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_f is
generic(
C_NUM_BITS : integer := 9;
C_FAMILY : string := "nofamily"
);
port(
Clk : in std_logic;
Rst : in std_logic;
Load_In : in std_logic_vector(C_NUM_BITS - 1 downto 0);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(C_NUM_BITS - 1 downto 0);
Carry_Out : out std_logic
);
end entity counter_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_f is
---------------------------------------------------------------------
-- Component declarations
---------------------------------------------------------------------
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
---------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------
constant USE_STRUCTURAL_A : boolean :=
supported(C_FAMILY, (u_MUXCY_L, u_XORCY, u_FDRE));
constant USE_INFERRED : boolean := not USE_STRUCTURAL_A;
---------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Generate structural code
---------------------------------------------------------------------
STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate
signal alu_cy : std_logic_vector(C_NUM_BITS+1 downto 0);
signal alu_cy_init : std_logic;
signal icount_out : std_logic_vector(C_NUM_BITS downto 0);
signal icount_out_x : std_logic_vector(C_NUM_BITS downto 0);
signal load_in_x : std_logic_vector(C_NUM_BITS downto 0);
signal count_AddSub : std_logic_vector(C_NUM_BITS downto 0);
signal count_Result : std_logic_vector(C_NUM_BITS downto 0);
signal count_clock_en : std_logic;
begin
alu_cy_init <= (Count_Down and Count_Load) or
(not Count_Down and not Count_load);
I_MUXCY_I : component MUXCY_L
port map (
DI => '0',
CI => '1',
S => alu_cy_init,
LO => alu_cy(0));
count_clock_en <= Count_Enable or Count_Load;
load_in_x <= ('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0));
-----------------------------------------------------------------
-- Generate counter using MUXCY_L, XORCY and FDRE
-----------------------------------------------------------------
I_ADDSUB_GEN : for i in 0 to C_NUM_BITS generate
count_AddSub(i) <= load_in_x(i) xor Count_Down
when Count_Load ='1' else
icount_out_x(i) xor Count_Down ; -- LUT
MUXCY_I : component MUXCY_L
port map (
DI => Count_Down,
CI => alu_cy(i),
S => count_AddSub(i),
LO => alu_cy(i+1));
XOR_I : component XORCY
port map (
LI => count_AddSub(i),
CI => alu_cy(i),
O => count_Result(i));
FDRE_I: component FDRE
port map (
Q => iCount_Out(i),
C => Clk,
CE => count_clock_en,
D => count_Result(i),
R => Rst);
end generate I_ADDSUB_GEN;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= icount_out(C_NUM_BITS-1 downto 0);
end generate STRUCTURAL_A_GEN;
---------------------------------------------------------------------
-- Generate Inferred code
---------------------------------------------------------------------
--INFERRED_GEN : if USE_INFERRED generate
INFERRED_GEN : if (not USE_STRUCTURAL_A) generate
signal icount_out : unsigned(C_NUM_BITS downto 0);
signal icount_out_x : unsigned(C_NUM_BITS downto 0);
signal load_in_x : unsigned(C_NUM_BITS downto 0);
begin
load_in_x <= unsigned('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
-- icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0)); -- Echeck WA
icount_out_x <= unsigned('0' & std_logic_vector(icount_out(C_NUM_BITS-1 downto 0)));
-----------------------------------------------------------------
-- Process to generate counter with - synchronous reset, load,
-- counter enable, count down / up features.
-----------------------------------------------------------------
CNTR_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
icount_out <= (others => '0');
elsif Count_Load = '1' then
icount_out <= load_in_x;
elsif Count_Down = '1' and Count_Enable = '1' then
icount_out <= icount_out_x - 1;
elsif Count_Enable = '1' then
icount_out <= icount_out_x + 1;
end if;
end if;
end process CNTR_PROC;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= std_logic_vector(icount_out(C_NUM_BITS-1 downto 0));
end generate INFERRED_GEN;
end architecture imp;
---------------------------------------------------------------
-- End of file counter_f.vhd
---------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- counter_f - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_f.vhd
--
-- Description: Implements a parameterizable N-bit counter_f
-- Up/Down Counter
-- Count Enable
-- Parallel Load
-- Synchronous Reset
-- The structural implementation has incremental cost
-- of one LUT per bit.
-- Precedence of operations when simultaneous:
-- reset, load, count
--
-- A default inferred-RTL implementation is provided and
-- is used if the user explicitly specifies C_FAMILY=nofamily
-- or ommits C_FAMILY (allowing it to default to nofamily).
-- The default implementation is also used
-- if needed primitives are not available in FPGAs of the
-- type given by C_FAMILY.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- Author: FLO & Nitin 06/06/2006 First Version, functional equivalent
-- of counter.vhd.
-- History:
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.unsigned;
use IEEE.numeric_std."+";
use IEEE.numeric_std."-";
library unisim;
use unisim.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_f is
generic(
C_NUM_BITS : integer := 9;
C_FAMILY : string := "nofamily"
);
port(
Clk : in std_logic;
Rst : in std_logic;
Load_In : in std_logic_vector(C_NUM_BITS - 1 downto 0);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(C_NUM_BITS - 1 downto 0);
Carry_Out : out std_logic
);
end entity counter_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_f is
---------------------------------------------------------------------
-- Component declarations
---------------------------------------------------------------------
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
---------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------
constant USE_STRUCTURAL_A : boolean :=
supported(C_FAMILY, (u_MUXCY_L, u_XORCY, u_FDRE));
constant USE_INFERRED : boolean := not USE_STRUCTURAL_A;
---------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Generate structural code
---------------------------------------------------------------------
STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate
signal alu_cy : std_logic_vector(C_NUM_BITS+1 downto 0);
signal alu_cy_init : std_logic;
signal icount_out : std_logic_vector(C_NUM_BITS downto 0);
signal icount_out_x : std_logic_vector(C_NUM_BITS downto 0);
signal load_in_x : std_logic_vector(C_NUM_BITS downto 0);
signal count_AddSub : std_logic_vector(C_NUM_BITS downto 0);
signal count_Result : std_logic_vector(C_NUM_BITS downto 0);
signal count_clock_en : std_logic;
begin
alu_cy_init <= (Count_Down and Count_Load) or
(not Count_Down and not Count_load);
I_MUXCY_I : component MUXCY_L
port map (
DI => '0',
CI => '1',
S => alu_cy_init,
LO => alu_cy(0));
count_clock_en <= Count_Enable or Count_Load;
load_in_x <= ('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0));
-----------------------------------------------------------------
-- Generate counter using MUXCY_L, XORCY and FDRE
-----------------------------------------------------------------
I_ADDSUB_GEN : for i in 0 to C_NUM_BITS generate
count_AddSub(i) <= load_in_x(i) xor Count_Down
when Count_Load ='1' else
icount_out_x(i) xor Count_Down ; -- LUT
MUXCY_I : component MUXCY_L
port map (
DI => Count_Down,
CI => alu_cy(i),
S => count_AddSub(i),
LO => alu_cy(i+1));
XOR_I : component XORCY
port map (
LI => count_AddSub(i),
CI => alu_cy(i),
O => count_Result(i));
FDRE_I: component FDRE
port map (
Q => iCount_Out(i),
C => Clk,
CE => count_clock_en,
D => count_Result(i),
R => Rst);
end generate I_ADDSUB_GEN;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= icount_out(C_NUM_BITS-1 downto 0);
end generate STRUCTURAL_A_GEN;
---------------------------------------------------------------------
-- Generate Inferred code
---------------------------------------------------------------------
--INFERRED_GEN : if USE_INFERRED generate
INFERRED_GEN : if (not USE_STRUCTURAL_A) generate
signal icount_out : unsigned(C_NUM_BITS downto 0);
signal icount_out_x : unsigned(C_NUM_BITS downto 0);
signal load_in_x : unsigned(C_NUM_BITS downto 0);
begin
load_in_x <= unsigned('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
-- icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0)); -- Echeck WA
icount_out_x <= unsigned('0' & std_logic_vector(icount_out(C_NUM_BITS-1 downto 0)));
-----------------------------------------------------------------
-- Process to generate counter with - synchronous reset, load,
-- counter enable, count down / up features.
-----------------------------------------------------------------
CNTR_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
icount_out <= (others => '0');
elsif Count_Load = '1' then
icount_out <= load_in_x;
elsif Count_Down = '1' and Count_Enable = '1' then
icount_out <= icount_out_x - 1;
elsif Count_Enable = '1' then
icount_out <= icount_out_x + 1;
end if;
end if;
end process CNTR_PROC;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= std_logic_vector(icount_out(C_NUM_BITS-1 downto 0));
end generate INFERRED_GEN;
end architecture imp;
---------------------------------------------------------------
-- End of file counter_f.vhd
---------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- counter_f - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_f.vhd
--
-- Description: Implements a parameterizable N-bit counter_f
-- Up/Down Counter
-- Count Enable
-- Parallel Load
-- Synchronous Reset
-- The structural implementation has incremental cost
-- of one LUT per bit.
-- Precedence of operations when simultaneous:
-- reset, load, count
--
-- A default inferred-RTL implementation is provided and
-- is used if the user explicitly specifies C_FAMILY=nofamily
-- or ommits C_FAMILY (allowing it to default to nofamily).
-- The default implementation is also used
-- if needed primitives are not available in FPGAs of the
-- type given by C_FAMILY.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- Author: FLO & Nitin 06/06/2006 First Version, functional equivalent
-- of counter.vhd.
-- History:
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.unsigned;
use IEEE.numeric_std."+";
use IEEE.numeric_std."-";
library unisim;
use unisim.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_f is
generic(
C_NUM_BITS : integer := 9;
C_FAMILY : string := "nofamily"
);
port(
Clk : in std_logic;
Rst : in std_logic;
Load_In : in std_logic_vector(C_NUM_BITS - 1 downto 0);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(C_NUM_BITS - 1 downto 0);
Carry_Out : out std_logic
);
end entity counter_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_f is
---------------------------------------------------------------------
-- Component declarations
---------------------------------------------------------------------
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
---------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------
constant USE_STRUCTURAL_A : boolean :=
supported(C_FAMILY, (u_MUXCY_L, u_XORCY, u_FDRE));
constant USE_INFERRED : boolean := not USE_STRUCTURAL_A;
---------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Generate structural code
---------------------------------------------------------------------
STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate
signal alu_cy : std_logic_vector(C_NUM_BITS+1 downto 0);
signal alu_cy_init : std_logic;
signal icount_out : std_logic_vector(C_NUM_BITS downto 0);
signal icount_out_x : std_logic_vector(C_NUM_BITS downto 0);
signal load_in_x : std_logic_vector(C_NUM_BITS downto 0);
signal count_AddSub : std_logic_vector(C_NUM_BITS downto 0);
signal count_Result : std_logic_vector(C_NUM_BITS downto 0);
signal count_clock_en : std_logic;
begin
alu_cy_init <= (Count_Down and Count_Load) or
(not Count_Down and not Count_load);
I_MUXCY_I : component MUXCY_L
port map (
DI => '0',
CI => '1',
S => alu_cy_init,
LO => alu_cy(0));
count_clock_en <= Count_Enable or Count_Load;
load_in_x <= ('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0));
-----------------------------------------------------------------
-- Generate counter using MUXCY_L, XORCY and FDRE
-----------------------------------------------------------------
I_ADDSUB_GEN : for i in 0 to C_NUM_BITS generate
count_AddSub(i) <= load_in_x(i) xor Count_Down
when Count_Load ='1' else
icount_out_x(i) xor Count_Down ; -- LUT
MUXCY_I : component MUXCY_L
port map (
DI => Count_Down,
CI => alu_cy(i),
S => count_AddSub(i),
LO => alu_cy(i+1));
XOR_I : component XORCY
port map (
LI => count_AddSub(i),
CI => alu_cy(i),
O => count_Result(i));
FDRE_I: component FDRE
port map (
Q => iCount_Out(i),
C => Clk,
CE => count_clock_en,
D => count_Result(i),
R => Rst);
end generate I_ADDSUB_GEN;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= icount_out(C_NUM_BITS-1 downto 0);
end generate STRUCTURAL_A_GEN;
---------------------------------------------------------------------
-- Generate Inferred code
---------------------------------------------------------------------
--INFERRED_GEN : if USE_INFERRED generate
INFERRED_GEN : if (not USE_STRUCTURAL_A) generate
signal icount_out : unsigned(C_NUM_BITS downto 0);
signal icount_out_x : unsigned(C_NUM_BITS downto 0);
signal load_in_x : unsigned(C_NUM_BITS downto 0);
begin
load_in_x <= unsigned('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
-- icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0)); -- Echeck WA
icount_out_x <= unsigned('0' & std_logic_vector(icount_out(C_NUM_BITS-1 downto 0)));
-----------------------------------------------------------------
-- Process to generate counter with - synchronous reset, load,
-- counter enable, count down / up features.
-----------------------------------------------------------------
CNTR_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
icount_out <= (others => '0');
elsif Count_Load = '1' then
icount_out <= load_in_x;
elsif Count_Down = '1' and Count_Enable = '1' then
icount_out <= icount_out_x - 1;
elsif Count_Enable = '1' then
icount_out <= icount_out_x + 1;
end if;
end if;
end process CNTR_PROC;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= std_logic_vector(icount_out(C_NUM_BITS-1 downto 0));
end generate INFERRED_GEN;
end architecture imp;
---------------------------------------------------------------
-- End of file counter_f.vhd
---------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- counter_f - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_f.vhd
--
-- Description: Implements a parameterizable N-bit counter_f
-- Up/Down Counter
-- Count Enable
-- Parallel Load
-- Synchronous Reset
-- The structural implementation has incremental cost
-- of one LUT per bit.
-- Precedence of operations when simultaneous:
-- reset, load, count
--
-- A default inferred-RTL implementation is provided and
-- is used if the user explicitly specifies C_FAMILY=nofamily
-- or ommits C_FAMILY (allowing it to default to nofamily).
-- The default implementation is also used
-- if needed primitives are not available in FPGAs of the
-- type given by C_FAMILY.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- Author: FLO & Nitin 06/06/2006 First Version, functional equivalent
-- of counter.vhd.
-- History:
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.unsigned;
use IEEE.numeric_std."+";
use IEEE.numeric_std."-";
library unisim;
use unisim.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_f is
generic(
C_NUM_BITS : integer := 9;
C_FAMILY : string := "nofamily"
);
port(
Clk : in std_logic;
Rst : in std_logic;
Load_In : in std_logic_vector(C_NUM_BITS - 1 downto 0);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(C_NUM_BITS - 1 downto 0);
Carry_Out : out std_logic
);
end entity counter_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_f is
---------------------------------------------------------------------
-- Component declarations
---------------------------------------------------------------------
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
---------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------
constant USE_STRUCTURAL_A : boolean :=
supported(C_FAMILY, (u_MUXCY_L, u_XORCY, u_FDRE));
constant USE_INFERRED : boolean := not USE_STRUCTURAL_A;
---------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Generate structural code
---------------------------------------------------------------------
STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate
signal alu_cy : std_logic_vector(C_NUM_BITS+1 downto 0);
signal alu_cy_init : std_logic;
signal icount_out : std_logic_vector(C_NUM_BITS downto 0);
signal icount_out_x : std_logic_vector(C_NUM_BITS downto 0);
signal load_in_x : std_logic_vector(C_NUM_BITS downto 0);
signal count_AddSub : std_logic_vector(C_NUM_BITS downto 0);
signal count_Result : std_logic_vector(C_NUM_BITS downto 0);
signal count_clock_en : std_logic;
begin
alu_cy_init <= (Count_Down and Count_Load) or
(not Count_Down and not Count_load);
I_MUXCY_I : component MUXCY_L
port map (
DI => '0',
CI => '1',
S => alu_cy_init,
LO => alu_cy(0));
count_clock_en <= Count_Enable or Count_Load;
load_in_x <= ('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0));
-----------------------------------------------------------------
-- Generate counter using MUXCY_L, XORCY and FDRE
-----------------------------------------------------------------
I_ADDSUB_GEN : for i in 0 to C_NUM_BITS generate
count_AddSub(i) <= load_in_x(i) xor Count_Down
when Count_Load ='1' else
icount_out_x(i) xor Count_Down ; -- LUT
MUXCY_I : component MUXCY_L
port map (
DI => Count_Down,
CI => alu_cy(i),
S => count_AddSub(i),
LO => alu_cy(i+1));
XOR_I : component XORCY
port map (
LI => count_AddSub(i),
CI => alu_cy(i),
O => count_Result(i));
FDRE_I: component FDRE
port map (
Q => iCount_Out(i),
C => Clk,
CE => count_clock_en,
D => count_Result(i),
R => Rst);
end generate I_ADDSUB_GEN;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= icount_out(C_NUM_BITS-1 downto 0);
end generate STRUCTURAL_A_GEN;
---------------------------------------------------------------------
-- Generate Inferred code
---------------------------------------------------------------------
--INFERRED_GEN : if USE_INFERRED generate
INFERRED_GEN : if (not USE_STRUCTURAL_A) generate
signal icount_out : unsigned(C_NUM_BITS downto 0);
signal icount_out_x : unsigned(C_NUM_BITS downto 0);
signal load_in_x : unsigned(C_NUM_BITS downto 0);
begin
load_in_x <= unsigned('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
-- icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0)); -- Echeck WA
icount_out_x <= unsigned('0' & std_logic_vector(icount_out(C_NUM_BITS-1 downto 0)));
-----------------------------------------------------------------
-- Process to generate counter with - synchronous reset, load,
-- counter enable, count down / up features.
-----------------------------------------------------------------
CNTR_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
icount_out <= (others => '0');
elsif Count_Load = '1' then
icount_out <= load_in_x;
elsif Count_Down = '1' and Count_Enable = '1' then
icount_out <= icount_out_x - 1;
elsif Count_Enable = '1' then
icount_out <= icount_out_x + 1;
end if;
end if;
end process CNTR_PROC;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= std_logic_vector(icount_out(C_NUM_BITS-1 downto 0));
end generate INFERRED_GEN;
end architecture imp;
---------------------------------------------------------------
-- End of file counter_f.vhd
---------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- counter_f - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_f.vhd
--
-- Description: Implements a parameterizable N-bit counter_f
-- Up/Down Counter
-- Count Enable
-- Parallel Load
-- Synchronous Reset
-- The structural implementation has incremental cost
-- of one LUT per bit.
-- Precedence of operations when simultaneous:
-- reset, load, count
--
-- A default inferred-RTL implementation is provided and
-- is used if the user explicitly specifies C_FAMILY=nofamily
-- or ommits C_FAMILY (allowing it to default to nofamily).
-- The default implementation is also used
-- if needed primitives are not available in FPGAs of the
-- type given by C_FAMILY.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- Author: FLO & Nitin 06/06/2006 First Version, functional equivalent
-- of counter.vhd.
-- History:
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.unsigned;
use IEEE.numeric_std."+";
use IEEE.numeric_std."-";
library unisim;
use unisim.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_f is
generic(
C_NUM_BITS : integer := 9;
C_FAMILY : string := "nofamily"
);
port(
Clk : in std_logic;
Rst : in std_logic;
Load_In : in std_logic_vector(C_NUM_BITS - 1 downto 0);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(C_NUM_BITS - 1 downto 0);
Carry_Out : out std_logic
);
end entity counter_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_f is
---------------------------------------------------------------------
-- Component declarations
---------------------------------------------------------------------
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
---------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------
constant USE_STRUCTURAL_A : boolean :=
supported(C_FAMILY, (u_MUXCY_L, u_XORCY, u_FDRE));
constant USE_INFERRED : boolean := not USE_STRUCTURAL_A;
---------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Generate structural code
---------------------------------------------------------------------
STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate
signal alu_cy : std_logic_vector(C_NUM_BITS+1 downto 0);
signal alu_cy_init : std_logic;
signal icount_out : std_logic_vector(C_NUM_BITS downto 0);
signal icount_out_x : std_logic_vector(C_NUM_BITS downto 0);
signal load_in_x : std_logic_vector(C_NUM_BITS downto 0);
signal count_AddSub : std_logic_vector(C_NUM_BITS downto 0);
signal count_Result : std_logic_vector(C_NUM_BITS downto 0);
signal count_clock_en : std_logic;
begin
alu_cy_init <= (Count_Down and Count_Load) or
(not Count_Down and not Count_load);
I_MUXCY_I : component MUXCY_L
port map (
DI => '0',
CI => '1',
S => alu_cy_init,
LO => alu_cy(0));
count_clock_en <= Count_Enable or Count_Load;
load_in_x <= ('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0));
-----------------------------------------------------------------
-- Generate counter using MUXCY_L, XORCY and FDRE
-----------------------------------------------------------------
I_ADDSUB_GEN : for i in 0 to C_NUM_BITS generate
count_AddSub(i) <= load_in_x(i) xor Count_Down
when Count_Load ='1' else
icount_out_x(i) xor Count_Down ; -- LUT
MUXCY_I : component MUXCY_L
port map (
DI => Count_Down,
CI => alu_cy(i),
S => count_AddSub(i),
LO => alu_cy(i+1));
XOR_I : component XORCY
port map (
LI => count_AddSub(i),
CI => alu_cy(i),
O => count_Result(i));
FDRE_I: component FDRE
port map (
Q => iCount_Out(i),
C => Clk,
CE => count_clock_en,
D => count_Result(i),
R => Rst);
end generate I_ADDSUB_GEN;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= icount_out(C_NUM_BITS-1 downto 0);
end generate STRUCTURAL_A_GEN;
---------------------------------------------------------------------
-- Generate Inferred code
---------------------------------------------------------------------
--INFERRED_GEN : if USE_INFERRED generate
INFERRED_GEN : if (not USE_STRUCTURAL_A) generate
signal icount_out : unsigned(C_NUM_BITS downto 0);
signal icount_out_x : unsigned(C_NUM_BITS downto 0);
signal load_in_x : unsigned(C_NUM_BITS downto 0);
begin
load_in_x <= unsigned('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
-- icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0)); -- Echeck WA
icount_out_x <= unsigned('0' & std_logic_vector(icount_out(C_NUM_BITS-1 downto 0)));
-----------------------------------------------------------------
-- Process to generate counter with - synchronous reset, load,
-- counter enable, count down / up features.
-----------------------------------------------------------------
CNTR_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
icount_out <= (others => '0');
elsif Count_Load = '1' then
icount_out <= load_in_x;
elsif Count_Down = '1' and Count_Enable = '1' then
icount_out <= icount_out_x - 1;
elsif Count_Enable = '1' then
icount_out <= icount_out_x + 1;
end if;
end if;
end process CNTR_PROC;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= std_logic_vector(icount_out(C_NUM_BITS-1 downto 0));
end generate INFERRED_GEN;
end architecture imp;
---------------------------------------------------------------
-- End of file counter_f.vhd
---------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- counter_f - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_f.vhd
--
-- Description: Implements a parameterizable N-bit counter_f
-- Up/Down Counter
-- Count Enable
-- Parallel Load
-- Synchronous Reset
-- The structural implementation has incremental cost
-- of one LUT per bit.
-- Precedence of operations when simultaneous:
-- reset, load, count
--
-- A default inferred-RTL implementation is provided and
-- is used if the user explicitly specifies C_FAMILY=nofamily
-- or ommits C_FAMILY (allowing it to default to nofamily).
-- The default implementation is also used
-- if needed primitives are not available in FPGAs of the
-- type given by C_FAMILY.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- Author: FLO & Nitin 06/06/2006 First Version, functional equivalent
-- of counter.vhd.
-- History:
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.unsigned;
use IEEE.numeric_std."+";
use IEEE.numeric_std."-";
library unisim;
use unisim.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_f is
generic(
C_NUM_BITS : integer := 9;
C_FAMILY : string := "nofamily"
);
port(
Clk : in std_logic;
Rst : in std_logic;
Load_In : in std_logic_vector(C_NUM_BITS - 1 downto 0);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(C_NUM_BITS - 1 downto 0);
Carry_Out : out std_logic
);
end entity counter_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_f is
---------------------------------------------------------------------
-- Component declarations
---------------------------------------------------------------------
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
---------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------
constant USE_STRUCTURAL_A : boolean :=
supported(C_FAMILY, (u_MUXCY_L, u_XORCY, u_FDRE));
constant USE_INFERRED : boolean := not USE_STRUCTURAL_A;
---------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Generate structural code
---------------------------------------------------------------------
STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate
signal alu_cy : std_logic_vector(C_NUM_BITS+1 downto 0);
signal alu_cy_init : std_logic;
signal icount_out : std_logic_vector(C_NUM_BITS downto 0);
signal icount_out_x : std_logic_vector(C_NUM_BITS downto 0);
signal load_in_x : std_logic_vector(C_NUM_BITS downto 0);
signal count_AddSub : std_logic_vector(C_NUM_BITS downto 0);
signal count_Result : std_logic_vector(C_NUM_BITS downto 0);
signal count_clock_en : std_logic;
begin
alu_cy_init <= (Count_Down and Count_Load) or
(not Count_Down and not Count_load);
I_MUXCY_I : component MUXCY_L
port map (
DI => '0',
CI => '1',
S => alu_cy_init,
LO => alu_cy(0));
count_clock_en <= Count_Enable or Count_Load;
load_in_x <= ('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0));
-----------------------------------------------------------------
-- Generate counter using MUXCY_L, XORCY and FDRE
-----------------------------------------------------------------
I_ADDSUB_GEN : for i in 0 to C_NUM_BITS generate
count_AddSub(i) <= load_in_x(i) xor Count_Down
when Count_Load ='1' else
icount_out_x(i) xor Count_Down ; -- LUT
MUXCY_I : component MUXCY_L
port map (
DI => Count_Down,
CI => alu_cy(i),
S => count_AddSub(i),
LO => alu_cy(i+1));
XOR_I : component XORCY
port map (
LI => count_AddSub(i),
CI => alu_cy(i),
O => count_Result(i));
FDRE_I: component FDRE
port map (
Q => iCount_Out(i),
C => Clk,
CE => count_clock_en,
D => count_Result(i),
R => Rst);
end generate I_ADDSUB_GEN;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= icount_out(C_NUM_BITS-1 downto 0);
end generate STRUCTURAL_A_GEN;
---------------------------------------------------------------------
-- Generate Inferred code
---------------------------------------------------------------------
--INFERRED_GEN : if USE_INFERRED generate
INFERRED_GEN : if (not USE_STRUCTURAL_A) generate
signal icount_out : unsigned(C_NUM_BITS downto 0);
signal icount_out_x : unsigned(C_NUM_BITS downto 0);
signal load_in_x : unsigned(C_NUM_BITS downto 0);
begin
load_in_x <= unsigned('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
-- icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0)); -- Echeck WA
icount_out_x <= unsigned('0' & std_logic_vector(icount_out(C_NUM_BITS-1 downto 0)));
-----------------------------------------------------------------
-- Process to generate counter with - synchronous reset, load,
-- counter enable, count down / up features.
-----------------------------------------------------------------
CNTR_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
icount_out <= (others => '0');
elsif Count_Load = '1' then
icount_out <= load_in_x;
elsif Count_Down = '1' and Count_Enable = '1' then
icount_out <= icount_out_x - 1;
elsif Count_Enable = '1' then
icount_out <= icount_out_x + 1;
end if;
end if;
end process CNTR_PROC;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= std_logic_vector(icount_out(C_NUM_BITS-1 downto 0));
end generate INFERRED_GEN;
end architecture imp;
---------------------------------------------------------------
-- End of file counter_f.vhd
---------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- counter_f - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_f.vhd
--
-- Description: Implements a parameterizable N-bit counter_f
-- Up/Down Counter
-- Count Enable
-- Parallel Load
-- Synchronous Reset
-- The structural implementation has incremental cost
-- of one LUT per bit.
-- Precedence of operations when simultaneous:
-- reset, load, count
--
-- A default inferred-RTL implementation is provided and
-- is used if the user explicitly specifies C_FAMILY=nofamily
-- or ommits C_FAMILY (allowing it to default to nofamily).
-- The default implementation is also used
-- if needed primitives are not available in FPGAs of the
-- type given by C_FAMILY.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- Author: FLO & Nitin 06/06/2006 First Version, functional equivalent
-- of counter.vhd.
-- History:
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.unsigned;
use IEEE.numeric_std."+";
use IEEE.numeric_std."-";
library unisim;
use unisim.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_f is
generic(
C_NUM_BITS : integer := 9;
C_FAMILY : string := "nofamily"
);
port(
Clk : in std_logic;
Rst : in std_logic;
Load_In : in std_logic_vector(C_NUM_BITS - 1 downto 0);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(C_NUM_BITS - 1 downto 0);
Carry_Out : out std_logic
);
end entity counter_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_f is
---------------------------------------------------------------------
-- Component declarations
---------------------------------------------------------------------
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
---------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------
constant USE_STRUCTURAL_A : boolean :=
supported(C_FAMILY, (u_MUXCY_L, u_XORCY, u_FDRE));
constant USE_INFERRED : boolean := not USE_STRUCTURAL_A;
---------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Generate structural code
---------------------------------------------------------------------
STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate
signal alu_cy : std_logic_vector(C_NUM_BITS+1 downto 0);
signal alu_cy_init : std_logic;
signal icount_out : std_logic_vector(C_NUM_BITS downto 0);
signal icount_out_x : std_logic_vector(C_NUM_BITS downto 0);
signal load_in_x : std_logic_vector(C_NUM_BITS downto 0);
signal count_AddSub : std_logic_vector(C_NUM_BITS downto 0);
signal count_Result : std_logic_vector(C_NUM_BITS downto 0);
signal count_clock_en : std_logic;
begin
alu_cy_init <= (Count_Down and Count_Load) or
(not Count_Down and not Count_load);
I_MUXCY_I : component MUXCY_L
port map (
DI => '0',
CI => '1',
S => alu_cy_init,
LO => alu_cy(0));
count_clock_en <= Count_Enable or Count_Load;
load_in_x <= ('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0));
-----------------------------------------------------------------
-- Generate counter using MUXCY_L, XORCY and FDRE
-----------------------------------------------------------------
I_ADDSUB_GEN : for i in 0 to C_NUM_BITS generate
count_AddSub(i) <= load_in_x(i) xor Count_Down
when Count_Load ='1' else
icount_out_x(i) xor Count_Down ; -- LUT
MUXCY_I : component MUXCY_L
port map (
DI => Count_Down,
CI => alu_cy(i),
S => count_AddSub(i),
LO => alu_cy(i+1));
XOR_I : component XORCY
port map (
LI => count_AddSub(i),
CI => alu_cy(i),
O => count_Result(i));
FDRE_I: component FDRE
port map (
Q => iCount_Out(i),
C => Clk,
CE => count_clock_en,
D => count_Result(i),
R => Rst);
end generate I_ADDSUB_GEN;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= icount_out(C_NUM_BITS-1 downto 0);
end generate STRUCTURAL_A_GEN;
---------------------------------------------------------------------
-- Generate Inferred code
---------------------------------------------------------------------
--INFERRED_GEN : if USE_INFERRED generate
INFERRED_GEN : if (not USE_STRUCTURAL_A) generate
signal icount_out : unsigned(C_NUM_BITS downto 0);
signal icount_out_x : unsigned(C_NUM_BITS downto 0);
signal load_in_x : unsigned(C_NUM_BITS downto 0);
begin
load_in_x <= unsigned('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
-- icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0)); -- Echeck WA
icount_out_x <= unsigned('0' & std_logic_vector(icount_out(C_NUM_BITS-1 downto 0)));
-----------------------------------------------------------------
-- Process to generate counter with - synchronous reset, load,
-- counter enable, count down / up features.
-----------------------------------------------------------------
CNTR_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
icount_out <= (others => '0');
elsif Count_Load = '1' then
icount_out <= load_in_x;
elsif Count_Down = '1' and Count_Enable = '1' then
icount_out <= icount_out_x - 1;
elsif Count_Enable = '1' then
icount_out <= icount_out_x + 1;
end if;
end if;
end process CNTR_PROC;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= std_logic_vector(icount_out(C_NUM_BITS-1 downto 0));
end generate INFERRED_GEN;
end architecture imp;
---------------------------------------------------------------
-- End of file counter_f.vhd
---------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- Title : includeModuleBVHDL Project :
-------------------------------------------------------------------------------
-- File : includeModuleBVHDL.vhdl Author : Adrian Fiergolski <[email protected]> Company : CERN Created : 2014-09-26 Last update: 2014-09-26 Platform : Standard : VHDL'2008
-------------------------------------------------------------------------------
-- Description: The module to test HDLMake
-------------------------------------------------------------------------------
-- Copyright (c) 2014 CERN
--
-- This file is part of .
--
-- is free firmware: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with . If not, see http://www.gnu.org/licenses/.
-------------------------------------------------------------------------------
-- Revisions : Date Version Author Description 2014-09-26 1.0 afiergol Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity includeModuleBVHDL is
end entity includeModuleBVHDL;
architecture Behavioral of includeModuleBVHDL is
signal probe : STD_LOGIC;
begin -- architecture Behavioral
end architecture Behavioral;
|
-- Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.11.10:36:05
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL is
port (
data_en : out std_logic; -- data_en.wire
ctrl_pak2 : in std_logic_vector(23 downto 0) := (others => '0'); -- ctrl_pak2.wire
ready : in std_logic := '0'; -- ready.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset
data : out std_logic_vector(24 downto 0); -- data.wire
counter_1 : out std_logic_vector(23 downto 0); -- counter_1.wire
check_en : out std_logic; -- check_en.wire
eop : out std_logic; -- eop.wire
ctrl_pak3 : in std_logic_vector(23 downto 0) := (others => '0'); -- ctrl_pak3.wire
colorbar : in std_logic_vector(23 downto 0) := (others => '0'); -- colorbar.wire
ctrl_pak1 : in std_logic_vector(23 downto 0) := (others => '0'); -- ctrl_pak1.wire
col : in std_logic_vector(31 downto 0) := (others => '0'); -- col.wire
sop : out std_logic; -- sop.wire
ctrl_en : out std_logic; -- ctrl_en.wire
row : in std_logic_vector(31 downto 0) := (others => '0') -- row.wire
);
end entity Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL;
architecture rtl of Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_port_GNEPKLLZKY is
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(31 downto 0) -- wire
);
end component alt_dspbuilder_port_GNEPKLLZKY;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_pipelined_adder_GNTWZRTG4I is
generic (
width : natural := 0;
pipeline : integer := 0
);
port (
aclr : in std_logic := 'X'; -- clk
add_sub : in std_logic := 'X'; -- wire
cin : in std_logic := 'X'; -- wire
clock : in std_logic := 'X'; -- clk
cout : out std_logic; -- wire
dataa : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
datab : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
result : out std_logic_vector(width-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_pipelined_adder_GNTWZRTG4I;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component alt_dspbuilder_port_GNEHYJMBQS is
port (
input : in std_logic_vector(24 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(24 downto 0) -- wire
);
end component alt_dspbuilder_port_GNEHYJMBQS;
component alt_dspbuilder_if_statement_GNIV4UP6ZO is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNIV4UP6ZO;
component alt_dspbuilder_counter_GNKAA2ZBZG is
generic (
use_usr_aclr : string := "false";
use_ena : string := "false";
use_cin : string := "false";
use_sset : string := "false";
ndirection : natural := 1;
svalue : string := "0";
use_sload : string := "false";
use_sclr : string := "false";
use_cout : string := "false";
modulus : integer := 256;
use_cnt_ena : string := "false";
width : natural := 8;
use_aset : string := "false";
use_aload : string := "false";
avalue : string := "0"
);
port (
aclr : in std_logic := 'X'; -- clk
aload : in std_logic := 'X'; -- wire
aset : in std_logic := 'X'; -- wire
cin : in std_logic := 'X'; -- wire
clock : in std_logic := 'X'; -- clk
cnt_ena : in std_logic := 'X'; -- wire
cout : out std_logic; -- wire
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
direction : in std_logic := 'X'; -- wire
ena : in std_logic := 'X'; -- wire
q : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X'; -- wire
sload : in std_logic := 'X'; -- wire
sset : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_counter_GNKAA2ZBZG;
component alt_dspbuilder_constant_GNQJ63TWA6 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNQJ63TWA6;
component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP is
port (
check_en : out std_logic; -- wire
ready : in std_logic := 'X'; -- wire
data_en : out std_logic; -- wire
counter : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
Clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
pixel_num : in std_logic_vector(47 downto 0) := (others => 'X'); -- wire
ctrl_en : out std_logic -- wire
);
end component Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP;
component alt_dspbuilder_multiplier_GNEIWYOKUR is
generic (
DEDICATED_MULTIPLIER_CIRCUITRY : string := "AUTO";
Signed : natural := 0;
OutputMsb : integer := 8;
aWidth : natural := 8;
bWidth : natural := 8;
OutputLsb : integer := 0;
pipeline : integer := 0
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
dataa : in std_logic_vector(aWidth-1 downto 0) := (others => 'X'); -- wire
datab : in std_logic_vector(bWidth-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
result : out std_logic_vector(OutputMsb-OutputLsb+1-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_multiplier_GNEIWYOKUR;
component Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT is
port (
eop : out std_logic; -- wire
data_en : in std_logic := 'X'; -- wire
ctrl_pak3 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
ctrl_pak1 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
ctrl_en : in std_logic := 'X'; -- wire
sop : out std_logic; -- wire
data : out std_logic_vector(24 downto 0); -- wire
ctrl_pak2 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
pixel_num : in std_logic_vector(47 downto 0) := (others => 'X'); -- wire
colorbar : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
counter : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
Clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X' -- reset
);
end component Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT;
component alt_dspbuilder_logical_bit_op_GNUQ2R64DV is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNUQ2R64DV;
component alt_dspbuilder_cast_GN7PRGDOVA is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN7PRGDOVA;
component alt_dspbuilder_cast_GNKIWLRTQI is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(47 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNKIWLRTQI;
signal pipelined_adder5user_aclrgnd_output_wire : std_logic; -- Pipelined_Adder5user_aclrGND:output -> Pipelined_Adder5:user_aclr
signal pipelined_adder5enavcc_output_wire : std_logic; -- Pipelined_Adder5enaVCC:output -> Pipelined_Adder5:ena
signal multiplier1user_aclrgnd_output_wire : std_logic; -- Multiplier1user_aclrGND:output -> Multiplier1:user_aclr
signal multiplier1enavcc_output_wire : std_logic; -- Multiplier1enaVCC:output -> Multiplier1:ena
signal ready_0_output_wire : std_logic; -- ready_0:output -> Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP_0:ready
signal counter_q_wire : std_logic_vector(23 downto 0); -- Counter:q -> [If_Statement4:a, Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP_0:counter, Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:counter, counter_1_0:input]
signal test_pattern_generator_main_ctrl_ctrl_top_0_ctrl_en_wire : std_logic; -- Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP_0:ctrl_en -> [Logical_Bit_Operator1:data0, Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:ctrl_en, ctrl_en_0:input]
signal test_pattern_generator_main_ctrl_ctrl_top_0_data_en_wire : std_logic; -- Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP_0:data_en -> [Logical_Bit_Operator11:data0, Logical_Bit_Operator1:data1, Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:data_en, data_en_0:input]
signal logical_bit_operator1_result_wire : std_logic; -- Logical_Bit_Operator1:result -> Counter:cnt_ena
signal if_statement4_true_wire : std_logic; -- If_Statement4:true -> Logical_Bit_Operator11:data1
signal logical_bit_operator11_result_wire : std_logic; -- Logical_Bit_Operator11:result -> Counter:sclr
signal multiplier1_result_wire : std_logic_vector(47 downto 0); -- Multiplier1:result -> [Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP_0:pixel_num, Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:pixel_num, cast43:input]
signal constant4_output_wire : std_logic_vector(23 downto 0); -- Constant4:output -> Pipelined_Adder5:datab
signal pipelined_adder5_result_wire : std_logic_vector(23 downto 0); -- Pipelined_Adder5:result -> If_Statement4:b
signal ctrl_pak1_0_output_wire : std_logic_vector(23 downto 0); -- ctrl_pak1_0:output -> Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:ctrl_pak1
signal ctrl_pak2_0_output_wire : std_logic_vector(23 downto 0); -- ctrl_pak2_0:output -> Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:ctrl_pak2
signal ctrl_pak3_0_output_wire : std_logic_vector(23 downto 0); -- ctrl_pak3_0:output -> Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:ctrl_pak3
signal colorbar_0_output_wire : std_logic_vector(23 downto 0); -- colorbar_0:output -> Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:colorbar
signal test_pattern_generator_main_ctrl_signal_out_0_data_wire : std_logic_vector(24 downto 0); -- Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:data -> data_0:input
signal test_pattern_generator_main_ctrl_signal_out_0_sop_wire : std_logic; -- Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:sop -> sop_0:input
signal test_pattern_generator_main_ctrl_signal_out_0_eop_wire : std_logic; -- Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:eop -> eop_0:input
signal test_pattern_generator_main_ctrl_ctrl_top_0_check_en_wire : std_logic; -- Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP_0:check_en -> check_en_0:input
signal col_0_output_wire : std_logic_vector(31 downto 0); -- col_0:output -> cast41:input
signal cast41_output_wire : std_logic_vector(23 downto 0); -- cast41:output -> Multiplier1:dataa
signal row_0_output_wire : std_logic_vector(31 downto 0); -- row_0:output -> cast42:input
signal cast42_output_wire : std_logic_vector(23 downto 0); -- cast42:output -> Multiplier1:datab
signal cast43_output_wire : std_logic_vector(23 downto 0); -- cast43:output -> Pipelined_Adder5:dataa
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Counter:aclr, Multiplier1:aclr, Pipelined_Adder5:aclr, Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP_0:aclr, Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:aclr]
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Counter:clock, Multiplier1:clock, Pipelined_Adder5:clock, Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP_0:Clock, Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:Clock]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
col_0 : component alt_dspbuilder_port_GNEPKLLZKY
port map (
input => col, -- input.wire
output => col_0_output_wire -- output.wire
);
counter_1_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => counter_q_wire, -- input.wire
output => counter_1 -- output.wire
);
colorbar_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => colorbar, -- input.wire
output => colorbar_0_output_wire -- output.wire
);
pipelined_adder5 : component alt_dspbuilder_pipelined_adder_GNTWZRTG4I
generic map (
width => 24,
pipeline => 0
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => cast43_output_wire, -- dataa.wire
datab => constant4_output_wire, -- datab.wire
result => pipelined_adder5_result_wire, -- result.wire
user_aclr => pipelined_adder5user_aclrgnd_output_wire, -- user_aclr.wire
ena => pipelined_adder5enavcc_output_wire -- ena.wire
);
pipelined_adder5user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => pipelined_adder5user_aclrgnd_output_wire -- output.wire
);
pipelined_adder5enavcc : component alt_dspbuilder_vcc_GN
port map (
output => pipelined_adder5enavcc_output_wire -- output.wire
);
data_0 : component alt_dspbuilder_port_GNEHYJMBQS
port map (
input => test_pattern_generator_main_ctrl_signal_out_0_data_wire, -- input.wire
output => data -- output.wire
);
if_statement4 : component alt_dspbuilder_if_statement_GNIV4UP6ZO
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "a=b",
number_inputs => 2,
width => 24
)
port map (
true => if_statement4_true_wire, -- true.wire
a => counter_q_wire, -- a.wire
b => pipelined_adder5_result_wire -- b.wire
);
counter : component alt_dspbuilder_counter_GNKAA2ZBZG
generic map (
use_usr_aclr => "false",
use_ena => "false",
use_cin => "false",
use_sset => "false",
ndirection => 1,
svalue => "1",
use_sload => "false",
use_sclr => "true",
use_cout => "false",
modulus => 8388608,
use_cnt_ena => "true",
width => 24,
use_aset => "false",
use_aload => "false",
avalue => "0"
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
cnt_ena => logical_bit_operator1_result_wire, -- cnt_ena.wire
sclr => logical_bit_operator11_result_wire, -- sclr.wire
q => counter_q_wire, -- q.wire
cout => open -- cout.wire
);
constant4 : component alt_dspbuilder_constant_GNQJ63TWA6
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000100",
width => 24
)
port map (
output => constant4_output_wire -- output.wire
);
logical_bit_operator11 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator11_result_wire, -- result.wire
data0 => test_pattern_generator_main_ctrl_ctrl_top_0_data_en_wire, -- data0.wire
data1 => if_statement4_true_wire -- data1.wire
);
sop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => test_pattern_generator_main_ctrl_signal_out_0_sop_wire, -- input.wire
output => sop -- output.wire
);
ready_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => ready, -- input.wire
output => ready_0_output_wire -- output.wire
);
row_0 : component alt_dspbuilder_port_GNEPKLLZKY
port map (
input => row, -- input.wire
output => row_0_output_wire -- output.wire
);
test_pattern_generator_main_ctrl_ctrl_top_0 : component Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP
port map (
check_en => test_pattern_generator_main_ctrl_ctrl_top_0_check_en_wire, -- check_en.wire
ready => ready_0_output_wire, -- ready.wire
data_en => test_pattern_generator_main_ctrl_ctrl_top_0_data_en_wire, -- data_en.wire
counter => counter_q_wire, -- counter.wire
Clock => clock_0_clock_output_clk, -- Clock.clk
aclr => clock_0_clock_output_reset, -- .reset
pixel_num => multiplier1_result_wire, -- pixel_num.wire
ctrl_en => test_pattern_generator_main_ctrl_ctrl_top_0_ctrl_en_wire -- ctrl_en.wire
);
ctrl_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => test_pattern_generator_main_ctrl_ctrl_top_0_ctrl_en_wire, -- input.wire
output => ctrl_en -- output.wire
);
ctrl_pak2_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => ctrl_pak2, -- input.wire
output => ctrl_pak2_0_output_wire -- output.wire
);
ctrl_pak3_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => ctrl_pak3, -- input.wire
output => ctrl_pak3_0_output_wire -- output.wire
);
ctrl_pak1_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => ctrl_pak1, -- input.wire
output => ctrl_pak1_0_output_wire -- output.wire
);
data_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => test_pattern_generator_main_ctrl_ctrl_top_0_data_en_wire, -- input.wire
output => data_en -- output.wire
);
multiplier1 : component alt_dspbuilder_multiplier_GNEIWYOKUR
generic map (
DEDICATED_MULTIPLIER_CIRCUITRY => "YES",
Signed => 0,
OutputMsb => 47,
aWidth => 24,
bWidth => 24,
OutputLsb => 0,
pipeline => 0
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => cast41_output_wire, -- dataa.wire
datab => cast42_output_wire, -- datab.wire
result => multiplier1_result_wire, -- result.wire
user_aclr => multiplier1user_aclrgnd_output_wire, -- user_aclr.wire
ena => multiplier1enavcc_output_wire -- ena.wire
);
multiplier1user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplier1user_aclrgnd_output_wire -- output.wire
);
multiplier1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplier1enavcc_output_wire -- output.wire
);
test_pattern_generator_main_ctrl_signal_out_0 : component Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT
port map (
eop => test_pattern_generator_main_ctrl_signal_out_0_eop_wire, -- eop.wire
data_en => test_pattern_generator_main_ctrl_ctrl_top_0_data_en_wire, -- data_en.wire
ctrl_pak3 => ctrl_pak3_0_output_wire, -- ctrl_pak3.wire
ctrl_pak1 => ctrl_pak1_0_output_wire, -- ctrl_pak1.wire
ctrl_en => test_pattern_generator_main_ctrl_ctrl_top_0_ctrl_en_wire, -- ctrl_en.wire
sop => test_pattern_generator_main_ctrl_signal_out_0_sop_wire, -- sop.wire
data => test_pattern_generator_main_ctrl_signal_out_0_data_wire, -- data.wire
ctrl_pak2 => ctrl_pak2_0_output_wire, -- ctrl_pak2.wire
pixel_num => multiplier1_result_wire, -- pixel_num.wire
colorbar => colorbar_0_output_wire, -- colorbar.wire
counter => counter_q_wire, -- counter.wire
Clock => clock_0_clock_output_clk, -- Clock.clk
aclr => clock_0_clock_output_reset -- .reset
);
check_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => test_pattern_generator_main_ctrl_ctrl_top_0_check_en_wire, -- input.wire
output => check_en -- output.wire
);
eop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => test_pattern_generator_main_ctrl_signal_out_0_eop_wire, -- input.wire
output => eop -- output.wire
);
logical_bit_operator1 : component alt_dspbuilder_logical_bit_op_GNUQ2R64DV
generic map (
LogicalOp => "AltOR",
number_inputs => 2
)
port map (
result => logical_bit_operator1_result_wire, -- result.wire
data0 => test_pattern_generator_main_ctrl_ctrl_top_0_ctrl_en_wire, -- data0.wire
data1 => test_pattern_generator_main_ctrl_ctrl_top_0_data_en_wire -- data1.wire
);
cast41 : component alt_dspbuilder_cast_GN7PRGDOVA
generic map (
round => 0,
saturate => 0
)
port map (
input => col_0_output_wire, -- input.wire
output => cast41_output_wire -- output.wire
);
cast42 : component alt_dspbuilder_cast_GN7PRGDOVA
generic map (
round => 0,
saturate => 0
)
port map (
input => row_0_output_wire, -- input.wire
output => cast42_output_wire -- output.wire
);
cast43 : component alt_dspbuilder_cast_GNKIWLRTQI
generic map (
round => 0,
saturate => 0
)
port map (
input => multiplier1_result_wire, -- input.wire
output => cast43_output_wire -- output.wire
);
end architecture rtl; -- of Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL
|
-- Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.11.10:36:05
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL is
port (
data_en : out std_logic; -- data_en.wire
ctrl_pak2 : in std_logic_vector(23 downto 0) := (others => '0'); -- ctrl_pak2.wire
ready : in std_logic := '0'; -- ready.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset
data : out std_logic_vector(24 downto 0); -- data.wire
counter_1 : out std_logic_vector(23 downto 0); -- counter_1.wire
check_en : out std_logic; -- check_en.wire
eop : out std_logic; -- eop.wire
ctrl_pak3 : in std_logic_vector(23 downto 0) := (others => '0'); -- ctrl_pak3.wire
colorbar : in std_logic_vector(23 downto 0) := (others => '0'); -- colorbar.wire
ctrl_pak1 : in std_logic_vector(23 downto 0) := (others => '0'); -- ctrl_pak1.wire
col : in std_logic_vector(31 downto 0) := (others => '0'); -- col.wire
sop : out std_logic; -- sop.wire
ctrl_en : out std_logic; -- ctrl_en.wire
row : in std_logic_vector(31 downto 0) := (others => '0') -- row.wire
);
end entity Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL;
architecture rtl of Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_port_GNEPKLLZKY is
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(31 downto 0) -- wire
);
end component alt_dspbuilder_port_GNEPKLLZKY;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_pipelined_adder_GNTWZRTG4I is
generic (
width : natural := 0;
pipeline : integer := 0
);
port (
aclr : in std_logic := 'X'; -- clk
add_sub : in std_logic := 'X'; -- wire
cin : in std_logic := 'X'; -- wire
clock : in std_logic := 'X'; -- clk
cout : out std_logic; -- wire
dataa : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
datab : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
result : out std_logic_vector(width-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_pipelined_adder_GNTWZRTG4I;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component alt_dspbuilder_port_GNEHYJMBQS is
port (
input : in std_logic_vector(24 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(24 downto 0) -- wire
);
end component alt_dspbuilder_port_GNEHYJMBQS;
component alt_dspbuilder_if_statement_GNIV4UP6ZO is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNIV4UP6ZO;
component alt_dspbuilder_counter_GNKAA2ZBZG is
generic (
use_usr_aclr : string := "false";
use_ena : string := "false";
use_cin : string := "false";
use_sset : string := "false";
ndirection : natural := 1;
svalue : string := "0";
use_sload : string := "false";
use_sclr : string := "false";
use_cout : string := "false";
modulus : integer := 256;
use_cnt_ena : string := "false";
width : natural := 8;
use_aset : string := "false";
use_aload : string := "false";
avalue : string := "0"
);
port (
aclr : in std_logic := 'X'; -- clk
aload : in std_logic := 'X'; -- wire
aset : in std_logic := 'X'; -- wire
cin : in std_logic := 'X'; -- wire
clock : in std_logic := 'X'; -- clk
cnt_ena : in std_logic := 'X'; -- wire
cout : out std_logic; -- wire
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
direction : in std_logic := 'X'; -- wire
ena : in std_logic := 'X'; -- wire
q : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X'; -- wire
sload : in std_logic := 'X'; -- wire
sset : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_counter_GNKAA2ZBZG;
component alt_dspbuilder_constant_GNQJ63TWA6 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNQJ63TWA6;
component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP is
port (
check_en : out std_logic; -- wire
ready : in std_logic := 'X'; -- wire
data_en : out std_logic; -- wire
counter : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
Clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
pixel_num : in std_logic_vector(47 downto 0) := (others => 'X'); -- wire
ctrl_en : out std_logic -- wire
);
end component Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP;
component alt_dspbuilder_multiplier_GNEIWYOKUR is
generic (
DEDICATED_MULTIPLIER_CIRCUITRY : string := "AUTO";
Signed : natural := 0;
OutputMsb : integer := 8;
aWidth : natural := 8;
bWidth : natural := 8;
OutputLsb : integer := 0;
pipeline : integer := 0
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
dataa : in std_logic_vector(aWidth-1 downto 0) := (others => 'X'); -- wire
datab : in std_logic_vector(bWidth-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
result : out std_logic_vector(OutputMsb-OutputLsb+1-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_multiplier_GNEIWYOKUR;
component Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT is
port (
eop : out std_logic; -- wire
data_en : in std_logic := 'X'; -- wire
ctrl_pak3 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
ctrl_pak1 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
ctrl_en : in std_logic := 'X'; -- wire
sop : out std_logic; -- wire
data : out std_logic_vector(24 downto 0); -- wire
ctrl_pak2 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
pixel_num : in std_logic_vector(47 downto 0) := (others => 'X'); -- wire
colorbar : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
counter : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
Clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X' -- reset
);
end component Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT;
component alt_dspbuilder_logical_bit_op_GNUQ2R64DV is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNUQ2R64DV;
component alt_dspbuilder_cast_GN7PRGDOVA is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN7PRGDOVA;
component alt_dspbuilder_cast_GNKIWLRTQI is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(47 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNKIWLRTQI;
signal pipelined_adder5user_aclrgnd_output_wire : std_logic; -- Pipelined_Adder5user_aclrGND:output -> Pipelined_Adder5:user_aclr
signal pipelined_adder5enavcc_output_wire : std_logic; -- Pipelined_Adder5enaVCC:output -> Pipelined_Adder5:ena
signal multiplier1user_aclrgnd_output_wire : std_logic; -- Multiplier1user_aclrGND:output -> Multiplier1:user_aclr
signal multiplier1enavcc_output_wire : std_logic; -- Multiplier1enaVCC:output -> Multiplier1:ena
signal ready_0_output_wire : std_logic; -- ready_0:output -> Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP_0:ready
signal counter_q_wire : std_logic_vector(23 downto 0); -- Counter:q -> [If_Statement4:a, Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP_0:counter, Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:counter, counter_1_0:input]
signal test_pattern_generator_main_ctrl_ctrl_top_0_ctrl_en_wire : std_logic; -- Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP_0:ctrl_en -> [Logical_Bit_Operator1:data0, Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:ctrl_en, ctrl_en_0:input]
signal test_pattern_generator_main_ctrl_ctrl_top_0_data_en_wire : std_logic; -- Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP_0:data_en -> [Logical_Bit_Operator11:data0, Logical_Bit_Operator1:data1, Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:data_en, data_en_0:input]
signal logical_bit_operator1_result_wire : std_logic; -- Logical_Bit_Operator1:result -> Counter:cnt_ena
signal if_statement4_true_wire : std_logic; -- If_Statement4:true -> Logical_Bit_Operator11:data1
signal logical_bit_operator11_result_wire : std_logic; -- Logical_Bit_Operator11:result -> Counter:sclr
signal multiplier1_result_wire : std_logic_vector(47 downto 0); -- Multiplier1:result -> [Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP_0:pixel_num, Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:pixel_num, cast43:input]
signal constant4_output_wire : std_logic_vector(23 downto 0); -- Constant4:output -> Pipelined_Adder5:datab
signal pipelined_adder5_result_wire : std_logic_vector(23 downto 0); -- Pipelined_Adder5:result -> If_Statement4:b
signal ctrl_pak1_0_output_wire : std_logic_vector(23 downto 0); -- ctrl_pak1_0:output -> Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:ctrl_pak1
signal ctrl_pak2_0_output_wire : std_logic_vector(23 downto 0); -- ctrl_pak2_0:output -> Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:ctrl_pak2
signal ctrl_pak3_0_output_wire : std_logic_vector(23 downto 0); -- ctrl_pak3_0:output -> Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:ctrl_pak3
signal colorbar_0_output_wire : std_logic_vector(23 downto 0); -- colorbar_0:output -> Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:colorbar
signal test_pattern_generator_main_ctrl_signal_out_0_data_wire : std_logic_vector(24 downto 0); -- Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:data -> data_0:input
signal test_pattern_generator_main_ctrl_signal_out_0_sop_wire : std_logic; -- Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:sop -> sop_0:input
signal test_pattern_generator_main_ctrl_signal_out_0_eop_wire : std_logic; -- Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:eop -> eop_0:input
signal test_pattern_generator_main_ctrl_ctrl_top_0_check_en_wire : std_logic; -- Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP_0:check_en -> check_en_0:input
signal col_0_output_wire : std_logic_vector(31 downto 0); -- col_0:output -> cast41:input
signal cast41_output_wire : std_logic_vector(23 downto 0); -- cast41:output -> Multiplier1:dataa
signal row_0_output_wire : std_logic_vector(31 downto 0); -- row_0:output -> cast42:input
signal cast42_output_wire : std_logic_vector(23 downto 0); -- cast42:output -> Multiplier1:datab
signal cast43_output_wire : std_logic_vector(23 downto 0); -- cast43:output -> Pipelined_Adder5:dataa
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Counter:aclr, Multiplier1:aclr, Pipelined_Adder5:aclr, Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP_0:aclr, Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:aclr]
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Counter:clock, Multiplier1:clock, Pipelined_Adder5:clock, Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP_0:Clock, Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT_0:Clock]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
col_0 : component alt_dspbuilder_port_GNEPKLLZKY
port map (
input => col, -- input.wire
output => col_0_output_wire -- output.wire
);
counter_1_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => counter_q_wire, -- input.wire
output => counter_1 -- output.wire
);
colorbar_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => colorbar, -- input.wire
output => colorbar_0_output_wire -- output.wire
);
pipelined_adder5 : component alt_dspbuilder_pipelined_adder_GNTWZRTG4I
generic map (
width => 24,
pipeline => 0
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => cast43_output_wire, -- dataa.wire
datab => constant4_output_wire, -- datab.wire
result => pipelined_adder5_result_wire, -- result.wire
user_aclr => pipelined_adder5user_aclrgnd_output_wire, -- user_aclr.wire
ena => pipelined_adder5enavcc_output_wire -- ena.wire
);
pipelined_adder5user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => pipelined_adder5user_aclrgnd_output_wire -- output.wire
);
pipelined_adder5enavcc : component alt_dspbuilder_vcc_GN
port map (
output => pipelined_adder5enavcc_output_wire -- output.wire
);
data_0 : component alt_dspbuilder_port_GNEHYJMBQS
port map (
input => test_pattern_generator_main_ctrl_signal_out_0_data_wire, -- input.wire
output => data -- output.wire
);
if_statement4 : component alt_dspbuilder_if_statement_GNIV4UP6ZO
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "a=b",
number_inputs => 2,
width => 24
)
port map (
true => if_statement4_true_wire, -- true.wire
a => counter_q_wire, -- a.wire
b => pipelined_adder5_result_wire -- b.wire
);
counter : component alt_dspbuilder_counter_GNKAA2ZBZG
generic map (
use_usr_aclr => "false",
use_ena => "false",
use_cin => "false",
use_sset => "false",
ndirection => 1,
svalue => "1",
use_sload => "false",
use_sclr => "true",
use_cout => "false",
modulus => 8388608,
use_cnt_ena => "true",
width => 24,
use_aset => "false",
use_aload => "false",
avalue => "0"
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
cnt_ena => logical_bit_operator1_result_wire, -- cnt_ena.wire
sclr => logical_bit_operator11_result_wire, -- sclr.wire
q => counter_q_wire, -- q.wire
cout => open -- cout.wire
);
constant4 : component alt_dspbuilder_constant_GNQJ63TWA6
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000100",
width => 24
)
port map (
output => constant4_output_wire -- output.wire
);
logical_bit_operator11 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator11_result_wire, -- result.wire
data0 => test_pattern_generator_main_ctrl_ctrl_top_0_data_en_wire, -- data0.wire
data1 => if_statement4_true_wire -- data1.wire
);
sop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => test_pattern_generator_main_ctrl_signal_out_0_sop_wire, -- input.wire
output => sop -- output.wire
);
ready_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => ready, -- input.wire
output => ready_0_output_wire -- output.wire
);
row_0 : component alt_dspbuilder_port_GNEPKLLZKY
port map (
input => row, -- input.wire
output => row_0_output_wire -- output.wire
);
test_pattern_generator_main_ctrl_ctrl_top_0 : component Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP
port map (
check_en => test_pattern_generator_main_ctrl_ctrl_top_0_check_en_wire, -- check_en.wire
ready => ready_0_output_wire, -- ready.wire
data_en => test_pattern_generator_main_ctrl_ctrl_top_0_data_en_wire, -- data_en.wire
counter => counter_q_wire, -- counter.wire
Clock => clock_0_clock_output_clk, -- Clock.clk
aclr => clock_0_clock_output_reset, -- .reset
pixel_num => multiplier1_result_wire, -- pixel_num.wire
ctrl_en => test_pattern_generator_main_ctrl_ctrl_top_0_ctrl_en_wire -- ctrl_en.wire
);
ctrl_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => test_pattern_generator_main_ctrl_ctrl_top_0_ctrl_en_wire, -- input.wire
output => ctrl_en -- output.wire
);
ctrl_pak2_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => ctrl_pak2, -- input.wire
output => ctrl_pak2_0_output_wire -- output.wire
);
ctrl_pak3_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => ctrl_pak3, -- input.wire
output => ctrl_pak3_0_output_wire -- output.wire
);
ctrl_pak1_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => ctrl_pak1, -- input.wire
output => ctrl_pak1_0_output_wire -- output.wire
);
data_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => test_pattern_generator_main_ctrl_ctrl_top_0_data_en_wire, -- input.wire
output => data_en -- output.wire
);
multiplier1 : component alt_dspbuilder_multiplier_GNEIWYOKUR
generic map (
DEDICATED_MULTIPLIER_CIRCUITRY => "YES",
Signed => 0,
OutputMsb => 47,
aWidth => 24,
bWidth => 24,
OutputLsb => 0,
pipeline => 0
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => cast41_output_wire, -- dataa.wire
datab => cast42_output_wire, -- datab.wire
result => multiplier1_result_wire, -- result.wire
user_aclr => multiplier1user_aclrgnd_output_wire, -- user_aclr.wire
ena => multiplier1enavcc_output_wire -- ena.wire
);
multiplier1user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplier1user_aclrgnd_output_wire -- output.wire
);
multiplier1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplier1enavcc_output_wire -- output.wire
);
test_pattern_generator_main_ctrl_signal_out_0 : component Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT
port map (
eop => test_pattern_generator_main_ctrl_signal_out_0_eop_wire, -- eop.wire
data_en => test_pattern_generator_main_ctrl_ctrl_top_0_data_en_wire, -- data_en.wire
ctrl_pak3 => ctrl_pak3_0_output_wire, -- ctrl_pak3.wire
ctrl_pak1 => ctrl_pak1_0_output_wire, -- ctrl_pak1.wire
ctrl_en => test_pattern_generator_main_ctrl_ctrl_top_0_ctrl_en_wire, -- ctrl_en.wire
sop => test_pattern_generator_main_ctrl_signal_out_0_sop_wire, -- sop.wire
data => test_pattern_generator_main_ctrl_signal_out_0_data_wire, -- data.wire
ctrl_pak2 => ctrl_pak2_0_output_wire, -- ctrl_pak2.wire
pixel_num => multiplier1_result_wire, -- pixel_num.wire
colorbar => colorbar_0_output_wire, -- colorbar.wire
counter => counter_q_wire, -- counter.wire
Clock => clock_0_clock_output_clk, -- Clock.clk
aclr => clock_0_clock_output_reset -- .reset
);
check_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => test_pattern_generator_main_ctrl_ctrl_top_0_check_en_wire, -- input.wire
output => check_en -- output.wire
);
eop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => test_pattern_generator_main_ctrl_signal_out_0_eop_wire, -- input.wire
output => eop -- output.wire
);
logical_bit_operator1 : component alt_dspbuilder_logical_bit_op_GNUQ2R64DV
generic map (
LogicalOp => "AltOR",
number_inputs => 2
)
port map (
result => logical_bit_operator1_result_wire, -- result.wire
data0 => test_pattern_generator_main_ctrl_ctrl_top_0_ctrl_en_wire, -- data0.wire
data1 => test_pattern_generator_main_ctrl_ctrl_top_0_data_en_wire -- data1.wire
);
cast41 : component alt_dspbuilder_cast_GN7PRGDOVA
generic map (
round => 0,
saturate => 0
)
port map (
input => col_0_output_wire, -- input.wire
output => cast41_output_wire -- output.wire
);
cast42 : component alt_dspbuilder_cast_GN7PRGDOVA
generic map (
round => 0,
saturate => 0
)
port map (
input => row_0_output_wire, -- input.wire
output => cast42_output_wire -- output.wire
);
cast43 : component alt_dspbuilder_cast_GNKIWLRTQI
generic map (
round => 0,
saturate => 0
)
port map (
input => multiplier1_result_wire, -- input.wire
output => cast43_output_wire -- output.wire
);
end architecture rtl; -- of Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL
|
-------------------------------------------------------------------------------
-- --
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2005 HT-LAB --
-- --
-- Contact : mailto:[email protected] --
-- Web: http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on the CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.STD_LOGIC_UNSIGNED.all;
LIBRARY std;
USE std.TEXTIO.all;
USE work.utils.all;
ENTITY tester IS
PORT(
resoutn : IN std_logic;
CTS : OUT std_logic;
RESET : OUT std_logic;
rxenable : OUT std_logic;
CLOCK_40MHZ : BUFFER std_logic:='0';
txenable : BUFFER std_logic;
txcmd : OUT std_logic
);
END tester ;
--
ARCHITECTURE behaviour OF tester IS
constant DIVIDER_c : std_logic_vector(7 downto 0):="01000001"; -- 65, baudrate divider 40MHz
signal divtx_s : std_logic_vector(3 downto 0);
signal divreg_s : std_logic_vector(7 downto 0);
signal divcnt_s : std_logic_vector(7 downto 0);
signal rxclk16_s : std_logic;
signal tdre_s : std_logic;
signal wrn_s : std_logic;
signal char_s : std_logic_vector(7 downto 0);
component uarttx
port (
clk : in std_logic ;
enable : in std_logic ; -- 1 x bit_rate transmit clock enable
resetn : in std_logic ;
dbus : in std_logic_vector (7 downto 0); -- input to txshift register
tdre : out std_logic ;
wrn : in std_logic ;
tx : out std_logic);
end component;
BEGIN
CLOCK_40MHZ <= not CLOCK_40MHZ after 12.5 ns; -- 40MHz
process
variable L : line;
procedure write_to_uart (char_in : IN character) is
begin
char_s <=to_std_logic_vector(char_in);
wait until rising_edge(CLOCK_40MHZ);
wrn_s <= '0';
wait until rising_edge(CLOCK_40MHZ);
wrn_s <= '1';
wait until rising_edge(CLOCK_40MHZ);
wait until rising_edge(tdre_s);
end;
begin
CTS <= '1';
RESET <= '0'; -- PIN3 on Drigmorn1 connected to PIN2
wait for 100 ns;
RESET <= '1';
wrn_s <= '1'; -- Active low write strobe to TX UART
char_s <= (others => '1');
wait for 25.1 ms; -- wait for > prompt before issuing commands
write_to_uart('R');
wait for 47 ms; -- wait for > prompt before issuing commands
write_to_uart('D'); -- Issue Fill Memory command
write_to_uart('M');
write_to_uart('0');
write_to_uart('1');
write_to_uart('0');
write_to_uart('0');
wait for 1 ms;
write_to_uart('0');
write_to_uart('1');
write_to_uart('2');
write_to_uart('4');
wait for 50 ms; -- wait for > prompt before issuing commands
wait;
end process;
------------------------------------------------------------------------------
-- 8 bits divider
-- Generate rxenable clock
------------------------------------------------------------------------------
process (CLOCK_40MHZ,resoutn) -- First divider
begin
if (resoutn='0') then
divcnt_s <= (others => '0');
rxclk16_s <= '0'; -- Receive clock (x16, pulse)
elsif (rising_edge(CLOCK_40MHZ)) then
if divcnt_s=DIVIDER_c then
divcnt_s <= (others => '0');
rxclk16_s <= '1';
else
rxclk16_s <= '0';
divcnt_s <= divcnt_s + '1';
end if;
end if;
end process;
rxenable <= rxclk16_s;
------------------------------------------------------------------------------
-- divider by 16
-- rxclk16/16=txclk
------------------------------------------------------------------------------
process (CLOCK_40MHZ,resoutn)
begin
if (resoutn='0') then
divtx_s <= (others => '0');
elsif (rising_edge(CLOCK_40MHZ)) then
if rxclk16_s='1' then
divtx_s <= divtx_s + '1';
if divtx_s="0000" then
txenable <= '1';
end if;
else
txenable <= '0';
end if;
end if;
end process;
------------------------------------------------------------------------------
-- TX Uart
------------------------------------------------------------------------------
I0 : uarttx
port map (
clk => CLOCK_40MHZ,
enable => txenable,
resetn => resoutn,
dbus => char_s,
tdre => tdre_s,
wrn => wrn_s,
tx => txcmd
);
END ARCHITECTURE behaviour;
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Technology specific RAM selector
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
library techmap;
use techmap.gencomp.all;
use techmap.types_mem.all;
entity Ram32_tech is
generic (
generic_tech : integer := 0;
generic_abits : integer := 10
);
port (
i_clk : in std_logic;
i_address : in std_logic_vector(generic_abits-1 downto 0);
i_wr_ena : in std_logic;
i_data : in std_logic_vector(31 downto 0);
o_data : out std_logic_vector(31 downto 0)
);
end;
architecture rtl of Ram32_tech is
component Ram32_inferred
generic (
generic_abits : integer := 10
);
port (
i_clk : in std_logic;
i_address : in std_logic_vector(generic_abits-1 downto 0);
i_wr_ena : in std_logic;
i_data : in std_logic_vector(31 downto 0);
o_data : out std_logic_vector(31 downto 0)
);
end component;
-- micron 180 nm tech
component micron180_syncram
generic (abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
-- TODO: add there other ASIC components
begin
genmem0 : if generic_tech = inferred or is_fpga(generic_tech) /= 0 generate
ram_infer : Ram32_inferred generic map
(
generic_abits => generic_abits
) port map
(
i_clk,
i_address,
i_wr_ena,
i_data,
o_data
);
end generate;
genmem1 : if generic_tech = mikron180 generate
x0 : micron180_syncram
generic map (generic_abits, 32)
port map (i_clk, i_address, i_data, o_data, '1', i_wr_ena);
end generate;
end;
|
-- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- application_core.vhd : Application core module
-- Copyright (C) 2009 CESNET
-- Author(s): Pavol Korcek <[email protected]>
-- Petr Kastovsky <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: application_core.vhd 12117 2009-11-25 13:35:03Z kastovsky $
--
-- --------------------------------------------------------------------
-- Entity declaration
-- --------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.lb_pkg.all; -- Local Bus Package
entity application_core is
port (
CLK : in std_logic;
RESET : in std_logic;
-- MI32
mi32_dwr : in std_logic_vector(31 downto 0);
mi32_addr : in std_logic_vector(31 downto 0);
mi32_rd : in std_logic;
mi32_wr : in std_logic;
mi32_be : in std_logic_vector(3 downto 0);
mi32_drd : out std_logic_vector(31 downto 0);
mi32_ardy : out std_logic;
mi32_drdy : out std_logic;
-- FL
fl_sof_n : out std_logic;
fl_sop_n : out std_logic;
fl_eop_n : out std_logic;
fl_eof_n : out std_logic;
fl_src_rdy_n : out std_logic;
fl_dst_rdy_n : in std_logic;
fl_data : out std_logic_vector(127 downto 0);
fl_rem : out std_logic_vector(3 downto 0)
);
end application_core;
architecture full of application_core is
-- ----------------------------------------------------------------------------
-- Signal declaration
-- ----------------------------------------------------------------------------
constant gndvec : std_logic_vector(31 downto 0) := X"00000000";
signal status : std_logic_vector(31 downto 0); -- status/control register
signal init0 : std_logic_vector(31 downto 0); -- init vector 0
signal init1 : std_logic_vector(31 downto 0); -- init vector 1
signal pkt_length : std_logic_vector(31 downto 0); -- actual sw packet length
signal pkt_num0 : std_logic_vector(31 downto 0); -- number of packet to send (low register)
signal pkt_num1 : std_logic_vector(31 downto 0); -- number of packet to send (high register)
signal pkt_send0 : std_logic_vector(31 downto 0); -- number of sent packets (low register)
signal pkt_send1 : std_logic_vector(31 downto 0); -- number of sent packets (high register)
signal seed : std_logic_vector(63 downto 0); -- initialization seed
signal clear : std_logic;
signal length_shift_enable : std_logic; -- shift to next random length
signal length_fill_enable : std_logic; -- filling with seed value enabled
signal rnd_length : std_logic_vector(10 downto 0); -- random length output
signal reg_length : std_logic_vector(10 downto 0); -- random length output
signal length : std_logic_vector(10 downto 0); -- finall length
signal length_sel : std_logic; -- length selector
signal data_shift_enable : std_logic; -- shift to next random data
signal data_fill_enable : std_logic; -- filling with seed value enabled
signal rnd_data : std_logic_vector(127 downto 0); -- random data output
signal last_data : std_logic; -- last data send (EOF and BE active)
signal last_be : std_logic_vector(3 downto 0); -- BE for network frame link
signal num_packets : std_logic_vector(63 downto 0); -- number of packetss to send
signal reg_send_packets : std_logic_vector(63 downto 0); -- number of actually sent packet
signal last_pkt : std_logic;
signal status_run_set : std_logic;
signal status_stp_set : std_logic;
signal status_run_clr : std_logic;
signal gen_fsm_eop : std_logic;
signal gen_fsm_sop : std_logic;
signal gen_fsm_nd : std_logic;
signal gen_fsm_nl : std_logic;
signal gen_fsm_stopped : std_logic;
signal gen_fsm_src_rdy : std_logic;
signal gen_fsm_dst_rdy : std_logic;
signal mux_rem_sel : std_logic;
signal mux_data_sel : std_logic;
-- ----------------------------------------------------------------------------
-- Architecture body
-- ----------------------------------------------------------------------------
begin
-- -------------------------------------------------------------------------
-- User registers
-- -------------------------------------------------------------------------
mi32_drdy <= mi32_rd;
mi32_ardy <= mi32_wr or mi32_rd;
REGISTERS_U : process(CLK)
begin
if (CLK = '1' and CLK'event) then
if (RESET = '1') then
status(31 downto 1) <= (others => '0');
init0 <= X"ABCDEF12"; -- init vector 0
init1 <= X"34567890"; -- init vector 1
pkt_length <= X"00000001"; -- actual packet length
pkt_num0 <= X"FFFFFFFF"; -- number of packet to send (low register)
pkt_num1 <= X"FFFFFFFF"; -- number of packet to send (high register)
-- pkt_send0 <= X"00000000"; -- number of sent packets (low register)
-- pkt_send1 <= X"00000000"; -- number of sent packets (high register)
else
status_run_set <= '0';
status_stp_set <= '0';
-- Write to my registers
if (mi32_wr = '1') then
case mi32_addr(4 downto 2) is
when "000" =>
status_run_set <= mi32_dwr(0);
status_stp_set <= not mi32_dwr(0);
status(31 downto 1) <= mi32_dwr(31 downto 1);
when "001" =>
for i in 0 to 3 loop
if mi32_be(i) = '1' then
init0(i*8+7 downto i*8) <= mi32_dwr(i*8+7 downto i*8);
end if;
end loop;
when "010" =>
for i in 0 to 3 loop
if mi32_be(i) = '1' then
init1(i*8+7 downto i*8) <= mi32_dwr(i*8+7 downto i*8);
end if;
end loop;
when "011" =>
for i in 0 to 3 loop
if mi32_be(i) = '1' then
pkt_length(i*8+7 downto i*8) <= mi32_dwr(i*8+7 downto i*8);
end if;
end loop;
when "100" =>
for i in 0 to 3 loop
if mi32_be(i) = '1' then
pkt_num0(i*8+7 downto i*8) <= mi32_dwr(i*8+7 downto i*8);
end if;
end loop;
when "101" =>
for i in 0 to 3 loop
if mi32_be(i) = '1' then
pkt_num1(i*8+7 downto i*8) <= mi32_dwr(i*8+7 downto i*8);
end if;
end loop;
when "110" =>
for i in 0 to 3 loop
if mi32_be(i) = '1' then
--pkt_send0(i*8+7 downto i*8) <= mi32_dwr(i*8+7 downto i*8); -- r
end if;
end loop;
when "111" =>
for i in 0 to 3 loop
if mi32_be(i) = '1' then
--pkt_send1(i*8+7 downto i*8) <= mi32_dwr(i*8+7 downto i*8); -- r
end if;
end loop;
when others => null;
end case;
end if;
-- Read from my registers
case mi32_addr(4 downto 2) is
when "000" => mi32_drd <= status;
when "001" => mi32_drd <= init0;
when "010" => mi32_drd <= init1;
when "011" => mi32_drd <= pkt_length;
when "100" => mi32_drd <= pkt_num0;
when "101" => mi32_drd <= pkt_num1;
when "110" => mi32_drd <= pkt_send0;
when "111" => mi32_drd <= pkt_send1;
when others => mi32_drd <= X"DEADBEEF";
end case;
end if;
end if;
end process;
status_run_clr <= gen_fsm_stopped or status_stp_set;
-- register reg_status ------------------------------------------------------
reg_statusp: process(CLK)
begin
if (CLK'event AND CLK = '1') then
if ( RESET = '1') then
status(0) <= '0';
elsif (status_run_set = '1') then
status(0) <= '1';
elsif (status_run_clr = '1') then
status(0) <= '0';
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- Generators
-- -------------------------------------------------------------------------
seed <= init1 & init0;
PKT_LENGTH_GEN_U : entity work.pseudorand_length_gen
port map (
RESET => RESET,
CLK => CLK,
S_EN => length_shift_enable,
F_EN => length_fill_enable,
DIN => seed(10 downto 0),
DOUT => rnd_length
);
PKT_DATA_GEN_U : entity work.pseudorand_data_gen
port map (
CLK => CLK,
S_EN => data_shift_enable,
F_EN => data_fill_enable,
DIN => seed,
DOUT => rnd_data
);
-- -------------------------------------------------------------------------
-- Internal registers
-- -------------------------------------------------------------------------
clear <= (last_data AND gen_fsm_dst_rdy) OR status_run_set;
-- register ---------------------------------------------------------------
reg_lengthp: process(RESET, CLK)
begin
if (RESET = '1') then
reg_length <= (others => '0');
elsif (CLK'event AND CLK = '1') then
if(clear = '1') then
reg_length <= length;
elsif(data_shift_enable = '1') then -- when request for next data
reg_length <= reg_length - 16; -- decrement
end if;
end if;
end process;
mux_data_sel <= status(2);
-- multiplexor mux_data ------------------------------------------------------
mux_datap: process(mux_data_sel, rnd_data)
begin
case mux_data_sel is
when '0' => fl_data <= (others => '0');
when '1' => fl_data <= rnd_data;
when others => fl_data <= (others => 'X');
end case;
end process;
length_sel <= status(1);
-- multiplexor length ------------------------------------------------------
length_muxp: process(length_sel, pkt_length(10 downto 0), rnd_length)
begin
case length_sel is
when '0' => length <= pkt_length(10 downto 0); -- user length
when '1' => length <= rnd_length;
when others => length <= (others => '1');
end case;
end process;
last_be <= length(3 downto 0) - 1; -- BE
mux_rem_sel <= gen_fsm_eop;
-- multiplexor mux_rem ------------------------------------------------------
mux_remp: process(mux_rem_sel, last_be)
begin
case mux_rem_sel is
when '0' => fl_rem <= (others => '1');
when '1' => fl_rem <= last_be;
when others => fl_rem <= (others => 'X');
end case;
end process;
-- register ---------------------------------------------------------------
reg_send_packetsp: process(RESET, CLK)
begin
if (RESET = '1') then
reg_send_packets <= (others => '0');
elsif (CLK'event AND CLK = '1') then
if (status_run_set = '1') then
reg_send_packets <= (others => '0');
elsif(length_shift_enable = '1') then -- when next packet send
reg_send_packets <= reg_send_packets + 1; -- increment
end if;
end if;
end process;
pkt_send0 <= reg_send_packets(31 downto 0);
pkt_send1 <= reg_send_packets(63 downto 32);
num_packets <= pkt_num1 & pkt_num0; -- from SW
-- -------------------------------------------------------------------------
-- Comparators
-- -------------------------------------------------------------------------
last_data <= '1' when (reg_length <= 16) else -- last data in packet
'0';
last_pkt <= '1' when (reg_send_packets = num_packets) else -- last packet to send
'0';
GEN_FSM_I: entity work.GEN_FSM
port map (
-- global signals
CLK => CLK,
RESET => RESET,
-- input signals
START => status(0),
PACKET_END => last_data,
TRANSMIT_END => last_pkt,
DST_RDY => gen_fsm_dst_rdy,
-- output signals
SOP => gen_fsm_sop,
EOP => gen_fsm_eop,
NEXT_DATA => gen_fsm_nd,
NEXT_LEN => gen_fsm_nl,
SRC_RDY => gen_fsm_src_rdy,
STOPPED => gen_fsm_stopped
);
gen_fsm_dst_rdy <= not fl_dst_rdy_n;
fl_src_rdy_n <= not gen_fsm_src_rdy;
length_shift_enable <= gen_fsm_nl XOR status_run_set;
data_shift_enable <= gen_fsm_nd XOR status_run_set;
length_fill_enable <= gen_fsm_stopped;
data_fill_enable <= gen_fsm_stopped;
fl_sof_n <= not gen_fsm_sop;
fl_sop_n <= not gen_fsm_sop;
fl_eof_n <= not gen_fsm_eop;
fl_eop_n <= not gen_fsm_eop;
end architecture full;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file adder_subtracter_virtex2p_7_0_453ed16ba8e84295.vhd when simulating
-- the core, adder_subtracter_virtex2p_7_0_453ed16ba8e84295. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY adder_subtracter_virtex2p_7_0_453ed16ba8e84295 IS
port (
A: IN std_logic_VECTOR(8 downto 0);
B: IN std_logic_VECTOR(8 downto 0);
S: OUT std_logic_VECTOR(8 downto 0));
END adder_subtracter_virtex2p_7_0_453ed16ba8e84295;
ARCHITECTURE adder_subtracter_virtex2p_7_0_453ed16ba8e84295_a OF adder_subtracter_virtex2p_7_0_453ed16ba8e84295 IS
-- synthesis translate_off
component wrapped_adder_subtracter_virtex2p_7_0_453ed16ba8e84295
port (
A: IN std_logic_VECTOR(8 downto 0);
B: IN std_logic_VECTOR(8 downto 0);
S: OUT std_logic_VECTOR(8 downto 0));
end component;
-- Configuration specification
for all : wrapped_adder_subtracter_virtex2p_7_0_453ed16ba8e84295 use entity XilinxCoreLib.C_ADDSUB_V7_0(behavioral)
generic map(
c_has_bypass_with_cin => 0,
c_a_type => 1,
c_has_sclr => 0,
c_sync_priority => 1,
c_has_aset => 0,
c_has_b_out => 0,
c_has_s => 1,
c_has_q => 0,
c_bypass_enable => 0,
c_b_constant => 0,
c_has_ovfl => 0,
c_high_bit => 8,
c_latency => 0,
c_sinit_val => "0",
c_has_bypass => 0,
c_pipe_stages => 1,
c_has_sset => 0,
c_has_ainit => 0,
c_has_a_signed => 0,
c_has_q_c_out => 0,
c_b_type => 1,
c_has_add => 0,
c_has_sinit => 0,
c_has_b_in => 0,
c_has_b_signed => 0,
c_bypass_low => 0,
c_enable_rlocs => 1,
c_b_value => "0",
c_add_mode => 0,
c_has_aclr => 0,
c_out_width => 9,
c_ainit_val => "0000",
c_low_bit => 0,
c_has_q_ovfl => 0,
c_has_q_b_out => 0,
c_has_c_out => 0,
c_b_width => 9,
c_a_width => 9,
c_sync_enable => 0,
c_has_ce => 1,
c_has_c_in => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_adder_subtracter_virtex2p_7_0_453ed16ba8e84295
port map (
A => A,
B => B,
S => S);
-- synthesis translate_on
END adder_subtracter_virtex2p_7_0_453ed16ba8e84295_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file adder_subtracter_virtex2p_7_0_7182743c9e7adf5e.vhd when simulating
-- the core, adder_subtracter_virtex2p_7_0_7182743c9e7adf5e. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY adder_subtracter_virtex2p_7_0_7182743c9e7adf5e IS
port (
A: IN std_logic_VECTOR(4 downto 0);
B: IN std_logic_VECTOR(4 downto 0);
S: OUT std_logic_VECTOR(4 downto 0));
END adder_subtracter_virtex2p_7_0_7182743c9e7adf5e;
ARCHITECTURE adder_subtracter_virtex2p_7_0_7182743c9e7adf5e_a OF adder_subtracter_virtex2p_7_0_7182743c9e7adf5e IS
-- synthesis translate_off
component wrapped_adder_subtracter_virtex2p_7_0_7182743c9e7adf5e
port (
A: IN std_logic_VECTOR(4 downto 0);
B: IN std_logic_VECTOR(4 downto 0);
S: OUT std_logic_VECTOR(4 downto 0));
end component;
-- Configuration specification
for all : wrapped_adder_subtracter_virtex2p_7_0_7182743c9e7adf5e use entity XilinxCoreLib.C_ADDSUB_V7_0(behavioral)
generic map(
c_has_bypass_with_cin => 0,
c_a_type => 1,
c_has_sclr => 0,
c_sync_priority => 1,
c_has_aset => 0,
c_has_b_out => 0,
c_has_s => 1,
c_has_q => 0,
c_bypass_enable => 0,
c_b_constant => 0,
c_has_ovfl => 0,
c_high_bit => 4,
c_latency => 0,
c_sinit_val => "0",
c_has_bypass => 0,
c_pipe_stages => 1,
c_has_sset => 0,
c_has_ainit => 0,
c_has_a_signed => 0,
c_has_q_c_out => 0,
c_b_type => 1,
c_has_add => 0,
c_has_sinit => 0,
c_has_b_in => 0,
c_has_b_signed => 0,
c_bypass_low => 0,
c_enable_rlocs => 1,
c_b_value => "0",
c_add_mode => 0,
c_has_aclr => 0,
c_out_width => 5,
c_ainit_val => "0000",
c_low_bit => 0,
c_has_q_ovfl => 0,
c_has_q_b_out => 0,
c_has_c_out => 0,
c_b_width => 5,
c_a_width => 5,
c_sync_enable => 0,
c_has_ce => 1,
c_has_c_in => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_adder_subtracter_virtex2p_7_0_7182743c9e7adf5e
port map (
A => A,
B => B,
S => S);
-- synthesis translate_on
END adder_subtracter_virtex2p_7_0_7182743c9e7adf5e_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3.vhd when simulating
-- the core, adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3 IS
port (
A: IN std_logic_VECTOR(8 downto 0);
B: IN std_logic_VECTOR(8 downto 0);
S: OUT std_logic_VECTOR(8 downto 0));
END adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3;
ARCHITECTURE adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3_a OF adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3 IS
-- synthesis translate_off
component wrapped_adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3
port (
A: IN std_logic_VECTOR(8 downto 0);
B: IN std_logic_VECTOR(8 downto 0);
S: OUT std_logic_VECTOR(8 downto 0));
end component;
-- Configuration specification
for all : wrapped_adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3 use entity XilinxCoreLib.C_ADDSUB_V7_0(behavioral)
generic map(
c_has_bypass_with_cin => 0,
c_a_type => 0,
c_has_sclr => 0,
c_sync_priority => 1,
c_has_aset => 0,
c_has_b_out => 0,
c_has_s => 1,
c_has_q => 0,
c_bypass_enable => 0,
c_b_constant => 0,
c_has_ovfl => 0,
c_high_bit => 8,
c_latency => 0,
c_sinit_val => "0",
c_has_bypass => 0,
c_pipe_stages => 1,
c_has_sset => 0,
c_has_ainit => 0,
c_has_a_signed => 0,
c_has_q_c_out => 0,
c_b_type => 0,
c_has_add => 0,
c_has_sinit => 0,
c_has_b_in => 0,
c_has_b_signed => 0,
c_bypass_low => 0,
c_enable_rlocs => 1,
c_b_value => "0",
c_add_mode => 1,
c_has_aclr => 0,
c_out_width => 9,
c_ainit_val => "0000",
c_low_bit => 0,
c_has_q_ovfl => 0,
c_has_q_b_out => 0,
c_has_c_out => 0,
c_b_width => 9,
c_a_width => 9,
c_sync_enable => 0,
c_has_ce => 1,
c_has_c_in => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3
port map (
A => A,
B => B,
S => S);
-- synthesis translate_on
END adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file binary_counter_virtex2p_7_0_23542cbcca0efa2e.vhd when simulating
-- the core, binary_counter_virtex2p_7_0_23542cbcca0efa2e. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY binary_counter_virtex2p_7_0_23542cbcca0efa2e IS
port (
Q: OUT std_logic_VECTOR(3 downto 0);
CLK: IN std_logic;
CE: IN std_logic;
SINIT: IN std_logic);
END binary_counter_virtex2p_7_0_23542cbcca0efa2e;
ARCHITECTURE binary_counter_virtex2p_7_0_23542cbcca0efa2e_a OF binary_counter_virtex2p_7_0_23542cbcca0efa2e IS
-- synthesis translate_off
component wrapped_binary_counter_virtex2p_7_0_23542cbcca0efa2e
port (
Q: OUT std_logic_VECTOR(3 downto 0);
CLK: IN std_logic;
CE: IN std_logic;
SINIT: IN std_logic);
end component;
-- Configuration specification
for all : wrapped_binary_counter_virtex2p_7_0_23542cbcca0efa2e use entity XilinxCoreLib.C_COUNTER_BINARY_V7_0(behavioral)
generic map(
c_count_mode => 0,
c_load_enable => 1,
c_has_aset => 0,
c_load_low => 0,
c_count_to => "1111111111111111",
c_sync_priority => 1,
c_has_iv => 0,
c_restrict_count => 0,
c_has_sclr => 0,
c_width => 4,
c_has_q_thresh1 => 0,
c_enable_rlocs => 0,
c_has_q_thresh0 => 0,
c_thresh1_value => "1111111111111111",
c_has_load => 0,
c_thresh_early => 1,
c_has_up => 0,
c_has_thresh1 => 0,
c_has_thresh0 => 0,
c_ainit_val => "0000",
c_has_ce => 1,
c_pipe_stages => 0,
c_has_aclr => 0,
c_sync_enable => 0,
c_has_ainit => 0,
c_sinit_val => "0000",
c_has_sset => 0,
c_has_sinit => 1,
c_count_by => "0001",
c_has_l => 0,
c_thresh0_value => "1111111111111111");
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_binary_counter_virtex2p_7_0_23542cbcca0efa2e
port map (
Q => Q,
CLK => CLK,
CE => CE,
SINIT => SINIT);
-- synthesis translate_on
END binary_counter_virtex2p_7_0_23542cbcca0efa2e_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file binary_counter_virtex2p_7_0_32a1863440903b9d.vhd when simulating
-- the core, binary_counter_virtex2p_7_0_32a1863440903b9d. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY binary_counter_virtex2p_7_0_32a1863440903b9d IS
port (
Q: OUT std_logic_VECTOR(14 downto 0);
CLK: IN std_logic;
CE: IN std_logic;
SINIT: IN std_logic);
END binary_counter_virtex2p_7_0_32a1863440903b9d;
ARCHITECTURE binary_counter_virtex2p_7_0_32a1863440903b9d_a OF binary_counter_virtex2p_7_0_32a1863440903b9d IS
-- synthesis translate_off
component wrapped_binary_counter_virtex2p_7_0_32a1863440903b9d
port (
Q: OUT std_logic_VECTOR(14 downto 0);
CLK: IN std_logic;
CE: IN std_logic;
SINIT: IN std_logic);
end component;
-- Configuration specification
for all : wrapped_binary_counter_virtex2p_7_0_32a1863440903b9d use entity XilinxCoreLib.C_COUNTER_BINARY_V7_0(behavioral)
generic map(
c_count_mode => 0,
c_load_enable => 1,
c_has_aset => 0,
c_load_low => 0,
c_count_to => "1111111111111111",
c_sync_priority => 1,
c_has_iv => 0,
c_restrict_count => 0,
c_has_sclr => 0,
c_width => 15,
c_has_q_thresh1 => 0,
c_enable_rlocs => 0,
c_has_q_thresh0 => 0,
c_thresh1_value => "1111111111111111",
c_has_load => 0,
c_thresh_early => 1,
c_has_up => 0,
c_has_thresh1 => 0,
c_has_thresh0 => 0,
c_ainit_val => "0000",
c_has_ce => 1,
c_pipe_stages => 0,
c_has_aclr => 0,
c_sync_enable => 0,
c_has_ainit => 0,
c_sinit_val => "0000",
c_has_sset => 0,
c_has_sinit => 1,
c_count_by => "0001",
c_has_l => 0,
c_thresh0_value => "1111111111111111");
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_binary_counter_virtex2p_7_0_32a1863440903b9d
port map (
Q => Q,
CLK => CLK,
CE => CE,
SINIT => SINIT);
-- synthesis translate_on
END binary_counter_virtex2p_7_0_32a1863440903b9d_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file binary_counter_virtex2p_7_0_77cea312f82499f0.vhd when simulating
-- the core, binary_counter_virtex2p_7_0_77cea312f82499f0. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY binary_counter_virtex2p_7_0_77cea312f82499f0 IS
port (
Q: OUT std_logic_VECTOR(3 downto 0);
CLK: IN std_logic;
LOAD: IN std_logic;
L: IN std_logic_VECTOR(3 downto 0);
CE: IN std_logic;
SINIT: IN std_logic);
END binary_counter_virtex2p_7_0_77cea312f82499f0;
ARCHITECTURE binary_counter_virtex2p_7_0_77cea312f82499f0_a OF binary_counter_virtex2p_7_0_77cea312f82499f0 IS
-- synthesis translate_off
component wrapped_binary_counter_virtex2p_7_0_77cea312f82499f0
port (
Q: OUT std_logic_VECTOR(3 downto 0);
CLK: IN std_logic;
LOAD: IN std_logic;
L: IN std_logic_VECTOR(3 downto 0);
CE: IN std_logic;
SINIT: IN std_logic);
end component;
-- Configuration specification
for all : wrapped_binary_counter_virtex2p_7_0_77cea312f82499f0 use entity XilinxCoreLib.C_COUNTER_BINARY_V7_0(behavioral)
generic map(
c_count_mode => 0,
c_load_enable => 1,
c_has_aset => 0,
c_load_low => 0,
c_count_to => "1111111111111111",
c_sync_priority => 1,
c_has_iv => 0,
c_restrict_count => 0,
c_has_sclr => 0,
c_width => 4,
c_has_q_thresh1 => 0,
c_enable_rlocs => 0,
c_has_q_thresh0 => 0,
c_thresh1_value => "1111111111111111",
c_has_load => 1,
c_thresh_early => 1,
c_has_up => 0,
c_has_thresh1 => 0,
c_has_thresh0 => 0,
c_ainit_val => "1111",
c_has_ce => 1,
c_pipe_stages => 0,
c_has_aclr => 0,
c_sync_enable => 0,
c_has_ainit => 0,
c_sinit_val => "1111",
c_has_sset => 0,
c_has_sinit => 1,
c_count_by => "0001",
c_has_l => 1,
c_thresh0_value => "1111111111111111");
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_binary_counter_virtex2p_7_0_77cea312f82499f0
port map (
Q => Q,
CLK => CLK,
LOAD => LOAD,
L => L,
CE => CE,
SINIT => SINIT);
-- synthesis translate_on
END binary_counter_virtex2p_7_0_77cea312f82499f0_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file binary_counter_virtex2p_7_0_950e4ab582797264.vhd when simulating
-- the core, binary_counter_virtex2p_7_0_950e4ab582797264. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY binary_counter_virtex2p_7_0_950e4ab582797264 IS
port (
Q: OUT std_logic_VECTOR(17 downto 0);
CLK: IN std_logic;
CE: IN std_logic;
SINIT: IN std_logic);
END binary_counter_virtex2p_7_0_950e4ab582797264;
ARCHITECTURE binary_counter_virtex2p_7_0_950e4ab582797264_a OF binary_counter_virtex2p_7_0_950e4ab582797264 IS
-- synthesis translate_off
component wrapped_binary_counter_virtex2p_7_0_950e4ab582797264
port (
Q: OUT std_logic_VECTOR(17 downto 0);
CLK: IN std_logic;
CE: IN std_logic;
SINIT: IN std_logic);
end component;
-- Configuration specification
for all : wrapped_binary_counter_virtex2p_7_0_950e4ab582797264 use entity XilinxCoreLib.C_COUNTER_BINARY_V7_0(behavioral)
generic map(
c_count_mode => 0,
c_load_enable => 1,
c_has_aset => 0,
c_load_low => 0,
c_count_to => "1111111111111111",
c_sync_priority => 1,
c_has_iv => 0,
c_restrict_count => 0,
c_has_sclr => 0,
c_width => 18,
c_has_q_thresh1 => 0,
c_enable_rlocs => 0,
c_has_q_thresh0 => 0,
c_thresh1_value => "1111111111111111",
c_has_load => 0,
c_thresh_early => 1,
c_has_up => 0,
c_has_thresh1 => 0,
c_has_thresh0 => 0,
c_ainit_val => "0000",
c_has_ce => 1,
c_pipe_stages => 0,
c_has_aclr => 0,
c_sync_enable => 0,
c_has_ainit => 0,
c_sinit_val => "0000",
c_has_sset => 0,
c_has_sinit => 1,
c_count_by => "0001",
c_has_l => 0,
c_thresh0_value => "1111111111111111");
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_binary_counter_virtex2p_7_0_950e4ab582797264
port map (
Q => Q,
CLK => CLK,
CE => CE,
SINIT => SINIT);
-- synthesis translate_on
END binary_counter_virtex2p_7_0_950e4ab582797264_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file binary_counter_virtex2p_7_0_a22528b4c55dc1cd.vhd when simulating
-- the core, binary_counter_virtex2p_7_0_a22528b4c55dc1cd. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY binary_counter_virtex2p_7_0_a22528b4c55dc1cd IS
port (
Q: OUT std_logic_VECTOR(13 downto 0);
CLK: IN std_logic;
CE: IN std_logic;
SINIT: IN std_logic);
END binary_counter_virtex2p_7_0_a22528b4c55dc1cd;
ARCHITECTURE binary_counter_virtex2p_7_0_a22528b4c55dc1cd_a OF binary_counter_virtex2p_7_0_a22528b4c55dc1cd IS
-- synthesis translate_off
component wrapped_binary_counter_virtex2p_7_0_a22528b4c55dc1cd
port (
Q: OUT std_logic_VECTOR(13 downto 0);
CLK: IN std_logic;
CE: IN std_logic;
SINIT: IN std_logic);
end component;
-- Configuration specification
for all : wrapped_binary_counter_virtex2p_7_0_a22528b4c55dc1cd use entity XilinxCoreLib.C_COUNTER_BINARY_V7_0(behavioral)
generic map(
c_count_mode => 0,
c_load_enable => 1,
c_has_aset => 0,
c_load_low => 0,
c_count_to => "1111111111111111",
c_sync_priority => 1,
c_has_iv => 0,
c_restrict_count => 0,
c_has_sclr => 0,
c_width => 14,
c_has_q_thresh1 => 0,
c_enable_rlocs => 0,
c_has_q_thresh0 => 0,
c_thresh1_value => "1111111111111111",
c_has_load => 0,
c_thresh_early => 1,
c_has_up => 0,
c_has_thresh1 => 0,
c_has_thresh0 => 0,
c_ainit_val => "11111111111111",
c_has_ce => 1,
c_pipe_stages => 0,
c_has_aclr => 0,
c_sync_enable => 0,
c_has_ainit => 0,
c_sinit_val => "11111111111111",
c_has_sset => 0,
c_has_sinit => 1,
c_count_by => "0001",
c_has_l => 0,
c_thresh0_value => "1111111111111111");
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_binary_counter_virtex2p_7_0_a22528b4c55dc1cd
port map (
Q => Q,
CLK => CLK,
CE => CE,
SINIT => SINIT);
-- synthesis translate_on
END binary_counter_virtex2p_7_0_a22528b4c55dc1cd_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file binary_counter_virtex2p_7_0_b0a257f5389d649a.vhd when simulating
-- the core, binary_counter_virtex2p_7_0_b0a257f5389d649a. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY binary_counter_virtex2p_7_0_b0a257f5389d649a IS
port (
Q: OUT std_logic_VECTOR(6 downto 0);
CLK: IN std_logic;
CE: IN std_logic;
SINIT: IN std_logic);
END binary_counter_virtex2p_7_0_b0a257f5389d649a;
ARCHITECTURE binary_counter_virtex2p_7_0_b0a257f5389d649a_a OF binary_counter_virtex2p_7_0_b0a257f5389d649a IS
-- synthesis translate_off
component wrapped_binary_counter_virtex2p_7_0_b0a257f5389d649a
port (
Q: OUT std_logic_VECTOR(6 downto 0);
CLK: IN std_logic;
CE: IN std_logic;
SINIT: IN std_logic);
end component;
-- Configuration specification
for all : wrapped_binary_counter_virtex2p_7_0_b0a257f5389d649a use entity XilinxCoreLib.C_COUNTER_BINARY_V7_0(behavioral)
generic map(
c_count_mode => 0,
c_load_enable => 1,
c_has_aset => 0,
c_load_low => 0,
c_count_to => "1111111111111111",
c_sync_priority => 1,
c_has_iv => 0,
c_restrict_count => 0,
c_has_sclr => 0,
c_width => 7,
c_has_q_thresh1 => 0,
c_enable_rlocs => 0,
c_has_q_thresh0 => 0,
c_thresh1_value => "1111111111111111",
c_has_load => 0,
c_thresh_early => 1,
c_has_up => 0,
c_has_thresh1 => 0,
c_has_thresh0 => 0,
c_ainit_val => "1111111",
c_has_ce => 1,
c_pipe_stages => 0,
c_has_aclr => 0,
c_sync_enable => 0,
c_has_ainit => 0,
c_sinit_val => "1111111",
c_has_sset => 0,
c_has_sinit => 1,
c_count_by => "0001",
c_has_l => 0,
c_thresh0_value => "1111111111111111");
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_binary_counter_virtex2p_7_0_b0a257f5389d649a
port map (
Q => Q,
CLK => CLK,
CE => CE,
SINIT => SINIT);
-- synthesis translate_on
END binary_counter_virtex2p_7_0_b0a257f5389d649a_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file binary_counter_virtex2p_7_0_b511f9871581ee23.vhd when simulating
-- the core, binary_counter_virtex2p_7_0_b511f9871581ee23. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY binary_counter_virtex2p_7_0_b511f9871581ee23 IS
port (
Q: OUT std_logic_VECTOR(2 downto 0);
CLK: IN std_logic;
LOAD: IN std_logic;
L: IN std_logic_VECTOR(2 downto 0);
CE: IN std_logic;
SINIT: IN std_logic);
END binary_counter_virtex2p_7_0_b511f9871581ee23;
ARCHITECTURE binary_counter_virtex2p_7_0_b511f9871581ee23_a OF binary_counter_virtex2p_7_0_b511f9871581ee23 IS
-- synthesis translate_off
component wrapped_binary_counter_virtex2p_7_0_b511f9871581ee23
port (
Q: OUT std_logic_VECTOR(2 downto 0);
CLK: IN std_logic;
LOAD: IN std_logic;
L: IN std_logic_VECTOR(2 downto 0);
CE: IN std_logic;
SINIT: IN std_logic);
end component;
-- Configuration specification
for all : wrapped_binary_counter_virtex2p_7_0_b511f9871581ee23 use entity XilinxCoreLib.C_COUNTER_BINARY_V7_0(behavioral)
generic map(
c_count_mode => 0,
c_load_enable => 1,
c_has_aset => 0,
c_load_low => 0,
c_count_to => "1111111111111111",
c_sync_priority => 1,
c_has_iv => 0,
c_restrict_count => 0,
c_has_sclr => 0,
c_width => 3,
c_has_q_thresh1 => 0,
c_enable_rlocs => 0,
c_has_q_thresh0 => 0,
c_thresh1_value => "1111111111111111",
c_has_load => 1,
c_thresh_early => 1,
c_has_up => 0,
c_has_thresh1 => 0,
c_has_thresh0 => 0,
c_ainit_val => "000",
c_has_ce => 1,
c_pipe_stages => 0,
c_has_aclr => 0,
c_sync_enable => 0,
c_has_ainit => 0,
c_sinit_val => "000",
c_has_sset => 0,
c_has_sinit => 1,
c_count_by => "001",
c_has_l => 1,
c_thresh0_value => "1111111111111111");
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_binary_counter_virtex2p_7_0_b511f9871581ee23
port map (
Q => Q,
CLK => CLK,
LOAD => LOAD,
L => L,
CE => CE,
SINIT => SINIT);
-- synthesis translate_on
END binary_counter_virtex2p_7_0_b511f9871581ee23_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file multiplier_virtex2p_10_1_817edd563258bb47.vhd when simulating
-- the core, multiplier_virtex2p_10_1_817edd563258bb47. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY multiplier_virtex2p_10_1_817edd563258bb47 IS
port (
clk: IN std_logic;
a: IN std_logic_VECTOR(17 downto 0);
b: IN std_logic_VECTOR(17 downto 0);
ce: IN std_logic;
sclr: IN std_logic;
p: OUT std_logic_VECTOR(35 downto 0));
END multiplier_virtex2p_10_1_817edd563258bb47;
ARCHITECTURE multiplier_virtex2p_10_1_817edd563258bb47_a OF multiplier_virtex2p_10_1_817edd563258bb47 IS
-- synthesis translate_off
component wrapped_multiplier_virtex2p_10_1_817edd563258bb47
port (
clk: IN std_logic;
a: IN std_logic_VECTOR(17 downto 0);
b: IN std_logic_VECTOR(17 downto 0);
ce: IN std_logic;
sclr: IN std_logic;
p: OUT std_logic_VECTOR(35 downto 0));
end component;
-- Configuration specification
for all : wrapped_multiplier_virtex2p_10_1_817edd563258bb47 use entity XilinxCoreLib.mult_gen_v10_1(behavioral)
generic map(
c_a_width => 18,
c_b_type => 1,
c_ce_overrides_sclr => 1,
c_has_sclr => 1,
c_round_pt => 0,
c_model_type => 0,
c_out_high => 35,
c_verbosity => 0,
c_mult_type => 1,
c_ccm_imp => 0,
c_latency => 1,
c_has_ce => 1,
c_has_zero_detect => 0,
c_round_output => 0,
c_optimize_goal => 1,
c_xdevicefamily => "virtex2p",
c_a_type => 1,
c_out_low => 0,
c_b_width => 18,
c_b_value => "10000001");
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_multiplier_virtex2p_10_1_817edd563258bb47
port map (
clk => clk,
a => a,
b => b,
ce => ce,
sclr => sclr,
p => p);
-- synthesis translate_on
END multiplier_virtex2p_10_1_817edd563258bb47_a;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package conv_pkg is
constant simulating : boolean := false
-- synopsys translate_off
or true
-- synopsys translate_on
;
constant xlUnsigned : integer := 1;
constant xlSigned : integer := 2;
constant xlWrap : integer := 1;
constant xlSaturate : integer := 2;
constant xlTruncate : integer := 1;
constant xlRound : integer := 2;
constant xlRoundBanker : integer := 3;
constant xlAddMode : integer := 1;
constant xlSubMode : integer := 2;
attribute black_box : boolean;
attribute syn_black_box : boolean;
attribute fpga_dont_touch: string;
attribute box_type : string;
attribute keep : string;
attribute syn_keep : boolean;
function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned;
function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector;
function std_logic_vector_to_signed(inp : std_logic_vector) return signed;
function signed_to_std_logic_vector(inp : signed) return std_logic_vector;
function unsigned_to_signed(inp : unsigned) return signed;
function signed_to_unsigned(inp : signed) return unsigned;
function pos(inp : std_logic_vector; arith : INTEGER) return boolean;
function all_same(inp: std_logic_vector) return boolean;
function all_zeros(inp: std_logic_vector) return boolean;
function is_point_five(inp: std_logic_vector) return boolean;
function all_ones(inp: std_logic_vector) return boolean;
function convert_type (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith,
quantization, overflow : INTEGER)
return std_logic_vector;
function cast (inp : std_logic_vector; old_bin_pt,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function vec_slice (inp : std_logic_vector; upper, lower : INTEGER)
return std_logic_vector;
function s2u_slice (inp : signed; upper, lower : INTEGER)
return unsigned;
function u2u_slice (inp : unsigned; upper, lower : INTEGER)
return unsigned;
function s2s_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return signed;
function u2s_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return signed;
function s2u_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return unsigned;
function u2u_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return unsigned;
function u2v_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return std_logic_vector;
function s2v_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return std_logic_vector;
function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt,
new_arith : INTEGER) return std_logic_vector;
function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt,
new_arith : INTEGER) return std_logic_vector;
function max_signed(width : INTEGER) return std_logic_vector;
function min_signed(width : INTEGER) return std_logic_vector;
function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER) return std_logic_vector;
function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER;
function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER)
return INTEGER;
function sign_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector;
function zero_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector;
function zero_ext(inp : std_logic; new_width : INTEGER)
return std_logic_vector;
function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER)
return std_logic_vector;
function align_input(inp : std_logic_vector; old_width, delta, new_arith,
new_width: INTEGER)
return std_logic_vector;
function pad_LSB(inp : std_logic_vector; new_width: integer)
return std_logic_vector;
function pad_LSB(inp : std_logic_vector; new_width, arith : integer)
return std_logic_vector;
function max(L, R: INTEGER) return INTEGER;
function min(L, R: INTEGER) return INTEGER;
function "="(left,right: STRING) return boolean;
function boolean_to_signed (inp : boolean; width: integer)
return signed;
function boolean_to_unsigned (inp : boolean; width: integer)
return unsigned;
function boolean_to_vector (inp : boolean)
return std_logic_vector;
function std_logic_to_vector (inp : std_logic)
return std_logic_vector;
function integer_to_std_logic_vector (inp : integer; width, arith : integer)
return std_logic_vector;
function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer)
return integer;
function std_logic_to_integer(constant inp : std_logic := '0')
return integer;
function bin_string_element_to_std_logic_vector (inp : string; width, index : integer)
return std_logic_vector;
function bin_string_to_std_logic_vector (inp : string)
return std_logic_vector;
function hex_string_to_std_logic_vector (inp : string; width : integer)
return std_logic_vector;
function makeZeroBinStr (width : integer) return STRING;
function and_reduce(inp: std_logic_vector) return std_logic;
-- synopsys translate_off
function is_binary_string_invalid (inp : string)
return boolean;
function is_binary_string_undefined (inp : string)
return boolean;
function is_XorU(inp : std_logic_vector)
return boolean;
function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer)
return real;
function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer)
return real;
function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer)
return std_logic_vector;
function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer)
return std_logic_vector;
constant display_precision : integer := 20;
function real_to_string (inp : real) return string;
function valid_bin_string(inp : string) return boolean;
function std_logic_vector_to_bin_string(inp : std_logic_vector) return string;
function std_logic_to_bin_string(inp : std_logic) return string;
function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer)
return string;
function real_to_bin_string(inp : real; width, bin_pt, arith : integer)
return string;
type stdlogic_to_char_t is array(std_logic) of character;
constant to_char : stdlogic_to_char_t := (
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => '-');
-- synopsys translate_on
end conv_pkg;
package body conv_pkg is
function std_logic_vector_to_unsigned(inp : std_logic_vector)
return unsigned
is
begin
return unsigned (inp);
end;
function unsigned_to_std_logic_vector(inp : unsigned)
return std_logic_vector
is
begin
return std_logic_vector(inp);
end;
function std_logic_vector_to_signed(inp : std_logic_vector)
return signed
is
begin
return signed (inp);
end;
function signed_to_std_logic_vector(inp : signed)
return std_logic_vector
is
begin
return std_logic_vector(inp);
end;
function unsigned_to_signed (inp : unsigned)
return signed
is
begin
return signed(std_logic_vector(inp));
end;
function signed_to_unsigned (inp : signed)
return unsigned
is
begin
return unsigned(std_logic_vector(inp));
end;
function pos(inp : std_logic_vector; arith : INTEGER)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
if arith = xlUnsigned then
return true;
else
if vec(width-1) = '0' then
return true;
else
return false;
end if;
end if;
return true;
end;
function max_signed(width : INTEGER)
return std_logic_vector
is
variable ones : std_logic_vector(width-2 downto 0);
variable result : std_logic_vector(width-1 downto 0);
begin
ones := (others => '1');
result(width-1) := '0';
result(width-2 downto 0) := ones;
return result;
end;
function min_signed(width : INTEGER)
return std_logic_vector
is
variable zeros : std_logic_vector(width-2 downto 0);
variable result : std_logic_vector(width-1 downto 0);
begin
zeros := (others => '0');
result(width-1) := '1';
result(width-2 downto 0) := zeros;
return result;
end;
function and_reduce(inp: std_logic_vector) return std_logic
is
variable result: std_logic;
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := vec(0);
if width > 1 then
for i in 1 to width-1 loop
result := result and vec(i);
end loop;
end if;
return result;
end;
function all_same(inp: std_logic_vector) return boolean
is
variable result: boolean;
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := true;
if width > 0 then
for i in 1 to width-1 loop
if vec(i) /= vec(0) then
result := false;
end if;
end loop;
end if;
return result;
end;
function all_zeros(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable zero : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
zero := (others => '0');
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(zero)) then
result := true;
else
result := false;
end if;
return result;
end;
function is_point_five(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (width > 1) then
if ((vec(width-1) = '1') and (all_zeros(vec(width-2 downto 0)) = true)) then
result := true;
else
result := false;
end if;
else
if (vec(width-1) = '1') then
result := true;
else
result := false;
end if;
end if;
return result;
end;
function all_ones(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable one : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
one := (others => '1');
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(one)) then
result := true;
else
result := false;
end if;
return result;
end;
function full_precision_num_width(quantization, overflow, old_width,
old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return integer
is
variable result : integer;
begin
result := old_width + 2;
return result;
end;
function quantized_num_width(quantization, overflow, old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return integer
is
variable right_of_dp, left_of_dp, result : integer;
begin
right_of_dp := max(new_bin_pt, old_bin_pt);
left_of_dp := max((new_width - new_bin_pt), (old_width - old_bin_pt));
result := (old_width + 2) + (new_bin_pt - old_bin_pt);
return result;
end;
function convert_type (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith,
quantization, overflow : INTEGER)
return std_logic_vector
is
constant fp_width : integer :=
full_precision_num_width(quantization, overflow, old_width,
old_bin_pt, old_arith, new_width,
new_bin_pt, new_arith);
constant fp_bin_pt : integer := old_bin_pt;
constant fp_arith : integer := old_arith;
variable full_precision_result : std_logic_vector(fp_width-1 downto 0);
constant q_width : integer :=
quantized_num_width(quantization, overflow, old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith);
constant q_bin_pt : integer := new_bin_pt;
constant q_arith : integer := old_arith;
variable quantized_result : std_logic_vector(q_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
result := (others => '0');
full_precision_result := cast(inp, old_bin_pt, fp_width, fp_bin_pt,
fp_arith);
if (quantization = xlRound) then
quantized_result := round_towards_inf(full_precision_result,
fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt,
q_arith);
elsif (quantization = xlRoundBanker) then
quantized_result := round_towards_even(full_precision_result,
fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt,
q_arith);
else
quantized_result := trunc(full_precision_result, fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt, q_arith);
end if;
if (overflow = xlSaturate) then
result := saturation_arith(quantized_result, q_width, q_bin_pt,
q_arith, new_width, new_bin_pt, new_arith);
else
result := wrap_arith(quantized_result, q_width, q_bin_pt, q_arith,
new_width, new_bin_pt, new_arith);
end if;
return result;
end;
function cast (inp : std_logic_vector; old_bin_pt, new_width,
new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
constant left_of_dp : integer := (new_width - new_bin_pt)
- (old_width - old_bin_pt);
constant right_of_dp : integer := (new_bin_pt - old_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable j : integer;
begin
vec := inp;
for i in new_width-1 downto 0 loop
j := i - right_of_dp;
if ( j > old_width-1) then
if (new_arith = xlUnsigned) then
result(i) := '0';
else
result(i) := vec(old_width-1);
end if;
elsif ( j >= 0) then
result(i) := vec(j);
else
result(i) := '0';
end if;
end loop;
return result;
end;
function vec_slice (inp : std_logic_vector; upper, lower : INTEGER)
return std_logic_vector
is
begin
return inp(upper downto lower);
end;
function s2u_slice (inp : signed; upper, lower : INTEGER)
return unsigned
is
begin
return unsigned(vec_slice(std_logic_vector(inp), upper, lower));
end;
function u2u_slice (inp : unsigned; upper, lower : INTEGER)
return unsigned
is
begin
return unsigned(vec_slice(std_logic_vector(inp), upper, lower));
end;
function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER)
return signed
is
begin
return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned));
end;
function s2u_cast (inp : signed; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return unsigned
is
begin
return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned));
end;
function u2s_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return signed
is
begin
return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned));
end;
function u2u_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return unsigned
is
begin
return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned));
end;
function u2v_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return std_logic_vector
is
begin
return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned);
end;
function s2v_cast (inp : signed; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return std_logic_vector
is
begin
return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned);
end;
function boolean_to_signed (inp : boolean; width : integer)
return signed
is
variable result : signed(width - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function boolean_to_unsigned (inp : boolean; width : integer)
return unsigned
is
variable result : unsigned(width - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function boolean_to_vector (inp : boolean)
return std_logic_vector
is
variable result : std_logic_vector(1 - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function std_logic_to_vector (inp : std_logic)
return std_logic_vector
is
variable result : std_logic_vector(1 - 1 downto 0);
begin
result(0) := inp;
return result;
end;
function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
result := zero_ext(vec(old_width-1 downto right_of_dp), new_width);
else
result := sign_ext(vec(old_width-1 downto right_of_dp), new_width);
end if;
else
if new_arith = xlUnsigned then
result := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
result := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
return result;
end;
function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
constant expected_new_width : integer := old_width - right_of_dp + 1;
variable vec : std_logic_vector(old_width-1 downto 0);
variable one_or_zero : std_logic_vector(new_width-1 downto 0);
variable truncated_val : std_logic_vector(new_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
truncated_val := zero_ext(vec(old_width-1 downto right_of_dp),
new_width);
else
truncated_val := sign_ext(vec(old_width-1 downto right_of_dp),
new_width);
end if;
else
if new_arith = xlUnsigned then
truncated_val := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
truncated_val := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
one_or_zero := (others => '0');
if (new_arith = xlSigned) then
if (vec(old_width-1) = '0') then
one_or_zero(0) := '1';
end if;
if (right_of_dp >= 2) and (right_of_dp <= old_width) then
if (all_zeros(vec(right_of_dp-2 downto 0)) = false) then
one_or_zero(0) := '1';
end if;
end if;
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
if vec(right_of_dp-1) = '0' then
one_or_zero(0) := '0';
end if;
else
one_or_zero(0) := '0';
end if;
else
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
one_or_zero(0) := vec(right_of_dp-1);
end if;
end if;
if new_arith = xlSigned then
result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) +
std_logic_vector_to_signed(one_or_zero));
else
result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) +
std_logic_vector_to_unsigned(one_or_zero));
end if;
return result;
end;
function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
constant expected_new_width : integer := old_width - right_of_dp + 1;
variable vec : std_logic_vector(old_width-1 downto 0);
variable one_or_zero : std_logic_vector(new_width-1 downto 0);
variable truncated_val : std_logic_vector(new_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
truncated_val := zero_ext(vec(old_width-1 downto right_of_dp),
new_width);
else
truncated_val := sign_ext(vec(old_width-1 downto right_of_dp),
new_width);
end if;
else
if new_arith = xlUnsigned then
truncated_val := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
truncated_val := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
one_or_zero := (others => '0');
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
if (is_point_five(vec(right_of_dp-1 downto 0)) = false) then
one_or_zero(0) := vec(right_of_dp-1);
else
one_or_zero(0) := vec(right_of_dp);
end if;
end if;
if new_arith = xlSigned then
result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) +
std_logic_vector_to_signed(one_or_zero));
else
result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) +
std_logic_vector_to_unsigned(one_or_zero));
end if;
return result;
end;
function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant left_of_dp : integer := (old_width - old_bin_pt) -
(new_width - new_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable overflow : boolean;
begin
vec := inp;
overflow := true;
result := (others => '0');
if (new_width >= old_width) then
overflow := false;
end if;
if ((old_arith = xlSigned and new_arith = xlSigned) and (old_width > new_width)) then
if all_same(vec(old_width-1 downto new_width-1)) then
overflow := false;
end if;
end if;
if (old_arith = xlSigned and new_arith = xlUnsigned) then
if (old_width > new_width) then
if all_zeros(vec(old_width-1 downto new_width)) then
overflow := false;
end if;
else
if (old_width = new_width) then
if (vec(new_width-1) = '0') then
overflow := false;
end if;
end if;
end if;
end if;
if (old_arith = xlUnsigned and new_arith = xlUnsigned) then
if (old_width > new_width) then
if all_zeros(vec(old_width-1 downto new_width)) then
overflow := false;
end if;
else
if (old_width = new_width) then
overflow := false;
end if;
end if;
end if;
if ((old_arith = xlUnsigned and new_arith = xlSigned) and (old_width > new_width)) then
if all_same(vec(old_width-1 downto new_width-1)) then
overflow := false;
end if;
end if;
if overflow then
if new_arith = xlSigned then
if vec(old_width-1) = '0' then
result := max_signed(new_width);
else
result := min_signed(new_width);
end if;
else
if ((old_arith = xlSigned) and vec(old_width-1) = '1') then
result := (others => '0');
else
result := (others => '1');
end if;
end if;
else
if (old_arith = xlSigned) and (new_arith = xlUnsigned) then
if (vec(old_width-1) = '1') then
vec := (others => '0');
end if;
end if;
if new_width <= old_width then
result := vec(new_width-1 downto 0);
else
if new_arith = xlUnsigned then
result := zero_ext(vec, new_width);
else
result := sign_ext(vec, new_width);
end if;
end if;
end if;
return result;
end;
function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
variable result : std_logic_vector(new_width-1 downto 0);
variable result_arith : integer;
begin
if (old_arith = xlSigned) and (new_arith = xlUnsigned) then
result_arith := xlSigned;
end if;
result := cast(inp, old_bin_pt, new_width, new_bin_pt, result_arith);
return result;
end;
function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER is
begin
return max(a_bin_pt, b_bin_pt);
end;
function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER)
return INTEGER is
begin
return max(a_width - a_bin_pt, b_width - b_bin_pt);
end;
function pad_LSB(inp : std_logic_vector; new_width: integer)
return STD_LOGIC_VECTOR
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable pos : integer;
constant pad_pos : integer := new_width - orig_width - 1;
begin
vec := inp;
pos := new_width-1;
if (new_width >= orig_width) then
for i in orig_width-1 downto 0 loop
result(pos) := vec(i);
pos := pos - 1;
end loop;
if pad_pos >= 0 then
for i in pad_pos downto 0 loop
result(i) := '0';
end loop;
end if;
end if;
return result;
end;
function sign_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if new_width >= old_width then
result(old_width-1 downto 0) := vec;
if new_width-1 >= old_width then
for i in new_width-1 downto old_width loop
result(i) := vec(old_width-1);
end loop;
end if;
else
result(new_width-1 downto 0) := vec(new_width-1 downto 0);
end if;
return result;
end;
function zero_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if new_width >= old_width then
result(old_width-1 downto 0) := vec;
if new_width-1 >= old_width then
for i in new_width-1 downto old_width loop
result(i) := '0';
end loop;
end if;
else
result(new_width-1 downto 0) := vec(new_width-1 downto 0);
end if;
return result;
end;
function zero_ext(inp : std_logic; new_width : INTEGER)
return std_logic_vector
is
variable result : std_logic_vector(new_width-1 downto 0);
begin
result(0) := inp;
for i in new_width-1 downto 1 loop
result(i) := '0';
end loop;
return result;
end;
function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER)
return std_logic_vector
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if arith = xlUnsigned then
result := zero_ext(vec, new_width);
else
result := sign_ext(vec, new_width);
end if;
return result;
end;
function pad_LSB(inp : std_logic_vector; new_width, arith: integer)
return STD_LOGIC_VECTOR
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable pos : integer;
begin
vec := inp;
pos := new_width-1;
if (arith = xlUnsigned) then
result(pos) := '0';
pos := pos - 1;
else
result(pos) := vec(orig_width-1);
pos := pos - 1;
end if;
if (new_width >= orig_width) then
for i in orig_width-1 downto 0 loop
result(pos) := vec(i);
pos := pos - 1;
end loop;
if pos >= 0 then
for i in pos downto 0 loop
result(i) := '0';
end loop;
end if;
end if;
return result;
end;
function align_input(inp : std_logic_vector; old_width, delta, new_arith,
new_width: INTEGER)
return std_logic_vector
is
variable vec : std_logic_vector(old_width-1 downto 0);
variable padded_inp : std_logic_vector((old_width + delta)-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if delta > 0 then
padded_inp := pad_LSB(vec, old_width+delta);
result := extend_MSB(padded_inp, new_width, new_arith);
else
result := extend_MSB(vec, new_width, new_arith);
end if;
return result;
end;
function max(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
function "="(left,right: STRING) return boolean is
begin
if (left'length /= right'length) then
return false;
else
test : for i in 1 to left'length loop
if left(i) /= right(i) then
return false;
end if;
end loop test;
return true;
end if;
end;
-- synopsys translate_off
function is_binary_string_invalid (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 1 to vec'length loop
if ( vec(i) = 'X' ) then
result := true;
end if;
end loop;
return result;
end;
function is_binary_string_undefined (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 1 to vec'length loop
if ( vec(i) = 'U' ) then
result := true;
end if;
end loop;
return result;
end;
function is_XorU(inp : std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 0 to width-1 loop
if (vec(i) = 'U') or (vec(i) = 'X') then
result := true;
end if;
end loop;
return result;
end;
function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer)
return real
is
variable vec : std_logic_vector(inp'length-1 downto 0);
variable result, shift_val, undefined_real : real;
variable neg_num : boolean;
begin
vec := inp;
result := 0.0;
neg_num := false;
if vec(inp'length-1) = '1' then
neg_num := true;
end if;
for i in 0 to inp'length-1 loop
if vec(i) = 'U' or vec(i) = 'X' then
return undefined_real;
end if;
if arith = xlSigned then
if neg_num then
if vec(i) = '0' then
result := result + 2.0**i;
end if;
else
if vec(i) = '1' then
result := result + 2.0**i;
end if;
end if;
else
if vec(i) = '1' then
result := result + 2.0**i;
end if;
end if;
end loop;
if arith = xlSigned then
if neg_num then
result := result + 1.0;
result := result * (-1.0);
end if;
end if;
shift_val := 2.0**(-1*bin_pt);
result := result * shift_val;
return result;
end;
function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer)
return real
is
variable result : real := 0.0;
begin
if inp = '1' then
result := 1.0;
end if;
if arith = xlSigned then
assert false
report "It doesn't make sense to convert a 1 bit number to a signed real.";
end if;
return result;
end;
-- synopsys translate_on
function integer_to_std_logic_vector (inp : integer; width, arith : integer)
return std_logic_vector
is
variable result : std_logic_vector(width-1 downto 0);
variable unsigned_val : unsigned(width-1 downto 0);
variable signed_val : signed(width-1 downto 0);
begin
if (arith = xlSigned) then
signed_val := to_signed(inp, width);
result := signed_to_std_logic_vector(signed_val);
else
unsigned_val := to_unsigned(inp, width);
result := unsigned_to_std_logic_vector(unsigned_val);
end if;
return result;
end;
function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer)
return integer
is
constant width : integer := inp'length;
variable unsigned_val : unsigned(width-1 downto 0);
variable signed_val : signed(width-1 downto 0);
variable result : integer;
begin
if (arith = xlSigned) then
signed_val := std_logic_vector_to_signed(inp);
result := to_integer(signed_val);
else
unsigned_val := std_logic_vector_to_unsigned(inp);
result := to_integer(unsigned_val);
end if;
return result;
end;
function std_logic_to_integer(constant inp : std_logic := '0')
return integer
is
begin
if inp = '1' then
return 1;
else
return 0;
end if;
end;
function makeZeroBinStr (width : integer) return STRING is
variable result : string(1 to width+3);
begin
result(1) := '0';
result(2) := 'b';
for i in 3 to width+2 loop
result(i) := '0';
end loop;
result(width+3) := '.';
return result;
end;
-- synopsys translate_off
function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer)
return std_logic_vector
is
variable result : std_logic_vector(width-1 downto 0);
begin
result := (others => '0');
return result;
end;
function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer)
return std_logic_vector
is
variable real_val : real;
variable int_val : integer;
variable result : std_logic_vector(width-1 downto 0) := (others => '0');
variable unsigned_val : unsigned(width-1 downto 0) := (others => '0');
variable signed_val : signed(width-1 downto 0) := (others => '0');
begin
real_val := inp;
int_val := integer(real_val * 2.0**(bin_pt));
if (arith = xlSigned) then
signed_val := to_signed(int_val, width);
result := signed_to_std_logic_vector(signed_val);
else
unsigned_val := to_unsigned(int_val, width);
result := unsigned_to_std_logic_vector(unsigned_val);
end if;
return result;
end;
-- synopsys translate_on
function valid_bin_string (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
begin
vec := inp;
if (vec(1) = '0' and vec(2) = 'b') then
return true;
else
return false;
end if;
end;
function hex_string_to_std_logic_vector(inp: string; width : integer)
return std_logic_vector is
constant strlen : integer := inp'LENGTH;
variable result : std_logic_vector(width-1 downto 0);
variable bitval : std_logic_vector((strlen*4)-1 downto 0);
variable posn : integer;
variable ch : character;
variable vec : string(1 to strlen);
begin
vec := inp;
result := (others => '0');
posn := (strlen*4)-1;
for i in 1 to strlen loop
ch := vec(i);
case ch is
when '0' => bitval(posn downto posn-3) := "0000";
when '1' => bitval(posn downto posn-3) := "0001";
when '2' => bitval(posn downto posn-3) := "0010";
when '3' => bitval(posn downto posn-3) := "0011";
when '4' => bitval(posn downto posn-3) := "0100";
when '5' => bitval(posn downto posn-3) := "0101";
when '6' => bitval(posn downto posn-3) := "0110";
when '7' => bitval(posn downto posn-3) := "0111";
when '8' => bitval(posn downto posn-3) := "1000";
when '9' => bitval(posn downto posn-3) := "1001";
when 'A' | 'a' => bitval(posn downto posn-3) := "1010";
when 'B' | 'b' => bitval(posn downto posn-3) := "1011";
when 'C' | 'c' => bitval(posn downto posn-3) := "1100";
when 'D' | 'd' => bitval(posn downto posn-3) := "1101";
when 'E' | 'e' => bitval(posn downto posn-3) := "1110";
when 'F' | 'f' => bitval(posn downto posn-3) := "1111";
when others => bitval(posn downto posn-3) := "XXXX";
-- synopsys translate_off
ASSERT false
REPORT "Invalid hex value" SEVERITY ERROR;
-- synopsys translate_on
end case;
posn := posn - 4;
end loop;
if (width <= strlen*4) then
result := bitval(width-1 downto 0);
else
result((strlen*4)-1 downto 0) := bitval;
end if;
return result;
end;
function bin_string_to_std_logic_vector (inp : string)
return std_logic_vector
is
variable pos : integer;
variable vec : string(1 to inp'length);
variable result : std_logic_vector(inp'length-1 downto 0);
begin
vec := inp;
pos := inp'length-1;
result := (others => '0');
for i in 1 to vec'length loop
-- synopsys translate_off
if (pos < 0) and (vec(i) = '0' or vec(i) = '1' or vec(i) = 'X' or vec(i) = 'U') then
assert false
report "Input string is larger than output std_logic_vector. Truncating output.";
return result;
end if;
-- synopsys translate_on
if vec(i) = '0' then
result(pos) := '0';
pos := pos - 1;
end if;
if vec(i) = '1' then
result(pos) := '1';
pos := pos - 1;
end if;
-- synopsys translate_off
if (vec(i) = 'X' or vec(i) = 'U') then
result(pos) := 'U';
pos := pos - 1;
end if;
-- synopsys translate_on
end loop;
return result;
end;
function bin_string_element_to_std_logic_vector (inp : string; width, index : integer)
return std_logic_vector
is
constant str_width : integer := width + 4;
constant inp_len : integer := inp'length;
constant num_elements : integer := (inp_len + 1)/str_width;
constant reverse_index : integer := (num_elements-1) - index;
variable left_pos : integer;
variable right_pos : integer;
variable vec : string(1 to inp'length);
variable result : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := (others => '0');
if (reverse_index = 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then
left_pos := 1;
right_pos := width + 3;
result := bin_string_to_std_logic_vector(vec(left_pos to right_pos));
end if;
if (reverse_index > 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then
left_pos := (reverse_index * str_width) + 1;
right_pos := left_pos + width + 2;
result := bin_string_to_std_logic_vector(vec(left_pos to right_pos));
end if;
return result;
end;
-- synopsys translate_off
function std_logic_vector_to_bin_string(inp : std_logic_vector)
return string
is
variable vec : std_logic_vector(1 to inp'length);
variable result : string(vec'range);
begin
vec := inp;
for i in vec'range loop
result(i) := to_char(vec(i));
end loop;
return result;
end;
function std_logic_to_bin_string(inp : std_logic)
return string
is
variable result : string(1 to 3);
begin
result(1) := '0';
result(2) := 'b';
result(3) := to_char(inp);
return result;
end;
function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer)
return string
is
variable width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable str_pos : integer;
variable result : string(1 to width+3);
begin
vec := inp;
str_pos := 1;
result(str_pos) := '0';
str_pos := 2;
result(str_pos) := 'b';
str_pos := 3;
for i in width-1 downto 0 loop
if (((width+3) - bin_pt) = str_pos) then
result(str_pos) := '.';
str_pos := str_pos + 1;
end if;
result(str_pos) := to_char(vec(i));
str_pos := str_pos + 1;
end loop;
if (bin_pt = 0) then
result(str_pos) := '.';
end if;
return result;
end;
function real_to_bin_string(inp : real; width, bin_pt, arith : integer)
return string
is
variable result : string(1 to width);
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := real_to_std_logic_vector(inp, width, bin_pt, arith);
result := std_logic_vector_to_bin_string(vec);
return result;
end;
function real_to_string (inp : real) return string
is
variable result : string(1 to display_precision) := (others => ' ');
begin
result(real'image(inp)'range) := real'image(inp);
return result;
end;
-- synopsys translate_on
end conv_pkg;
library IEEE;
use IEEE.std_logic_1164.all;
package clock_pkg is
-- synopsys translate_off
signal int_clk : std_logic;
-- synopsys translate_on
end clock_pkg;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity srl17e is
generic (width : integer:=16;
latency : integer :=8);
port (clk : in std_logic;
ce : in std_logic;
d : in std_logic_vector(width-1 downto 0);
q : out std_logic_vector(width-1 downto 0));
end srl17e;
architecture structural of srl17e is
component SRL16E
port (D : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
attribute syn_black_box of SRL16E : component is true;
attribute fpga_dont_touch of SRL16E : component is "true";
component FDE
port(
Q : out STD_ULOGIC;
D : in STD_ULOGIC;
C : in STD_ULOGIC;
CE : in STD_ULOGIC);
end component;
attribute syn_black_box of FDE : component is true;
attribute fpga_dont_touch of FDE : component is "true";
constant a : std_logic_vector(4 downto 0) :=
integer_to_std_logic_vector(latency-2,5,xlSigned);
signal d_delayed : std_logic_vector(width-1 downto 0);
signal srl16_out : std_logic_vector(width-1 downto 0);
begin
d_delayed <= d after 200 ps;
reg_array : for i in 0 to width-1 generate
srl16_used: if latency > 1 generate
u1 : srl16e port map(clk => clk,
d => d_delayed(i),
q => srl16_out(i),
ce => ce,
a0 => a(0),
a1 => a(1),
a2 => a(2),
a3 => a(3));
end generate;
srl16_not_used: if latency <= 1 generate
srl16_out(i) <= d_delayed(i);
end generate;
fde_used: if latency /= 0 generate
u2 : fde port map(c => clk,
d => srl16_out(i),
q => q(i),
ce => ce);
end generate;
fde_not_used: if latency = 0 generate
q(i) <= srl16_out(i);
end generate;
end generate;
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg is
generic (width : integer := 8;
latency : integer := 1);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end synth_reg;
architecture structural of synth_reg is
component srl17e
generic (width : integer:=16;
latency : integer :=8);
port (clk : in std_logic;
ce : in std_logic;
d : in std_logic_vector(width-1 downto 0);
q : out std_logic_vector(width-1 downto 0));
end component;
function calc_num_srl17es (latency : integer)
return integer
is
variable remaining_latency : integer;
variable result : integer;
begin
result := latency / 17;
remaining_latency := latency - (result * 17);
if (remaining_latency /= 0) then
result := result + 1;
end if;
return result;
end;
constant complete_num_srl17es : integer := latency / 17;
constant num_srl17es : integer := calc_num_srl17es(latency);
constant remaining_latency : integer := latency - (complete_num_srl17es * 17);
type register_array is array (num_srl17es downto 0) of
std_logic_vector(width-1 downto 0);
signal z : register_array;
begin
z(0) <= i;
complete_ones : if complete_num_srl17es > 0 generate
srl17e_array: for i in 0 to complete_num_srl17es-1 generate
delay_comp : srl17e
generic map (width => width,
latency => 17)
port map (clk => clk,
ce => ce,
d => z(i),
q => z(i+1));
end generate;
end generate;
partial_one : if remaining_latency > 0 generate
last_srl17e : srl17e
generic map (width => width,
latency => remaining_latency)
port map (clk => clk,
ce => ce,
d => z(num_srl17es-1),
q => z(num_srl17es));
end generate;
o <= z(num_srl17es);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg_reg is
generic (width : integer := 8;
latency : integer := 1);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end synth_reg_reg;
architecture behav of synth_reg_reg is
type reg_array_type is array (latency-1 downto 0) of std_logic_vector(width -1 downto 0);
signal reg_bank : reg_array_type := (others => (others => '0'));
signal reg_bank_in : reg_array_type := (others => (others => '0'));
attribute syn_allow_retiming : boolean;
attribute syn_srlstyle : string;
attribute syn_allow_retiming of reg_bank : signal is true;
attribute syn_allow_retiming of reg_bank_in : signal is true;
attribute syn_srlstyle of reg_bank : signal is "registers";
attribute syn_srlstyle of reg_bank_in : signal is "registers";
begin
latency_eq_0: if latency = 0 generate
o <= i;
end generate latency_eq_0;
latency_gt_0: if latency >= 1 generate
o <= reg_bank(latency-1);
reg_bank_in(0) <= i;
loop_gen: for idx in latency-2 downto 0 generate
reg_bank_in(idx+1) <= reg_bank(idx);
end generate loop_gen;
sync_loop: for sync_idx in latency-1 downto 0 generate
sync_proc: process (clk)
begin
if clk'event and clk = '1' then
if ce = '1' then
reg_bank(sync_idx) <= reg_bank_in(sync_idx);
end if;
end if;
end process sync_proc;
end generate sync_loop;
end generate latency_gt_0;
end behav;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity single_reg_w_init is
generic (
width: integer := 8;
init_index: integer := 0;
init_value: bit_vector := b"0000"
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end single_reg_w_init;
architecture structural of single_reg_w_init is
function build_init_const(width: integer;
init_index: integer;
init_value: bit_vector)
return std_logic_vector
is
variable result: std_logic_vector(width - 1 downto 0);
begin
if init_index = 0 then
result := (others => '0');
elsif init_index = 1 then
result := (others => '0');
result(0) := '1';
else
result := to_stdlogicvector(init_value);
end if;
return result;
end;
component fdre
port (
q: out std_ulogic;
d: in std_ulogic;
c: in std_ulogic;
ce: in std_ulogic;
r: in std_ulogic
);
end component;
attribute syn_black_box of fdre: component is true;
attribute fpga_dont_touch of fdre: component is "true";
component fdse
port (
q: out std_ulogic;
d: in std_ulogic;
c: in std_ulogic;
ce: in std_ulogic;
s: in std_ulogic
);
end component;
attribute syn_black_box of fdse: component is true;
attribute fpga_dont_touch of fdse: component is "true";
constant init_const: std_logic_vector(width - 1 downto 0)
:= build_init_const(width, init_index, init_value);
begin
fd_prim_array: for index in 0 to width - 1 generate
bit_is_0: if (init_const(index) = '0') generate
fdre_comp: fdre
port map (
c => clk,
d => i(index),
q => o(index),
ce => ce,
r => clr
);
end generate;
bit_is_1: if (init_const(index) = '1') generate
fdse_comp: fdse
port map (
c => clk,
d => i(index),
q => o(index),
ce => ce,
s => clr
);
end generate;
end generate;
end architecture structural;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg_w_init is
generic (
width: integer := 8;
init_index: integer := 0;
init_value: bit_vector := b"0000";
latency: integer := 1
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end synth_reg_w_init;
architecture structural of synth_reg_w_init is
component single_reg_w_init
generic (
width: integer := 8;
init_index: integer := 0;
init_value: bit_vector := b"0000"
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
signal dly_i: std_logic_vector((latency + 1) * width - 1 downto 0);
signal dly_clr: std_logic;
begin
latency_eq_0: if (latency = 0) generate
o <= i;
end generate;
latency_gt_0: if (latency >= 1) generate
dly_i((latency + 1) * width - 1 downto latency * width) <= i
after 200 ps;
dly_clr <= clr after 200 ps;
fd_array: for index in latency downto 1 generate
reg_comp: single_reg_w_init
generic map (
width => width,
init_index => init_index,
init_value => init_value
)
port map (
clk => clk,
i => dly_i((index + 1) * width - 1 downto index * width),
o => dly_i(index * width - 1 downto (index - 1) * width),
ce => ce,
clr => dly_clr
);
end generate;
o <= dly_i(width - 1 downto 0);
end generate;
end structural;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity convert_func_call is
generic (
din_width : integer := 16;
din_bin_pt : integer := 4;
din_arith : integer := xlUnsigned;
dout_width : integer := 8;
dout_bin_pt : integer := 2;
dout_arith : integer := xlUnsigned;
quantization : integer := xlTruncate;
overflow : integer := xlWrap);
port (
din : in std_logic_vector (din_width-1 downto 0);
result : out std_logic_vector (dout_width-1 downto 0));
end convert_func_call;
architecture behavior of convert_func_call is
begin
result <= convert_type(din, din_width, din_bin_pt, din_arith,
dout_width, dout_bin_pt, dout_arith,
quantization, overflow);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xlconvert is
generic (
din_width : integer := 16;
din_bin_pt : integer := 4;
din_arith : integer := xlUnsigned;
dout_width : integer := 8;
dout_bin_pt : integer := 2;
dout_arith : integer := xlUnsigned;
bool_conversion : integer :=0;
latency : integer := 0;
quantization : integer := xlTruncate;
overflow : integer := xlWrap);
port (
din : in std_logic_vector (din_width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
dout : out std_logic_vector (dout_width-1 downto 0));
end xlconvert;
architecture behavior of xlconvert is
component synth_reg
generic (width : integer;
latency : integer);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end component;
component convert_func_call
generic (
din_width : integer := 16;
din_bin_pt : integer := 4;
din_arith : integer := xlUnsigned;
dout_width : integer := 8;
dout_bin_pt : integer := 2;
dout_arith : integer := xlUnsigned;
quantization : integer := xlTruncate;
overflow : integer := xlWrap);
port (
din : in std_logic_vector (din_width-1 downto 0);
result : out std_logic_vector (dout_width-1 downto 0));
end component;
-- synopsys translate_off
signal real_din, real_dout : real;
-- synopsys translate_on
signal result : std_logic_vector(dout_width-1 downto 0);
begin
-- synopsys translate_off
-- synopsys translate_on
bool_conversion_generate : if (bool_conversion = 1)
generate
result <= din;
end generate;
std_conversion_generate : if (bool_conversion = 0)
generate
convert : convert_func_call
generic map (
din_width => din_width,
din_bin_pt => din_bin_pt,
din_arith => din_arith,
dout_width => dout_width,
dout_bin_pt => dout_bin_pt,
dout_arith => dout_arith,
quantization => quantization,
overflow => overflow)
port map (
din => din,
result => result);
end generate;
latency_test : if (latency > 0)
generate
reg : synth_reg
generic map ( width => dout_width,
latency => latency)
port map (i => result,
ce => ce,
clr => clr,
clk => clk,
o => dout);
end generate;
latency0 : if (latency = 0)
generate
dout <= result;
end generate latency0;
end behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library XilinxCoreLib;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xlcounter_free is
generic (
core_name0: string := "";
op_width: integer := 5;
op_arith: integer := xlSigned
);
port (
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
op: out std_logic_vector(op_width - 1 downto 0);
up: in std_logic_vector(0 downto 0) := (others => '0');
load: in std_logic_vector(0 downto 0) := (others => '0');
din: in std_logic_vector(op_width - 1 downto 0) := (others => '0');
en: in std_logic_vector(0 downto 0);
rst: in std_logic_vector(0 downto 0)
);
end xlcounter_free ;
architecture behavior of xlcounter_free is
component binary_counter_virtex2p_7_0_950e4ab582797264
port (
clk: in std_logic;
ce: in std_logic;
sinit: in std_logic;
q: out std_logic_vector(op_width - 1 downto 0)
);
end component;
attribute syn_black_box of binary_counter_virtex2p_7_0_950e4ab582797264:
component is true;
attribute fpga_dont_touch of binary_counter_virtex2p_7_0_950e4ab582797264:
component is "true";
attribute box_type of binary_counter_virtex2p_7_0_950e4ab582797264:
component is "black_box";
component binary_counter_virtex2p_7_0_b0a257f5389d649a
port (
clk: in std_logic;
ce: in std_logic;
sinit: in std_logic;
q: out std_logic_vector(op_width - 1 downto 0)
);
end component;
attribute syn_black_box of binary_counter_virtex2p_7_0_b0a257f5389d649a:
component is true;
attribute fpga_dont_touch of binary_counter_virtex2p_7_0_b0a257f5389d649a:
component is "true";
attribute box_type of binary_counter_virtex2p_7_0_b0a257f5389d649a:
component is "black_box";
component binary_counter_virtex2p_7_0_b511f9871581ee23
port (
clk: in std_logic;
ce: in std_logic;
sinit: in std_logic;
load: in std_logic;
l: in std_logic_vector(op_width - 1 downto 0);
q: out std_logic_vector(op_width - 1 downto 0)
);
end component;
attribute syn_black_box of binary_counter_virtex2p_7_0_b511f9871581ee23:
component is true;
attribute fpga_dont_touch of binary_counter_virtex2p_7_0_b511f9871581ee23:
component is "true";
attribute box_type of binary_counter_virtex2p_7_0_b511f9871581ee23:
component is "black_box";
component binary_counter_virtex2p_7_0_a22528b4c55dc1cd
port (
clk: in std_logic;
ce: in std_logic;
sinit: in std_logic;
q: out std_logic_vector(op_width - 1 downto 0)
);
end component;
attribute syn_black_box of binary_counter_virtex2p_7_0_a22528b4c55dc1cd:
component is true;
attribute fpga_dont_touch of binary_counter_virtex2p_7_0_a22528b4c55dc1cd:
component is "true";
attribute box_type of binary_counter_virtex2p_7_0_a22528b4c55dc1cd:
component is "black_box";
component binary_counter_virtex2p_7_0_77cea312f82499f0
port (
clk: in std_logic;
ce: in std_logic;
sinit: in std_logic;
load: in std_logic;
l: in std_logic_vector(op_width - 1 downto 0);
q: out std_logic_vector(op_width - 1 downto 0)
);
end component;
attribute syn_black_box of binary_counter_virtex2p_7_0_77cea312f82499f0:
component is true;
attribute fpga_dont_touch of binary_counter_virtex2p_7_0_77cea312f82499f0:
component is "true";
attribute box_type of binary_counter_virtex2p_7_0_77cea312f82499f0:
component is "black_box";
-- synopsys translate_off
constant zeroVec: std_logic_vector(op_width - 1 downto 0) := (others => '0');
constant oneVec: std_logic_vector(op_width - 1 downto 0) := (others => '1');
constant zeroStr: string(1 to op_width) :=
std_logic_vector_to_bin_string(zeroVec);
constant oneStr: string(1 to op_width) :=
std_logic_vector_to_bin_string(oneVec);
-- synopsys translate_on
signal core_sinit: std_logic;
signal core_ce: std_logic;
signal op_net: std_logic_vector(op_width - 1 downto 0);
begin
core_ce <= ce and en(0);
core_sinit <= (clr or rst(0)) and ce;
op <= op_net;
comp0: if ((core_name0 = "binary_counter_virtex2p_7_0_950e4ab582797264")) generate
core_instance0: binary_counter_virtex2p_7_0_950e4ab582797264
port map (
clk => clk,
ce => core_ce,
sinit => core_sinit,
q => op_net
);
end generate;
comp1: if ((core_name0 = "binary_counter_virtex2p_7_0_b0a257f5389d649a")) generate
core_instance1: binary_counter_virtex2p_7_0_b0a257f5389d649a
port map (
clk => clk,
ce => core_ce,
sinit => core_sinit,
q => op_net
);
end generate;
comp2: if ((core_name0 = "binary_counter_virtex2p_7_0_b511f9871581ee23")) generate
core_instance2: binary_counter_virtex2p_7_0_b511f9871581ee23
port map (
clk => clk,
ce => core_ce,
sinit => core_sinit,
load => load(0),
l => din,
q => op_net
);
end generate;
comp3: if ((core_name0 = "binary_counter_virtex2p_7_0_a22528b4c55dc1cd")) generate
core_instance3: binary_counter_virtex2p_7_0_a22528b4c55dc1cd
port map (
clk => clk,
ce => core_ce,
sinit => core_sinit,
q => op_net
);
end generate;
comp4: if ((core_name0 = "binary_counter_virtex2p_7_0_77cea312f82499f0")) generate
core_instance4: binary_counter_virtex2p_7_0_77cea312f82499f0
port map (
clk => clk,
ce => core_ce,
sinit => core_sinit,
load => load(0),
l => din,
q => op_net
);
end generate;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity inverter_e2b989a05e is
port (
ip : in std_logic_vector((1 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end inverter_e2b989a05e;
architecture behavior of inverter_e2b989a05e is
signal ip_1_26: unsigned((1 - 1) downto 0);
type array_type_op_mem_22_20 is array (0 to (1 - 1)) of unsigned((1 - 1) downto 0);
signal op_mem_22_20: array_type_op_mem_22_20 := (
0 => "0");
signal op_mem_22_20_front_din: unsigned((1 - 1) downto 0);
signal op_mem_22_20_back: unsigned((1 - 1) downto 0);
signal op_mem_22_20_push_front_pop_back_en: std_logic;
signal internal_ip_12_1_bitnot: unsigned((1 - 1) downto 0);
begin
ip_1_26 <= std_logic_vector_to_unsigned(ip);
op_mem_22_20_back <= op_mem_22_20(0);
proc_op_mem_22_20: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_22_20_push_front_pop_back_en = '1')) then
op_mem_22_20(0) <= op_mem_22_20_front_din;
end if;
end if;
end process proc_op_mem_22_20;
internal_ip_12_1_bitnot <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(ip_1_26));
op_mem_22_20_push_front_pop_back_en <= '0';
op <= unsigned_to_std_logic_vector(internal_ip_12_1_bitnot);
end behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library XilinxCoreLib;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.conv_pkg.all;
entity xlmult_v9_0 is
generic (
core_name0: string := "";
a_width: integer := 4;
a_bin_pt: integer := 2;
a_arith: integer := xlSigned;
b_width: integer := 4;
b_bin_pt: integer := 1;
b_arith: integer := xlSigned;
p_width: integer := 8;
p_bin_pt: integer := 2;
p_arith: integer := xlSigned;
rst_width: integer := 1;
rst_bin_pt: integer := 0;
rst_arith: integer := xlUnsigned;
en_width: integer := 1;
en_bin_pt: integer := 0;
en_arith: integer := xlUnsigned;
quantization: integer := xlTruncate;
overflow: integer := xlWrap;
extra_registers: integer := 0;
c_a_width: integer := 7;
c_b_width: integer := 7;
c_type: integer := 0;
c_a_type: integer := 0;
c_b_type: integer := 0;
c_pipelined: integer := 1;
c_baat: integer := 4;
multsign: integer := xlSigned;
c_output_width: integer := 16
);
port (
a: in std_logic_vector(a_width - 1 downto 0);
b: in std_logic_vector(b_width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
core_ce: in std_logic := '0';
core_clr: in std_logic := '0';
core_clk: in std_logic := '0';
rst: in std_logic_vector(rst_width - 1 downto 0);
en: in std_logic_vector(en_width - 1 downto 0);
p: out std_logic_vector(p_width - 1 downto 0)
);
end xlmult_v9_0 ;
architecture behavior of xlmult_v9_0 is
component synth_reg
generic (
width: integer := 16;
latency: integer := 5
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
component multiplier_virtex2p_10_1_817edd563258bb47
port (
b: in std_logic_vector(c_b_width - 1 downto 0);
p: out std_logic_vector(c_output_width - 1 downto 0);
clk: in std_logic;
ce: in std_logic;
sclr: in std_logic;
a: in std_logic_vector(c_a_width - 1 downto 0)
);
end component;
attribute syn_black_box of multiplier_virtex2p_10_1_817edd563258bb47:
component is true;
attribute fpga_dont_touch of multiplier_virtex2p_10_1_817edd563258bb47:
component is "true";
attribute box_type of multiplier_virtex2p_10_1_817edd563258bb47:
component is "black_box";
signal tmp_a: std_logic_vector(c_a_width - 1 downto 0);
signal conv_a: std_logic_vector(c_a_width - 1 downto 0);
signal tmp_b: std_logic_vector(c_b_width - 1 downto 0);
signal conv_b: std_logic_vector(c_b_width - 1 downto 0);
signal tmp_p: std_logic_vector(c_output_width - 1 downto 0);
signal conv_p: std_logic_vector(p_width - 1 downto 0);
-- synopsys translate_off
signal real_a, real_b, real_p: real;
-- synopsys translate_on
signal rfd: std_logic;
signal rdy: std_logic;
signal nd: std_logic;
signal internal_ce: std_logic;
signal internal_clr: std_logic;
signal internal_core_ce: std_logic;
begin
-- synopsys translate_off
-- synopsys translate_on
internal_ce <= ce and en(0);
internal_core_ce <= core_ce and en(0);
internal_clr <= (clr or rst(0)) and ce;
nd <= internal_ce;
input_process: process (a,b)
begin
tmp_a <= zero_ext(a, c_a_width);
tmp_b <= zero_ext(b, c_b_width);
end process;
output_process: process (tmp_p)
begin
conv_p <= convert_type(tmp_p, c_output_width, a_bin_pt+b_bin_pt, multsign,
p_width, p_bin_pt, p_arith, quantization, overflow);
end process;
comp0: if ((core_name0 = "multiplier_virtex2p_10_1_817edd563258bb47")) generate
core_instance0: multiplier_virtex2p_10_1_817edd563258bb47
port map (
a => tmp_a,
clk => clk,
ce => internal_ce,
sclr => internal_clr,
p => tmp_p,
b => tmp_b
);
end generate;
latency_gt_0: if (extra_registers > 0) generate
reg: synth_reg
generic map (
width => p_width,
latency => extra_registers
)
port map (
i => conv_p,
ce => internal_ce,
clr => internal_clr,
clk => clk,
o => p
);
end generate;
latency_eq_0: if (extra_registers = 0) generate
p <= conv_p;
end generate;
end architecture behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xlregister is
generic (d_width : integer := 5;
init_value : bit_vector := b"00");
port (d : in std_logic_vector (d_width-1 downto 0);
rst : in std_logic_vector(0 downto 0) := "0";
en : in std_logic_vector(0 downto 0) := "1";
ce : in std_logic;
clk : in std_logic;
q : out std_logic_vector (d_width-1 downto 0));
end xlregister;
architecture behavior of xlregister is
component synth_reg_w_init
generic (width : integer;
init_index : integer;
init_value : bit_vector;
latency : integer);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end component;
-- synopsys translate_off
signal real_d, real_q : real;
-- synopsys translate_on
signal internal_clr : std_logic;
signal internal_ce : std_logic;
begin
internal_clr <= rst(0) and ce;
internal_ce <= en(0) and ce;
synth_reg_inst : synth_reg_w_init
generic map (width => d_width,
init_index => 2,
init_value => init_value,
latency => 1)
port map (i => d,
ce => internal_ce,
clr => internal_clr,
clk => clk,
o => q);
end architecture behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity relational_4e76b03051 is
port (
a : in std_logic_vector((18 - 1) downto 0);
b : in std_logic_vector((18 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end relational_4e76b03051;
architecture behavior of relational_4e76b03051 is
signal a_1_31: unsigned((18 - 1) downto 0);
signal b_1_34: unsigned((18 - 1) downto 0);
type array_type_op_mem_32_22 is array (0 to (1 - 1)) of boolean;
signal op_mem_32_22: array_type_op_mem_32_22 := (
0 => false);
signal op_mem_32_22_front_din: boolean;
signal op_mem_32_22_back: boolean;
signal op_mem_32_22_push_front_pop_back_en: std_logic;
signal result_12_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_unsigned(a);
b_1_34 <= std_logic_vector_to_unsigned(b);
op_mem_32_22_back <= op_mem_32_22(0);
proc_op_mem_32_22: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_32_22_push_front_pop_back_en = '1')) then
op_mem_32_22(0) <= op_mem_32_22_front_din;
end if;
end if;
end process proc_op_mem_32_22;
result_12_3_rel <= a_1_31 = b_1_34;
op_mem_32_22_front_din <= result_12_3_rel;
op_mem_32_22_push_front_pop_back_en <= '1';
op <= boolean_to_vector(op_mem_32_22_back);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity relational_1433264a0c is
port (
a : in std_logic_vector((18 - 1) downto 0);
b : in std_logic_vector((18 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end relational_1433264a0c;
architecture behavior of relational_1433264a0c is
signal a_1_31: unsigned((18 - 1) downto 0);
signal b_1_34: unsigned((18 - 1) downto 0);
type array_type_op_mem_32_22 is array (0 to (1 - 1)) of boolean;
signal op_mem_32_22: array_type_op_mem_32_22 := (
0 => false);
signal op_mem_32_22_front_din: boolean;
signal op_mem_32_22_back: boolean;
signal op_mem_32_22_push_front_pop_back_en: std_logic;
signal result_22_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_unsigned(a);
b_1_34 <= std_logic_vector_to_unsigned(b);
op_mem_32_22_back <= op_mem_32_22(0);
proc_op_mem_32_22: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_32_22_push_front_pop_back_en = '1')) then
op_mem_32_22(0) <= op_mem_32_22_front_din;
end if;
end if;
end process proc_op_mem_32_22;
result_22_3_rel <= a_1_31 >= b_1_34;
op_mem_32_22_front_din <= result_22_3_rel;
op_mem_32_22_push_front_pop_back_en <= '1';
op <= boolean_to_vector(op_mem_32_22_back);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_963ed6358a is
port (
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_963ed6358a;
architecture behavior of constant_963ed6358a is
begin
op <= "0";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mcode_block_8231ed31e4 is
port (
plbrst : in std_logic_vector((1 - 1) downto 0);
plbabus : in std_logic_vector((32 - 1) downto 0);
plbpavalid : in std_logic_vector((1 - 1) downto 0);
plbrnw : in std_logic_vector((1 - 1) downto 0);
plbwrdbus : in std_logic_vector((32 - 1) downto 0);
rddata : in std_logic_vector((32 - 1) downto 0);
addrpref : in std_logic_vector((15 - 1) downto 0);
wrdbusreg : out std_logic_vector((32 - 1) downto 0);
addrack : out std_logic_vector((1 - 1) downto 0);
rdcomp : out std_logic_vector((1 - 1) downto 0);
wrdack : out std_logic_vector((1 - 1) downto 0);
bankaddr : out std_logic_vector((2 - 1) downto 0);
rnwreg : out std_logic_vector((1 - 1) downto 0);
rddack : out std_logic_vector((1 - 1) downto 0);
rddbus : out std_logic_vector((32 - 1) downto 0);
linearaddr : out std_logic_vector((13 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mcode_block_8231ed31e4;
architecture behavior of mcode_block_8231ed31e4 is
signal plbrst_2_20: unsigned((1 - 1) downto 0);
signal plbabus_2_28: unsigned((32 - 1) downto 0);
signal plbpavalid_2_37: unsigned((1 - 1) downto 0);
signal plbrnw_2_49: unsigned((1 - 1) downto 0);
signal plbwrdbus_2_57: unsigned((32 - 1) downto 0);
signal rddata_2_68: unsigned((32 - 1) downto 0);
signal addrpref_2_76: unsigned((15 - 1) downto 0);
signal plbrstreg_13_24_next: boolean;
signal plbrstreg_13_24: boolean := false;
signal plbabusreg_14_25_next: unsigned((32 - 1) downto 0);
signal plbabusreg_14_25: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal plbpavalidreg_15_28_next: boolean;
signal plbpavalidreg_15_28: boolean := false;
signal plbrnwreg_16_24_next: unsigned((1 - 1) downto 0);
signal plbrnwreg_16_24: unsigned((1 - 1) downto 0) := "0";
signal plbwrdbusreg_17_27_next: unsigned((32 - 1) downto 0);
signal plbwrdbusreg_17_27: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal avalidreg_29_23_next: boolean;
signal avalidreg_29_23: boolean := false;
signal ps1reg_40_20_next: boolean;
signal ps1reg_40_20: boolean := false;
signal psreg_48_19_next: boolean;
signal psreg_48_19: boolean := false;
type array_type_rdcompdelay_59_25 is array (0 to (3 - 1)) of unsigned((1 - 1) downto 0);
signal rdcompdelay_59_25: array_type_rdcompdelay_59_25 := (
"0",
"0",
"0");
signal rdcompdelay_59_25_front_din: unsigned((1 - 1) downto 0);
signal rdcompdelay_59_25_back: unsigned((1 - 1) downto 0);
signal rdcompdelay_59_25_push_front_pop_back_en: std_logic;
signal rdcompreg_63_23_next: unsigned((1 - 1) downto 0);
signal rdcompreg_63_23: unsigned((1 - 1) downto 0) := "0";
signal rddackreg_67_23_next: unsigned((1 - 1) downto 0);
signal rddackreg_67_23: unsigned((1 - 1) downto 0) := "0";
signal wrdackreg_71_23_next: unsigned((1 - 1) downto 0);
signal wrdackreg_71_23: unsigned((1 - 1) downto 0) := "0";
signal rddbusreg_85_23_next: unsigned((32 - 1) downto 0);
signal rddbusreg_85_23: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal bankaddr_21_1_slice: unsigned((2 - 1) downto 0);
signal linearaddr_22_1_slice: unsigned((13 - 1) downto 0);
signal addrpref_in_33_1_slice: unsigned((15 - 1) downto 0);
signal rel_34_4: boolean;
signal ps1_join_34_1: boolean;
signal ps_43_1_bit: boolean;
signal bitnot_50_49: boolean;
signal bitnot_50_73: boolean;
signal bit_50_49: boolean;
signal addrack_50_1_convert: unsigned((1 - 1) downto 0);
signal bit_56_43: unsigned((1 - 1) downto 0);
signal bitnot_73_35: unsigned((1 - 1) downto 0);
signal wrdackreg_73_1_bit: unsigned((1 - 1) downto 0);
signal rdsel_77_1_bit: unsigned((1 - 1) downto 0);
signal rel_79_4: boolean;
signal rddbus1_join_79_1: unsigned((32 - 1) downto 0);
signal plbwrdbusreg_98_1_slice: unsigned((32 - 1) downto 0);
signal plbrstreg_13_24_next_x_000000: boolean;
signal plbpavalidreg_15_28_next_x_000000: boolean;
begin
plbrst_2_20 <= std_logic_vector_to_unsigned(plbrst);
plbabus_2_28 <= std_logic_vector_to_unsigned(plbabus);
plbpavalid_2_37 <= std_logic_vector_to_unsigned(plbpavalid);
plbrnw_2_49 <= std_logic_vector_to_unsigned(plbrnw);
plbwrdbus_2_57 <= std_logic_vector_to_unsigned(plbwrdbus);
rddata_2_68 <= std_logic_vector_to_unsigned(rddata);
addrpref_2_76 <= std_logic_vector_to_unsigned(addrpref);
proc_plbrstreg_13_24: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbrstreg_13_24 <= plbrstreg_13_24_next;
end if;
end if;
end process proc_plbrstreg_13_24;
proc_plbabusreg_14_25: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbabusreg_14_25 <= plbabusreg_14_25_next;
end if;
end if;
end process proc_plbabusreg_14_25;
proc_plbpavalidreg_15_28: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbpavalidreg_15_28 <= plbpavalidreg_15_28_next;
end if;
end if;
end process proc_plbpavalidreg_15_28;
proc_plbrnwreg_16_24: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbrnwreg_16_24 <= plbrnwreg_16_24_next;
end if;
end if;
end process proc_plbrnwreg_16_24;
proc_plbwrdbusreg_17_27: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbwrdbusreg_17_27 <= plbwrdbusreg_17_27_next;
end if;
end if;
end process proc_plbwrdbusreg_17_27;
proc_avalidreg_29_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
avalidreg_29_23 <= avalidreg_29_23_next;
end if;
end if;
end process proc_avalidreg_29_23;
proc_ps1reg_40_20: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
ps1reg_40_20 <= ps1reg_40_20_next;
end if;
end if;
end process proc_ps1reg_40_20;
proc_psreg_48_19: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
psreg_48_19 <= psreg_48_19_next;
end if;
end if;
end process proc_psreg_48_19;
rdcompdelay_59_25_back <= rdcompdelay_59_25(2);
proc_rdcompdelay_59_25: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (rdcompdelay_59_25_push_front_pop_back_en = '1')) then
for i in 2 downto 1 loop
rdcompdelay_59_25(i) <= rdcompdelay_59_25(i-1);
end loop;
rdcompdelay_59_25(0) <= rdcompdelay_59_25_front_din;
end if;
end if;
end process proc_rdcompdelay_59_25;
proc_rdcompreg_63_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
rdcompreg_63_23 <= rdcompreg_63_23_next;
end if;
end if;
end process proc_rdcompreg_63_23;
proc_rddackreg_67_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
rddackreg_67_23 <= rddackreg_67_23_next;
end if;
end if;
end process proc_rddackreg_67_23;
proc_wrdackreg_71_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
wrdackreg_71_23 <= wrdackreg_71_23_next;
end if;
end if;
end process proc_wrdackreg_71_23;
proc_rddbusreg_85_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
rddbusreg_85_23 <= rddbusreg_85_23_next;
end if;
end if;
end process proc_rddbusreg_85_23;
bankaddr_21_1_slice <= u2u_slice(plbabusreg_14_25, 16, 15);
linearaddr_22_1_slice <= u2u_slice(plbabusreg_14_25, 14, 2);
addrpref_in_33_1_slice <= u2u_slice(plbabusreg_14_25, 31, 17);
rel_34_4 <= addrpref_in_33_1_slice = addrpref_2_76;
proc_if_34_1: process (rel_34_4)
is
begin
if rel_34_4 then
ps1_join_34_1 <= true;
else
ps1_join_34_1 <= false;
end if;
end process proc_if_34_1;
ps_43_1_bit <= ((boolean_to_vector(ps1_join_34_1) and boolean_to_vector(plbpavalidreg_15_28)) = "1");
bitnot_50_49 <= ((not boolean_to_vector(plbrstreg_13_24)) = "1");
bitnot_50_73 <= ((not boolean_to_vector(psreg_48_19)) = "1");
bit_50_49 <= ((boolean_to_vector(bitnot_50_49) and boolean_to_vector(ps_43_1_bit) and boolean_to_vector(bitnot_50_73)) = "1");
addrack_50_1_convert <= u2u_cast(std_logic_vector_to_unsigned(boolean_to_vector(bit_50_49)), 0, 1, 0);
bit_56_43 <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_50_1_convert) and unsigned_to_std_logic_vector(plbrnwreg_16_24));
bitnot_73_35 <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(plbrnwreg_16_24));
wrdackreg_73_1_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_50_1_convert) and unsigned_to_std_logic_vector(bitnot_73_35));
rdsel_77_1_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(rdcompdelay_59_25_back) or unsigned_to_std_logic_vector(rdcompreg_63_23));
rel_79_4 <= rdsel_77_1_bit = std_logic_vector_to_unsigned("1");
proc_if_79_1: process (rddata_2_68, rel_79_4)
is
begin
if rel_79_4 then
rddbus1_join_79_1 <= rddata_2_68;
else
rddbus1_join_79_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000");
end if;
end process proc_if_79_1;
plbwrdbusreg_98_1_slice <= u2u_slice(plbwrdbus_2_57, 31, 0);
plbrstreg_13_24_next_x_000000 <= (plbrst_2_20 /= "0");
plbrstreg_13_24_next <= plbrstreg_13_24_next_x_000000;
plbabusreg_14_25_next <= plbabus_2_28;
plbpavalidreg_15_28_next_x_000000 <= (plbpavalid_2_37 /= "0");
plbpavalidreg_15_28_next <= plbpavalidreg_15_28_next_x_000000;
plbrnwreg_16_24_next <= plbrnw_2_49;
plbwrdbusreg_17_27_next <= plbwrdbusreg_98_1_slice;
avalidreg_29_23_next <= plbpavalidreg_15_28;
ps1reg_40_20_next <= ps1_join_34_1;
psreg_48_19_next <= ps_43_1_bit;
rdcompdelay_59_25_front_din <= bit_56_43;
rdcompdelay_59_25_push_front_pop_back_en <= '1';
rdcompreg_63_23_next <= rdcompdelay_59_25_back;
rddackreg_67_23_next <= rdcompreg_63_23;
wrdackreg_71_23_next <= wrdackreg_73_1_bit;
rddbusreg_85_23_next <= rddbus1_join_79_1;
wrdbusreg <= unsigned_to_std_logic_vector(plbwrdbusreg_17_27);
addrack <= unsigned_to_std_logic_vector(addrack_50_1_convert);
rdcomp <= unsigned_to_std_logic_vector(rdcompreg_63_23);
wrdack <= unsigned_to_std_logic_vector(wrdackreg_71_23);
bankaddr <= unsigned_to_std_logic_vector(bankaddr_21_1_slice);
rnwreg <= unsigned_to_std_logic_vector(plbrnwreg_16_24);
rddack <= unsigned_to_std_logic_vector(rddackreg_67_23);
rddbus <= unsigned_to_std_logic_vector(rddbusreg_85_23);
linearaddr <= unsigned_to_std_logic_vector(linearaddr_22_1_slice);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mcode_block_66f25059c9 is
port (
wrdbus : in std_logic_vector((32 - 1) downto 0);
bankaddr : in std_logic_vector((2 - 1) downto 0);
linearaddr : in std_logic_vector((13 - 1) downto 0);
rnwreg : in std_logic_vector((1 - 1) downto 0);
addrack : in std_logic_vector((1 - 1) downto 0);
sm_buttons_big : in std_logic_vector((2 - 1) downto 0);
sm_buttons_small : in std_logic_vector((6 - 1) downto 0);
sm_dip_switch : in std_logic_vector((4 - 1) downto 0);
sm_trackball : in std_logic_vector((5 - 1) downto 0);
sm_buzzer_dutycycle : in std_logic_vector((18 - 1) downto 0);
sm_buzzer_enable : in std_logic_vector((1 - 1) downto 0);
sm_buzzer_period : in std_logic_vector((18 - 1) downto 0);
sm_lcd_backgroundcolor : in std_logic_vector((9 - 1) downto 0);
sm_lcd_characteroffset : in std_logic_vector((4 - 1) downto 0);
sm_lcd_charactersselect : in std_logic_vector((3 - 1) downto 0);
sm_lcd_colset : in std_logic_vector((9 - 1) downto 0);
sm_lcd_configlocation : in std_logic_vector((2 - 1) downto 0);
sm_lcd_dividerselect : in std_logic_vector((1 - 1) downto 0);
sm_lcd_firstend : in std_logic_vector((9 - 1) downto 0);
sm_lcd_firststart : in std_logic_vector((9 - 1) downto 0);
sm_lcd_lineoffset : in std_logic_vector((4 - 1) downto 0);
sm_lcd_ramwrite : in std_logic_vector((9 - 1) downto 0);
sm_lcd_reset : in std_logic_vector((1 - 1) downto 0);
sm_lcd_resetlcd : in std_logic_vector((1 - 1) downto 0);
sm_lcd_rowset : in std_logic_vector((9 - 1) downto 0);
sm_lcd_secondend : in std_logic_vector((9 - 1) downto 0);
sm_lcd_secondstart : in std_logic_vector((9 - 1) downto 0);
sm_lcd_send : in std_logic_vector((1 - 1) downto 0);
sm_lcd_totalcmdtransfer : in std_logic_vector((8 - 1) downto 0);
sm_leds : in std_logic_vector((8 - 1) downto 0);
sm_lcd_charactermap : in std_logic_vector((32 - 1) downto 0);
sm_lcd_characters : in std_logic_vector((32 - 1) downto 0);
sm_lcd_commands : in std_logic_vector((32 - 1) downto 0);
read_bank_out : out std_logic_vector((32 - 1) downto 0);
sm_buzzer_dutycycle_din : out std_logic_vector((18 - 1) downto 0);
sm_buzzer_dutycycle_en : out std_logic_vector((1 - 1) downto 0);
sm_buzzer_enable_din : out std_logic_vector((1 - 1) downto 0);
sm_buzzer_enable_en : out std_logic_vector((1 - 1) downto 0);
sm_buzzer_period_din : out std_logic_vector((18 - 1) downto 0);
sm_buzzer_period_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_backgroundcolor_din : out std_logic_vector((9 - 1) downto 0);
sm_lcd_backgroundcolor_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_characteroffset_din : out std_logic_vector((4 - 1) downto 0);
sm_lcd_characteroffset_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_charactersselect_din : out std_logic_vector((3 - 1) downto 0);
sm_lcd_charactersselect_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_colset_din : out std_logic_vector((9 - 1) downto 0);
sm_lcd_colset_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_configlocation_din : out std_logic_vector((2 - 1) downto 0);
sm_lcd_configlocation_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_dividerselect_din : out std_logic_vector((1 - 1) downto 0);
sm_lcd_dividerselect_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_firstend_din : out std_logic_vector((9 - 1) downto 0);
sm_lcd_firstend_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_firststart_din : out std_logic_vector((9 - 1) downto 0);
sm_lcd_firststart_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_lineoffset_din : out std_logic_vector((4 - 1) downto 0);
sm_lcd_lineoffset_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_ramwrite_din : out std_logic_vector((9 - 1) downto 0);
sm_lcd_ramwrite_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_reset_din : out std_logic_vector((1 - 1) downto 0);
sm_lcd_reset_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_resetlcd_din : out std_logic_vector((1 - 1) downto 0);
sm_lcd_resetlcd_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_rowset_din : out std_logic_vector((9 - 1) downto 0);
sm_lcd_rowset_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_secondend_din : out std_logic_vector((9 - 1) downto 0);
sm_lcd_secondend_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_secondstart_din : out std_logic_vector((9 - 1) downto 0);
sm_lcd_secondstart_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_send_din : out std_logic_vector((1 - 1) downto 0);
sm_lcd_send_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_totalcmdtransfer_din : out std_logic_vector((8 - 1) downto 0);
sm_lcd_totalcmdtransfer_en : out std_logic_vector((1 - 1) downto 0);
sm_leds_din : out std_logic_vector((8 - 1) downto 0);
sm_leds_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_charactermap_addr : out std_logic_vector((12 - 1) downto 0);
sm_lcd_charactermap_din : out std_logic_vector((32 - 1) downto 0);
sm_lcd_charactermap_we : out std_logic_vector((1 - 1) downto 0);
sm_lcd_characters_addr : out std_logic_vector((9 - 1) downto 0);
sm_lcd_characters_din : out std_logic_vector((32 - 1) downto 0);
sm_lcd_characters_we : out std_logic_vector((1 - 1) downto 0);
sm_lcd_commands_addr : out std_logic_vector((8 - 1) downto 0);
sm_lcd_commands_din : out std_logic_vector((32 - 1) downto 0);
sm_lcd_commands_we : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mcode_block_66f25059c9;
architecture behavior of mcode_block_66f25059c9 is
signal wrdbus_1_1186: unsigned((32 - 1) downto 0);
signal bankaddr_1_1194: unsigned((2 - 1) downto 0);
signal linearaddr_1_1204: unsigned((13 - 1) downto 0);
signal rnwreg_1_1216: unsigned((1 - 1) downto 0);
signal addrack_1_1224: unsigned((1 - 1) downto 0);
signal sm_buttons_big_1_1233: unsigned((2 - 1) downto 0);
signal sm_buttons_small_1_1249: unsigned((6 - 1) downto 0);
signal sm_dip_switch_1_1267: unsigned((4 - 1) downto 0);
signal sm_trackball_1_1282: unsigned((5 - 1) downto 0);
signal sm_buzzer_dutycycle_1_1296: unsigned((18 - 1) downto 0);
signal sm_buzzer_enable_1_1317: unsigned((1 - 1) downto 0);
signal sm_buzzer_period_1_1335: unsigned((18 - 1) downto 0);
signal sm_lcd_backgroundcolor_1_1353: unsigned((9 - 1) downto 0);
signal sm_lcd_characteroffset_1_1377: unsigned((4 - 1) downto 0);
signal sm_lcd_charactersselect_1_1401: unsigned((3 - 1) downto 0);
signal sm_lcd_colset_1_1426: unsigned((9 - 1) downto 0);
signal sm_lcd_configlocation_1_1441: unsigned((2 - 1) downto 0);
signal sm_lcd_dividerselect_1_1464: unsigned((1 - 1) downto 0);
signal sm_lcd_firstend_1_1486: unsigned((9 - 1) downto 0);
signal sm_lcd_firststart_1_1503: unsigned((9 - 1) downto 0);
signal sm_lcd_lineoffset_1_1522: unsigned((4 - 1) downto 0);
signal sm_lcd_ramwrite_1_1541: unsigned((9 - 1) downto 0);
signal sm_lcd_reset_1_1558: unsigned((1 - 1) downto 0);
signal sm_lcd_resetlcd_1_1572: unsigned((1 - 1) downto 0);
signal sm_lcd_rowset_1_1589: unsigned((9 - 1) downto 0);
signal sm_lcd_secondend_1_1604: unsigned((9 - 1) downto 0);
signal sm_lcd_secondstart_1_1622: unsigned((9 - 1) downto 0);
signal sm_lcd_send_1_1642: unsigned((1 - 1) downto 0);
signal sm_lcd_totalcmdtransfer_1_1655: unsigned((8 - 1) downto 0);
signal sm_leds_1_1680: unsigned((8 - 1) downto 0);
signal sm_lcd_charactermap_1_1689: unsigned((32 - 1) downto 0);
signal sm_lcd_characters_1_1710: unsigned((32 - 1) downto 0);
signal sm_lcd_commands_1_1729: unsigned((32 - 1) downto 0);
signal reg_bank_out_reg_98_30_next: unsigned((32 - 1) downto 0);
signal reg_bank_out_reg_98_30: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal ram_bank_out_reg_203_30_next: unsigned((32 - 1) downto 0);
signal ram_bank_out_reg_203_30: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal sm_lcd_charactermap_we_reg_226_40_next: boolean;
signal sm_lcd_charactermap_we_reg_226_40: boolean := false;
signal sm_lcd_characters_we_reg_245_38_next: boolean;
signal sm_lcd_characters_we_reg_245_38: boolean := false;
signal sm_lcd_commands_we_reg_264_36_next: boolean;
signal sm_lcd_commands_we_reg_264_36: boolean := false;
signal sm_lcd_charactermap_addr_reg_287_1_next: unsigned((12 - 1) downto 0);
signal sm_lcd_charactermap_addr_reg_287_1: unsigned((12 - 1) downto 0) := "000000000000";
signal sm_lcd_charactermap_addr_reg_287_1_en: std_logic;
signal sm_lcd_characters_addr_reg_295_1_next: unsigned((9 - 1) downto 0);
signal sm_lcd_characters_addr_reg_295_1: unsigned((9 - 1) downto 0) := "000000000";
signal sm_lcd_characters_addr_reg_295_1_en: std_logic;
signal sm_lcd_commands_addr_reg_303_1_next: unsigned((8 - 1) downto 0);
signal sm_lcd_commands_addr_reg_303_1: unsigned((8 - 1) downto 0) := "00000000";
signal sm_lcd_commands_addr_reg_303_1_en: std_logic;
signal read_bank_out_reg_516_31_next: unsigned((32 - 1) downto 0);
signal read_bank_out_reg_516_31: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal bankaddr_reg_519_26_next: unsigned((2 - 1) downto 0);
signal bankaddr_reg_519_26: unsigned((2 - 1) downto 0) := "00";
signal rel_101_4: boolean;
signal rel_103_8: boolean;
signal rel_105_8: boolean;
signal rel_107_8: boolean;
signal rel_109_8: boolean;
signal rel_111_8: boolean;
signal rel_113_8: boolean;
signal rel_115_8: boolean;
signal rel_117_8: boolean;
signal rel_119_8: boolean;
signal rel_121_8: boolean;
signal rel_123_8: boolean;
signal rel_125_8: boolean;
signal rel_127_8: boolean;
signal rel_129_8: boolean;
signal rel_131_8: boolean;
signal rel_133_8: boolean;
signal rel_135_8: boolean;
signal rel_137_8: boolean;
signal rel_139_8: boolean;
signal rel_141_8: boolean;
signal rel_143_8: boolean;
signal rel_145_8: boolean;
signal rel_147_8: boolean;
signal rel_149_8: boolean;
signal reg_bank_out_reg_join_101_1: unsigned((32 - 1) downto 0);
signal opcode_160_1_concat: unsigned((17 - 1) downto 0);
signal slice_164_51: unsigned((1 - 1) downto 0);
signal sm_lcd_charactermap_sel_value_164_1_concat: unsigned((1 - 1) downto 0);
signal rel_168_4: boolean;
signal sm_lcd_charactermap_sel_join_168_1: boolean;
signal slice_176_49: unsigned((4 - 1) downto 0);
signal sm_lcd_characters_sel_value_176_1_concat: unsigned((4 - 1) downto 0);
signal rel_180_4: boolean;
signal sm_lcd_characters_sel_join_180_1: boolean;
signal slice_188_47: unsigned((5 - 1) downto 0);
signal sm_lcd_commands_sel_value_188_1_concat: unsigned((5 - 1) downto 0);
signal rel_192_4: boolean;
signal sm_lcd_commands_sel_join_192_1: boolean;
signal ram_bank_out_reg_join_205_1: unsigned((32 - 1) downto 0);
signal slice_214_44: unsigned((32 - 1) downto 0);
signal slice_217_42: unsigned((32 - 1) downto 0);
signal slice_220_40: unsigned((32 - 1) downto 0);
signal slice_231_46: unsigned((1 - 1) downto 0);
signal opcode_sm_lcd_charactermap_228_1_concat: unsigned((5 - 1) downto 0);
signal rel_235_4: boolean;
signal sm_lcd_charactermap_we_reg_join_235_1: boolean;
signal slice_250_46: unsigned((4 - 1) downto 0);
signal opcode_sm_lcd_characters_247_1_concat: unsigned((8 - 1) downto 0);
signal rel_254_4: boolean;
signal sm_lcd_characters_we_reg_join_254_1: boolean;
signal slice_269_46: unsigned((5 - 1) downto 0);
signal opcode_sm_lcd_commands_266_1_concat: unsigned((9 - 1) downto 0);
signal rel_273_4: boolean;
signal sm_lcd_commands_we_reg_join_273_1: boolean;
signal sm_lcd_charactermap_addr_reg_290_5_slice: unsigned((13 - 1) downto 0);
signal rel_289_4: boolean;
signal sm_lcd_charactermap_addr_reg_join_289_1: unsigned((13 - 1) downto 0);
signal sm_lcd_charactermap_addr_reg_join_289_1_en: std_logic;
signal sm_lcd_characters_addr_reg_298_5_slice: unsigned((10 - 1) downto 0);
signal rel_297_4: boolean;
signal sm_lcd_characters_addr_reg_join_297_1: unsigned((10 - 1) downto 0);
signal sm_lcd_characters_addr_reg_join_297_1_en: std_logic;
signal sm_lcd_commands_addr_reg_306_5_slice: unsigned((9 - 1) downto 0);
signal rel_305_4: boolean;
signal sm_lcd_commands_addr_reg_join_305_1: unsigned((9 - 1) downto 0);
signal sm_lcd_commands_addr_reg_join_305_1_en: std_logic;
signal rel_316_4: boolean;
signal sm_buzzer_dutycycle_en_join_316_1: boolean;
signal rel_322_4: boolean;
signal sm_buzzer_enable_en_join_322_1: boolean;
signal rel_328_4: boolean;
signal sm_buzzer_period_en_join_328_1: boolean;
signal rel_334_4: boolean;
signal sm_lcd_backgroundcolor_en_join_334_1: boolean;
signal rel_340_4: boolean;
signal sm_lcd_characteroffset_en_join_340_1: boolean;
signal rel_346_4: boolean;
signal sm_lcd_charactersselect_en_join_346_1: boolean;
signal rel_352_4: boolean;
signal sm_lcd_colset_en_join_352_1: boolean;
signal rel_358_4: boolean;
signal sm_lcd_configlocation_en_join_358_1: boolean;
signal rel_364_4: boolean;
signal sm_lcd_dividerselect_en_join_364_1: boolean;
signal rel_370_4: boolean;
signal sm_lcd_firstend_en_join_370_1: boolean;
signal rel_376_4: boolean;
signal sm_lcd_firststart_en_join_376_1: boolean;
signal rel_382_4: boolean;
signal sm_lcd_lineoffset_en_join_382_1: boolean;
signal rel_388_4: boolean;
signal sm_lcd_ramwrite_en_join_388_1: boolean;
signal rel_394_4: boolean;
signal sm_lcd_reset_en_join_394_1: boolean;
signal rel_400_4: boolean;
signal sm_lcd_resetlcd_en_join_400_1: boolean;
signal rel_406_4: boolean;
signal sm_lcd_rowset_en_join_406_1: boolean;
signal rel_412_4: boolean;
signal sm_lcd_secondend_en_join_412_1: boolean;
signal rel_418_4: boolean;
signal sm_lcd_secondstart_en_join_418_1: boolean;
signal rel_424_4: boolean;
signal sm_lcd_send_en_join_424_1: boolean;
signal rel_430_4: boolean;
signal sm_lcd_totalcmdtransfer_en_join_430_1: boolean;
signal rel_436_4: boolean;
signal sm_leds_en_join_436_1: boolean;
signal slice_451_44: unsigned((18 - 1) downto 0);
signal slice_454_41: unsigned((1 - 1) downto 0);
signal slice_457_41: unsigned((18 - 1) downto 0);
signal slice_460_47: unsigned((9 - 1) downto 0);
signal slice_463_47: unsigned((4 - 1) downto 0);
signal slice_466_48: unsigned((3 - 1) downto 0);
signal slice_469_38: unsigned((9 - 1) downto 0);
signal slice_472_46: unsigned((2 - 1) downto 0);
signal slice_475_45: unsigned((1 - 1) downto 0);
signal slice_478_40: unsigned((9 - 1) downto 0);
signal slice_481_42: unsigned((9 - 1) downto 0);
signal slice_484_42: unsigned((4 - 1) downto 0);
signal slice_487_40: unsigned((9 - 1) downto 0);
signal slice_490_37: unsigned((1 - 1) downto 0);
signal slice_493_40: unsigned((1 - 1) downto 0);
signal slice_496_38: unsigned((9 - 1) downto 0);
signal slice_499_41: unsigned((9 - 1) downto 0);
signal slice_502_43: unsigned((9 - 1) downto 0);
signal slice_505_36: unsigned((1 - 1) downto 0);
signal slice_508_48: unsigned((8 - 1) downto 0);
signal slice_511_32: unsigned((8 - 1) downto 0);
signal rel_521_4: boolean;
signal rel_524_8: boolean;
signal rel_527_8: boolean;
signal rel_530_8: boolean;
signal read_bank_out_reg_join_521_1: unsigned((32 - 1) downto 0);
signal cast_sm_lcd_charactermap_addr_reg_287_1_next: unsigned((12 - 1) downto 0);
signal cast_sm_lcd_characters_addr_reg_295_1_next: unsigned((9 - 1) downto 0);
signal cast_sm_lcd_commands_addr_reg_303_1_next: unsigned((8 - 1) downto 0);
begin
wrdbus_1_1186 <= std_logic_vector_to_unsigned(wrdbus);
bankaddr_1_1194 <= std_logic_vector_to_unsigned(bankaddr);
linearaddr_1_1204 <= std_logic_vector_to_unsigned(linearaddr);
rnwreg_1_1216 <= std_logic_vector_to_unsigned(rnwreg);
addrack_1_1224 <= std_logic_vector_to_unsigned(addrack);
sm_buttons_big_1_1233 <= std_logic_vector_to_unsigned(sm_buttons_big);
sm_buttons_small_1_1249 <= std_logic_vector_to_unsigned(sm_buttons_small);
sm_dip_switch_1_1267 <= std_logic_vector_to_unsigned(sm_dip_switch);
sm_trackball_1_1282 <= std_logic_vector_to_unsigned(sm_trackball);
sm_buzzer_dutycycle_1_1296 <= std_logic_vector_to_unsigned(sm_buzzer_dutycycle);
sm_buzzer_enable_1_1317 <= std_logic_vector_to_unsigned(sm_buzzer_enable);
sm_buzzer_period_1_1335 <= std_logic_vector_to_unsigned(sm_buzzer_period);
sm_lcd_backgroundcolor_1_1353 <= std_logic_vector_to_unsigned(sm_lcd_backgroundcolor);
sm_lcd_characteroffset_1_1377 <= std_logic_vector_to_unsigned(sm_lcd_characteroffset);
sm_lcd_charactersselect_1_1401 <= std_logic_vector_to_unsigned(sm_lcd_charactersselect);
sm_lcd_colset_1_1426 <= std_logic_vector_to_unsigned(sm_lcd_colset);
sm_lcd_configlocation_1_1441 <= std_logic_vector_to_unsigned(sm_lcd_configlocation);
sm_lcd_dividerselect_1_1464 <= std_logic_vector_to_unsigned(sm_lcd_dividerselect);
sm_lcd_firstend_1_1486 <= std_logic_vector_to_unsigned(sm_lcd_firstend);
sm_lcd_firststart_1_1503 <= std_logic_vector_to_unsigned(sm_lcd_firststart);
sm_lcd_lineoffset_1_1522 <= std_logic_vector_to_unsigned(sm_lcd_lineoffset);
sm_lcd_ramwrite_1_1541 <= std_logic_vector_to_unsigned(sm_lcd_ramwrite);
sm_lcd_reset_1_1558 <= std_logic_vector_to_unsigned(sm_lcd_reset);
sm_lcd_resetlcd_1_1572 <= std_logic_vector_to_unsigned(sm_lcd_resetlcd);
sm_lcd_rowset_1_1589 <= std_logic_vector_to_unsigned(sm_lcd_rowset);
sm_lcd_secondend_1_1604 <= std_logic_vector_to_unsigned(sm_lcd_secondend);
sm_lcd_secondstart_1_1622 <= std_logic_vector_to_unsigned(sm_lcd_secondstart);
sm_lcd_send_1_1642 <= std_logic_vector_to_unsigned(sm_lcd_send);
sm_lcd_totalcmdtransfer_1_1655 <= std_logic_vector_to_unsigned(sm_lcd_totalcmdtransfer);
sm_leds_1_1680 <= std_logic_vector_to_unsigned(sm_leds);
sm_lcd_charactermap_1_1689 <= std_logic_vector_to_unsigned(sm_lcd_charactermap);
sm_lcd_characters_1_1710 <= std_logic_vector_to_unsigned(sm_lcd_characters);
sm_lcd_commands_1_1729 <= std_logic_vector_to_unsigned(sm_lcd_commands);
proc_reg_bank_out_reg_98_30: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
reg_bank_out_reg_98_30 <= reg_bank_out_reg_98_30_next;
end if;
end if;
end process proc_reg_bank_out_reg_98_30;
proc_ram_bank_out_reg_203_30: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
ram_bank_out_reg_203_30 <= ram_bank_out_reg_203_30_next;
end if;
end if;
end process proc_ram_bank_out_reg_203_30;
proc_sm_lcd_charactermap_we_reg_226_40: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
sm_lcd_charactermap_we_reg_226_40 <= sm_lcd_charactermap_we_reg_226_40_next;
end if;
end if;
end process proc_sm_lcd_charactermap_we_reg_226_40;
proc_sm_lcd_characters_we_reg_245_38: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
sm_lcd_characters_we_reg_245_38 <= sm_lcd_characters_we_reg_245_38_next;
end if;
end if;
end process proc_sm_lcd_characters_we_reg_245_38;
proc_sm_lcd_commands_we_reg_264_36: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
sm_lcd_commands_we_reg_264_36 <= sm_lcd_commands_we_reg_264_36_next;
end if;
end if;
end process proc_sm_lcd_commands_we_reg_264_36;
proc_sm_lcd_charactermap_addr_reg_287_1: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (sm_lcd_charactermap_addr_reg_287_1_en = '1')) then
sm_lcd_charactermap_addr_reg_287_1 <= sm_lcd_charactermap_addr_reg_287_1_next;
end if;
end if;
end process proc_sm_lcd_charactermap_addr_reg_287_1;
proc_sm_lcd_characters_addr_reg_295_1: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (sm_lcd_characters_addr_reg_295_1_en = '1')) then
sm_lcd_characters_addr_reg_295_1 <= sm_lcd_characters_addr_reg_295_1_next;
end if;
end if;
end process proc_sm_lcd_characters_addr_reg_295_1;
proc_sm_lcd_commands_addr_reg_303_1: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (sm_lcd_commands_addr_reg_303_1_en = '1')) then
sm_lcd_commands_addr_reg_303_1 <= sm_lcd_commands_addr_reg_303_1_next;
end if;
end if;
end process proc_sm_lcd_commands_addr_reg_303_1;
proc_read_bank_out_reg_516_31: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
read_bank_out_reg_516_31 <= read_bank_out_reg_516_31_next;
end if;
end if;
end process proc_read_bank_out_reg_516_31;
proc_bankaddr_reg_519_26: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
bankaddr_reg_519_26 <= bankaddr_reg_519_26_next;
end if;
end if;
end process proc_bankaddr_reg_519_26;
rel_101_4 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000010101");
rel_103_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000010110");
rel_105_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000010111");
rel_107_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000011000");
rel_109_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000000000");
rel_111_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000000001");
rel_113_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000000010");
rel_115_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000000011");
rel_117_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000000100");
rel_119_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000000101");
rel_121_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000000110");
rel_123_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000000111");
rel_125_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000001000");
rel_127_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000001001");
rel_129_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000001010");
rel_131_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000001011");
rel_133_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000001100");
rel_135_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000001101");
rel_137_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000001110");
rel_139_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000001111");
rel_141_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000010000");
rel_143_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000010001");
rel_145_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000010010");
rel_147_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000010011");
rel_149_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000010100");
proc_if_101_1: process (reg_bank_out_reg_98_30, rel_101_4, rel_103_8, rel_105_8, rel_107_8, rel_109_8, rel_111_8, rel_113_8, rel_115_8, rel_117_8, rel_119_8, rel_121_8, rel_123_8, rel_125_8, rel_127_8, rel_129_8, rel_131_8, rel_133_8, rel_135_8, rel_137_8, rel_139_8, rel_141_8, rel_143_8, rel_145_8, rel_147_8, rel_149_8, sm_buttons_big_1_1233, sm_buttons_small_1_1249, sm_buzzer_dutycycle_1_1296, sm_buzzer_enable_1_1317, sm_buzzer_period_1_1335, sm_dip_switch_1_1267, sm_lcd_backgroundcolor_1_1353, sm_lcd_characteroffset_1_1377, sm_lcd_charactersselect_1_1401, sm_lcd_colset_1_1426, sm_lcd_configlocation_1_1441, sm_lcd_dividerselect_1_1464, sm_lcd_firstend_1_1486, sm_lcd_firststart_1_1503, sm_lcd_lineoffset_1_1522, sm_lcd_ramwrite_1_1541, sm_lcd_reset_1_1558, sm_lcd_resetlcd_1_1572, sm_lcd_rowset_1_1589, sm_lcd_secondend_1_1604, sm_lcd_secondstart_1_1622, sm_lcd_send_1_1642, sm_lcd_totalcmdtransfer_1_1655, sm_leds_1_1680, sm_trackball_1_1282)
is
begin
if rel_101_4 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_buttons_big_1_1233, 0, 32, 0);
elsif rel_103_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_buttons_small_1_1249, 0, 32, 0);
elsif rel_105_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_dip_switch_1_1267, 0, 32, 0);
elsif rel_107_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_trackball_1_1282, 0, 32, 0);
elsif rel_109_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_buzzer_dutycycle_1_1296, 0, 32, 0);
elsif rel_111_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_buzzer_enable_1_1317, 0, 32, 0);
elsif rel_113_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_buzzer_period_1_1335, 0, 32, 0);
elsif rel_115_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_backgroundcolor_1_1353, 0, 32, 0);
elsif rel_117_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_characteroffset_1_1377, 0, 32, 0);
elsif rel_119_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_charactersselect_1_1401, 0, 32, 0);
elsif rel_121_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_colset_1_1426, 0, 32, 0);
elsif rel_123_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_configlocation_1_1441, 0, 32, 0);
elsif rel_125_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_dividerselect_1_1464, 0, 32, 0);
elsif rel_127_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_firstend_1_1486, 0, 32, 0);
elsif rel_129_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_firststart_1_1503, 0, 32, 0);
elsif rel_131_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_lineoffset_1_1522, 0, 32, 0);
elsif rel_133_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_ramwrite_1_1541, 0, 32, 0);
elsif rel_135_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_reset_1_1558, 0, 32, 0);
elsif rel_137_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_resetlcd_1_1572, 0, 32, 0);
elsif rel_139_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_rowset_1_1589, 0, 32, 0);
elsif rel_141_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_secondend_1_1604, 0, 32, 0);
elsif rel_143_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_secondstart_1_1622, 0, 32, 0);
elsif rel_145_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_send_1_1642, 0, 32, 0);
elsif rel_147_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_totalcmdtransfer_1_1655, 0, 32, 0);
elsif rel_149_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_leds_1_1680, 0, 32, 0);
else
reg_bank_out_reg_join_101_1 <= reg_bank_out_reg_98_30;
end if;
end process proc_if_101_1;
opcode_160_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_1_1224) & unsigned_to_std_logic_vector(rnwreg_1_1216) & unsigned_to_std_logic_vector(bankaddr_1_1194) & unsigned_to_std_logic_vector(linearaddr_1_1204));
slice_164_51 <= u2u_slice(linearaddr_1_1204, 12, 12);
sm_lcd_charactermap_sel_value_164_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(slice_164_51));
rel_168_4 <= sm_lcd_charactermap_sel_value_164_1_concat = std_logic_vector_to_unsigned("0");
proc_if_168_1: process (rel_168_4)
is
begin
if rel_168_4 then
sm_lcd_charactermap_sel_join_168_1 <= true;
else
sm_lcd_charactermap_sel_join_168_1 <= false;
end if;
end process proc_if_168_1;
slice_176_49 <= u2u_slice(linearaddr_1_1204, 12, 9);
sm_lcd_characters_sel_value_176_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(slice_176_49));
rel_180_4 <= sm_lcd_characters_sel_value_176_1_concat = std_logic_vector_to_unsigned("1000");
proc_if_180_1: process (rel_180_4)
is
begin
if rel_180_4 then
sm_lcd_characters_sel_join_180_1 <= true;
else
sm_lcd_characters_sel_join_180_1 <= false;
end if;
end process proc_if_180_1;
slice_188_47 <= u2u_slice(linearaddr_1_1204, 12, 8);
sm_lcd_commands_sel_value_188_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(slice_188_47));
rel_192_4 <= sm_lcd_commands_sel_value_188_1_concat = std_logic_vector_to_unsigned("10010");
proc_if_192_1: process (rel_192_4)
is
begin
if rel_192_4 then
sm_lcd_commands_sel_join_192_1 <= true;
else
sm_lcd_commands_sel_join_192_1 <= false;
end if;
end process proc_if_192_1;
proc_if_205_1: process (ram_bank_out_reg_203_30, sm_lcd_charactermap_1_1689, sm_lcd_charactermap_sel_join_168_1, sm_lcd_characters_1_1710, sm_lcd_characters_sel_join_180_1, sm_lcd_commands_1_1729, sm_lcd_commands_sel_join_192_1)
is
begin
if sm_lcd_charactermap_sel_join_168_1 then
ram_bank_out_reg_join_205_1 <= sm_lcd_charactermap_1_1689;
elsif sm_lcd_characters_sel_join_180_1 then
ram_bank_out_reg_join_205_1 <= sm_lcd_characters_1_1710;
elsif sm_lcd_commands_sel_join_192_1 then
ram_bank_out_reg_join_205_1 <= sm_lcd_commands_1_1729;
else
ram_bank_out_reg_join_205_1 <= ram_bank_out_reg_203_30;
end if;
end process proc_if_205_1;
slice_214_44 <= u2u_slice(wrdbus_1_1186, 31, 0);
slice_217_42 <= u2u_slice(wrdbus_1_1186, 31, 0);
slice_220_40 <= u2u_slice(wrdbus_1_1186, 31, 0);
slice_231_46 <= u2u_slice(linearaddr_1_1204, 12, 12);
opcode_sm_lcd_charactermap_228_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_1_1224) & unsigned_to_std_logic_vector(rnwreg_1_1216) & unsigned_to_std_logic_vector(bankaddr_1_1194) & unsigned_to_std_logic_vector(slice_231_46));
rel_235_4 <= opcode_sm_lcd_charactermap_228_1_concat = std_logic_vector_to_unsigned("10000");
proc_if_235_1: process (rel_235_4)
is
begin
if rel_235_4 then
sm_lcd_charactermap_we_reg_join_235_1 <= true;
else
sm_lcd_charactermap_we_reg_join_235_1 <= false;
end if;
end process proc_if_235_1;
slice_250_46 <= u2u_slice(linearaddr_1_1204, 12, 9);
opcode_sm_lcd_characters_247_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_1_1224) & unsigned_to_std_logic_vector(rnwreg_1_1216) & unsigned_to_std_logic_vector(bankaddr_1_1194) & unsigned_to_std_logic_vector(slice_250_46));
rel_254_4 <= opcode_sm_lcd_characters_247_1_concat = std_logic_vector_to_unsigned("10001000");
proc_if_254_1: process (rel_254_4)
is
begin
if rel_254_4 then
sm_lcd_characters_we_reg_join_254_1 <= true;
else
sm_lcd_characters_we_reg_join_254_1 <= false;
end if;
end process proc_if_254_1;
slice_269_46 <= u2u_slice(linearaddr_1_1204, 12, 8);
opcode_sm_lcd_commands_266_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_1_1224) & unsigned_to_std_logic_vector(rnwreg_1_1216) & unsigned_to_std_logic_vector(bankaddr_1_1194) & unsigned_to_std_logic_vector(slice_269_46));
rel_273_4 <= opcode_sm_lcd_commands_266_1_concat = std_logic_vector_to_unsigned("100010010");
proc_if_273_1: process (rel_273_4)
is
begin
if rel_273_4 then
sm_lcd_commands_we_reg_join_273_1 <= true;
else
sm_lcd_commands_we_reg_join_273_1 <= false;
end if;
end process proc_if_273_1;
sm_lcd_charactermap_addr_reg_290_5_slice <= u2u_slice(linearaddr_1_1204, 12, 0);
rel_289_4 <= addrack_1_1224 = std_logic_vector_to_unsigned("1");
proc_if_289_1: process (rel_289_4, sm_lcd_charactermap_addr_reg_290_5_slice)
is
begin
if rel_289_4 then
sm_lcd_charactermap_addr_reg_join_289_1_en <= '1';
else
sm_lcd_charactermap_addr_reg_join_289_1_en <= '0';
end if;
sm_lcd_charactermap_addr_reg_join_289_1 <= sm_lcd_charactermap_addr_reg_290_5_slice;
end process proc_if_289_1;
sm_lcd_characters_addr_reg_298_5_slice <= u2u_slice(linearaddr_1_1204, 9, 0);
rel_297_4 <= addrack_1_1224 = std_logic_vector_to_unsigned("1");
proc_if_297_1: process (rel_297_4, sm_lcd_characters_addr_reg_298_5_slice)
is
begin
if rel_297_4 then
sm_lcd_characters_addr_reg_join_297_1_en <= '1';
else
sm_lcd_characters_addr_reg_join_297_1_en <= '0';
end if;
sm_lcd_characters_addr_reg_join_297_1 <= sm_lcd_characters_addr_reg_298_5_slice;
end process proc_if_297_1;
sm_lcd_commands_addr_reg_306_5_slice <= u2u_slice(linearaddr_1_1204, 8, 0);
rel_305_4 <= addrack_1_1224 = std_logic_vector_to_unsigned("1");
proc_if_305_1: process (rel_305_4, sm_lcd_commands_addr_reg_306_5_slice)
is
begin
if rel_305_4 then
sm_lcd_commands_addr_reg_join_305_1_en <= '1';
else
sm_lcd_commands_addr_reg_join_305_1_en <= '0';
end if;
sm_lcd_commands_addr_reg_join_305_1 <= sm_lcd_commands_addr_reg_306_5_slice;
end process proc_if_305_1;
rel_316_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000000000");
proc_if_316_1: process (rel_316_4)
is
begin
if rel_316_4 then
sm_buzzer_dutycycle_en_join_316_1 <= true;
else
sm_buzzer_dutycycle_en_join_316_1 <= false;
end if;
end process proc_if_316_1;
rel_322_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000000001");
proc_if_322_1: process (rel_322_4)
is
begin
if rel_322_4 then
sm_buzzer_enable_en_join_322_1 <= true;
else
sm_buzzer_enable_en_join_322_1 <= false;
end if;
end process proc_if_322_1;
rel_328_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000000010");
proc_if_328_1: process (rel_328_4)
is
begin
if rel_328_4 then
sm_buzzer_period_en_join_328_1 <= true;
else
sm_buzzer_period_en_join_328_1 <= false;
end if;
end process proc_if_328_1;
rel_334_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000000011");
proc_if_334_1: process (rel_334_4)
is
begin
if rel_334_4 then
sm_lcd_backgroundcolor_en_join_334_1 <= true;
else
sm_lcd_backgroundcolor_en_join_334_1 <= false;
end if;
end process proc_if_334_1;
rel_340_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000000100");
proc_if_340_1: process (rel_340_4)
is
begin
if rel_340_4 then
sm_lcd_characteroffset_en_join_340_1 <= true;
else
sm_lcd_characteroffset_en_join_340_1 <= false;
end if;
end process proc_if_340_1;
rel_346_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000000101");
proc_if_346_1: process (rel_346_4)
is
begin
if rel_346_4 then
sm_lcd_charactersselect_en_join_346_1 <= true;
else
sm_lcd_charactersselect_en_join_346_1 <= false;
end if;
end process proc_if_346_1;
rel_352_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000000110");
proc_if_352_1: process (rel_352_4)
is
begin
if rel_352_4 then
sm_lcd_colset_en_join_352_1 <= true;
else
sm_lcd_colset_en_join_352_1 <= false;
end if;
end process proc_if_352_1;
rel_358_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000000111");
proc_if_358_1: process (rel_358_4)
is
begin
if rel_358_4 then
sm_lcd_configlocation_en_join_358_1 <= true;
else
sm_lcd_configlocation_en_join_358_1 <= false;
end if;
end process proc_if_358_1;
rel_364_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000001000");
proc_if_364_1: process (rel_364_4)
is
begin
if rel_364_4 then
sm_lcd_dividerselect_en_join_364_1 <= true;
else
sm_lcd_dividerselect_en_join_364_1 <= false;
end if;
end process proc_if_364_1;
rel_370_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000001001");
proc_if_370_1: process (rel_370_4)
is
begin
if rel_370_4 then
sm_lcd_firstend_en_join_370_1 <= true;
else
sm_lcd_firstend_en_join_370_1 <= false;
end if;
end process proc_if_370_1;
rel_376_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000001010");
proc_if_376_1: process (rel_376_4)
is
begin
if rel_376_4 then
sm_lcd_firststart_en_join_376_1 <= true;
else
sm_lcd_firststart_en_join_376_1 <= false;
end if;
end process proc_if_376_1;
rel_382_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000001011");
proc_if_382_1: process (rel_382_4)
is
begin
if rel_382_4 then
sm_lcd_lineoffset_en_join_382_1 <= true;
else
sm_lcd_lineoffset_en_join_382_1 <= false;
end if;
end process proc_if_382_1;
rel_388_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000001100");
proc_if_388_1: process (rel_388_4)
is
begin
if rel_388_4 then
sm_lcd_ramwrite_en_join_388_1 <= true;
else
sm_lcd_ramwrite_en_join_388_1 <= false;
end if;
end process proc_if_388_1;
rel_394_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000001101");
proc_if_394_1: process (rel_394_4)
is
begin
if rel_394_4 then
sm_lcd_reset_en_join_394_1 <= true;
else
sm_lcd_reset_en_join_394_1 <= false;
end if;
end process proc_if_394_1;
rel_400_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000001110");
proc_if_400_1: process (rel_400_4)
is
begin
if rel_400_4 then
sm_lcd_resetlcd_en_join_400_1 <= true;
else
sm_lcd_resetlcd_en_join_400_1 <= false;
end if;
end process proc_if_400_1;
rel_406_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000001111");
proc_if_406_1: process (rel_406_4)
is
begin
if rel_406_4 then
sm_lcd_rowset_en_join_406_1 <= true;
else
sm_lcd_rowset_en_join_406_1 <= false;
end if;
end process proc_if_406_1;
rel_412_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000010000");
proc_if_412_1: process (rel_412_4)
is
begin
if rel_412_4 then
sm_lcd_secondend_en_join_412_1 <= true;
else
sm_lcd_secondend_en_join_412_1 <= false;
end if;
end process proc_if_412_1;
rel_418_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000010001");
proc_if_418_1: process (rel_418_4)
is
begin
if rel_418_4 then
sm_lcd_secondstart_en_join_418_1 <= true;
else
sm_lcd_secondstart_en_join_418_1 <= false;
end if;
end process proc_if_418_1;
rel_424_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000010010");
proc_if_424_1: process (rel_424_4)
is
begin
if rel_424_4 then
sm_lcd_send_en_join_424_1 <= true;
else
sm_lcd_send_en_join_424_1 <= false;
end if;
end process proc_if_424_1;
rel_430_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000010011");
proc_if_430_1: process (rel_430_4)
is
begin
if rel_430_4 then
sm_lcd_totalcmdtransfer_en_join_430_1 <= true;
else
sm_lcd_totalcmdtransfer_en_join_430_1 <= false;
end if;
end process proc_if_430_1;
rel_436_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000010100");
proc_if_436_1: process (rel_436_4)
is
begin
if rel_436_4 then
sm_leds_en_join_436_1 <= true;
else
sm_leds_en_join_436_1 <= false;
end if;
end process proc_if_436_1;
slice_451_44 <= u2u_slice(wrdbus_1_1186, 17, 0);
slice_454_41 <= u2u_slice(wrdbus_1_1186, 0, 0);
slice_457_41 <= u2u_slice(wrdbus_1_1186, 17, 0);
slice_460_47 <= u2u_slice(wrdbus_1_1186, 8, 0);
slice_463_47 <= u2u_slice(wrdbus_1_1186, 3, 0);
slice_466_48 <= u2u_slice(wrdbus_1_1186, 2, 0);
slice_469_38 <= u2u_slice(wrdbus_1_1186, 8, 0);
slice_472_46 <= u2u_slice(wrdbus_1_1186, 1, 0);
slice_475_45 <= u2u_slice(wrdbus_1_1186, 0, 0);
slice_478_40 <= u2u_slice(wrdbus_1_1186, 8, 0);
slice_481_42 <= u2u_slice(wrdbus_1_1186, 8, 0);
slice_484_42 <= u2u_slice(wrdbus_1_1186, 3, 0);
slice_487_40 <= u2u_slice(wrdbus_1_1186, 8, 0);
slice_490_37 <= u2u_slice(wrdbus_1_1186, 0, 0);
slice_493_40 <= u2u_slice(wrdbus_1_1186, 0, 0);
slice_496_38 <= u2u_slice(wrdbus_1_1186, 8, 0);
slice_499_41 <= u2u_slice(wrdbus_1_1186, 8, 0);
slice_502_43 <= u2u_slice(wrdbus_1_1186, 8, 0);
slice_505_36 <= u2u_slice(wrdbus_1_1186, 0, 0);
slice_508_48 <= u2u_slice(wrdbus_1_1186, 7, 0);
slice_511_32 <= u2u_slice(wrdbus_1_1186, 7, 0);
rel_521_4 <= bankaddr_reg_519_26 = std_logic_vector_to_unsigned("00");
rel_524_8 <= bankaddr_reg_519_26 = std_logic_vector_to_unsigned("01");
rel_527_8 <= bankaddr_reg_519_26 = std_logic_vector_to_unsigned("10");
rel_530_8 <= bankaddr_reg_519_26 = std_logic_vector_to_unsigned("11");
proc_if_521_1: process (ram_bank_out_reg_203_30, read_bank_out_reg_516_31, reg_bank_out_reg_98_30, rel_521_4, rel_524_8, rel_527_8, rel_530_8)
is
begin
if rel_521_4 then
read_bank_out_reg_join_521_1 <= ram_bank_out_reg_203_30;
elsif rel_524_8 then
read_bank_out_reg_join_521_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000");
elsif rel_527_8 then
read_bank_out_reg_join_521_1 <= reg_bank_out_reg_98_30;
elsif rel_530_8 then
read_bank_out_reg_join_521_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000");
else
read_bank_out_reg_join_521_1 <= read_bank_out_reg_516_31;
end if;
end process proc_if_521_1;
reg_bank_out_reg_98_30_next <= reg_bank_out_reg_join_101_1;
ram_bank_out_reg_203_30_next <= ram_bank_out_reg_join_205_1;
sm_lcd_charactermap_we_reg_226_40_next <= sm_lcd_charactermap_we_reg_join_235_1;
sm_lcd_characters_we_reg_245_38_next <= sm_lcd_characters_we_reg_join_254_1;
sm_lcd_commands_we_reg_264_36_next <= sm_lcd_commands_we_reg_join_273_1;
cast_sm_lcd_charactermap_addr_reg_287_1_next <= u2u_cast(sm_lcd_charactermap_addr_reg_join_289_1, 0, 12, 0);
sm_lcd_charactermap_addr_reg_287_1_next <= cast_sm_lcd_charactermap_addr_reg_287_1_next;
sm_lcd_charactermap_addr_reg_287_1_en <= sm_lcd_charactermap_addr_reg_join_289_1_en;
cast_sm_lcd_characters_addr_reg_295_1_next <= u2u_cast(sm_lcd_characters_addr_reg_join_297_1, 0, 9, 0);
sm_lcd_characters_addr_reg_295_1_next <= cast_sm_lcd_characters_addr_reg_295_1_next;
sm_lcd_characters_addr_reg_295_1_en <= sm_lcd_characters_addr_reg_join_297_1_en;
cast_sm_lcd_commands_addr_reg_303_1_next <= u2u_cast(sm_lcd_commands_addr_reg_join_305_1, 0, 8, 0);
sm_lcd_commands_addr_reg_303_1_next <= cast_sm_lcd_commands_addr_reg_303_1_next;
sm_lcd_commands_addr_reg_303_1_en <= sm_lcd_commands_addr_reg_join_305_1_en;
read_bank_out_reg_516_31_next <= read_bank_out_reg_join_521_1;
bankaddr_reg_519_26_next <= bankaddr_1_1194;
read_bank_out <= unsigned_to_std_logic_vector(read_bank_out_reg_516_31);
sm_buzzer_dutycycle_din <= unsigned_to_std_logic_vector(slice_451_44);
sm_buzzer_dutycycle_en <= boolean_to_vector(sm_buzzer_dutycycle_en_join_316_1);
sm_buzzer_enable_din <= unsigned_to_std_logic_vector(slice_454_41);
sm_buzzer_enable_en <= boolean_to_vector(sm_buzzer_enable_en_join_322_1);
sm_buzzer_period_din <= unsigned_to_std_logic_vector(slice_457_41);
sm_buzzer_period_en <= boolean_to_vector(sm_buzzer_period_en_join_328_1);
sm_lcd_backgroundcolor_din <= unsigned_to_std_logic_vector(slice_460_47);
sm_lcd_backgroundcolor_en <= boolean_to_vector(sm_lcd_backgroundcolor_en_join_334_1);
sm_lcd_characteroffset_din <= unsigned_to_std_logic_vector(slice_463_47);
sm_lcd_characteroffset_en <= boolean_to_vector(sm_lcd_characteroffset_en_join_340_1);
sm_lcd_charactersselect_din <= unsigned_to_std_logic_vector(slice_466_48);
sm_lcd_charactersselect_en <= boolean_to_vector(sm_lcd_charactersselect_en_join_346_1);
sm_lcd_colset_din <= unsigned_to_std_logic_vector(slice_469_38);
sm_lcd_colset_en <= boolean_to_vector(sm_lcd_colset_en_join_352_1);
sm_lcd_configlocation_din <= unsigned_to_std_logic_vector(slice_472_46);
sm_lcd_configlocation_en <= boolean_to_vector(sm_lcd_configlocation_en_join_358_1);
sm_lcd_dividerselect_din <= unsigned_to_std_logic_vector(slice_475_45);
sm_lcd_dividerselect_en <= boolean_to_vector(sm_lcd_dividerselect_en_join_364_1);
sm_lcd_firstend_din <= unsigned_to_std_logic_vector(slice_478_40);
sm_lcd_firstend_en <= boolean_to_vector(sm_lcd_firstend_en_join_370_1);
sm_lcd_firststart_din <= unsigned_to_std_logic_vector(slice_481_42);
sm_lcd_firststart_en <= boolean_to_vector(sm_lcd_firststart_en_join_376_1);
sm_lcd_lineoffset_din <= unsigned_to_std_logic_vector(slice_484_42);
sm_lcd_lineoffset_en <= boolean_to_vector(sm_lcd_lineoffset_en_join_382_1);
sm_lcd_ramwrite_din <= unsigned_to_std_logic_vector(slice_487_40);
sm_lcd_ramwrite_en <= boolean_to_vector(sm_lcd_ramwrite_en_join_388_1);
sm_lcd_reset_din <= unsigned_to_std_logic_vector(slice_490_37);
sm_lcd_reset_en <= boolean_to_vector(sm_lcd_reset_en_join_394_1);
sm_lcd_resetlcd_din <= unsigned_to_std_logic_vector(slice_493_40);
sm_lcd_resetlcd_en <= boolean_to_vector(sm_lcd_resetlcd_en_join_400_1);
sm_lcd_rowset_din <= unsigned_to_std_logic_vector(slice_496_38);
sm_lcd_rowset_en <= boolean_to_vector(sm_lcd_rowset_en_join_406_1);
sm_lcd_secondend_din <= unsigned_to_std_logic_vector(slice_499_41);
sm_lcd_secondend_en <= boolean_to_vector(sm_lcd_secondend_en_join_412_1);
sm_lcd_secondstart_din <= unsigned_to_std_logic_vector(slice_502_43);
sm_lcd_secondstart_en <= boolean_to_vector(sm_lcd_secondstart_en_join_418_1);
sm_lcd_send_din <= unsigned_to_std_logic_vector(slice_505_36);
sm_lcd_send_en <= boolean_to_vector(sm_lcd_send_en_join_424_1);
sm_lcd_totalcmdtransfer_din <= unsigned_to_std_logic_vector(slice_508_48);
sm_lcd_totalcmdtransfer_en <= boolean_to_vector(sm_lcd_totalcmdtransfer_en_join_430_1);
sm_leds_din <= unsigned_to_std_logic_vector(slice_511_32);
sm_leds_en <= boolean_to_vector(sm_leds_en_join_436_1);
sm_lcd_charactermap_addr <= unsigned_to_std_logic_vector(sm_lcd_charactermap_addr_reg_287_1);
sm_lcd_charactermap_din <= unsigned_to_std_logic_vector(slice_214_44);
sm_lcd_charactermap_we <= boolean_to_vector(sm_lcd_charactermap_we_reg_226_40);
sm_lcd_characters_addr <= unsigned_to_std_logic_vector(sm_lcd_characters_addr_reg_295_1);
sm_lcd_characters_din <= unsigned_to_std_logic_vector(slice_217_42);
sm_lcd_characters_we <= boolean_to_vector(sm_lcd_characters_we_reg_245_38);
sm_lcd_commands_addr <= unsigned_to_std_logic_vector(sm_lcd_commands_addr_reg_303_1);
sm_lcd_commands_din <= unsigned_to_std_logic_vector(slice_220_40);
sm_lcd_commands_we <= boolean_to_vector(sm_lcd_commands_we_reg_264_36);
end behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xldelay is
generic(width : integer := -1;
latency : integer := -1;
reg_retiming : integer := 0);
port(d : in std_logic_vector (width-1 downto 0);
ce : in std_logic;
clk : in std_logic;
en : in std_logic;
q : out std_logic_vector (width-1 downto 0));
end xldelay;
architecture behavior of xldelay is
component synth_reg
generic (width : integer;
latency : integer);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end component;
component synth_reg_reg
generic (width : integer;
latency : integer);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end component;
signal internal_ce : std_logic;
begin
internal_ce <= ce and en;
srl_delay: if (reg_retiming = 0) or (latency < 1) generate
synth_reg_srl_inst : synth_reg
generic map (
width => width,
latency => latency)
port map (
i => d,
ce => internal_ce,
clr => '0',
clk => clk,
o => q);
end generate srl_delay;
reg_delay: if (reg_retiming = 1) and (latency >= 1) generate
synth_reg_reg_inst : synth_reg_reg
generic map (
width => width,
latency => latency)
port map (
i => d,
ce => internal_ce,
clr => '0',
clk => clk,
o => q);
end generate reg_delay;
end architecture behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity logical_4ad38e8aed is
port (
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
d2 : in std_logic_vector((1 - 1) downto 0);
d3 : in std_logic_vector((1 - 1) downto 0);
d4 : in std_logic_vector((1 - 1) downto 0);
d5 : in std_logic_vector((1 - 1) downto 0);
d6 : in std_logic_vector((1 - 1) downto 0);
d7 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end logical_4ad38e8aed;
architecture behavior of logical_4ad38e8aed is
signal d0_1_24: std_logic_vector((1 - 1) downto 0);
signal d1_1_27: std_logic_vector((1 - 1) downto 0);
signal d2_1_30: std_logic_vector((1 - 1) downto 0);
signal d3_1_33: std_logic_vector((1 - 1) downto 0);
signal d4_1_36: std_logic_vector((1 - 1) downto 0);
signal d5_1_39: std_logic_vector((1 - 1) downto 0);
signal d6_1_42: std_logic_vector((1 - 1) downto 0);
signal d7_1_45: std_logic_vector((1 - 1) downto 0);
signal fully_2_1_bit: std_logic_vector((1 - 1) downto 0);
begin
d0_1_24 <= d0;
d1_1_27 <= d1;
d2_1_30 <= d2;
d3_1_33 <= d3;
d4_1_36 <= d4;
d5_1_39 <= d5;
d6_1_42 <= d6;
d7_1_45 <= d7;
fully_2_1_bit <= d0_1_24 or d1_1_27 or d2_1_30 or d3_1_33 or d4_1_36 or d5_1_39 or d6_1_42 or d7_1_45;
y <= fully_2_1_bit;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_2b3acb49f4 is
port (
in0 : in std_logic_vector((1 - 1) downto 0);
in1 : in std_logic_vector((1 - 1) downto 0);
in2 : in std_logic_vector((1 - 1) downto 0);
in3 : in std_logic_vector((1 - 1) downto 0);
in4 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((5 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end concat_2b3acb49f4;
architecture behavior of concat_2b3acb49f4 is
signal in0_1_23: unsigned((1 - 1) downto 0);
signal in1_1_27: unsigned((1 - 1) downto 0);
signal in2_1_31: unsigned((1 - 1) downto 0);
signal in3_1_35: unsigned((1 - 1) downto 0);
signal in4_1_39: unsigned((1 - 1) downto 0);
signal y_2_1_concat: unsigned((5 - 1) downto 0);
begin
in0_1_23 <= std_logic_vector_to_unsigned(in0);
in1_1_27 <= std_logic_vector_to_unsigned(in1);
in2_1_31 <= std_logic_vector_to_unsigned(in2);
in3_1_35 <= std_logic_vector_to_unsigned(in3);
in4_1_39 <= std_logic_vector_to_unsigned(in4);
y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & unsigned_to_std_logic_vector(in2_1_31) & unsigned_to_std_logic_vector(in3_1_35) & unsigned_to_std_logic_vector(in4_1_39));
y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_6293007044 is
port (
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_6293007044;
architecture behavior of constant_6293007044 is
begin
op <= "1";
end behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.conv_pkg.all;
entity xlslice is
generic (
new_msb : integer := 9;
new_lsb : integer := 1;
x_width : integer := 16;
y_width : integer := 8);
port (
x : in std_logic_vector (x_width-1 downto 0);
y : out std_logic_vector (y_width-1 downto 0));
end xlslice;
architecture behavior of xlslice is
begin
y <= x(new_msb downto new_lsb);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_37567836aa is
port (
op : out std_logic_vector((32 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_37567836aa;
architecture behavior of constant_37567836aa is
begin
op <= "00000000000000000000000000000000";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_2c45f290ed is
port (
sel : in std_logic_vector((1 - 1) downto 0);
d0 : in std_logic_vector((16 - 1) downto 0);
d1 : in std_logic_vector((16 - 1) downto 0);
y : out std_logic_vector((16 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_2c45f290ed;
architecture behavior of mux_2c45f290ed is
signal sel_1_20: std_logic_vector((1 - 1) downto 0);
signal d0_1_24: std_logic_vector((16 - 1) downto 0);
signal d1_1_27: std_logic_vector((16 - 1) downto 0);
signal unregy_join_6_1: std_logic_vector((16 - 1) downto 0);
begin
sel_1_20 <= sel;
d0_1_24 <= d0;
d1_1_27 <= d1;
proc_switch_6_1: process (d0_1_24, d1_1_27, sel_1_20)
is
begin
case sel_1_20 is
when "0" =>
unregy_join_6_1 <= d0_1_24;
when others =>
unregy_join_6_1 <= d1_1_27;
end case;
end process proc_switch_6_1;
y <= unregy_join_6_1;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity logical_b1e9d7c303 is
port (
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end logical_b1e9d7c303;
architecture behavior of logical_b1e9d7c303 is
signal d0_1_24: std_logic_vector((1 - 1) downto 0);
signal d1_1_27: std_logic_vector((1 - 1) downto 0);
signal bit_2_26: std_logic_vector((1 - 1) downto 0);
signal fully_2_1_bitnot: std_logic_vector((1 - 1) downto 0);
begin
d0_1_24 <= d0;
d1_1_27 <= d1;
bit_2_26 <= d0_1_24 or d1_1_27;
fully_2_1_bitnot <= not bit_2_26;
y <= fully_2_1_bitnot;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity accum_2cb0e56e96 is
port (
b : in std_logic_vector((1 - 1) downto 0);
rst : in std_logic_vector((1 - 1) downto 0);
en : in std_logic_vector((1 - 1) downto 0);
q : out std_logic_vector((7 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end accum_2cb0e56e96;
architecture behavior of accum_2cb0e56e96 is
signal b_17_24: unsigned((1 - 1) downto 0);
signal rst_17_27: boolean;
signal en_17_32: boolean;
signal accum_reg_41_23: unsigned((7 - 1) downto 0) := "0000000";
signal accum_reg_41_23_rst: std_logic;
signal accum_reg_41_23_en: std_logic;
signal cast_51_42: unsigned((7 - 1) downto 0);
signal accum_reg_join_47_1: unsigned((8 - 1) downto 0);
signal accum_reg_join_47_1_en: std_logic;
signal accum_reg_join_47_1_rst: std_logic;
begin
b_17_24 <= std_logic_vector_to_unsigned(b);
rst_17_27 <= ((rst) = "1");
en_17_32 <= ((en) = "1");
proc_accum_reg_41_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (accum_reg_41_23_rst = '1')) then
accum_reg_41_23 <= "0000000";
elsif ((ce = '1') and (accum_reg_41_23_en = '1')) then
accum_reg_41_23 <= accum_reg_41_23 + cast_51_42;
end if;
end if;
end process proc_accum_reg_41_23;
cast_51_42 <= u2u_cast(b_17_24, 0, 7, 0);
proc_if_47_1: process (accum_reg_41_23, cast_51_42, en_17_32, rst_17_27)
is
begin
if rst_17_27 then
accum_reg_join_47_1_rst <= '1';
elsif en_17_32 then
accum_reg_join_47_1_rst <= '0';
else
accum_reg_join_47_1_rst <= '0';
end if;
if en_17_32 then
accum_reg_join_47_1_en <= '1';
else
accum_reg_join_47_1_en <= '0';
end if;
end process proc_if_47_1;
accum_reg_41_23_rst <= accum_reg_join_47_1_rst;
accum_reg_41_23_en <= accum_reg_join_47_1_en;
q <= unsigned_to_std_logic_vector(accum_reg_41_23);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity accum_be45dd0aa2 is
port (
b : in std_logic_vector((1 - 1) downto 0);
rst : in std_logic_vector((1 - 1) downto 0);
q : out std_logic_vector((4 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end accum_be45dd0aa2;
architecture behavior of accum_be45dd0aa2 is
signal b_17_24: unsigned((1 - 1) downto 0);
signal rst_17_27: boolean;
signal accum_reg_41_23: unsigned((4 - 1) downto 0) := "0000";
signal accum_reg_41_23_rst: std_logic;
signal cast_51_42: unsigned((4 - 1) downto 0);
signal accum_reg_join_47_1: unsigned((5 - 1) downto 0);
signal accum_reg_join_47_1_rst: std_logic;
begin
b_17_24 <= std_logic_vector_to_unsigned(b);
rst_17_27 <= ((rst) = "1");
proc_accum_reg_41_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (accum_reg_41_23_rst = '1')) then
accum_reg_41_23 <= "0000";
elsif (ce = '1') then
accum_reg_41_23 <= accum_reg_41_23 + cast_51_42;
end if;
end if;
end process proc_accum_reg_41_23;
cast_51_42 <= u2u_cast(b_17_24, 0, 4, 0);
proc_if_47_1: process (accum_reg_41_23, cast_51_42, rst_17_27)
is
begin
if rst_17_27 then
accum_reg_join_47_1_rst <= '1';
else
accum_reg_join_47_1_rst <= '0';
end if;
end process proc_if_47_1;
accum_reg_41_23_rst <= accum_reg_join_47_1_rst;
q <= unsigned_to_std_logic_vector(accum_reg_41_23);
end behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library XilinxCoreLib;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.conv_pkg.all;
entity xladdsub is
generic (
core_name0: string := "";
a_width: integer := 16;
a_bin_pt: integer := 4;
a_arith: integer := xlUnsigned;
c_in_width: integer := 16;
c_in_bin_pt: integer := 4;
c_in_arith: integer := xlUnsigned;
c_out_width: integer := 16;
c_out_bin_pt: integer := 4;
c_out_arith: integer := xlUnsigned;
b_width: integer := 8;
b_bin_pt: integer := 2;
b_arith: integer := xlUnsigned;
s_width: integer := 17;
s_bin_pt: integer := 4;
s_arith: integer := xlUnsigned;
rst_width: integer := 1;
rst_bin_pt: integer := 0;
rst_arith: integer := xlUnsigned;
en_width: integer := 1;
en_bin_pt: integer := 0;
en_arith: integer := xlUnsigned;
full_s_width: integer := 17;
full_s_arith: integer := xlUnsigned;
mode: integer := xlAddMode;
extra_registers: integer := 0;
latency: integer := 0;
quantization: integer := xlTruncate;
overflow: integer := xlWrap;
c_latency: integer := 0;
c_output_width: integer := 17;
c_has_q : integer := 1;
c_has_s : integer := 0;
c_has_c_out : integer := 0;
c_has_q_c_out : integer := 0;
c_has_b_out : integer := 0;
c_has_q_b_out : integer := 0;
c_has_q_ovfl : integer := 0;
c_has_ovfl : integer := 0
);
port (
a: in std_logic_vector(a_width - 1 downto 0);
b: in std_logic_vector(b_width - 1 downto 0);
c_in : in std_logic_vector (0 downto 0) := "0";
ce: in std_logic;
clr: in std_logic := '0';
clk: in std_logic;
rst: in std_logic_vector(rst_width - 1 downto 0) := "0";
en: in std_logic_vector(en_width - 1 downto 0) := "1";
c_out : out std_logic_vector (0 downto 0);
s: out std_logic_vector(s_width - 1 downto 0)
);
end xladdsub ;
architecture behavior of xladdsub is
component synth_reg
generic (
width: integer := 16;
latency: integer := 5
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
function format_input(inp: std_logic_vector; old_width, delta, new_arith,
new_width: integer)
return std_logic_vector
is
variable vec: std_logic_vector(old_width-1 downto 0);
variable padded_inp: std_logic_vector((old_width + delta)-1 downto 0);
variable result: std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if delta > 0 then
padded_inp := pad_LSB(vec, old_width+delta);
result := extend_MSB(padded_inp, new_width, new_arith);
else
result := extend_MSB(vec, new_width, new_arith);
end if;
return result;
end;
constant full_s_bin_pt: integer := fractional_bits(a_bin_pt, b_bin_pt);
constant full_a_width: integer := full_s_width;
constant full_b_width: integer := full_s_width;
signal full_a: std_logic_vector(full_a_width - 1 downto 0);
signal full_b: std_logic_vector(full_b_width - 1 downto 0);
signal core_s: std_logic_vector(full_s_width - 1 downto 0);
signal conv_s: std_logic_vector(s_width - 1 downto 0);
signal temp_cout : std_logic;
signal internal_clr: std_logic;
signal internal_ce: std_logic;
signal extra_reg_ce: std_logic;
signal override: std_logic;
signal logic1: std_logic_vector(0 downto 0);
component adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3
port (
a: in std_logic_vector( 9 - 1 downto 0);
s: out std_logic_vector(c_output_width - 1 downto 0);
b: in std_logic_vector(9 - 1 downto 0)
);
end component;
attribute syn_black_box of adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3:
component is true;
attribute fpga_dont_touch of adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3:
component is "true";
attribute box_type of adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3:
component is "black_box";
component adder_subtracter_virtex2p_7_0_453ed16ba8e84295
port (
a: in std_logic_vector( 9 - 1 downto 0);
s: out std_logic_vector(c_output_width - 1 downto 0);
b: in std_logic_vector(9 - 1 downto 0)
);
end component;
attribute syn_black_box of adder_subtracter_virtex2p_7_0_453ed16ba8e84295:
component is true;
attribute fpga_dont_touch of adder_subtracter_virtex2p_7_0_453ed16ba8e84295:
component is "true";
attribute box_type of adder_subtracter_virtex2p_7_0_453ed16ba8e84295:
component is "black_box";
component adder_subtracter_virtex2p_7_0_7182743c9e7adf5e
port (
a: in std_logic_vector( 5 - 1 downto 0);
s: out std_logic_vector(c_output_width - 1 downto 0);
b: in std_logic_vector(5 - 1 downto 0)
);
end component;
attribute syn_black_box of adder_subtracter_virtex2p_7_0_7182743c9e7adf5e:
component is true;
attribute fpga_dont_touch of adder_subtracter_virtex2p_7_0_7182743c9e7adf5e:
component is "true";
attribute box_type of adder_subtracter_virtex2p_7_0_7182743c9e7adf5e:
component is "black_box";
begin
internal_clr <= (clr or (rst(0))) and ce;
internal_ce <= ce and en(0);
logic1(0) <= '1';
addsub_process: process(a, b, core_s)
begin
full_a <= format_input(a, a_width, b_bin_pt - a_bin_pt, a_arith,
full_a_width);
full_b <= format_input(b, b_width, a_bin_pt - b_bin_pt, b_arith,
full_b_width);
conv_s <= convert_type(core_s, full_s_width, full_s_bin_pt, full_s_arith,
s_width, s_bin_pt, s_arith, quantization, overflow);
end process addsub_process;
comp0: if ((core_name0 = "adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3")) generate
core_instance0: adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3
port map (
a => full_a,
s => core_s,
b => full_b
);
end generate;
comp1: if ((core_name0 = "adder_subtracter_virtex2p_7_0_453ed16ba8e84295")) generate
core_instance1: adder_subtracter_virtex2p_7_0_453ed16ba8e84295
port map (
a => full_a,
s => core_s,
b => full_b
);
end generate;
comp2: if ((core_name0 = "adder_subtracter_virtex2p_7_0_7182743c9e7adf5e")) generate
core_instance2: adder_subtracter_virtex2p_7_0_7182743c9e7adf5e
port map (
a => full_a,
s => core_s,
b => full_b
);
end generate;
latency_test: if (extra_registers > 0) generate
override_test: if (c_latency > 1) generate
override_pipe: synth_reg
generic map (
width => 1,
latency => c_latency)
port map (
i => logic1,
ce => internal_ce,
clr => internal_clr,
clk => clk,
o(0) => override);
extra_reg_ce <= ce and en(0) and override;
end generate override_test;
no_override: if (c_latency = 0) or (c_latency = 1) generate
extra_reg_ce <= ce and en(0);
end generate no_override;
extra_reg: synth_reg
generic map (
width => s_width,
latency => extra_registers
)
port map (
i => conv_s,
ce => extra_reg_ce,
clr => internal_clr,
clk => clk,
o => s
);
cout_test : if((c_has_c_out = 1) or
(c_has_b_out = 1) or
(c_has_q_c_out = 1) or
(c_has_q_b_out = 1)) generate
c_out_extra_reg: synth_reg
generic map (
width => 1,
latency => extra_registers
)
port map (
i(0) => temp_cout,
ce => extra_reg_ce,
clr => internal_clr,
clk => clk,
o => c_out
);
end generate cout_test;
end generate;
latency_s: if ((latency = 0) or (extra_registers = 0)) generate
s <= conv_s;
end generate latency_s;
latency0: if ( ((latency = 0) or (extra_registers = 0)) and
((c_has_b_out = 1) or
(c_has_q_c_out = 1) or
(c_has_c_out = 1) or
(c_has_q_b_out = 1))) generate
c_out(0) <= temp_cout;
end generate latency0;
tie_dangling_cout: if ((c_has_c_out = 0) and
(c_has_b_out = 0) and
(c_has_q_c_out = 0) and
(c_has_q_b_out = 0)) generate
c_out <= "0";
end generate tie_dangling_cout;
end architecture behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_f62149b02a is
port (
in0 : in std_logic_vector((2 - 1) downto 0);
in1 : in std_logic_vector((7 - 1) downto 0);
y : out std_logic_vector((9 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end concat_f62149b02a;
architecture behavior of concat_f62149b02a is
signal in0_1_23: unsigned((2 - 1) downto 0);
signal in1_1_27: unsigned((7 - 1) downto 0);
signal y_2_1_concat: unsigned((9 - 1) downto 0);
begin
in0_1_23 <= std_logic_vector_to_unsigned(in0);
in1_1_27 <= std_logic_vector_to_unsigned(in1);
y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27));
y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_1ece14600f is
port (
in0 : in std_logic_vector((1 - 1) downto 0);
in1 : in std_logic_vector((8 - 1) downto 0);
y : out std_logic_vector((9 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end concat_1ece14600f;
architecture behavior of concat_1ece14600f is
signal in0_1_23: unsigned((1 - 1) downto 0);
signal in1_1_27: unsigned((8 - 1) downto 0);
signal y_2_1_concat: unsigned((9 - 1) downto 0);
begin
in0_1_23 <= std_logic_vector_to_unsigned(in0);
in1_1_27 <= std_logic_vector_to_unsigned(in1);
y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27));
y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_443ed96427 is
port (
op : out std_logic_vector((9 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_443ed96427;
architecture behavior of constant_443ed96427 is
begin
op <= "101011100";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_145086465d is
port (
op : out std_logic_vector((4 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_145086465d;
architecture behavior of constant_145086465d is
begin
op <= "1000";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_fb9f6d3796 is
port (
op : out std_logic_vector((9 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_fb9f6d3796;
architecture behavior of constant_fb9f6d3796 is
begin
op <= "100010101";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_09a4afb2ee is
port (
op : out std_logic_vector((9 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_09a4afb2ee;
architecture behavior of constant_09a4afb2ee is
begin
op <= "101110101";
end behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library XilinxCoreLib;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity xlcounter_limit is
generic (
core_name0: string := "";
op_width: integer := 5;
op_arith: integer := xlSigned;
cnt_63_48: integer:= 0;
cnt_47_32: integer:= 0;
cnt_31_16: integer:= 0;
cnt_15_0: integer:= 0;
count_limited: integer := 0
);
port (
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
op: out std_logic_vector(op_width - 1 downto 0);
up: in std_logic_vector(0 downto 0) := (others => '0');
en: in std_logic_vector(0 downto 0);
rst: in std_logic_vector(0 downto 0)
);
end xlcounter_limit ;
architecture behavior of xlcounter_limit is
signal high_cnt_to: std_logic_vector(31 downto 0);
signal low_cnt_to: std_logic_vector(31 downto 0);
signal cnt_to: std_logic_vector(63 downto 0);
signal core_sinit, op_thresh0, core_ce: std_logic;
signal rst_overrides_en: std_logic;
signal op_net: std_logic_vector(op_width - 1 downto 0);
-- synopsys translate_off
signal real_op : real;
-- synopsys translate_on
function equals(op, cnt_to : std_logic_vector; width, arith : integer)
return std_logic
is
variable signed_op, signed_cnt_to : signed (width - 1 downto 0);
variable unsigned_op, unsigned_cnt_to : unsigned (width - 1 downto 0);
variable result : std_logic;
begin
-- synopsys translate_off
if ((is_XorU(op)) or (is_XorU(cnt_to)) ) then
result := '0';
return result;
end if;
-- synopsys translate_on
if (op = cnt_to) then
result := '1';
else
result := '0';
end if;
return result;
end;
component binary_counter_virtex2p_7_0_32a1863440903b9d
port (
clk: in std_logic;
ce: in std_logic;
sinit: in std_logic;
q: out std_logic_vector(op_width - 1 downto 0)
);
end component;
attribute syn_black_box of binary_counter_virtex2p_7_0_32a1863440903b9d:
component is true;
attribute fpga_dont_touch of binary_counter_virtex2p_7_0_32a1863440903b9d:
component is "true";
attribute box_type of binary_counter_virtex2p_7_0_32a1863440903b9d:
component is "black_box";
component binary_counter_virtex2p_7_0_23542cbcca0efa2e
port (
clk: in std_logic;
ce: in std_logic;
sinit: in std_logic;
q: out std_logic_vector(op_width - 1 downto 0)
);
end component;
attribute syn_black_box of binary_counter_virtex2p_7_0_23542cbcca0efa2e:
component is true;
attribute fpga_dont_touch of binary_counter_virtex2p_7_0_23542cbcca0efa2e:
component is "true";
attribute box_type of binary_counter_virtex2p_7_0_23542cbcca0efa2e:
component is "black_box";
-- synopsys translate_off
constant zeroVec : std_logic_vector(op_width - 1 downto 0) := (others => '0');
constant oneVec : std_logic_vector(op_width - 1 downto 0) := (others => '1');
constant zeroStr : string(1 to op_width) :=
std_logic_vector_to_bin_string(zeroVec);
constant oneStr : string(1 to op_width) :=
std_logic_vector_to_bin_string(oneVec);
-- synopsys translate_on
begin
-- synopsys translate_off
-- synopsys translate_on
cnt_to(63 downto 48) <= integer_to_std_logic_vector(cnt_63_48, 16, op_arith);
cnt_to(47 downto 32) <= integer_to_std_logic_vector(cnt_47_32, 16, op_arith);
cnt_to(31 downto 16) <= integer_to_std_logic_vector(cnt_31_16, 16, op_arith);
cnt_to(15 downto 0) <= integer_to_std_logic_vector(cnt_15_0, 16, op_arith);
op <= op_net;
core_ce <= ce and en(0);
rst_overrides_en <= rst(0) or en(0);
limit : if (count_limited = 1) generate
eq_cnt_to : process (op_net, cnt_to)
begin
op_thresh0 <= equals(op_net, cnt_to(op_width - 1 downto 0),
op_width, op_arith);
end process;
core_sinit <= (op_thresh0 or clr or rst(0)) and ce and rst_overrides_en;
end generate;
no_limit : if (count_limited = 0) generate
core_sinit <= (clr or rst(0)) and ce and rst_overrides_en;
end generate;
comp0: if ((core_name0 = "binary_counter_virtex2p_7_0_32a1863440903b9d")) generate
core_instance0: binary_counter_virtex2p_7_0_32a1863440903b9d
port map (
clk => clk,
ce => core_ce,
sinit => core_sinit,
q => op_net
);
end generate;
comp1: if ((core_name0 = "binary_counter_virtex2p_7_0_23542cbcca0efa2e")) generate
core_instance1: binary_counter_virtex2p_7_0_23542cbcca0efa2e
port map (
clk => clk,
ce => core_ce,
sinit => core_sinit,
q => op_net
);
end generate;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity inverter_e5b38cca3b is
port (
ip : in std_logic_vector((1 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end inverter_e5b38cca3b;
architecture behavior of inverter_e5b38cca3b is
signal ip_1_26: boolean;
type array_type_op_mem_22_20 is array (0 to (1 - 1)) of boolean;
signal op_mem_22_20: array_type_op_mem_22_20 := (
0 => false);
signal op_mem_22_20_front_din: boolean;
signal op_mem_22_20_back: boolean;
signal op_mem_22_20_push_front_pop_back_en: std_logic;
signal internal_ip_12_1_bitnot: boolean;
begin
ip_1_26 <= ((ip) = "1");
op_mem_22_20_back <= op_mem_22_20(0);
proc_op_mem_22_20: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_22_20_push_front_pop_back_en = '1')) then
op_mem_22_20(0) <= op_mem_22_20_front_din;
end if;
end if;
end process proc_op_mem_22_20;
internal_ip_12_1_bitnot <= ((not boolean_to_vector(ip_1_26)) = "1");
op_mem_22_20_push_front_pop_back_en <= '0';
op <= boolean_to_vector(internal_ip_12_1_bitnot);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity logical_aacf6e1b0e is
port (
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end logical_aacf6e1b0e;
architecture behavior of logical_aacf6e1b0e is
signal d0_1_24: std_logic;
signal d1_1_27: std_logic;
signal fully_2_1_bit: std_logic;
begin
d0_1_24 <= d0(0);
d1_1_27 <= d1(0);
fully_2_1_bit <= d0_1_24 or d1_1_27;
y <= std_logic_to_vector(fully_2_1_bit);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity logical_80f90b97d0 is
port (
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end logical_80f90b97d0;
architecture behavior of logical_80f90b97d0 is
signal d0_1_24: std_logic;
signal d1_1_27: std_logic;
signal fully_2_1_bit: std_logic;
begin
d0_1_24 <= d0(0);
d1_1_27 <= d1(0);
fully_2_1_bit <= d0_1_24 and d1_1_27;
y <= std_logic_to_vector(fully_2_1_bit);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_d99e59b6d4 is
port (
sel : in std_logic_vector((1 - 1) downto 0);
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_d99e59b6d4;
architecture behavior of mux_d99e59b6d4 is
signal sel_1_20: std_logic;
signal d0_1_24: std_logic;
signal d1_1_27: std_logic;
signal sel_internal_2_1_convert: std_logic_vector((1 - 1) downto 0);
signal unregy_join_6_1: std_logic;
begin
sel_1_20 <= sel(0);
d0_1_24 <= d0(0);
d1_1_27 <= d1(0);
sel_internal_2_1_convert <= cast(std_logic_to_vector(sel_1_20), 0, 1, 0, xlUnsigned);
proc_switch_6_1: process (d0_1_24, d1_1_27, sel_internal_2_1_convert)
is
begin
case sel_internal_2_1_convert is
when "0" =>
unregy_join_6_1 <= d0_1_24;
when others =>
unregy_join_6_1 <= d1_1_27;
end case;
end process proc_switch_6_1;
y <= std_logic_to_vector(unregy_join_6_1);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_1f00a411aa is
port (
sel : in std_logic_vector((4 - 1) downto 0);
d0 : in std_logic_vector((9 - 1) downto 0);
d1 : in std_logic_vector((9 - 1) downto 0);
d2 : in std_logic_vector((9 - 1) downto 0);
d3 : in std_logic_vector((9 - 1) downto 0);
d4 : in std_logic_vector((9 - 1) downto 0);
d5 : in std_logic_vector((9 - 1) downto 0);
d6 : in std_logic_vector((9 - 1) downto 0);
d7 : in std_logic_vector((9 - 1) downto 0);
d8 : in std_logic_vector((9 - 1) downto 0);
y : out std_logic_vector((9 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_1f00a411aa;
architecture behavior of mux_1f00a411aa is
signal sel_1_20: std_logic_vector((4 - 1) downto 0);
signal d0_1_24: std_logic_vector((9 - 1) downto 0);
signal d1_1_27: std_logic_vector((9 - 1) downto 0);
signal d2_1_30: std_logic_vector((9 - 1) downto 0);
signal d3_1_33: std_logic_vector((9 - 1) downto 0);
signal d4_1_36: std_logic_vector((9 - 1) downto 0);
signal d5_1_39: std_logic_vector((9 - 1) downto 0);
signal d6_1_42: std_logic_vector((9 - 1) downto 0);
signal d7_1_45: std_logic_vector((9 - 1) downto 0);
signal d8_1_48: std_logic_vector((9 - 1) downto 0);
signal unregy_join_6_1: std_logic_vector((9 - 1) downto 0);
begin
sel_1_20 <= sel;
d0_1_24 <= d0;
d1_1_27 <= d1;
d2_1_30 <= d2;
d3_1_33 <= d3;
d4_1_36 <= d4;
d5_1_39 <= d5;
d6_1_42 <= d6;
d7_1_45 <= d7;
d8_1_48 <= d8;
proc_switch_6_1: process (d0_1_24, d1_1_27, d2_1_30, d3_1_33, d4_1_36, d5_1_39, d6_1_42, d7_1_45, d8_1_48, sel_1_20)
is
begin
case sel_1_20 is
when "0000" =>
unregy_join_6_1 <= d0_1_24;
when "0001" =>
unregy_join_6_1 <= d1_1_27;
when "0010" =>
unregy_join_6_1 <= d2_1_30;
when "0011" =>
unregy_join_6_1 <= d3_1_33;
when "0100" =>
unregy_join_6_1 <= d4_1_36;
when "0101" =>
unregy_join_6_1 <= d5_1_39;
when "0110" =>
unregy_join_6_1 <= d6_1_42;
when "0111" =>
unregy_join_6_1 <= d7_1_45;
when others =>
unregy_join_6_1 <= d8_1_48;
end case;
end process proc_switch_6_1;
y <= unregy_join_6_1;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity relational_92c392c8b6 is
port (
a : in std_logic_vector((7 - 1) downto 0);
b : in std_logic_vector((9 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end relational_92c392c8b6;
architecture behavior of relational_92c392c8b6 is
signal a_1_31: unsigned((7 - 1) downto 0);
signal b_1_34: signed((9 - 1) downto 0);
type array_type_op_mem_32_22 is array (0 to (1 - 1)) of boolean;
signal op_mem_32_22: array_type_op_mem_32_22 := (
0 => false);
signal op_mem_32_22_front_din: boolean;
signal op_mem_32_22_back: boolean;
signal op_mem_32_22_push_front_pop_back_en: std_logic;
signal cast_20_12: signed((9 - 1) downto 0);
signal result_20_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_unsigned(a);
b_1_34 <= std_logic_vector_to_signed(b);
op_mem_32_22_back <= op_mem_32_22(0);
proc_op_mem_32_22: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_32_22_push_front_pop_back_en = '1')) then
op_mem_32_22(0) <= op_mem_32_22_front_din;
end if;
end if;
end process proc_op_mem_32_22;
cast_20_12 <= u2s_cast(a_1_31, 0, 9, 0);
result_20_3_rel <= cast_20_12 <= b_1_34;
op_mem_32_22_front_din <= result_20_3_rel;
op_mem_32_22_push_front_pop_back_en <= '1';
op <= boolean_to_vector(op_mem_32_22_back);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity relational_fb96203f91 is
port (
a : in std_logic_vector((4 - 1) downto 0);
b : in std_logic_vector((4 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end relational_fb96203f91;
architecture behavior of relational_fb96203f91 is
signal a_1_31: unsigned((4 - 1) downto 0);
signal b_1_34: unsigned((4 - 1) downto 0);
signal result_16_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_unsigned(a);
b_1_34 <= std_logic_vector_to_unsigned(b);
result_16_3_rel <= a_1_31 < b_1_34;
op <= boolean_to_vector(result_16_3_rel);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_998e20a1ca is
port (
sel : in std_logic_vector((2 - 1) downto 0);
d0 : in std_logic_vector((8 - 1) downto 0);
d1 : in std_logic_vector((8 - 1) downto 0);
d2 : in std_logic_vector((8 - 1) downto 0);
d3 : in std_logic_vector((8 - 1) downto 0);
y : out std_logic_vector((8 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_998e20a1ca;
architecture behavior of mux_998e20a1ca is
signal sel_1_20: std_logic_vector((2 - 1) downto 0);
signal d0_1_24: std_logic_vector((8 - 1) downto 0);
signal d1_1_27: std_logic_vector((8 - 1) downto 0);
signal d2_1_30: std_logic_vector((8 - 1) downto 0);
signal d3_1_33: std_logic_vector((8 - 1) downto 0);
signal unregy_join_6_1: std_logic_vector((8 - 1) downto 0);
begin
sel_1_20 <= sel;
d0_1_24 <= d0;
d1_1_27 <= d1;
d2_1_30 <= d2;
d3_1_33 <= d3;
proc_switch_6_1: process (d0_1_24, d1_1_27, d2_1_30, d3_1_33, sel_1_20)
is
begin
case sel_1_20 is
when "00" =>
unregy_join_6_1 <= d0_1_24;
when "01" =>
unregy_join_6_1 <= d1_1_27;
when "10" =>
unregy_join_6_1 <= d2_1_30;
when others =>
unregy_join_6_1 <= d3_1_33;
end case;
end process proc_switch_6_1;
y <= unregy_join_6_1;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_32864ba5d6 is
port (
in0 : in std_logic_vector((4 - 1) downto 0);
in1 : in std_logic_vector((3 - 1) downto 0);
y : out std_logic_vector((7 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end concat_32864ba5d6;
architecture behavior of concat_32864ba5d6 is
signal in0_1_23: unsigned((4 - 1) downto 0);
signal in1_1_27: unsigned((3 - 1) downto 0);
signal y_2_1_concat: unsigned((7 - 1) downto 0);
begin
in0_1_23 <= std_logic_vector_to_unsigned(in0);
in1_1_27 <= std_logic_vector_to_unsigned(in1);
y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27));
y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_822933f89b is
port (
op : out std_logic_vector((3 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_822933f89b;
architecture behavior of constant_822933f89b is
begin
op <= "000";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_21d4a28b7e is
port (
op : out std_logic_vector((8 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_21d4a28b7e;
architecture behavior of constant_21d4a28b7e is
begin
op <= "00000011";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_b940b9054a is
port (
op : out std_logic_vector((8 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_b940b9054a;
architecture behavior of constant_b940b9054a is
begin
op <= "00001010";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_78218439f3 is
port (
in0 : in std_logic_vector((3 - 1) downto 0);
in1 : in std_logic_vector((4 - 1) downto 0);
in2 : in std_logic_vector((4 - 1) downto 0);
y : out std_logic_vector((11 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end concat_78218439f3;
architecture behavior of concat_78218439f3 is
signal in0_1_23: unsigned((3 - 1) downto 0);
signal in1_1_27: unsigned((4 - 1) downto 0);
signal in2_1_31: unsigned((4 - 1) downto 0);
signal y_2_1_concat: unsigned((11 - 1) downto 0);
begin
in0_1_23 <= std_logic_vector_to_unsigned(in0);
in1_1_27 <= std_logic_vector_to_unsigned(in1);
in2_1_31 <= std_logic_vector_to_unsigned(in2);
y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & unsigned_to_std_logic_vector(in2_1_31));
y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_25ab81b400 is
port (
in0 : in std_logic_vector((8 - 1) downto 0);
in1 : in std_logic_vector((6 - 1) downto 0);
y : out std_logic_vector((14 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end concat_25ab81b400;
architecture behavior of concat_25ab81b400 is
signal in0_1_23: unsigned((8 - 1) downto 0);
signal in1_1_27: unsigned((6 - 1) downto 0);
signal y_2_1_concat: unsigned((14 - 1) downto 0);
begin
in0_1_23 <= std_logic_vector_to_unsigned(in0);
in1_1_27 <= std_logic_vector_to_unsigned(in1);
y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27));
y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_e6f5ee726b is
port (
in0 : in std_logic_vector((1 - 1) downto 0);
in1 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((2 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end concat_e6f5ee726b;
architecture behavior of concat_e6f5ee726b is
signal in0_1_23: unsigned((1 - 1) downto 0);
signal in1_1_27: unsigned((1 - 1) downto 0);
signal y_2_1_concat: unsigned((2 - 1) downto 0);
begin
in0_1_23 <= std_logic_vector_to_unsigned(in0);
in1_1_27 <= std_logic_vector_to_unsigned(in1);
y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27));
y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_469094441c is
port (
op : out std_logic_vector((3 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_469094441c;
architecture behavior of constant_469094441c is
begin
op <= "100";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_a1c496ea88 is
port (
op : out std_logic_vector((3 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_a1c496ea88;
architecture behavior of constant_a1c496ea88 is
begin
op <= "001";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_2ec2057ae3 is
port (
sel : in std_logic_vector((2 - 1) downto 0);
d0 : in std_logic_vector((3 - 1) downto 0);
d1 : in std_logic_vector((3 - 1) downto 0);
d2 : in std_logic_vector((3 - 1) downto 0);
d3 : in std_logic_vector((3 - 1) downto 0);
y : out std_logic_vector((3 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_2ec2057ae3;
architecture behavior of mux_2ec2057ae3 is
signal sel_1_20: std_logic_vector((2 - 1) downto 0);
signal d0_1_24: std_logic_vector((3 - 1) downto 0);
signal d1_1_27: std_logic_vector((3 - 1) downto 0);
signal d2_1_30: std_logic_vector((3 - 1) downto 0);
signal d3_1_33: std_logic_vector((3 - 1) downto 0);
signal unregy_join_6_1: std_logic_vector((3 - 1) downto 0);
begin
sel_1_20 <= sel;
d0_1_24 <= d0;
d1_1_27 <= d1;
d2_1_30 <= d2;
d3_1_33 <= d3;
proc_switch_6_1: process (d0_1_24, d1_1_27, d2_1_30, d3_1_33, sel_1_20)
is
begin
case sel_1_20 is
when "00" =>
unregy_join_6_1 <= d0_1_24;
when "01" =>
unregy_join_6_1 <= d1_1_27;
when "10" =>
unregy_join_6_1 <= d2_1_30;
when others =>
unregy_join_6_1 <= d3_1_33;
end case;
end process proc_switch_6_1;
y <= unregy_join_6_1;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_7586447000 is
port (
sel : in std_logic_vector((3 - 1) downto 0);
d0 : in std_logic_vector((9 - 1) downto 0);
d1 : in std_logic_vector((9 - 1) downto 0);
d2 : in std_logic_vector((9 - 1) downto 0);
d3 : in std_logic_vector((9 - 1) downto 0);
d4 : in std_logic_vector((9 - 1) downto 0);
d5 : in std_logic_vector((9 - 1) downto 0);
d6 : in std_logic_vector((9 - 1) downto 0);
d7 : in std_logic_vector((9 - 1) downto 0);
y : out std_logic_vector((9 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_7586447000;
architecture behavior of mux_7586447000 is
signal sel_1_20: std_logic_vector((3 - 1) downto 0);
signal d0_1_24: std_logic_vector((9 - 1) downto 0);
signal d1_1_27: std_logic_vector((9 - 1) downto 0);
signal d2_1_30: std_logic_vector((9 - 1) downto 0);
signal d3_1_33: std_logic_vector((9 - 1) downto 0);
signal d4_1_36: std_logic_vector((9 - 1) downto 0);
signal d5_1_39: std_logic_vector((9 - 1) downto 0);
signal d6_1_42: std_logic_vector((9 - 1) downto 0);
signal d7_1_45: std_logic_vector((9 - 1) downto 0);
signal unregy_join_6_1: std_logic_vector((9 - 1) downto 0);
begin
sel_1_20 <= sel;
d0_1_24 <= d0;
d1_1_27 <= d1;
d2_1_30 <= d2;
d3_1_33 <= d3;
d4_1_36 <= d4;
d5_1_39 <= d5;
d6_1_42 <= d6;
d7_1_45 <= d7;
proc_switch_6_1: process (d0_1_24, d1_1_27, d2_1_30, d3_1_33, d4_1_36, d5_1_39, d6_1_42, d7_1_45, sel_1_20)
is
begin
case sel_1_20 is
when "000" =>
unregy_join_6_1 <= d0_1_24;
when "001" =>
unregy_join_6_1 <= d1_1_27;
when "010" =>
unregy_join_6_1 <= d2_1_30;
when "011" =>
unregy_join_6_1 <= d3_1_33;
when "100" =>
unregy_join_6_1 <= d4_1_36;
when "101" =>
unregy_join_6_1 <= d5_1_39;
when "110" =>
unregy_join_6_1 <= d6_1_42;
when others =>
unregy_join_6_1 <= d7_1_45;
end case;
end process proc_switch_6_1;
y <= unregy_join_6_1;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity relational_f7cb2b0c31 is
port (
a : in std_logic_vector((6 - 1) downto 0);
b : in std_logic_vector((1 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end relational_f7cb2b0c31;
architecture behavior of relational_f7cb2b0c31 is
signal a_1_31: unsigned((6 - 1) downto 0);
signal b_1_34: unsigned((1 - 1) downto 0);
signal cast_12_17: unsigned((6 - 1) downto 0);
signal result_12_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_unsigned(a);
b_1_34 <= std_logic_vector_to_unsigned(b);
cast_12_17 <= u2u_cast(b_1_34, 0, 6, 0);
result_12_3_rel <= a_1_31 = cast_12_17;
op <= boolean_to_vector(result_12_3_rel);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity relational_ee03197e2c is
port (
a : in std_logic_vector((4 - 1) downto 0);
b : in std_logic_vector((1 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end relational_ee03197e2c;
architecture behavior of relational_ee03197e2c is
signal a_1_31: unsigned((4 - 1) downto 0);
signal b_1_34: unsigned((1 - 1) downto 0);
signal cast_12_17: unsigned((4 - 1) downto 0);
signal result_12_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_unsigned(a);
b_1_34 <= std_logic_vector_to_unsigned(b);
cast_12_17 <= u2u_cast(b_1_34, 0, 4, 0);
result_12_3_rel <= a_1_31 = cast_12_17;
op <= boolean_to_vector(result_12_3_rel);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity relational_04b069dd89 is
port (
a : in std_logic_vector((3 - 1) downto 0);
b : in std_logic_vector((1 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end relational_04b069dd89;
architecture behavior of relational_04b069dd89 is
signal a_1_31: unsigned((3 - 1) downto 0);
signal b_1_34: unsigned((1 - 1) downto 0);
signal cast_12_17: unsigned((3 - 1) downto 0);
signal result_12_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_unsigned(a);
b_1_34 <= std_logic_vector_to_unsigned(b);
cast_12_17 <= u2u_cast(b_1_34, 0, 3, 0);
result_12_3_rel <= a_1_31 = cast_12_17;
op <= boolean_to_vector(result_12_3_rel);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_8e3eece8f2 is
port (
sel : in std_logic_vector((4 - 1) downto 0);
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
d2 : in std_logic_vector((1 - 1) downto 0);
d3 : in std_logic_vector((1 - 1) downto 0);
d4 : in std_logic_vector((1 - 1) downto 0);
d5 : in std_logic_vector((1 - 1) downto 0);
d6 : in std_logic_vector((1 - 1) downto 0);
d7 : in std_logic_vector((1 - 1) downto 0);
d8 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_8e3eece8f2;
architecture behavior of mux_8e3eece8f2 is
signal sel_1_20: std_logic_vector((4 - 1) downto 0);
signal d0_1_24: std_logic_vector((1 - 1) downto 0);
signal d1_1_27: std_logic_vector((1 - 1) downto 0);
signal d2_1_30: std_logic_vector((1 - 1) downto 0);
signal d3_1_33: std_logic_vector((1 - 1) downto 0);
signal d4_1_36: std_logic_vector((1 - 1) downto 0);
signal d5_1_39: std_logic_vector((1 - 1) downto 0);
signal d6_1_42: std_logic_vector((1 - 1) downto 0);
signal d7_1_45: std_logic_vector((1 - 1) downto 0);
signal d8_1_48: std_logic_vector((1 - 1) downto 0);
type array_type_pipe_30_22 is array (0 to (1 - 1)) of std_logic_vector((1 - 1) downto 0);
signal pipe_30_22: array_type_pipe_30_22 := (
0 => "0");
signal pipe_30_22_front_din: std_logic_vector((1 - 1) downto 0);
signal pipe_30_22_back: std_logic_vector((1 - 1) downto 0);
signal pipe_30_22_push_front_pop_back_en: std_logic;
signal unregy_join_6_1: std_logic_vector((1 - 1) downto 0);
begin
sel_1_20 <= sel;
d0_1_24 <= d0;
d1_1_27 <= d1;
d2_1_30 <= d2;
d3_1_33 <= d3;
d4_1_36 <= d4;
d5_1_39 <= d5;
d6_1_42 <= d6;
d7_1_45 <= d7;
d8_1_48 <= d8;
pipe_30_22_back <= pipe_30_22(0);
proc_pipe_30_22: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (pipe_30_22_push_front_pop_back_en = '1')) then
pipe_30_22(0) <= pipe_30_22_front_din;
end if;
end if;
end process proc_pipe_30_22;
proc_switch_6_1: process (d0_1_24, d1_1_27, d2_1_30, d3_1_33, d4_1_36, d5_1_39, d6_1_42, d7_1_45, d8_1_48, sel_1_20)
is
begin
case sel_1_20 is
when "0000" =>
unregy_join_6_1 <= d0_1_24;
when "0001" =>
unregy_join_6_1 <= d1_1_27;
when "0010" =>
unregy_join_6_1 <= d2_1_30;
when "0011" =>
unregy_join_6_1 <= d3_1_33;
when "0100" =>
unregy_join_6_1 <= d4_1_36;
when "0101" =>
unregy_join_6_1 <= d5_1_39;
when "0110" =>
unregy_join_6_1 <= d6_1_42;
when "0111" =>
unregy_join_6_1 <= d7_1_45;
when others =>
unregy_join_6_1 <= d8_1_48;
end case;
end process proc_switch_6_1;
pipe_30_22_front_din <= unregy_join_6_1;
pipe_30_22_push_front_pop_back_en <= '1';
y <= pipe_30_22_back;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity logical_938d99ac11 is
port (
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end logical_938d99ac11;
architecture behavior of logical_938d99ac11 is
signal d0_1_24: std_logic_vector((1 - 1) downto 0);
signal d1_1_27: std_logic_vector((1 - 1) downto 0);
signal fully_2_1_bit: std_logic_vector((1 - 1) downto 0);
begin
d0_1_24 <= d0;
d1_1_27 <= d1;
fully_2_1_bit <= d0_1_24 and d1_1_27;
y <= fully_2_1_bit;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_06590e4008 is
port (
op : out std_logic_vector((4 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_06590e4008;
architecture behavior of constant_06590e4008 is
begin
op <= "1111";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_112ed141f4 is
port (
sel : in std_logic_vector((1 - 1) downto 0);
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_112ed141f4;
architecture behavior of mux_112ed141f4 is
signal sel_1_20: std_logic;
signal d0_1_24: std_logic_vector((1 - 1) downto 0);
signal d1_1_27: std_logic_vector((1 - 1) downto 0);
signal sel_internal_2_1_convert: std_logic_vector((1 - 1) downto 0);
signal unregy_join_6_1: std_logic_vector((1 - 1) downto 0);
begin
sel_1_20 <= sel(0);
d0_1_24 <= d0;
d1_1_27 <= d1;
sel_internal_2_1_convert <= cast(std_logic_to_vector(sel_1_20), 0, 1, 0, xlUnsigned);
proc_switch_6_1: process (d0_1_24, d1_1_27, sel_internal_2_1_convert)
is
begin
case sel_internal_2_1_convert is
when "0" =>
unregy_join_6_1 <= d0_1_24;
when others =>
unregy_join_6_1 <= d1_1_27;
end case;
end process proc_switch_6_1;
y <= unregy_join_6_1;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity logical_3e1f051fb7 is
port (
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end logical_3e1f051fb7;
architecture behavior of logical_3e1f051fb7 is
signal d0_1_24: std_logic_vector((1 - 1) downto 0);
signal d1_1_27: std_logic_vector((1 - 1) downto 0);
signal fully_2_1_bit: std_logic_vector((1 - 1) downto 0);
begin
d0_1_24 <= d0;
d1_1_27 <= d1;
fully_2_1_bit <= d0_1_24 or d1_1_27;
y <= fully_2_1_bit;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_791081a00e is
port (
sel : in std_logic_vector((1 - 1) downto 0);
d0 : in std_logic_vector((9 - 1) downto 0);
d1 : in std_logic_vector((9 - 1) downto 0);
y : out std_logic_vector((9 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_791081a00e;
architecture behavior of mux_791081a00e is
signal sel_1_20: std_logic;
signal d0_1_24: std_logic_vector((9 - 1) downto 0);
signal d1_1_27: std_logic_vector((9 - 1) downto 0);
signal sel_internal_2_1_convert: std_logic_vector((1 - 1) downto 0);
signal unregy_join_6_1: std_logic_vector((9 - 1) downto 0);
begin
sel_1_20 <= sel(0);
d0_1_24 <= d0;
d1_1_27 <= d1;
sel_internal_2_1_convert <= cast(std_logic_to_vector(sel_1_20), 0, 1, 0, xlUnsigned);
proc_switch_6_1: process (d0_1_24, d1_1_27, sel_internal_2_1_convert)
is
begin
case sel_internal_2_1_convert is
when "0" =>
unregy_join_6_1 <= d0_1_24;
when others =>
unregy_join_6_1 <= d1_1_27;
end case;
end process proc_switch_6_1;
y <= unregy_join_6_1;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/Buzzer Controller"
entity buzzer_controller_entity_063692c849 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
from_register: in std_logic_vector(17 downto 0);
from_register1: in std_logic_vector(17 downto 0);
from_register2: in std_logic;
register9_x0: out std_logic
);
end buzzer_controller_entity_063692c849;
architecture structural of buzzer_controller_entity_063692c849 is
signal ce_1_sg_x0: std_logic;
signal clk_1_sg_x0: std_logic;
signal convert_dout_net: std_logic;
signal counter_op_net: std_logic_vector(17 downto 0);
signal from_register1_data_out_net_x0: std_logic_vector(17 downto 0);
signal from_register2_data_out_net_x0: std_logic;
signal from_register_data_out_net_x0: std_logic_vector(17 downto 0);
signal inverter_op_net: std_logic;
signal mult_p_net: std_logic_vector(17 downto 0);
signal register8_q_net: std_logic;
signal register9_q_net_x0: std_logic;
signal relational1_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_1_sg_x0 <= ce_1;
clk_1_sg_x0 <= clk_1;
from_register_data_out_net_x0 <= from_register;
from_register1_data_out_net_x0 <= from_register1;
from_register2_data_out_net_x0 <= from_register2;
register9_x0 <= register9_q_net_x0;
convert: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din(0) => inverter_op_net,
dout(0) => convert_dout_net
);
counter: entity work.xlcounter_free
generic map (
core_name0 => "binary_counter_virtex2p_7_0_950e4ab582797264",
op_arith => xlUnsigned,
op_width => 18
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
en => "1",
rst(0) => relational_op_net,
op => counter_op_net
);
inverter: entity work.inverter_e2b989a05e
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
ip(0) => from_register2_data_out_net_x0,
op(0) => inverter_op_net
);
mult: entity work.xlmult_v9_0
generic map (
a_arith => xlUnsigned,
a_bin_pt => 0,
a_width => 18,
b_arith => xlUnsigned,
b_bin_pt => 18,
b_width => 18,
c_a_type => 1,
c_a_width => 18,
c_b_type => 1,
c_b_width => 18,
c_baat => 18,
c_output_width => 36,
c_type => 1,
core_name0 => "multiplier_virtex2p_10_1_817edd563258bb47",
extra_registers => 0,
multsign => 1,
overflow => 1,
p_arith => xlUnsigned,
p_bin_pt => 0,
p_width => 18,
quantization => 1
)
port map (
a => from_register_data_out_net_x0,
b => from_register1_data_out_net_x0,
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
core_ce => ce_1_sg_x0,
core_clk => clk_1_sg_x0,
core_clr => '1',
en => "1",
rst => "0",
p => mult_p_net
);
register8: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d(0) => relational1_op_net,
en => "1",
rst(0) => convert_dout_net,
q(0) => register8_q_net
);
register9: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d(0) => register8_q_net,
en => "1",
rst => "0",
q(0) => register9_q_net_x0
);
relational: entity work.relational_4e76b03051
port map (
a => counter_op_net,
b => from_register_data_out_net_x0,
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_1433264a0c
port map (
a => counter_op_net,
b => mult_p_net,
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
op(0) => relational1_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/EDK Processor"
entity edk_processor_entity_94deb4def9 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
from_register: in std_logic_vector(1 downto 0);
from_register1: in std_logic_vector(5 downto 0);
from_register2: in std_logic_vector(3 downto 0);
from_register3: in std_logic_vector(4 downto 0);
plb_abus: in std_logic_vector(31 downto 0);
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(31 downto 0);
sg_plb_addrpref: in std_logic_vector(14 downto 0);
shared_memory: in std_logic_vector(31 downto 0);
shared_memory1: in std_logic_vector(31 downto 0);
shared_memory2: in std_logic_vector(31 downto 0);
splb_rst: in std_logic;
to_register: in std_logic_vector(17 downto 0);
to_register1: in std_logic;
to_register10: in std_logic_vector(8 downto 0);
to_register11: in std_logic_vector(3 downto 0);
to_register12: in std_logic_vector(8 downto 0);
to_register13: in std_logic;
to_register14: in std_logic;
to_register15: in std_logic_vector(8 downto 0);
to_register16: in std_logic_vector(8 downto 0);
to_register17: in std_logic_vector(8 downto 0);
to_register18: in std_logic;
to_register19: in std_logic_vector(7 downto 0);
to_register2: in std_logic_vector(17 downto 0);
to_register20: in std_logic_vector(7 downto 0);
to_register3: in std_logic_vector(8 downto 0);
to_register4: in std_logic_vector(3 downto 0);
to_register5: in std_logic_vector(2 downto 0);
to_register6: in std_logic_vector(8 downto 0);
to_register7: in std_logic_vector(1 downto 0);
to_register8: in std_logic;
to_register9: in std_logic_vector(8 downto 0);
constant5_x0: out std_logic;
plb_decode_x0: out std_logic;
plb_decode_x1: out std_logic;
plb_decode_x2: out std_logic;
plb_decode_x3: out std_logic;
plb_decode_x4: out std_logic_vector(31 downto 0);
plb_memmap_x0: out std_logic_vector(17 downto 0);
plb_memmap_x1: out std_logic;
plb_memmap_x10: out std_logic_vector(2 downto 0);
plb_memmap_x11: out std_logic;
plb_memmap_x12: out std_logic_vector(8 downto 0);
plb_memmap_x13: out std_logic;
plb_memmap_x14: out std_logic_vector(1 downto 0);
plb_memmap_x15: out std_logic;
plb_memmap_x16: out std_logic;
plb_memmap_x17: out std_logic;
plb_memmap_x18: out std_logic_vector(8 downto 0);
plb_memmap_x19: out std_logic;
plb_memmap_x2: out std_logic;
plb_memmap_x20: out std_logic_vector(8 downto 0);
plb_memmap_x21: out std_logic;
plb_memmap_x22: out std_logic_vector(3 downto 0);
plb_memmap_x23: out std_logic;
plb_memmap_x24: out std_logic_vector(8 downto 0);
plb_memmap_x25: out std_logic;
plb_memmap_x26: out std_logic;
plb_memmap_x27: out std_logic;
plb_memmap_x28: out std_logic;
plb_memmap_x29: out std_logic;
plb_memmap_x3: out std_logic;
plb_memmap_x30: out std_logic_vector(8 downto 0);
plb_memmap_x31: out std_logic;
plb_memmap_x32: out std_logic_vector(8 downto 0);
plb_memmap_x33: out std_logic;
plb_memmap_x34: out std_logic_vector(8 downto 0);
plb_memmap_x35: out std_logic;
plb_memmap_x36: out std_logic;
plb_memmap_x37: out std_logic;
plb_memmap_x38: out std_logic_vector(7 downto 0);
plb_memmap_x39: out std_logic;
plb_memmap_x4: out std_logic_vector(17 downto 0);
plb_memmap_x40: out std_logic_vector(7 downto 0);
plb_memmap_x41: out std_logic;
plb_memmap_x42: out std_logic_vector(11 downto 0);
plb_memmap_x43: out std_logic_vector(31 downto 0);
plb_memmap_x44: out std_logic;
plb_memmap_x45: out std_logic_vector(8 downto 0);
plb_memmap_x46: out std_logic_vector(31 downto 0);
plb_memmap_x47: out std_logic;
plb_memmap_x48: out std_logic_vector(7 downto 0);
plb_memmap_x49: out std_logic_vector(31 downto 0);
plb_memmap_x5: out std_logic;
plb_memmap_x50: out std_logic;
plb_memmap_x6: out std_logic_vector(8 downto 0);
plb_memmap_x7: out std_logic;
plb_memmap_x8: out std_logic_vector(3 downto 0);
plb_memmap_x9: out std_logic
);
end edk_processor_entity_94deb4def9;
architecture structural of edk_processor_entity_94deb4def9 is
signal bankaddr: std_logic_vector(1 downto 0);
signal buttons_big_dout_x0: std_logic_vector(1 downto 0);
signal buttons_small_dout_x0: std_logic_vector(5 downto 0);
signal buzzer_dutycycle_din_x0: std_logic_vector(17 downto 0);
signal buzzer_dutycycle_dout_x0: std_logic_vector(17 downto 0);
signal buzzer_dutycycle_en_x0: std_logic;
signal buzzer_enable_din_x0: std_logic;
signal buzzer_enable_dout_x0: std_logic;
signal buzzer_enable_en_x0: std_logic;
signal buzzer_period_din_x0: std_logic_vector(17 downto 0);
signal buzzer_period_dout_x0: std_logic_vector(17 downto 0);
signal buzzer_period_en_x0: std_logic;
signal ce_1_sg_x1: std_logic;
signal clk_1_sg_x1: std_logic;
signal dip_switch_dout_x0: std_logic_vector(3 downto 0);
signal lcd_backgroundcolor_din_x0: std_logic_vector(8 downto 0);
signal lcd_backgroundcolor_dout_x0: std_logic_vector(8 downto 0);
signal lcd_backgroundcolor_en_x0: std_logic;
signal lcd_charactermap_addr_x0: std_logic_vector(11 downto 0);
signal lcd_charactermap_din_x0: std_logic_vector(31 downto 0);
signal lcd_charactermap_dout_x0: std_logic_vector(31 downto 0);
signal lcd_charactermap_we_x0: std_logic;
signal lcd_characteroffset_din_x0: std_logic_vector(3 downto 0);
signal lcd_characteroffset_dout_x0: std_logic_vector(3 downto 0);
signal lcd_characteroffset_en_x0: std_logic;
signal lcd_characters_addr_x0: std_logic_vector(8 downto 0);
signal lcd_characters_din_x0: std_logic_vector(31 downto 0);
signal lcd_characters_dout_x0: std_logic_vector(31 downto 0);
signal lcd_characters_we_x0: std_logic;
signal lcd_charactersselect_din_x0: std_logic_vector(2 downto 0);
signal lcd_charactersselect_dout_x0: std_logic_vector(2 downto 0);
signal lcd_charactersselect_en_x0: std_logic;
signal lcd_colset_din_x0: std_logic_vector(8 downto 0);
signal lcd_colset_dout_x0: std_logic_vector(8 downto 0);
signal lcd_colset_en_x0: std_logic;
signal lcd_commands_addr_x0: std_logic_vector(7 downto 0);
signal lcd_commands_din_x0: std_logic_vector(31 downto 0);
signal lcd_commands_dout_x0: std_logic_vector(31 downto 0);
signal lcd_commands_we_x0: std_logic;
signal lcd_configlocation_din_x0: std_logic_vector(1 downto 0);
signal lcd_configlocation_dout_x0: std_logic_vector(1 downto 0);
signal lcd_configlocation_en_x0: std_logic;
signal lcd_dividerselect_din_x0: std_logic;
signal lcd_dividerselect_dout_x0: std_logic;
signal lcd_dividerselect_en_x0: std_logic;
signal lcd_firstend_din_x0: std_logic_vector(8 downto 0);
signal lcd_firstend_dout_x0: std_logic_vector(8 downto 0);
signal lcd_firstend_en_x0: std_logic;
signal lcd_firststart_din_x0: std_logic_vector(8 downto 0);
signal lcd_firststart_dout_x0: std_logic_vector(8 downto 0);
signal lcd_firststart_en_x0: std_logic;
signal lcd_lineoffset_din_x0: std_logic_vector(3 downto 0);
signal lcd_lineoffset_dout_x0: std_logic_vector(3 downto 0);
signal lcd_lineoffset_en_x0: std_logic;
signal lcd_ramwrite_din_x0: std_logic_vector(8 downto 0);
signal lcd_ramwrite_dout_x0: std_logic_vector(8 downto 0);
signal lcd_ramwrite_en_x0: std_logic;
signal lcd_reset_din_x0: std_logic;
signal lcd_reset_dout_x0: std_logic;
signal lcd_reset_en_x0: std_logic;
signal lcd_resetlcd_din_x0: std_logic;
signal lcd_resetlcd_dout_x0: std_logic;
signal lcd_resetlcd_en_x0: std_logic;
signal lcd_rowset_din_x0: std_logic_vector(8 downto 0);
signal lcd_rowset_dout_x0: std_logic_vector(8 downto 0);
signal lcd_rowset_en_x0: std_logic;
signal lcd_secondend_din_x0: std_logic_vector(8 downto 0);
signal lcd_secondend_dout_x0: std_logic_vector(8 downto 0);
signal lcd_secondend_en_x0: std_logic;
signal lcd_secondstart_din_x0: std_logic_vector(8 downto 0);
signal lcd_secondstart_dout_x0: std_logic_vector(8 downto 0);
signal lcd_secondstart_en_x0: std_logic;
signal lcd_send_din_x0: std_logic;
signal lcd_send_dout_x0: std_logic;
signal lcd_send_en_x0: std_logic;
signal lcd_totalcmdtransfer_din_x0: std_logic_vector(7 downto 0);
signal lcd_totalcmdtransfer_dout_x0: std_logic_vector(7 downto 0);
signal lcd_totalcmdtransfer_en_x0: std_logic;
signal leds_din_x0: std_logic_vector(7 downto 0);
signal leds_dout_x0: std_logic_vector(7 downto 0);
signal leds_en_x0: std_logic;
signal linearaddr: std_logic_vector(12 downto 0);
signal plb_abus_net_x0: std_logic_vector(31 downto 0);
signal plb_pavalid_net_x0: std_logic;
signal plb_rnw_net_x0: std_logic;
signal plb_wrdbus_net_x0: std_logic_vector(31 downto 0);
signal rddata: std_logic_vector(31 downto 0);
signal rnwreg: std_logic;
signal sg_plb_addrpref_net_x0: std_logic_vector(14 downto 0);
signal sl_addrack_x0: std_logic;
signal sl_rdcomp_x0: std_logic;
signal sl_rddack_x0: std_logic;
signal sl_rddbus_x0: std_logic_vector(31 downto 0);
signal sl_wait_x0: std_logic;
signal sl_wrdack_x0: std_logic;
signal splb_rst_net_x0: std_logic;
signal trackball_dout_x0: std_logic_vector(4 downto 0);
signal wrdbusreg: std_logic_vector(31 downto 0);
begin
ce_1_sg_x1 <= ce_1;
clk_1_sg_x1 <= clk_1;
buttons_big_dout_x0 <= from_register;
buttons_small_dout_x0 <= from_register1;
dip_switch_dout_x0 <= from_register2;
trackball_dout_x0 <= from_register3;
plb_abus_net_x0 <= plb_abus;
plb_pavalid_net_x0 <= plb_pavalid;
plb_rnw_net_x0 <= plb_rnw;
plb_wrdbus_net_x0 <= plb_wrdbus;
sg_plb_addrpref_net_x0 <= sg_plb_addrpref;
lcd_charactermap_dout_x0 <= shared_memory;
lcd_characters_dout_x0 <= shared_memory1;
lcd_commands_dout_x0 <= shared_memory2;
splb_rst_net_x0 <= splb_rst;
buzzer_dutycycle_dout_x0 <= to_register;
buzzer_enable_dout_x0 <= to_register1;
lcd_firststart_dout_x0 <= to_register10;
lcd_lineoffset_dout_x0 <= to_register11;
lcd_ramwrite_dout_x0 <= to_register12;
lcd_reset_dout_x0 <= to_register13;
lcd_resetlcd_dout_x0 <= to_register14;
lcd_rowset_dout_x0 <= to_register15;
lcd_secondend_dout_x0 <= to_register16;
lcd_secondstart_dout_x0 <= to_register17;
lcd_send_dout_x0 <= to_register18;
lcd_totalcmdtransfer_dout_x0 <= to_register19;
buzzer_period_dout_x0 <= to_register2;
leds_dout_x0 <= to_register20;
lcd_backgroundcolor_dout_x0 <= to_register3;
lcd_characteroffset_dout_x0 <= to_register4;
lcd_charactersselect_dout_x0 <= to_register5;
lcd_colset_dout_x0 <= to_register6;
lcd_configlocation_dout_x0 <= to_register7;
lcd_dividerselect_dout_x0 <= to_register8;
lcd_firstend_dout_x0 <= to_register9;
constant5_x0 <= sl_wait_x0;
plb_decode_x0 <= sl_addrack_x0;
plb_decode_x1 <= sl_rdcomp_x0;
plb_decode_x2 <= sl_wrdack_x0;
plb_decode_x3 <= sl_rddack_x0;
plb_decode_x4 <= sl_rddbus_x0;
plb_memmap_x0 <= buzzer_dutycycle_din_x0;
plb_memmap_x1 <= buzzer_dutycycle_en_x0;
plb_memmap_x10 <= lcd_charactersselect_din_x0;
plb_memmap_x11 <= lcd_charactersselect_en_x0;
plb_memmap_x12 <= lcd_colset_din_x0;
plb_memmap_x13 <= lcd_colset_en_x0;
plb_memmap_x14 <= lcd_configlocation_din_x0;
plb_memmap_x15 <= lcd_configlocation_en_x0;
plb_memmap_x16 <= lcd_dividerselect_din_x0;
plb_memmap_x17 <= lcd_dividerselect_en_x0;
plb_memmap_x18 <= lcd_firstend_din_x0;
plb_memmap_x19 <= lcd_firstend_en_x0;
plb_memmap_x2 <= buzzer_enable_din_x0;
plb_memmap_x20 <= lcd_firststart_din_x0;
plb_memmap_x21 <= lcd_firststart_en_x0;
plb_memmap_x22 <= lcd_lineoffset_din_x0;
plb_memmap_x23 <= lcd_lineoffset_en_x0;
plb_memmap_x24 <= lcd_ramwrite_din_x0;
plb_memmap_x25 <= lcd_ramwrite_en_x0;
plb_memmap_x26 <= lcd_reset_din_x0;
plb_memmap_x27 <= lcd_reset_en_x0;
plb_memmap_x28 <= lcd_resetlcd_din_x0;
plb_memmap_x29 <= lcd_resetlcd_en_x0;
plb_memmap_x3 <= buzzer_enable_en_x0;
plb_memmap_x30 <= lcd_rowset_din_x0;
plb_memmap_x31 <= lcd_rowset_en_x0;
plb_memmap_x32 <= lcd_secondend_din_x0;
plb_memmap_x33 <= lcd_secondend_en_x0;
plb_memmap_x34 <= lcd_secondstart_din_x0;
plb_memmap_x35 <= lcd_secondstart_en_x0;
plb_memmap_x36 <= lcd_send_din_x0;
plb_memmap_x37 <= lcd_send_en_x0;
plb_memmap_x38 <= lcd_totalcmdtransfer_din_x0;
plb_memmap_x39 <= lcd_totalcmdtransfer_en_x0;
plb_memmap_x4 <= buzzer_period_din_x0;
plb_memmap_x40 <= leds_din_x0;
plb_memmap_x41 <= leds_en_x0;
plb_memmap_x42 <= lcd_charactermap_addr_x0;
plb_memmap_x43 <= lcd_charactermap_din_x0;
plb_memmap_x44 <= lcd_charactermap_we_x0;
plb_memmap_x45 <= lcd_characters_addr_x0;
plb_memmap_x46 <= lcd_characters_din_x0;
plb_memmap_x47 <= lcd_characters_we_x0;
plb_memmap_x48 <= lcd_commands_addr_x0;
plb_memmap_x49 <= lcd_commands_din_x0;
plb_memmap_x5 <= buzzer_period_en_x0;
plb_memmap_x50 <= lcd_commands_we_x0;
plb_memmap_x6 <= lcd_backgroundcolor_din_x0;
plb_memmap_x7 <= lcd_backgroundcolor_en_x0;
plb_memmap_x8 <= lcd_characteroffset_din_x0;
plb_memmap_x9 <= lcd_characteroffset_en_x0;
constant5: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => sl_wait_x0
);
plb_decode: entity work.mcode_block_8231ed31e4
port map (
addrpref => sg_plb_addrpref_net_x0,
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
plbabus => plb_abus_net_x0,
plbpavalid(0) => plb_pavalid_net_x0,
plbrnw(0) => plb_rnw_net_x0,
plbrst(0) => splb_rst_net_x0,
plbwrdbus => plb_wrdbus_net_x0,
rddata => rddata,
addrack(0) => sl_addrack_x0,
bankaddr => bankaddr,
linearaddr => linearaddr,
rdcomp(0) => sl_rdcomp_x0,
rddack(0) => sl_rddack_x0,
rddbus => sl_rddbus_x0,
rnwreg(0) => rnwreg,
wrdack(0) => sl_wrdack_x0,
wrdbusreg => wrdbusreg
);
plb_memmap: entity work.mcode_block_66f25059c9
port map (
addrack(0) => sl_addrack_x0,
bankaddr => bankaddr,
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
linearaddr => linearaddr,
rnwreg(0) => rnwreg,
sm_buttons_big => buttons_big_dout_x0,
sm_buttons_small => buttons_small_dout_x0,
sm_buzzer_dutycycle => buzzer_dutycycle_dout_x0,
sm_buzzer_enable(0) => buzzer_enable_dout_x0,
sm_buzzer_period => buzzer_period_dout_x0,
sm_dip_switch => dip_switch_dout_x0,
sm_lcd_backgroundcolor => lcd_backgroundcolor_dout_x0,
sm_lcd_charactermap => lcd_charactermap_dout_x0,
sm_lcd_characteroffset => lcd_characteroffset_dout_x0,
sm_lcd_characters => lcd_characters_dout_x0,
sm_lcd_charactersselect => lcd_charactersselect_dout_x0,
sm_lcd_colset => lcd_colset_dout_x0,
sm_lcd_commands => lcd_commands_dout_x0,
sm_lcd_configlocation => lcd_configlocation_dout_x0,
sm_lcd_dividerselect(0) => lcd_dividerselect_dout_x0,
sm_lcd_firstend => lcd_firstend_dout_x0,
sm_lcd_firststart => lcd_firststart_dout_x0,
sm_lcd_lineoffset => lcd_lineoffset_dout_x0,
sm_lcd_ramwrite => lcd_ramwrite_dout_x0,
sm_lcd_reset(0) => lcd_reset_dout_x0,
sm_lcd_resetlcd(0) => lcd_resetlcd_dout_x0,
sm_lcd_rowset => lcd_rowset_dout_x0,
sm_lcd_secondend => lcd_secondend_dout_x0,
sm_lcd_secondstart => lcd_secondstart_dout_x0,
sm_lcd_send(0) => lcd_send_dout_x0,
sm_lcd_totalcmdtransfer => lcd_totalcmdtransfer_dout_x0,
sm_leds => leds_dout_x0,
sm_trackball => trackball_dout_x0,
wrdbus => wrdbusreg,
read_bank_out => rddata,
sm_buzzer_dutycycle_din => buzzer_dutycycle_din_x0,
sm_buzzer_dutycycle_en(0) => buzzer_dutycycle_en_x0,
sm_buzzer_enable_din(0) => buzzer_enable_din_x0,
sm_buzzer_enable_en(0) => buzzer_enable_en_x0,
sm_buzzer_period_din => buzzer_period_din_x0,
sm_buzzer_period_en(0) => buzzer_period_en_x0,
sm_lcd_backgroundcolor_din => lcd_backgroundcolor_din_x0,
sm_lcd_backgroundcolor_en(0) => lcd_backgroundcolor_en_x0,
sm_lcd_charactermap_addr => lcd_charactermap_addr_x0,
sm_lcd_charactermap_din => lcd_charactermap_din_x0,
sm_lcd_charactermap_we(0) => lcd_charactermap_we_x0,
sm_lcd_characteroffset_din => lcd_characteroffset_din_x0,
sm_lcd_characteroffset_en(0) => lcd_characteroffset_en_x0,
sm_lcd_characters_addr => lcd_characters_addr_x0,
sm_lcd_characters_din => lcd_characters_din_x0,
sm_lcd_characters_we(0) => lcd_characters_we_x0,
sm_lcd_charactersselect_din => lcd_charactersselect_din_x0,
sm_lcd_charactersselect_en(0) => lcd_charactersselect_en_x0,
sm_lcd_colset_din => lcd_colset_din_x0,
sm_lcd_colset_en(0) => lcd_colset_en_x0,
sm_lcd_commands_addr => lcd_commands_addr_x0,
sm_lcd_commands_din => lcd_commands_din_x0,
sm_lcd_commands_we(0) => lcd_commands_we_x0,
sm_lcd_configlocation_din => lcd_configlocation_din_x0,
sm_lcd_configlocation_en(0) => lcd_configlocation_en_x0,
sm_lcd_dividerselect_din(0) => lcd_dividerselect_din_x0,
sm_lcd_dividerselect_en(0) => lcd_dividerselect_en_x0,
sm_lcd_firstend_din => lcd_firstend_din_x0,
sm_lcd_firstend_en(0) => lcd_firstend_en_x0,
sm_lcd_firststart_din => lcd_firststart_din_x0,
sm_lcd_firststart_en(0) => lcd_firststart_en_x0,
sm_lcd_lineoffset_din => lcd_lineoffset_din_x0,
sm_lcd_lineoffset_en(0) => lcd_lineoffset_en_x0,
sm_lcd_ramwrite_din => lcd_ramwrite_din_x0,
sm_lcd_ramwrite_en(0) => lcd_ramwrite_en_x0,
sm_lcd_reset_din(0) => lcd_reset_din_x0,
sm_lcd_reset_en(0) => lcd_reset_en_x0,
sm_lcd_resetlcd_din(0) => lcd_resetlcd_din_x0,
sm_lcd_resetlcd_en(0) => lcd_resetlcd_en_x0,
sm_lcd_rowset_din => lcd_rowset_din_x0,
sm_lcd_rowset_en(0) => lcd_rowset_en_x0,
sm_lcd_secondend_din => lcd_secondend_din_x0,
sm_lcd_secondend_en(0) => lcd_secondend_en_x0,
sm_lcd_secondstart_din => lcd_secondstart_din_x0,
sm_lcd_secondstart_en(0) => lcd_secondstart_en_x0,
sm_lcd_send_din(0) => lcd_send_din_x0,
sm_lcd_send_en(0) => lcd_send_en_x0,
sm_lcd_totalcmdtransfer_din => lcd_totalcmdtransfer_din_x0,
sm_lcd_totalcmdtransfer_en(0) => lcd_totalcmdtransfer_en_x0,
sm_leds_din => leds_din_x0,
sm_leds_en(0) => leds_en_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/Interactive I/O/8xDebounce"
entity x8xdebounce_entity_bf5cd80880 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
d: in std_logic;
q: out std_logic
);
end x8xdebounce_entity_bf5cd80880;
architecture structural of x8xdebounce_entity_bf5cd80880 is
signal ce_1_sg_x2: std_logic;
signal clk_1_sg_x2: std_logic;
signal delay1_q_net: std_logic;
signal delay2_q_net: std_logic;
signal delay3_q_net: std_logic;
signal delay4_q_net: std_logic;
signal delay5_q_net: std_logic;
signal delay6_q_net: std_logic;
signal delay_q_net: std_logic;
signal logical_y_net_x0: std_logic;
signal trackball_sel2_net_x0: std_logic;
begin
ce_1_sg_x2 <= ce_1;
clk_1_sg_x2 <= clk_1;
trackball_sel2_net_x0 <= d;
q <= logical_y_net_x0;
delay: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x2,
clk => clk_1_sg_x2,
d(0) => trackball_sel2_net_x0,
en => '1',
q(0) => delay_q_net
);
delay1: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x2,
clk => clk_1_sg_x2,
d(0) => delay_q_net,
en => '1',
q(0) => delay1_q_net
);
delay2: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x2,
clk => clk_1_sg_x2,
d(0) => delay1_q_net,
en => '1',
q(0) => delay2_q_net
);
delay3: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x2,
clk => clk_1_sg_x2,
d(0) => delay2_q_net,
en => '1',
q(0) => delay3_q_net
);
delay4: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x2,
clk => clk_1_sg_x2,
d(0) => delay3_q_net,
en => '1',
q(0) => delay4_q_net
);
delay5: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x2,
clk => clk_1_sg_x2,
d(0) => delay4_q_net,
en => '1',
q(0) => delay5_q_net
);
delay6: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x2,
clk => clk_1_sg_x2,
d(0) => delay5_q_net,
en => '1',
q(0) => delay6_q_net
);
logical: entity work.logical_4ad38e8aed
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => trackball_sel2_net_x0,
d1(0) => delay_q_net,
d2(0) => delay1_q_net,
d3(0) => delay2_q_net,
d4(0) => delay3_q_net,
d5(0) => delay4_q_net,
d6(0) => delay5_q_net,
d7(0) => delay6_q_net,
y(0) => logical_y_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/Interactive I/O"
entity o_entity_1f30dfdbf5 is
port (
buttons_big: in std_logic_vector(1 downto 0);
buttons_small: in std_logic_vector(5 downto 0);
ce_1: in std_logic;
clk_1: in std_logic;
dip_switch: in std_logic_vector(3 downto 0);
from_register: in std_logic_vector(7 downto 0);
trackball_ox: in std_logic;
trackball_oxn: in std_logic;
trackball_oy: in std_logic;
trackball_oyn: in std_logic;
trackball_sel2: in std_logic;
concat_x0: out std_logic_vector(4 downto 0);
constant2_x0: out std_logic;
constant4_x0: out std_logic;
constant6_x0: out std_logic;
constant_x1: out std_logic;
register10_x0: out std_logic;
register11_x0: out std_logic;
register12_x0: out std_logic;
register3_x0: out std_logic_vector(1 downto 0);
register5_x0: out std_logic_vector(5 downto 0);
register7_x0: out std_logic_vector(3 downto 0);
register9_x0: out std_logic_vector(7 downto 0)
);
end o_entity_1f30dfdbf5;
architecture structural of o_entity_1f30dfdbf5 is
signal buttons_big_net_x0: std_logic_vector(1 downto 0);
signal buttons_small_net_x0: std_logic_vector(5 downto 0);
signal ce_1_sg_x7: std_logic;
signal clk_1_sg_x7: std_logic;
signal concat_y_net_x0: std_logic_vector(4 downto 0);
signal constant13_op_net: std_logic;
signal constant2_op_net_x0: std_logic;
signal constant4_op_net_x0: std_logic;
signal constant6_op_net_x0: std_logic;
signal constant_op_net_x0: std_logic;
signal dip_switch_net_x0: std_logic_vector(3 downto 0);
signal from_register_data_out_net_x0: std_logic_vector(7 downto 0);
signal logical_y_net_x0: std_logic;
signal logical_y_net_x1: std_logic;
signal logical_y_net_x2: std_logic;
signal logical_y_net_x3: std_logic;
signal logical_y_net_x4: std_logic;
signal register10_q_net_x0: std_logic;
signal register11_q_net_x0: std_logic;
signal register12_q_net_x0: std_logic;
signal register13_q_net: std_logic;
signal register14_q_net: std_logic;
signal register15_q_net: std_logic;
signal register16_q_net: std_logic;
signal register17_q_net: std_logic;
signal register18_q_net: std_logic;
signal register19_q_net: std_logic;
signal register1_q_net: std_logic;
signal register20_q_net: std_logic;
signal register2_q_net: std_logic_vector(1 downto 0);
signal register3_q_net_x0: std_logic_vector(1 downto 0);
signal register4_q_net: std_logic_vector(5 downto 0);
signal register5_q_net_x0: std_logic_vector(5 downto 0);
signal register6_q_net: std_logic_vector(3 downto 0);
signal register7_q_net_x0: std_logic_vector(3 downto 0);
signal register8_q_net: std_logic_vector(7 downto 0);
signal register9_q_net_x0: std_logic_vector(7 downto 0);
signal register_q_net: std_logic;
signal trackball_ox_net_x1: std_logic;
signal trackball_oxn_net_x1: std_logic;
signal trackball_oy_net_x1: std_logic;
signal trackball_oyn_net_x1: std_logic;
signal trackball_sel2_net_x1: std_logic;
begin
buttons_big_net_x0 <= buttons_big;
buttons_small_net_x0 <= buttons_small;
ce_1_sg_x7 <= ce_1;
clk_1_sg_x7 <= clk_1;
dip_switch_net_x0 <= dip_switch;
from_register_data_out_net_x0 <= from_register;
trackball_ox_net_x1 <= trackball_ox;
trackball_oxn_net_x1 <= trackball_oxn;
trackball_oy_net_x1 <= trackball_oy;
trackball_oyn_net_x1 <= trackball_oyn;
trackball_sel2_net_x1 <= trackball_sel2;
concat_x0 <= concat_y_net_x0;
constant2_x0 <= constant2_op_net_x0;
constant4_x0 <= constant4_op_net_x0;
constant6_x0 <= constant6_op_net_x0;
constant_x1 <= constant_op_net_x0;
register10_x0 <= register10_q_net_x0;
register11_x0 <= register11_q_net_x0;
register12_x0 <= register12_q_net_x0;
register3_x0 <= register3_q_net_x0;
register5_x0 <= register5_q_net_x0;
register7_x0 <= register7_q_net_x0;
register9_x0 <= register9_q_net_x0;
concat: entity work.concat_2b3acb49f4
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => register20_q_net,
in1(0) => register1_q_net,
in2(0) => register14_q_net,
in3(0) => register16_q_net,
in4(0) => register18_q_net,
y => concat_y_net_x0
);
constant13: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant13_op_net
);
constant2: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant2_op_net_x0
);
constant4: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant4_op_net_x0
);
constant6: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant6_op_net_x0
);
constant_x0: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant_op_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => register_q_net,
en => "1",
rst => "0",
q(0) => register1_q_net
);
register10: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => constant13_op_net,
en => "1",
rst => "0",
q(0) => register10_q_net_x0
);
register11: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => constant13_op_net,
en => "1",
rst => "0",
q(0) => register11_q_net_x0
);
register12: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => constant13_op_net,
en => "1",
rst => "0",
q(0) => register12_q_net_x0
);
register13: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => logical_y_net_x2,
en => "1",
rst => "0",
q(0) => register13_q_net
);
register14: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => register13_q_net,
en => "1",
rst => "0",
q(0) => register14_q_net
);
register15: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => logical_y_net_x3,
en => "1",
rst => "0",
q(0) => register15_q_net
);
register16: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => register15_q_net,
en => "1",
rst => "0",
q(0) => register16_q_net
);
register17: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => logical_y_net_x4,
en => "1",
rst => "0",
q(0) => register17_q_net
);
register18: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => register17_q_net,
en => "1",
rst => "0",
q(0) => register18_q_net
);
register19: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => logical_y_net_x0,
en => "1",
rst => "0",
q(0) => register19_q_net
);
register2: entity work.xlregister
generic map (
d_width => 2,
init_value => b"00"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d => buttons_big_net_x0,
en => "1",
rst => "0",
q => register2_q_net
);
register20: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => register19_q_net,
en => "1",
rst => "0",
q(0) => register20_q_net
);
register3: entity work.xlregister
generic map (
d_width => 2,
init_value => b"00"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d => register2_q_net,
en => "1",
rst => "0",
q => register3_q_net_x0
);
register4: entity work.xlregister
generic map (
d_width => 6,
init_value => b"000000"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d => buttons_small_net_x0,
en => "1",
rst => "0",
q => register4_q_net
);
register5: entity work.xlregister
generic map (
d_width => 6,
init_value => b"000000"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d => register4_q_net,
en => "1",
rst => "0",
q => register5_q_net_x0
);
register6: entity work.xlregister
generic map (
d_width => 4,
init_value => b"0000"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d => dip_switch_net_x0,
en => "1",
rst => "0",
q => register6_q_net
);
register7: entity work.xlregister
generic map (
d_width => 4,
init_value => b"0000"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d => register6_q_net,
en => "1",
rst => "0",
q => register7_q_net_x0
);
register8: entity work.xlregister
generic map (
d_width => 8,
init_value => b"00000000"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d => from_register_data_out_net_x0,
en => "1",
rst => "0",
q => register8_q_net
);
register9: entity work.xlregister
generic map (
d_width => 8,
init_value => b"00000000"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d => register8_q_net,
en => "1",
rst => "0",
q => register9_q_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => logical_y_net_x1,
en => "1",
rst => "0",
q(0) => register_q_net
);
x8xdebounce1_e364c4890f: entity work.x8xdebounce_entity_bf5cd80880
port map (
ce_1 => ce_1_sg_x7,
clk_1 => clk_1_sg_x7,
d => trackball_ox_net_x1,
q => logical_y_net_x1
);
x8xdebounce2_5537837997: entity work.x8xdebounce_entity_bf5cd80880
port map (
ce_1 => ce_1_sg_x7,
clk_1 => clk_1_sg_x7,
d => trackball_oxn_net_x1,
q => logical_y_net_x2
);
x8xdebounce3_1e40372202: entity work.x8xdebounce_entity_bf5cd80880
port map (
ce_1 => ce_1_sg_x7,
clk_1 => clk_1_sg_x7,
d => trackball_oy_net_x1,
q => logical_y_net_x3
);
x8xdebounce4_7911ba4284: entity work.x8xdebounce_entity_bf5cd80880
port map (
ce_1 => ce_1_sg_x7,
clk_1 => clk_1_sg_x7,
d => trackball_oyn_net_x1,
q => logical_y_net_x4
);
x8xdebounce_bf5cd80880: entity work.x8xdebounce_entity_bf5cd80880
port map (
ce_1 => ce_1_sg_x7,
clk_1 => clk_1_sg_x7,
d => trackball_sel2_net_x1,
q => logical_y_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller/CommandROM/Command Memory"
entity command_memory_entity_ca978db4f0 is
port (
addr_9b: in std_logic_vector(8 downto 0);
shared_memory: in std_logic_vector(31 downto 0);
constant1_x0: out std_logic;
constant_x1: out std_logic_vector(31 downto 0);
data_16b: out std_logic_vector(15 downto 0);
x8msb_x0: out std_logic_vector(7 downto 0)
);
end command_memory_entity_ca978db4f0;
architecture structural of command_memory_entity_ca978db4f0 is
signal concat_y_net_x0: std_logic_vector(8 downto 0);
signal constant1_op_net_x0: std_logic;
signal constant_op_net_x0: std_logic_vector(31 downto 0);
signal lsb_y_net: std_logic;
signal mux_y_net_x0: std_logic_vector(15 downto 0);
signal shared_memory_data_out_net_x0: std_logic_vector(31 downto 0);
signal x16lsb_y_net: std_logic_vector(15 downto 0);
signal x16msb_y_net: std_logic_vector(15 downto 0);
signal x8msb_y_net_x0: std_logic_vector(7 downto 0);
begin
concat_y_net_x0 <= addr_9b;
shared_memory_data_out_net_x0 <= shared_memory;
constant1_x0 <= constant1_op_net_x0;
constant_x1 <= constant_op_net_x0;
data_16b <= mux_y_net_x0;
x8msb_x0 <= x8msb_y_net_x0;
constant1: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant1_op_net_x0
);
constant_x0: entity work.constant_37567836aa
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant_op_net_x0
);
lsb: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 0,
x_width => 9,
y_width => 1
)
port map (
x => concat_y_net_x0,
y(0) => lsb_y_net
);
mux: entity work.mux_2c45f290ed
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => x16lsb_y_net,
d1 => x16msb_y_net,
sel(0) => lsb_y_net,
y => mux_y_net_x0
);
x16lsb: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 15,
x_width => 32,
y_width => 16
)
port map (
x => shared_memory_data_out_net_x0,
y => x16lsb_y_net
);
x16msb: entity work.xlslice
generic map (
new_lsb => 16,
new_msb => 31,
x_width => 32,
y_width => 16
)
port map (
x => shared_memory_data_out_net_x0,
y => x16msb_y_net
);
x8msb: entity work.xlslice
generic map (
new_lsb => 1,
new_msb => 8,
x_width => 9,
y_width => 8
)
port map (
x => concat_y_net_x0,
y => x8msb_y_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller/CommandROM/Neg Edge Detector"
entity neg_edge_detector_entity_b797592ea5 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
input_signal: in std_logic;
rising_edge: out std_logic
);
end neg_edge_detector_entity_b797592ea5;
architecture structural of neg_edge_detector_entity_b797592ea5 is
signal ce_1_sg_x8: std_logic;
signal clk_1_sg_x8: std_logic;
signal delay_q_net: std_logic;
signal inverter_op_net: std_logic;
signal logical_y_net_x0: std_logic;
signal slice4_y_net_x0: std_logic;
begin
ce_1_sg_x8 <= ce_1;
clk_1_sg_x8 <= clk_1;
slice4_y_net_x0 <= input_signal;
rising_edge <= logical_y_net_x0;
delay: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x8,
clk => clk_1_sg_x8,
d(0) => inverter_op_net,
en => '1',
q(0) => delay_q_net
);
inverter: entity work.inverter_e2b989a05e
port map (
ce => ce_1_sg_x8,
clk => clk_1_sg_x8,
clr => '0',
ip(0) => slice4_y_net_x0,
op(0) => inverter_op_net
);
logical: entity work.logical_b1e9d7c303
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => slice4_y_net_x0,
d1(0) => delay_q_net,
y(0) => logical_y_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller/CommandROM"
entity commandrom_entity_b68e0d97b7 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
from_register1: in std_logic_vector(8 downto 0);
from_register2: in std_logic_vector(8 downto 0);
from_register3: in std_logic_vector(8 downto 0);
from_register4: in std_logic_vector(8 downto 0);
from_register5: in std_logic_vector(8 downto 0);
from_register6: in std_logic_vector(1 downto 0);
reset: in std_logic;
sendcmds: in std_logic;
shared_memory: in std_logic_vector(31 downto 0);
totalnoofcmds: in std_logic_vector(7 downto 0);
transferdone: in std_logic;
cmdsdone: out std_logic;
command_memory: out std_logic_vector(7 downto 0);
command_memory_x0: out std_logic_vector(31 downto 0);
command_memory_x1: out std_logic;
datatosend: out std_logic_vector(8 downto 0);
starttransfer: out std_logic
);
end commandrom_entity_b68e0d97b7;
architecture structural of commandrom_entity_b68e0d97b7 is
signal accumulator1_q_net: std_logic_vector(3 downto 0);
signal accumulator_q_net: std_logic_vector(6 downto 0);
signal addsub_s_net: std_logic_vector(8 downto 0);
signal ce_1_sg_x9: std_logic;
signal clk_1_sg_x9: std_logic;
signal concat2_y_net_x0: std_logic_vector(8 downto 0);
signal concat_y_net_x0: std_logic_vector(8 downto 0);
signal constant11_op_net: std_logic_vector(8 downto 0);
signal constant1_op_net_x1: std_logic;
signal constant2_op_net: std_logic;
signal constant3_op_net: std_logic;
signal constant4_op_net: std_logic_vector(3 downto 0);
signal constant5_op_net: std_logic_vector(8 downto 0);
signal constant6_op_net: std_logic_vector(8 downto 0);
signal constant_op_net_x1: std_logic_vector(31 downto 0);
signal convert1_dout_net: std_logic;
signal convert1_dout_net_x2: std_logic;
signal convert1_dout_net_x3: std_logic;
signal convert2_dout_net: std_logic;
signal convert_dout_net: std_logic;
signal counter1_op_net: std_logic_vector(14 downto 0);
signal counter_op_net: std_logic_vector(6 downto 0);
signal delay_q_net: std_logic;
signal from_register1_data_out_net_x0: std_logic_vector(8 downto 0);
signal from_register2_data_out_net_x0: std_logic_vector(8 downto 0);
signal from_register3_data_out_net_x1: std_logic_vector(8 downto 0);
signal from_register3_data_out_net_x2: std_logic_vector(7 downto 0);
signal from_register4_data_out_net_x0: std_logic_vector(8 downto 0);
signal from_register5_data_out_net_x0: std_logic_vector(8 downto 0);
signal from_register6_data_out_net_x0: std_logic_vector(1 downto 0);
signal inverter1_op_net: std_logic;
signal inverter2_op_net: std_logic;
signal logical1_y_net: std_logic;
signal logical2_y_net: std_logic;
signal logical3_y_net: std_logic;
signal logical_y_net: std_logic;
signal logical_y_net_x0: std_logic;
signal logical_y_net_x2: std_logic;
signal mux1_y_net: std_logic;
signal mux2_y_net_x0: std_logic;
signal mux3_y_net: std_logic_vector(8 downto 0);
signal mux_y_net_x0: std_logic_vector(15 downto 0);
signal register_q_net_x0: std_logic;
signal relational1_op_net: std_logic;
signal relational_op_net: std_logic;
signal shared_memory_data_out_net_x1: std_logic_vector(31 downto 0);
signal slice2_y_net: std_logic_vector(7 downto 0);
signal slice3_y_net: std_logic;
signal slice4_y_net_x0: std_logic;
signal slice5_y_net: std_logic_vector(8 downto 0);
signal x8msb_y_net_x1: std_logic_vector(7 downto 0);
begin
ce_1_sg_x9 <= ce_1;
clk_1_sg_x9 <= clk_1;
from_register1_data_out_net_x0 <= from_register1;
from_register2_data_out_net_x0 <= from_register2;
from_register3_data_out_net_x1 <= from_register3;
from_register4_data_out_net_x0 <= from_register4;
from_register5_data_out_net_x0 <= from_register5;
from_register6_data_out_net_x0 <= from_register6;
convert1_dout_net_x2 <= reset;
logical_y_net_x2 <= sendcmds;
shared_memory_data_out_net_x1 <= shared_memory;
from_register3_data_out_net_x2 <= totalnoofcmds;
convert1_dout_net_x3 <= transferdone;
cmdsdone <= register_q_net_x0;
command_memory <= x8msb_y_net_x1;
command_memory_x0 <= constant_op_net_x1;
command_memory_x1 <= constant1_op_net_x1;
datatosend <= concat2_y_net_x0;
starttransfer <= mux2_y_net_x0;
accumulator: entity work.accum_2cb0e56e96
port map (
b(0) => convert_dout_net,
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
clr => '0',
en(0) => logical1_y_net,
rst(0) => logical_y_net_x2,
q => accumulator_q_net
);
accumulator1: entity work.accum_be45dd0aa2
port map (
b(0) => convert1_dout_net,
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
clr => '0',
rst(0) => convert1_dout_net_x2,
q => accumulator1_q_net
);
addsub: entity work.xladdsub
generic map (
a_arith => xlUnsigned,
a_bin_pt => 0,
a_width => 8,
b_arith => xlUnsigned,
b_bin_pt => 0,
b_width => 1,
c_has_b_out => 0,
c_has_c_out => 0,
c_has_q => 0,
c_has_q_b_out => 0,
c_has_q_c_out => 0,
c_has_s => 1,
c_latency => 0,
c_output_width => 9,
core_name0 => "adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 9,
latency => 0,
mode => 2,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 0,
s_width => 9
)
port map (
a => from_register3_data_out_net_x2,
b(0) => constant3_op_net,
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
clr => '0',
en => "1",
s => addsub_s_net
);
command_memory_ca978db4f0: entity work.command_memory_entity_ca978db4f0
port map (
addr_9b => concat_y_net_x0,
shared_memory => shared_memory_data_out_net_x1,
constant1_x0 => constant1_op_net_x1,
constant_x1 => constant_op_net_x1,
data_16b => mux_y_net_x0,
x8msb_x0 => x8msb_y_net_x1
);
concat: entity work.concat_f62149b02a
port map (
ce => '0',
clk => '0',
clr => '0',
in0 => from_register6_data_out_net_x0,
in1 => counter_op_net,
y => concat_y_net_x0
);
concat2: entity work.concat_1ece14600f
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => inverter1_op_net,
in1 => slice2_y_net,
y => concat2_y_net_x0
);
constant11: entity work.constant_443ed96427
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant11_op_net
);
constant2: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant2_op_net
);
constant3: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant3_op_net
);
constant4: entity work.constant_145086465d
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant4_op_net
);
constant5: entity work.constant_fb9f6d3796
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant5_op_net
);
constant6: entity work.constant_09a4afb2ee
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant6_op_net
);
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din(0) => delay_q_net,
dout(0) => convert_dout_net
);
convert1: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din(0) => logical3_y_net,
dout(0) => convert1_dout_net
);
convert2: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 5,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
clr => '0',
din(0) => logical_y_net_x0,
dout(0) => convert2_dout_net
);
counter: entity work.xlcounter_free
generic map (
core_name0 => "binary_counter_virtex2p_7_0_b0a257f5389d649a",
op_arith => xlUnsigned,
op_width => 7
)
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
clr => '0',
en(0) => logical_y_net,
rst(0) => convert1_dout_net_x2,
op => counter_op_net
);
counter1: entity work.xlcounter_limit
generic map (
cnt_15_0 => 17435,
cnt_31_16 => 0,
cnt_47_32 => 0,
cnt_63_48 => 0,
core_name0 => "binary_counter_virtex2p_7_0_32a1863440903b9d",
count_limited => 1,
op_arith => xlUnsigned,
op_width => 15
)
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
clr => '0',
en(0) => logical2_y_net,
rst(0) => convert1_dout_net_x2,
op => counter1_op_net
);
delay: entity work.xldelay
generic map (
latency => 4,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
d(0) => logical_y_net,
en => '1',
q(0) => delay_q_net
);
inverter1: entity work.inverter_e2b989a05e
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
clr => '0',
ip(0) => slice3_y_net,
op(0) => inverter1_op_net
);
inverter2: entity work.inverter_e5b38cca3b
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
clr => '0',
ip(0) => relational_op_net,
op(0) => inverter2_op_net
);
logical: entity work.logical_aacf6e1b0e
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => logical_y_net_x2,
d1(0) => convert1_dout_net_x3,
y(0) => logical_y_net
);
logical1: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => delay_q_net,
d1(0) => relational_op_net,
y(0) => logical1_y_net
);
logical2: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => inverter2_op_net,
d1(0) => convert1_dout_net_x3,
y(0) => logical2_y_net
);
logical3: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => relational1_op_net,
d1(0) => logical2_y_net,
y(0) => logical3_y_net
);
mux1: entity work.mux_d99e59b6d4
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => constant2_op_net,
d1(0) => delay_q_net,
sel(0) => relational_op_net,
y(0) => mux1_y_net
);
mux2: entity work.mux_d99e59b6d4
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => mux1_y_net,
d1(0) => delay_q_net,
sel(0) => inverter2_op_net,
y(0) => mux2_y_net_x0
);
mux3: entity work.mux_1f00a411aa
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => slice5_y_net,
d1 => constant5_op_net,
d2 => from_register1_data_out_net_x0,
d3 => from_register2_data_out_net_x0,
d4 => constant6_op_net,
d5 => from_register4_data_out_net_x0,
d6 => from_register5_data_out_net_x0,
d7 => constant11_op_net,
d8 => from_register3_data_out_net_x1,
sel => accumulator1_q_net,
y => mux3_y_net
);
neg_edge_detector_b797592ea5: entity work.neg_edge_detector_entity_b797592ea5
port map (
ce_1 => ce_1_sg_x9,
clk_1 => clk_1_sg_x9,
input_signal => slice4_y_net_x0,
rising_edge => logical_y_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
d(0) => convert2_dout_net,
en(0) => convert2_dout_net,
rst(0) => convert1_dout_net_x2,
q(0) => register_q_net_x0
);
relational: entity work.relational_92c392c8b6
port map (
a => accumulator_q_net,
b => addsub_s_net,
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_fb96203f91
port map (
a => accumulator1_q_net,
b => constant4_op_net,
ce => '0',
clk => '0',
clr => '0',
op(0) => relational1_op_net
);
slice2: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 7,
x_width => 9,
y_width => 8
)
port map (
x => mux3_y_net,
y => slice2_y_net
);
slice3: entity work.xlslice
generic map (
new_lsb => 8,
new_msb => 8,
x_width => 9,
y_width => 1
)
port map (
x => mux3_y_net,
y(0) => slice3_y_net
);
slice4: entity work.xlslice
generic map (
new_lsb => 14,
new_msb => 14,
x_width => 15,
y_width => 1
)
port map (
x => counter1_op_net,
y(0) => slice4_y_net_x0
);
slice5: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 8,
x_width => 16,
y_width => 9
)
port map (
x => mux_y_net_x0,
y => slice5_y_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller/DataROM/Character Buffer Shared Memory"
entity character_buffer_shared_memory_entity_1eeb1f8786 is
port (
addr_11b: in std_logic_vector(10 downto 0);
shared_memory: in std_logic_vector(31 downto 0);
constant1_x0: out std_logic;
constant_x1: out std_logic_vector(31 downto 0);
data_8b: out std_logic_vector(7 downto 0);
x9msb_x0: out std_logic_vector(8 downto 0)
);
end character_buffer_shared_memory_entity_1eeb1f8786;
architecture structural of character_buffer_shared_memory_entity_1eeb1f8786 is
signal concat1_y_net_x0: std_logic_vector(10 downto 0);
signal constant1_op_net_x0: std_logic;
signal constant_op_net_x0: std_logic_vector(31 downto 0);
signal mux_y_net_x0: std_logic_vector(7 downto 0);
signal shared_memory_data_out_net_x0: std_logic_vector(31 downto 0);
signal x2lsb_y_net: std_logic_vector(1 downto 0);
signal x8lsb_0_y_net: std_logic_vector(7 downto 0);
signal x8lsb_16_y_net: std_logic_vector(7 downto 0);
signal x8lsb_24_y_net: std_logic_vector(7 downto 0);
signal x8lsb_8_y_net: std_logic_vector(7 downto 0);
signal x9msb_y_net_x0: std_logic_vector(8 downto 0);
begin
concat1_y_net_x0 <= addr_11b;
shared_memory_data_out_net_x0 <= shared_memory;
constant1_x0 <= constant1_op_net_x0;
constant_x1 <= constant_op_net_x0;
data_8b <= mux_y_net_x0;
x9msb_x0 <= x9msb_y_net_x0;
constant1: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant1_op_net_x0
);
constant_x0: entity work.constant_37567836aa
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant_op_net_x0
);
mux: entity work.mux_998e20a1ca
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => x8lsb_24_y_net,
d1 => x8lsb_16_y_net,
d2 => x8lsb_8_y_net,
d3 => x8lsb_0_y_net,
sel => x2lsb_y_net,
y => mux_y_net_x0
);
x2lsb: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 1,
x_width => 11,
y_width => 2
)
port map (
x => concat1_y_net_x0,
y => x2lsb_y_net
);
x8lsb_0: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 7,
x_width => 32,
y_width => 8
)
port map (
x => shared_memory_data_out_net_x0,
y => x8lsb_0_y_net
);
x8lsb_16: entity work.xlslice
generic map (
new_lsb => 16,
new_msb => 23,
x_width => 32,
y_width => 8
)
port map (
x => shared_memory_data_out_net_x0,
y => x8lsb_16_y_net
);
x8lsb_24: entity work.xlslice
generic map (
new_lsb => 24,
new_msb => 31,
x_width => 32,
y_width => 8
)
port map (
x => shared_memory_data_out_net_x0,
y => x8lsb_24_y_net
);
x8lsb_8: entity work.xlslice
generic map (
new_lsb => 8,
new_msb => 15,
x_width => 32,
y_width => 8
)
port map (
x => shared_memory_data_out_net_x0,
y => x8lsb_8_y_net
);
x9msb: entity work.xlslice
generic map (
new_lsb => 2,
new_msb => 10,
x_width => 11,
y_width => 9
)
port map (
x => concat1_y_net_x0,
y => x9msb_y_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller/DataROM/Character Map Shared Memory"
entity character_map_shared_memory_entity_e504c38a5b is
port (
addr_14b: in std_logic_vector(13 downto 0);
shared_memory: in std_logic_vector(31 downto 0);
constant1_x0: out std_logic;
constant_x1: out std_logic_vector(31 downto 0);
data_8b: out std_logic_vector(7 downto 0);
x12msb_x0: out std_logic_vector(11 downto 0)
);
end character_map_shared_memory_entity_e504c38a5b;
architecture structural of character_map_shared_memory_entity_e504c38a5b is
signal concat_y_net_x0: std_logic_vector(13 downto 0);
signal constant1_op_net_x0: std_logic;
signal constant_op_net_x0: std_logic_vector(31 downto 0);
signal mux_y_net_x0: std_logic_vector(7 downto 0);
signal shared_memory_data_out_net_x0: std_logic_vector(31 downto 0);
signal x12msb_y_net_x0: std_logic_vector(11 downto 0);
signal x2lsb_y_net: std_logic_vector(1 downto 0);
signal x8lsb_0_y_net: std_logic_vector(7 downto 0);
signal x8lsb_16_y_net: std_logic_vector(7 downto 0);
signal x8lsb_24_y_net: std_logic_vector(7 downto 0);
signal x8lsb_8_y_net: std_logic_vector(7 downto 0);
begin
concat_y_net_x0 <= addr_14b;
shared_memory_data_out_net_x0 <= shared_memory;
constant1_x0 <= constant1_op_net_x0;
constant_x1 <= constant_op_net_x0;
data_8b <= mux_y_net_x0;
x12msb_x0 <= x12msb_y_net_x0;
constant1: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant1_op_net_x0
);
constant_x0: entity work.constant_37567836aa
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant_op_net_x0
);
mux: entity work.mux_998e20a1ca
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => x8lsb_24_y_net,
d1 => x8lsb_16_y_net,
d2 => x8lsb_8_y_net,
d3 => x8lsb_0_y_net,
sel => x2lsb_y_net,
y => mux_y_net_x0
);
x12msb: entity work.xlslice
generic map (
new_lsb => 2,
new_msb => 13,
x_width => 14,
y_width => 12
)
port map (
x => concat_y_net_x0,
y => x12msb_y_net_x0
);
x2lsb: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 1,
x_width => 14,
y_width => 2
)
port map (
x => concat_y_net_x0,
y => x2lsb_y_net
);
x8lsb_0: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 7,
x_width => 32,
y_width => 8
)
port map (
x => shared_memory_data_out_net_x0,
y => x8lsb_0_y_net
);
x8lsb_16: entity work.xlslice
generic map (
new_lsb => 16,
new_msb => 23,
x_width => 32,
y_width => 8
)
port map (
x => shared_memory_data_out_net_x0,
y => x8lsb_16_y_net
);
x8lsb_24: entity work.xlslice
generic map (
new_lsb => 24,
new_msb => 31,
x_width => 32,
y_width => 8
)
port map (
x => shared_memory_data_out_net_x0,
y => x8lsb_24_y_net
);
x8lsb_8: entity work.xlslice
generic map (
new_lsb => 8,
new_msb => 15,
x_width => 32,
y_width => 8
)
port map (
x => shared_memory_data_out_net_x0,
y => x8lsb_8_y_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller/DataROM/Pos Edge Detector"
entity pos_edge_detector_entity_90ec5fccc3 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
input_signal: in std_logic;
rising_edge: out std_logic
);
end pos_edge_detector_entity_90ec5fccc3;
architecture structural of pos_edge_detector_entity_90ec5fccc3 is
signal ce_1_sg_x10: std_logic;
signal clk_1_sg_x10: std_logic;
signal delay_q_net: std_logic;
signal inverter_op_net: std_logic;
signal logical_y_net_x0: std_logic;
signal relational_op_net_x0: std_logic;
begin
ce_1_sg_x10 <= ce_1;
clk_1_sg_x10 <= clk_1;
relational_op_net_x0 <= input_signal;
rising_edge <= logical_y_net_x0;
delay: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x10,
clk => clk_1_sg_x10,
d(0) => inverter_op_net,
en => '1',
q(0) => delay_q_net
);
inverter: entity work.inverter_e5b38cca3b
port map (
ce => ce_1_sg_x10,
clk => clk_1_sg_x10,
clr => '0',
ip(0) => relational_op_net_x0,
op(0) => inverter_op_net
);
logical: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => relational_op_net_x0,
d1(0) => delay_q_net,
y(0) => logical_y_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller/DataROM/Subsystem"
entity subsystem_entity_8d430c7bea is
port (
ce_1: in std_logic;
clk_1: in std_logic;
not0: in std_logic;
transferdone: in std_logic;
x6bitval: in std_logic;
out1: out std_logic
);
end subsystem_entity_8d430c7bea;
architecture structural of subsystem_entity_8d430c7bea is
signal ce_1_sg_x11: std_logic;
signal clk_1_sg_x11: std_logic;
signal delay_q_net: std_logic;
signal inverter2_op_net_x0: std_logic;
signal logical1_y_net: std_logic;
signal logical2_y_net: std_logic;
signal logical3_y_net_x0: std_logic;
signal logical_y_net_x0: std_logic;
signal relational_op_net_x1: std_logic;
begin
ce_1_sg_x11 <= ce_1;
clk_1_sg_x11 <= clk_1;
inverter2_op_net_x0 <= not0;
logical_y_net_x0 <= transferdone;
relational_op_net_x1 <= x6bitval;
out1 <= logical3_y_net_x0;
delay: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x11,
clk => clk_1_sg_x11,
d(0) => logical_y_net_x0,
en => '1',
q(0) => delay_q_net
);
logical1: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => inverter2_op_net_x0,
d1(0) => delay_q_net,
y(0) => logical1_y_net
);
logical2: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => relational_op_net_x1,
d1(0) => delay_q_net,
y(0) => logical2_y_net
);
logical3: entity work.logical_aacf6e1b0e
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => logical2_y_net,
d1(0) => logical1_y_net,
y(0) => logical3_y_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller/DataROM/Subsystem1"
entity subsystem1_entity_a91e11b915 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
x4bits: in std_logic_vector(3 downto 0);
end_x0: out std_logic_vector(8 downto 0);
start: out std_logic_vector(8 downto 0)
);
end subsystem1_entity_a91e11b915;
architecture structural of subsystem1_entity_a91e11b915 is
signal addsub1_s_net_x0: std_logic_vector(8 downto 0);
signal addsub_s_net_x0: std_logic_vector(8 downto 0);
signal ce_1_sg_x12: std_logic;
signal clk_1_sg_x12: std_logic;
signal concat6_y_net: std_logic_vector(6 downto 0);
signal constant1_op_net: std_logic_vector(7 downto 0);
signal constant2_op_net: std_logic_vector(7 downto 0);
signal constant_op_net: std_logic_vector(2 downto 0);
signal slice10_y_net_x0: std_logic_vector(3 downto 0);
begin
ce_1_sg_x12 <= ce_1;
clk_1_sg_x12 <= clk_1;
slice10_y_net_x0 <= x4bits;
end_x0 <= addsub1_s_net_x0;
start <= addsub_s_net_x0;
addsub: entity work.xladdsub
generic map (
a_arith => xlUnsigned,
a_bin_pt => 0,
a_width => 7,
b_arith => xlUnsigned,
b_bin_pt => 0,
b_width => 8,
c_has_b_out => 0,
c_has_c_out => 0,
c_has_q => 0,
c_has_q_b_out => 0,
c_has_q_c_out => 0,
c_has_s => 1,
c_latency => 0,
c_output_width => 9,
core_name0 => "adder_subtracter_virtex2p_7_0_453ed16ba8e84295",
extra_registers => 0,
full_s_arith => 1,
full_s_width => 9,
latency => 0,
mode => 1,
overflow => 1,
quantization => 1,
s_arith => xlUnsigned,
s_bin_pt => 0,
s_width => 9
)
port map (
a => concat6_y_net,
b => constant1_op_net,
ce => ce_1_sg_x12,
clk => clk_1_sg_x12,
clr => '0',
en => "1",
s => addsub_s_net_x0
);
addsub1: entity work.xladdsub
generic map (
a_arith => xlUnsigned,
a_bin_pt => 0,
a_width => 7,
b_arith => xlUnsigned,
b_bin_pt => 0,
b_width => 8,
c_has_b_out => 0,
c_has_c_out => 0,
c_has_q => 0,
c_has_q_b_out => 0,
c_has_q_c_out => 0,
c_has_s => 1,
c_latency => 0,
c_output_width => 9,
core_name0 => "adder_subtracter_virtex2p_7_0_453ed16ba8e84295",
extra_registers => 0,
full_s_arith => 1,
full_s_width => 9,
latency => 0,
mode => 1,
overflow => 1,
quantization => 1,
s_arith => xlUnsigned,
s_bin_pt => 0,
s_width => 9
)
port map (
a => concat6_y_net,
b => constant2_op_net,
ce => ce_1_sg_x12,
clk => clk_1_sg_x12,
clr => '0',
en => "1",
s => addsub1_s_net_x0
);
concat6: entity work.concat_32864ba5d6
port map (
ce => '0',
clk => '0',
clr => '0',
in0 => slice10_y_net_x0,
in1 => constant_op_net,
y => concat6_y_net
);
constant1: entity work.constant_21d4a28b7e
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant1_op_net
);
constant2: entity work.constant_b940b9054a
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant2_op_net
);
constant_x0: entity work.constant_822933f89b
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller/DataROM"
entity datarom_entity_fd2cd392cc is
port (
ce_1: in std_logic;
clk_1: in std_logic;
cmdsdone: in std_logic;
from_register1: in std_logic_vector(8 downto 0);
from_register2: in std_logic_vector(8 downto 0);
from_register3: in std_logic_vector(8 downto 0);
from_register4: in std_logic_vector(2 downto 0);
from_register5: in std_logic_vector(3 downto 0);
from_register7: in std_logic_vector(3 downto 0);
reset: in std_logic;
shared_memory: in std_logic_vector(31 downto 0);
shared_memory_x0: in std_logic_vector(31 downto 0);
transferdone: in std_logic;
character_buffer_shared_memory: out std_logic_vector(8 downto 0);
character_buffer_shared_memory_x0: out std_logic_vector(31 downto 0);
character_buffer_shared_memory_x1: out std_logic;
character_map_shared_memory: out std_logic_vector(11 downto 0);
character_map_shared_memory_x0: out std_logic_vector(31 downto 0);
character_map_shared_memory_x1: out std_logic;
data: out std_logic_vector(8 downto 0);
starttransfer: out std_logic
);
end datarom_entity_fd2cd392cc;
architecture structural of datarom_entity_fd2cd392cc is
signal addsub1_s_net: std_logic_vector(3 downto 0);
signal addsub1_s_net_x0: std_logic_vector(8 downto 0);
signal addsub1_s_net_x1: std_logic_vector(8 downto 0);
signal addsub2_s_net: std_logic_vector(3 downto 0);
signal addsub_s_net_x0: std_logic_vector(8 downto 0);
signal addsub_s_net_x1: std_logic_vector(8 downto 0);
signal ce_1_sg_x14: std_logic;
signal clk_1_sg_x14: std_logic;
signal concat1_y_net_x0: std_logic_vector(10 downto 0);
signal concat3_y_net: std_logic_vector(1 downto 0);
signal concat4_y_net_x0: std_logic_vector(8 downto 0);
signal concat5_y_net: std_logic_vector(8 downto 0);
signal concat_y_net_x0: std_logic_vector(13 downto 0);
signal constant10_op_net: std_logic;
signal constant1_op_net_x2: std_logic;
signal constant1_op_net_x3: std_logic;
signal constant4_op_net: std_logic;
signal constant5_op_net: std_logic;
signal constant6_op_net: std_logic_vector(2 downto 0);
signal constant7_op_net: std_logic_vector(2 downto 0);
signal constant8_op_net: std_logic_vector(2 downto 0);
signal constant9_op_net: std_logic;
signal constant_op_net_x2: std_logic_vector(31 downto 0);
signal constant_op_net_x3: std_logic_vector(31 downto 0);
signal convert1_dout_net: std_logic;
signal convert1_dout_net_x4: std_logic;
signal convert1_dout_net_x5: std_logic;
signal convert_dout_net: std_logic;
signal counter1_op_net: std_logic_vector(13 downto 0);
signal counter_op_net: std_logic_vector(2 downto 0);
signal delay_q_net_x0: std_logic;
signal from_register1_data_out_net_x0: std_logic_vector(8 downto 0);
signal from_register2_data_out_net_x0: std_logic_vector(8 downto 0);
signal from_register3_data_out_net_x0: std_logic_vector(8 downto 0);
signal from_register4_data_out_net_x0: std_logic_vector(2 downto 0);
signal from_register5_data_out_net_x0: std_logic_vector(3 downto 0);
signal from_register7_data_out_net_x0: std_logic_vector(3 downto 0);
signal inverter2_op_net_x0: std_logic;
signal inverter3_op_net: std_logic;
signal logical1_y_net: std_logic;
signal logical3_y_net_x0: std_logic;
signal logical_y_net_x0: std_logic;
signal logical_y_net_x1: std_logic;
signal mux2_y_net: std_logic_vector(2 downto 0);
signal mux3_y_net: std_logic_vector(8 downto 0);
signal mux_y_net_x0: std_logic_vector(7 downto 0);
signal mux_y_net_x1: std_logic_vector(7 downto 0);
signal register_q_net: std_logic_vector(5 downto 0);
signal register_q_net_x1: std_logic;
signal relational1_op_net: std_logic;
signal relational2_op_net: std_logic;
signal relational_op_net_x1: std_logic;
signal shared_memory_data_out_net_x2: std_logic_vector(31 downto 0);
signal shared_memory_data_out_net_x3: std_logic_vector(31 downto 0);
signal slice10_y_net_x0: std_logic_vector(3 downto 0);
signal slice11_y_net_x0: std_logic_vector(3 downto 0);
signal slice4_y_net: std_logic_vector(7 downto 0);
signal slice5_y_net: std_logic_vector(5 downto 0);
signal slice6_y_net: std_logic_vector(5 downto 0);
signal slice7_y_net: std_logic_vector(3 downto 0);
signal slice8_y_net: std_logic_vector(7 downto 0);
signal slice9_y_net: std_logic;
signal x12msb_y_net_x1: std_logic_vector(11 downto 0);
signal x4lsb_y_net: std_logic_vector(3 downto 0);
signal x4msb_y_net: std_logic_vector(3 downto 0);
signal x9msb_y_net_x1: std_logic_vector(8 downto 0);
begin
ce_1_sg_x14 <= ce_1;
clk_1_sg_x14 <= clk_1;
register_q_net_x1 <= cmdsdone;
from_register1_data_out_net_x0 <= from_register1;
from_register2_data_out_net_x0 <= from_register2;
from_register3_data_out_net_x0 <= from_register3;
from_register4_data_out_net_x0 <= from_register4;
from_register5_data_out_net_x0 <= from_register5;
from_register7_data_out_net_x0 <= from_register7;
convert1_dout_net_x4 <= reset;
shared_memory_data_out_net_x2 <= shared_memory;
shared_memory_data_out_net_x3 <= shared_memory_x0;
convert1_dout_net_x5 <= transferdone;
character_buffer_shared_memory <= x9msb_y_net_x1;
character_buffer_shared_memory_x0 <= constant_op_net_x2;
character_buffer_shared_memory_x1 <= constant1_op_net_x2;
character_map_shared_memory <= x12msb_y_net_x1;
character_map_shared_memory_x0 <= constant_op_net_x3;
character_map_shared_memory_x1 <= constant1_op_net_x3;
data <= concat4_y_net_x0;
starttransfer <= delay_q_net_x0;
addsub1: entity work.xladdsub
generic map (
a_arith => xlUnsigned,
a_bin_pt => 0,
a_width => 4,
b_arith => xlUnsigned,
b_bin_pt => 0,
b_width => 4,
c_has_b_out => 0,
c_has_c_out => 0,
c_has_q => 0,
c_has_q_b_out => 0,
c_has_q_c_out => 0,
c_has_s => 1,
c_latency => 0,
c_output_width => 5,
core_name0 => "adder_subtracter_virtex2p_7_0_7182743c9e7adf5e",
extra_registers => 0,
full_s_arith => 1,
full_s_width => 5,
latency => 0,
mode => 1,
overflow => 1,
quantization => 1,
s_arith => xlUnsigned,
s_bin_pt => 0,
s_width => 4
)
port map (
a => from_register7_data_out_net_x0,
b => x4msb_y_net,
ce => ce_1_sg_x14,
clk => clk_1_sg_x14,
clr => '0',
en => "1",
s => addsub1_s_net
);
addsub2: entity work.xladdsub
generic map (
a_arith => xlUnsigned,
a_bin_pt => 0,
a_width => 4,
b_arith => xlUnsigned,
b_bin_pt => 0,
b_width => 4,
c_has_b_out => 0,
c_has_c_out => 0,
c_has_q => 0,
c_has_q_b_out => 0,
c_has_q_c_out => 0,
c_has_s => 1,
c_latency => 0,
c_output_width => 5,
core_name0 => "adder_subtracter_virtex2p_7_0_7182743c9e7adf5e",
extra_registers => 0,
full_s_arith => 1,
full_s_width => 5,
latency => 0,
mode => 1,
overflow => 1,
quantization => 1,
s_arith => xlUnsigned,
s_bin_pt => 0,
s_width => 4
)
port map (
a => x4lsb_y_net,
b => from_register5_data_out_net_x0,
ce => ce_1_sg_x14,
clk => clk_1_sg_x14,
clr => '0',
en => "1",
s => addsub2_s_net
);
character_buffer_shared_memory_1eeb1f8786: entity work.character_buffer_shared_memory_entity_1eeb1f8786
port map (
addr_11b => concat1_y_net_x0,
shared_memory => shared_memory_data_out_net_x2,
constant1_x0 => constant1_op_net_x2,
constant_x1 => constant_op_net_x2,
data_8b => mux_y_net_x0,
x9msb_x0 => x9msb_y_net_x1
);
character_map_shared_memory_e504c38a5b: entity work.character_map_shared_memory_entity_e504c38a5b
port map (
addr_14b => concat_y_net_x0,
shared_memory => shared_memory_data_out_net_x3,
constant1_x0 => constant1_op_net_x3,
constant_x1 => constant_op_net_x3,
data_8b => mux_y_net_x1,
x12msb_x0 => x12msb_y_net_x1
);
concat: entity work.concat_25ab81b400
port map (
ce => '0',
clk => '0',
clr => '0',
in0 => mux_y_net_x0,
in1 => register_q_net,
y => concat_y_net_x0
);
concat1: entity work.concat_78218439f3
port map (
ce => '0',
clk => '0',
clr => '0',
in0 => from_register4_data_out_net_x0,
in1 => addsub1_s_net,
in2 => addsub2_s_net,
y => concat1_y_net_x0
);
concat3: entity work.concat_e6f5ee726b
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => convert_dout_net,
in1(0) => convert1_dout_net,
y => concat3_y_net
);
concat4: entity work.concat_1ece14600f
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => inverter3_op_net,
in1 => slice8_y_net,
y => concat4_y_net_x0
);
concat5: entity work.concat_1ece14600f
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => constant10_op_net,
in1 => mux_y_net_x1,
y => concat5_y_net
);
constant10: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant10_op_net
);
constant4: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant4_op_net
);
constant5: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant5_op_net
);
constant6: entity work.constant_822933f89b
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant6_op_net
);
constant7: entity work.constant_469094441c
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant7_op_net
);
constant8: entity work.constant_a1c496ea88
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant8_op_net
);
constant9: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant9_op_net
);
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din(0) => relational_op_net_x1,
dout(0) => convert_dout_net
);
convert1: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din(0) => relational1_op_net,
dout(0) => convert1_dout_net
);
counter: entity work.xlcounter_free
generic map (
core_name0 => "binary_counter_virtex2p_7_0_b511f9871581ee23",
op_arith => xlUnsigned,
op_width => 3
)
port map (
ce => ce_1_sg_x14,
clk => clk_1_sg_x14,
clr => '0',
din => mux2_y_net,
en(0) => logical3_y_net_x0,
load(0) => logical_y_net_x1,
rst => "0",
op => counter_op_net
);
counter1: entity work.xlcounter_free
generic map (
core_name0 => "binary_counter_virtex2p_7_0_a22528b4c55dc1cd",
op_arith => xlUnsigned,
op_width => 14
)
port map (
ce => ce_1_sg_x14,
clk => clk_1_sg_x14,
clr => '0',
en(0) => logical1_y_net,
rst(0) => convert1_dout_net_x4,
op => counter1_op_net
);
delay: entity work.xldelay
generic map (
latency => 4,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x14,
clk => clk_1_sg_x14,
d(0) => logical_y_net_x0,
en => '1',
q(0) => delay_q_net_x0
);
inverter2: entity work.inverter_e5b38cca3b
port map (
ce => ce_1_sg_x14,
clk => clk_1_sg_x14,
clr => '0',
ip(0) => relational2_op_net,
op(0) => inverter2_op_net_x0
);
inverter3: entity work.inverter_e2b989a05e
port map (
ce => ce_1_sg_x14,
clk => clk_1_sg_x14,
clr => '0',
ip(0) => slice9_y_net,
op(0) => inverter3_op_net
);
logical: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => convert1_dout_net_x5,
d1(0) => register_q_net_x1,
y(0) => logical_y_net_x0
);
logical1: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => relational2_op_net,
d1(0) => logical_y_net_x0,
y(0) => logical1_y_net
);
mux2: entity work.mux_2ec2057ae3
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => constant6_op_net,
d1 => constant6_op_net,
d2 => constant7_op_net,
d3 => constant8_op_net,
sel => concat3_y_net,
y => mux2_y_net
);
mux3: entity work.mux_7586447000
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => concat5_y_net,
d1 => from_register3_data_out_net_x0,
d2 => addsub_s_net_x0,
d3 => addsub1_s_net_x0,
d4 => from_register1_data_out_net_x0,
d5 => addsub_s_net_x1,
d6 => addsub1_s_net_x1,
d7 => from_register2_data_out_net_x0,
sel => counter_op_net,
y => mux3_y_net
);
pos_edge_detector_90ec5fccc3: entity work.pos_edge_detector_entity_90ec5fccc3
port map (
ce_1 => ce_1_sg_x14,
clk_1 => clk_1_sg_x14,
input_signal => relational_op_net_x1,
rising_edge => logical_y_net_x1
);
register_x0: entity work.xlregister
generic map (
d_width => 6,
init_value => b"000000"
)
port map (
ce => ce_1_sg_x14,
clk => clk_1_sg_x14,
d => slice5_y_net,
en => "1",
rst => "0",
q => register_q_net
);
relational: entity work.relational_f7cb2b0c31
port map (
a => slice6_y_net,
b(0) => constant4_op_net,
ce => '0',
clk => '0',
clr => '0',
op(0) => relational_op_net_x1
);
relational1: entity work.relational_ee03197e2c
port map (
a => slice7_y_net,
b(0) => constant5_op_net,
ce => '0',
clk => '0',
clr => '0',
op(0) => relational1_op_net
);
relational2: entity work.relational_04b069dd89
port map (
a => counter_op_net,
b(0) => constant9_op_net,
ce => '0',
clk => '0',
clr => '0',
op(0) => relational2_op_net
);
slice10: entity work.xlslice
generic map (
new_lsb => 10,
new_msb => 13,
x_width => 14,
y_width => 4
)
port map (
x => counter1_op_net,
y => slice10_y_net_x0
);
slice11: entity work.xlslice
generic map (
new_lsb => 6,
new_msb => 9,
x_width => 14,
y_width => 4
)
port map (
x => counter1_op_net,
y => slice11_y_net_x0
);
slice4: entity work.xlslice
generic map (
new_lsb => 6,
new_msb => 13,
x_width => 14,
y_width => 8
)
port map (
x => counter1_op_net,
y => slice4_y_net
);
slice5: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 5,
x_width => 14,
y_width => 6
)
port map (
x => counter1_op_net,
y => slice5_y_net
);
slice6: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 5,
x_width => 14,
y_width => 6
)
port map (
x => counter1_op_net,
y => slice6_y_net
);
slice7: entity work.xlslice
generic map (
new_lsb => 6,
new_msb => 9,
x_width => 14,
y_width => 4
)
port map (
x => counter1_op_net,
y => slice7_y_net
);
slice8: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 7,
x_width => 9,
y_width => 8
)
port map (
x => mux3_y_net,
y => slice8_y_net
);
slice9: entity work.xlslice
generic map (
new_lsb => 8,
new_msb => 8,
x_width => 9,
y_width => 1
)
port map (
x => mux3_y_net,
y(0) => slice9_y_net
);
subsystem1_a91e11b915: entity work.subsystem1_entity_a91e11b915
port map (
ce_1 => ce_1_sg_x14,
clk_1 => clk_1_sg_x14,
x4bits => slice10_y_net_x0,
end_x0 => addsub1_s_net_x0,
start => addsub_s_net_x0
);
subsystem2_4e1ae86655: entity work.subsystem1_entity_a91e11b915
port map (
ce_1 => ce_1_sg_x14,
clk_1 => clk_1_sg_x14,
x4bits => slice11_y_net_x0,
end_x0 => addsub1_s_net_x1,
start => addsub_s_net_x1
);
subsystem_8d430c7bea: entity work.subsystem_entity_8d430c7bea
port map (
ce_1 => ce_1_sg_x14,
clk_1 => clk_1_sg_x14,
not0 => inverter2_op_net_x0,
transferdone => logical_y_net_x0,
x6bitval => relational_op_net_x1,
out1 => logical3_y_net_x0
);
x4lsb: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 3,
x_width => 8,
y_width => 4
)
port map (
x => slice4_y_net,
y => x4lsb_y_net
);
x4msb: entity work.xlslice
generic map (
new_lsb => 4,
new_msb => 7,
x_width => 8,
y_width => 4
)
port map (
x => slice4_y_net,
y => x4msb_y_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller/SPI/Data_Latch"
entity data_latch_entity_d697580f4e is
port (
bit_select: in std_logic_vector(3 downto 0);
ce_1: in std_logic;
clk_1: in std_logic;
data_to_transmit: in std_logic_vector(8 downto 0);
latchdata: in std_logic;
reset: in std_logic;
spi_data: out std_logic
);
end data_latch_entity_d697580f4e;
architecture structural of data_latch_entity_d697580f4e is
signal ce_1_sg_x16: std_logic;
signal clk_1_sg_x16: std_logic;
signal convert1_dout_net_x5: std_logic;
signal counter_op_net_x0: std_logic_vector(3 downto 0);
signal mux1_y_net_x0: std_logic;
signal mux_y_net_x1: std_logic_vector(8 downto 0);
signal mux_y_net_x2: std_logic;
signal register_q_net: std_logic_vector(8 downto 0);
signal slice1_y_net: std_logic;
signal slice2_y_net: std_logic;
signal slice3_y_net: std_logic;
signal slice4_y_net: std_logic;
signal slice5_y_net: std_logic;
signal slice6_y_net: std_logic;
signal slice7_y_net: std_logic;
signal slice8_y_net: std_logic;
signal slice_y_net: std_logic;
begin
counter_op_net_x0 <= bit_select;
ce_1_sg_x16 <= ce_1;
clk_1_sg_x16 <= clk_1;
mux_y_net_x1 <= data_to_transmit;
mux1_y_net_x0 <= latchdata;
convert1_dout_net_x5 <= reset;
spi_data <= mux_y_net_x2;
mux: entity work.mux_8e3eece8f2
port map (
ce => ce_1_sg_x16,
clk => clk_1_sg_x16,
clr => '0',
d0(0) => slice_y_net,
d1(0) => slice1_y_net,
d2(0) => slice2_y_net,
d3(0) => slice3_y_net,
d4(0) => slice4_y_net,
d5(0) => slice5_y_net,
d6(0) => slice6_y_net,
d7(0) => slice7_y_net,
d8(0) => slice8_y_net,
sel => counter_op_net_x0,
y(0) => mux_y_net_x2
);
register_x0: entity work.xlregister
generic map (
d_width => 9,
init_value => b"000000000"
)
port map (
ce => ce_1_sg_x16,
clk => clk_1_sg_x16,
d => mux_y_net_x1,
en(0) => mux1_y_net_x0,
rst(0) => convert1_dout_net_x5,
q => register_q_net
);
slice: entity work.xlslice
generic map (
new_lsb => 8,
new_msb => 8,
x_width => 9,
y_width => 1
)
port map (
x => register_q_net,
y(0) => slice_y_net
);
slice1: entity work.xlslice
generic map (
new_lsb => 7,
new_msb => 7,
x_width => 9,
y_width => 1
)
port map (
x => register_q_net,
y(0) => slice1_y_net
);
slice2: entity work.xlslice
generic map (
new_lsb => 6,
new_msb => 6,
x_width => 9,
y_width => 1
)
port map (
x => register_q_net,
y(0) => slice2_y_net
);
slice3: entity work.xlslice
generic map (
new_lsb => 5,
new_msb => 5,
x_width => 9,
y_width => 1
)
port map (
x => register_q_net,
y(0) => slice3_y_net
);
slice4: entity work.xlslice
generic map (
new_lsb => 4,
new_msb => 4,
x_width => 9,
y_width => 1
)
port map (
x => register_q_net,
y(0) => slice4_y_net
);
slice5: entity work.xlslice
generic map (
new_lsb => 3,
new_msb => 3,
x_width => 9,
y_width => 1
)
port map (
x => register_q_net,
y(0) => slice5_y_net
);
slice6: entity work.xlslice
generic map (
new_lsb => 2,
new_msb => 2,
x_width => 9,
y_width => 1
)
port map (
x => register_q_net,
y(0) => slice6_y_net
);
slice7: entity work.xlslice
generic map (
new_lsb => 1,
new_msb => 1,
x_width => 9,
y_width => 1
)
port map (
x => register_q_net,
y(0) => slice7_y_net
);
slice8: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 0,
x_width => 9,
y_width => 1
)
port map (
x => register_q_net,
y(0) => slice8_y_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller/SPI/Pos Edge Detector"
entity pos_edge_detector_entity_ac86c1f1ba is
port (
ce_1: in std_logic;
clk_1: in std_logic;
input_signal: in std_logic;
rising_edge: out std_logic
);
end pos_edge_detector_entity_ac86c1f1ba;
architecture structural of pos_edge_detector_entity_ac86c1f1ba is
signal ce_1_sg_x17: std_logic;
signal clk_1_sg_x17: std_logic;
signal delay_q_net: std_logic;
signal inverter_op_net: std_logic;
signal logical_y_net_x0: std_logic;
signal mux_y_net_x0: std_logic;
begin
ce_1_sg_x17 <= ce_1;
clk_1_sg_x17 <= clk_1;
mux_y_net_x0 <= input_signal;
rising_edge <= logical_y_net_x0;
delay: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x17,
clk => clk_1_sg_x17,
d(0) => inverter_op_net,
en => '1',
q(0) => delay_q_net
);
inverter: entity work.inverter_e2b989a05e
port map (
ce => ce_1_sg_x17,
clk => clk_1_sg_x17,
clr => '0',
ip(0) => mux_y_net_x0,
op(0) => inverter_op_net
);
logical: entity work.logical_938d99ac11
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => mux_y_net_x0,
d1(0) => delay_q_net,
y(0) => logical_y_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller/SPI"
entity spi_entity_fd37afb7f3 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
data_to_transfer: in std_logic_vector(8 downto 0);
dividerselect: in std_logic;
reset: in std_logic;
send: in std_logic;
cs: out std_logic;
data: out std_logic;
done: out std_logic;
scl: out std_logic
);
end spi_entity_fd37afb7f3;
architecture structural of spi_entity_fd37afb7f3 is
signal ce_1_sg_x19: std_logic;
signal clk_1_sg_x19: std_logic;
signal constant_op_net: std_logic_vector(3 downto 0);
signal convert1_dout_net_x7: std_logic;
signal convert1_dout_net_x8: std_logic;
signal convert_dout_net_x0: std_logic;
signal convert_dout_net_x1: std_logic;
signal counter1_op_net: std_logic_vector(3 downto 0);
signal counter_op_net_x0: std_logic_vector(3 downto 0);
signal delay1_q_net: std_logic;
signal delay_q_net: std_logic;
signal inverter1_op_net_x0: std_logic;
signal inverter_op_net_x0: std_logic;
signal logical_y_net: std_logic;
signal logical_y_net_x0: std_logic;
signal logical_y_net_x1: std_logic;
signal mux1_y_net: std_logic;
signal mux1_y_net_x1: std_logic;
signal mux_y_net_x3: std_logic_vector(8 downto 0);
signal mux_y_net_x4: std_logic;
signal mux_y_net_x5: std_logic;
signal register_q_net: std_logic;
signal slice1_y_net: std_logic;
signal slice2_y_net: std_logic;
signal slice_y_net: std_logic;
begin
ce_1_sg_x19 <= ce_1;
clk_1_sg_x19 <= clk_1;
mux_y_net_x3 <= data_to_transfer;
convert_dout_net_x1 <= dividerselect;
convert1_dout_net_x7 <= reset;
mux1_y_net_x1 <= send;
cs <= inverter_op_net_x0;
data <= mux_y_net_x4;
done <= convert1_dout_net_x8;
scl <= mux_y_net_x5;
constant_x0: entity work.constant_06590e4008
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant_op_net
);
convert: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din(0) => mux1_y_net,
dout(0) => convert_dout_net_x0
);
convert1: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din(0) => logical_y_net_x1,
dout(0) => convert1_dout_net_x8
);
counter: entity work.xlcounter_limit
generic map (
cnt_15_0 => 8,
cnt_31_16 => 0,
cnt_47_32 => 0,
cnt_63_48 => 0,
core_name0 => "binary_counter_virtex2p_7_0_23542cbcca0efa2e",
count_limited => 1,
op_arith => xlUnsigned,
op_width => 4
)
port map (
ce => ce_1_sg_x19,
clk => clk_1_sg_x19,
clr => '0',
en(0) => convert_dout_net_x0,
rst(0) => convert1_dout_net_x7,
op => counter_op_net_x0
);
counter1: entity work.xlcounter_free
generic map (
core_name0 => "binary_counter_virtex2p_7_0_77cea312f82499f0",
op_arith => xlUnsigned,
op_width => 4
)
port map (
ce => ce_1_sg_x19,
clk => clk_1_sg_x19,
clr => '0',
din => constant_op_net,
en(0) => register_q_net,
load(0) => convert1_dout_net_x8,
rst(0) => convert1_dout_net_x7,
op => counter1_op_net
);
data_latch_d697580f4e: entity work.data_latch_entity_d697580f4e
port map (
bit_select => counter_op_net_x0,
ce_1 => ce_1_sg_x19,
clk_1 => clk_1_sg_x19,
data_to_transmit => mux_y_net_x3,
latchdata => mux1_y_net_x1,
reset => convert1_dout_net_x7,
spi_data => mux_y_net_x4
);
delay: entity work.xldelay
generic map (
latency => 2,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x19,
clk => clk_1_sg_x19,
d(0) => logical_y_net_x0,
en => '1',
q(0) => delay_q_net
);
delay1: entity work.xldelay
generic map (
latency => 6,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x19,
clk => clk_1_sg_x19,
d(0) => logical_y_net_x0,
en => '1',
q(0) => delay1_q_net
);
inverter: entity work.inverter_e5b38cca3b
port map (
ce => ce_1_sg_x19,
clk => clk_1_sg_x19,
clr => '0',
ip(0) => register_q_net,
op(0) => inverter_op_net_x0
);
inverter1: entity work.inverter_e2b989a05e
port map (
ce => ce_1_sg_x19,
clk => clk_1_sg_x19,
clr => '0',
ip(0) => slice1_y_net,
op(0) => inverter1_op_net_x0
);
logical: entity work.logical_aacf6e1b0e
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => convert1_dout_net_x8,
d1(0) => mux1_y_net_x1,
y(0) => logical_y_net
);
mux: entity work.mux_112ed141f4
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => slice_y_net,
d1(0) => slice2_y_net,
sel(0) => convert_dout_net_x1,
y(0) => mux_y_net_x5
);
mux1: entity work.mux_112ed141f4
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => delay_q_net,
d1(0) => delay1_q_net,
sel(0) => convert_dout_net_x1,
y(0) => mux1_y_net
);
pos_edge_detector2_d448638b52: entity work.pos_edge_detector_entity_ac86c1f1ba
port map (
ce_1 => ce_1_sg_x19,
clk_1 => clk_1_sg_x19,
input_signal => inverter1_op_net_x0,
rising_edge => logical_y_net_x1
);
pos_edge_detector_ac86c1f1ba: entity work.pos_edge_detector_entity_ac86c1f1ba
port map (
ce_1 => ce_1_sg_x19,
clk_1 => clk_1_sg_x19,
input_signal => mux_y_net_x5,
rising_edge => logical_y_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x19,
clk => clk_1_sg_x19,
d(0) => mux1_y_net_x1,
en(0) => logical_y_net,
rst(0) => convert1_dout_net_x7,
q(0) => register_q_net
);
slice: entity work.xlslice
generic map (
new_lsb => 2,
new_msb => 2,
x_width => 4,
y_width => 1
)
port map (
x => counter1_op_net,
y(0) => slice_y_net
);
slice1: entity work.xlslice
generic map (
new_lsb => 3,
new_msb => 3,
x_width => 4,
y_width => 1
)
port map (
x => counter_op_net_x0,
y(0) => slice1_y_net
);
slice2: entity work.xlslice
generic map (
new_lsb => 3,
new_msb => 3,
x_width => 4,
y_width => 1
)
port map (
x => counter1_op_net,
y(0) => slice2_y_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller"
entity lcd_controller_entity_e3a358fc2f is
port (
ce_1: in std_logic;
clk_1: in std_logic;
from_register: in std_logic;
from_register1: in std_logic_vector(8 downto 0);
from_register1_x0: in std_logic_vector(8 downto 0);
from_register2: in std_logic_vector(8 downto 0);
from_register2_x0: in std_logic_vector(8 downto 0);
from_register3: in std_logic_vector(8 downto 0);
from_register3_x0: in std_logic_vector(8 downto 0);
from_register3_x1: in std_logic_vector(7 downto 0);
from_register4: in std_logic_vector(8 downto 0);
from_register4_x0: in std_logic_vector(2 downto 0);
from_register4_x1: in std_logic;
from_register5: in std_logic_vector(8 downto 0);
from_register5_x0: in std_logic_vector(3 downto 0);
from_register5_x1: in std_logic;
from_register6: in std_logic_vector(1 downto 0);
from_register6_x0: in std_logic;
from_register7: in std_logic_vector(3 downto 0);
reset: in std_logic;
shared_memory: in std_logic_vector(31 downto 0);
shared_memory_x0: in std_logic_vector(31 downto 0);
shared_memory_x1: in std_logic_vector(31 downto 0);
commandrom: out std_logic_vector(7 downto 0);
commandrom_x0: out std_logic_vector(31 downto 0);
commandrom_x1: out std_logic;
datarom: out std_logic_vector(8 downto 0);
datarom_x0: out std_logic_vector(31 downto 0);
datarom_x1: out std_logic;
datarom_x2: out std_logic_vector(11 downto 0);
datarom_x3: out std_logic_vector(31 downto 0);
datarom_x4: out std_logic;
delay_x0: out std_logic;
spi: out std_logic;
spi_x0: out std_logic;
spi_x1: out std_logic
);
end lcd_controller_entity_e3a358fc2f;
architecture structural of lcd_controller_entity_e3a358fc2f is
signal ce_1_sg_x20: std_logic;
signal clk_1_sg_x20: std_logic;
signal concat2_y_net_x0: std_logic_vector(8 downto 0);
signal concat4_y_net_x0: std_logic_vector(8 downto 0);
signal constant1_op_net_x4: std_logic;
signal constant1_op_net_x5: std_logic;
signal constant1_op_net_x6: std_logic;
signal constant_op_net_x4: std_logic_vector(31 downto 0);
signal constant_op_net_x5: std_logic_vector(31 downto 0);
signal constant_op_net_x6: std_logic_vector(31 downto 0);
signal convert1_dout_net_x7: std_logic;
signal convert1_dout_net_x8: std_logic;
signal convert2_dout_net_x0: std_logic;
signal convert_dout_net_x1: std_logic;
signal delay_q_net_x0: std_logic;
signal delay_q_net_x1: std_logic;
signal from_register1_data_out_net_x2: std_logic_vector(8 downto 0);
signal from_register1_data_out_net_x3: std_logic_vector(8 downto 0);
signal from_register2_data_out_net_x2: std_logic_vector(8 downto 0);
signal from_register2_data_out_net_x3: std_logic_vector(8 downto 0);
signal from_register3_data_out_net_x3: std_logic_vector(8 downto 0);
signal from_register3_data_out_net_x4: std_logic_vector(8 downto 0);
signal from_register3_data_out_net_x5: std_logic_vector(7 downto 0);
signal from_register4_data_out_net_x2: std_logic_vector(8 downto 0);
signal from_register4_data_out_net_x3: std_logic_vector(2 downto 0);
signal from_register4_data_out_net_x4: std_logic;
signal from_register5_data_out_net_x2: std_logic_vector(8 downto 0);
signal from_register5_data_out_net_x3: std_logic_vector(3 downto 0);
signal from_register5_data_out_net_x4: std_logic;
signal from_register6_data_out_net_x1: std_logic_vector(1 downto 0);
signal from_register6_data_out_net_x2: std_logic;
signal from_register7_data_out_net_x1: std_logic_vector(3 downto 0);
signal from_register_data_out_net_x0: std_logic;
signal inverter_op_net_x1: std_logic;
signal logical1_y_net: std_logic;
signal logical_y_net_x3: std_logic;
signal mux1_y_net_x1: std_logic;
signal mux2_y_net_x0: std_logic;
signal mux_y_net_x3: std_logic_vector(8 downto 0);
signal mux_y_net_x6: std_logic;
signal mux_y_net_x7: std_logic;
signal register_q_net_x1: std_logic;
signal reset_net_x0: std_logic;
signal shared_memory_data_out_net_x4: std_logic_vector(31 downto 0);
signal shared_memory_data_out_net_x5: std_logic_vector(31 downto 0);
signal shared_memory_data_out_net_x6: std_logic_vector(31 downto 0);
signal x12msb_y_net_x2: std_logic_vector(11 downto 0);
signal x8msb_y_net_x2: std_logic_vector(7 downto 0);
signal x9msb_y_net_x2: std_logic_vector(8 downto 0);
begin
ce_1_sg_x20 <= ce_1;
clk_1_sg_x20 <= clk_1;
from_register_data_out_net_x0 <= from_register;
from_register1_data_out_net_x2 <= from_register1;
from_register1_data_out_net_x3 <= from_register1_x0;
from_register2_data_out_net_x2 <= from_register2;
from_register2_data_out_net_x3 <= from_register2_x0;
from_register3_data_out_net_x3 <= from_register3;
from_register3_data_out_net_x4 <= from_register3_x0;
from_register3_data_out_net_x5 <= from_register3_x1;
from_register4_data_out_net_x2 <= from_register4;
from_register4_data_out_net_x3 <= from_register4_x0;
from_register4_data_out_net_x4 <= from_register4_x1;
from_register5_data_out_net_x2 <= from_register5;
from_register5_data_out_net_x3 <= from_register5_x0;
from_register5_data_out_net_x4 <= from_register5_x1;
from_register6_data_out_net_x1 <= from_register6;
from_register6_data_out_net_x2 <= from_register6_x0;
from_register7_data_out_net_x1 <= from_register7;
reset_net_x0 <= reset;
shared_memory_data_out_net_x4 <= shared_memory;
shared_memory_data_out_net_x5 <= shared_memory_x0;
shared_memory_data_out_net_x6 <= shared_memory_x1;
commandrom <= x8msb_y_net_x2;
commandrom_x0 <= constant_op_net_x4;
commandrom_x1 <= constant1_op_net_x4;
datarom <= x9msb_y_net_x2;
datarom_x0 <= constant_op_net_x5;
datarom_x1 <= constant1_op_net_x5;
datarom_x2 <= x12msb_y_net_x2;
datarom_x3 <= constant_op_net_x6;
datarom_x4 <= constant1_op_net_x6;
delay_x0 <= delay_q_net_x1;
spi <= mux_y_net_x6;
spi_x0 <= inverter_op_net_x1;
spi_x1 <= mux_y_net_x7;
commandrom_b68e0d97b7: entity work.commandrom_entity_b68e0d97b7
port map (
ce_1 => ce_1_sg_x20,
clk_1 => clk_1_sg_x20,
from_register1 => from_register1_data_out_net_x2,
from_register2 => from_register2_data_out_net_x2,
from_register3 => from_register3_data_out_net_x3,
from_register4 => from_register4_data_out_net_x2,
from_register5 => from_register5_data_out_net_x2,
from_register6 => from_register6_data_out_net_x1,
reset => convert1_dout_net_x7,
sendcmds => logical_y_net_x3,
shared_memory => shared_memory_data_out_net_x4,
totalnoofcmds => from_register3_data_out_net_x5,
transferdone => convert1_dout_net_x8,
cmdsdone => register_q_net_x1,
command_memory => x8msb_y_net_x2,
command_memory_x0 => constant_op_net_x4,
command_memory_x1 => constant1_op_net_x4,
datatosend => concat2_y_net_x0,
starttransfer => mux2_y_net_x0
);
convert: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din(0) => from_register4_data_out_net_x4,
dout(0) => convert_dout_net_x1
);
convert1: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din(0) => logical1_y_net,
dout(0) => convert1_dout_net_x7
);
convert2: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din(0) => from_register5_data_out_net_x4,
dout(0) => convert2_dout_net_x0
);
datarom_fd2cd392cc: entity work.datarom_entity_fd2cd392cc
port map (
ce_1 => ce_1_sg_x20,
clk_1 => clk_1_sg_x20,
cmdsdone => register_q_net_x1,
from_register1 => from_register1_data_out_net_x3,
from_register2 => from_register2_data_out_net_x3,
from_register3 => from_register3_data_out_net_x4,
from_register4 => from_register4_data_out_net_x3,
from_register5 => from_register5_data_out_net_x3,
from_register7 => from_register7_data_out_net_x1,
reset => convert1_dout_net_x7,
shared_memory => shared_memory_data_out_net_x5,
shared_memory_x0 => shared_memory_data_out_net_x6,
transferdone => convert1_dout_net_x8,
character_buffer_shared_memory => x9msb_y_net_x2,
character_buffer_shared_memory_x0 => constant_op_net_x5,
character_buffer_shared_memory_x1 => constant1_op_net_x5,
character_map_shared_memory => x12msb_y_net_x2,
character_map_shared_memory_x0 => constant_op_net_x6,
character_map_shared_memory_x1 => constant1_op_net_x6,
data => concat4_y_net_x0,
starttransfer => delay_q_net_x0
);
delay: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x20,
clk => clk_1_sg_x20,
d(0) => from_register6_data_out_net_x2,
en => '1',
q(0) => delay_q_net_x1
);
logical1: entity work.logical_3e1f051fb7
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => reset_net_x0,
d1(0) => from_register_data_out_net_x0,
y(0) => logical1_y_net
);
mux: entity work.mux_791081a00e
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => concat2_y_net_x0,
d1 => concat4_y_net_x0,
sel(0) => register_q_net_x1,
y => mux_y_net_x3
);
mux1: entity work.mux_d99e59b6d4
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => mux2_y_net_x0,
d1(0) => delay_q_net_x0,
sel(0) => register_q_net_x1,
y(0) => mux1_y_net_x1
);
pos_edge_detector_63345fcb1c: entity work.pos_edge_detector_entity_90ec5fccc3
port map (
ce_1 => ce_1_sg_x20,
clk_1 => clk_1_sg_x20,
input_signal => convert2_dout_net_x0,
rising_edge => logical_y_net_x3
);
spi_fd37afb7f3: entity work.spi_entity_fd37afb7f3
port map (
ce_1 => ce_1_sg_x20,
clk_1 => clk_1_sg_x20,
data_to_transfer => mux_y_net_x3,
dividerselect => convert_dout_net_x1,
reset => convert1_dout_net_x7,
send => mux1_y_net_x1,
cs => inverter_op_net_x1,
data => mux_y_net_x6,
done => convert1_dout_net_x8,
scl => mux_y_net_x7
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller"
entity user_io_board_controller is
port (
buttons_big: in std_logic_vector(1 downto 0);
buttons_small: in std_logic_vector(5 downto 0);
ce_1: in std_logic;
clk_1: in std_logic;
data_out: in std_logic_vector(17 downto 0);
data_out_x0: in std_logic_vector(17 downto 0);
data_out_x1: in std_logic;
data_out_x10: in std_logic;
data_out_x11: in std_logic_vector(7 downto 0);
data_out_x12: in std_logic;
data_out_x13: in std_logic;
data_out_x14: in std_logic;
data_out_x15: in std_logic_vector(8 downto 0);
data_out_x16: in std_logic_vector(8 downto 0);
data_out_x17: in std_logic_vector(8 downto 0);
data_out_x18: in std_logic_vector(8 downto 0);
data_out_x19: in std_logic_vector(8 downto 0);
data_out_x2: in std_logic_vector(1 downto 0);
data_out_x20: in std_logic_vector(1 downto 0);
data_out_x21: in std_logic_vector(31 downto 0);
data_out_x22: in std_logic_vector(3 downto 0);
data_out_x23: in std_logic_vector(3 downto 0);
data_out_x24: in std_logic_vector(8 downto 0);
data_out_x25: in std_logic_vector(8 downto 0);
data_out_x26: in std_logic_vector(8 downto 0);
data_out_x27: in std_logic_vector(2 downto 0);
data_out_x28: in std_logic_vector(31 downto 0);
data_out_x29: in std_logic_vector(31 downto 0);
data_out_x3: in std_logic_vector(5 downto 0);
data_out_x4: in std_logic_vector(3 downto 0);
data_out_x5: in std_logic_vector(4 downto 0);
data_out_x6: in std_logic_vector(31 downto 0);
data_out_x7: in std_logic_vector(31 downto 0);
data_out_x8: in std_logic_vector(31 downto 0);
data_out_x9: in std_logic_vector(7 downto 0);
dip_switch: in std_logic_vector(3 downto 0);
dout: in std_logic_vector(17 downto 0);
dout_x0: in std_logic;
dout_x1: in std_logic_vector(17 downto 0);
dout_x10: in std_logic_vector(3 downto 0);
dout_x11: in std_logic_vector(8 downto 0);
dout_x12: in std_logic;
dout_x13: in std_logic;
dout_x14: in std_logic_vector(8 downto 0);
dout_x15: in std_logic_vector(8 downto 0);
dout_x16: in std_logic_vector(8 downto 0);
dout_x17: in std_logic;
dout_x18: in std_logic_vector(7 downto 0);
dout_x19: in std_logic_vector(7 downto 0);
dout_x2: in std_logic_vector(8 downto 0);
dout_x3: in std_logic_vector(3 downto 0);
dout_x4: in std_logic_vector(2 downto 0);
dout_x5: in std_logic_vector(8 downto 0);
dout_x6: in std_logic_vector(1 downto 0);
dout_x7: in std_logic;
dout_x8: in std_logic_vector(8 downto 0);
dout_x9: in std_logic_vector(8 downto 0);
plb_abus: in std_logic_vector(31 downto 0);
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(31 downto 0);
reset: in std_logic;
sg_plb_addrpref: in std_logic_vector(14 downto 0);
splb_rst: in std_logic;
trackball_ox: in std_logic;
trackball_oxn: in std_logic;
trackball_oy: in std_logic;
trackball_oyn: in std_logic;
trackball_sel2: in std_logic;
addr: out std_logic_vector(11 downto 0);
addr_x0: out std_logic_vector(8 downto 0);
addr_x1: out std_logic_vector(7 downto 0);
addr_x2: out std_logic_vector(7 downto 0);
addr_x3: out std_logic_vector(8 downto 0);
addr_x4: out std_logic_vector(11 downto 0);
buzzer: out std_logic;
cs: out std_logic;
data_in: out std_logic_vector(17 downto 0);
data_in_x0: out std_logic;
data_in_x1: out std_logic_vector(17 downto 0);
data_in_x10: out std_logic_vector(3 downto 0);
data_in_x11: out std_logic_vector(8 downto 0);
data_in_x12: out std_logic;
data_in_x13: out std_logic;
data_in_x14: out std_logic_vector(8 downto 0);
data_in_x15: out std_logic_vector(8 downto 0);
data_in_x16: out std_logic_vector(8 downto 0);
data_in_x17: out std_logic;
data_in_x18: out std_logic_vector(7 downto 0);
data_in_x19: out std_logic_vector(7 downto 0);
data_in_x2: out std_logic_vector(8 downto 0);
data_in_x20: out std_logic_vector(31 downto 0);
data_in_x21: out std_logic_vector(31 downto 0);
data_in_x22: out std_logic_vector(31 downto 0);
data_in_x23: out std_logic_vector(4 downto 0);
data_in_x24: out std_logic_vector(1 downto 0);
data_in_x25: out std_logic_vector(5 downto 0);
data_in_x26: out std_logic_vector(3 downto 0);
data_in_x27: out std_logic_vector(31 downto 0);
data_in_x28: out std_logic_vector(31 downto 0);
data_in_x29: out std_logic_vector(31 downto 0);
data_in_x3: out std_logic_vector(3 downto 0);
data_in_x4: out std_logic_vector(2 downto 0);
data_in_x5: out std_logic_vector(8 downto 0);
data_in_x6: out std_logic_vector(1 downto 0);
data_in_x7: out std_logic;
data_in_x8: out std_logic_vector(8 downto 0);
data_in_x9: out std_logic_vector(8 downto 0);
en: out std_logic;
en_x0: out std_logic;
en_x1: out std_logic;
en_x10: out std_logic;
en_x11: out std_logic;
en_x12: out std_logic;
en_x13: out std_logic;
en_x14: out std_logic;
en_x15: out std_logic;
en_x16: out std_logic;
en_x17: out std_logic;
en_x18: out std_logic;
en_x19: out std_logic;
en_x2: out std_logic;
en_x20: out std_logic;
en_x21: out std_logic;
en_x22: out std_logic;
en_x23: out std_logic;
en_x3: out std_logic;
en_x4: out std_logic;
en_x5: out std_logic;
en_x6: out std_logic;
en_x7: out std_logic;
en_x8: out std_logic;
en_x9: out std_logic;
leds: out std_logic_vector(7 downto 0);
resetlcd: out std_logic;
scl: out std_logic;
sdi: out std_logic;
sl_addrack: out std_logic;
sl_rdcomp: out std_logic;
sl_rddack: out std_logic;
sl_rddbus: out std_logic_vector(31 downto 0);
sl_wait: out std_logic;
sl_wrcomp: out std_logic;
sl_wrdack: out std_logic;
trackball_sel1: out std_logic;
trackball_xscn: out std_logic;
trackball_yscn: out std_logic;
we: out std_logic;
we_x0: out std_logic;
we_x1: out std_logic;
we_x2: out std_logic;
we_x3: out std_logic;
we_x4: out std_logic
);
end user_io_board_controller;
architecture structural of user_io_board_controller is
signal addr_net: std_logic_vector(11 downto 0);
signal addr_x0_net: std_logic_vector(8 downto 0);
signal addr_x1_net: std_logic_vector(7 downto 0);
signal addr_x2_net: std_logic_vector(7 downto 0);
signal addr_x3_net: std_logic_vector(8 downto 0);
signal addr_x4_net: std_logic_vector(11 downto 0);
signal buttons_big_net: std_logic_vector(1 downto 0);
signal buttons_small_net: std_logic_vector(5 downto 0);
signal buzzer_net: std_logic;
signal ce_1_sg_x21: std_logic;
signal clk_1_sg_x21: std_logic;
signal cs_net: std_logic;
signal data_in_net: std_logic_vector(17 downto 0);
signal data_in_x0_net: std_logic;
signal data_in_x10_net: std_logic_vector(3 downto 0);
signal data_in_x11_net: std_logic_vector(8 downto 0);
signal data_in_x12_net: std_logic;
signal data_in_x13_net: std_logic;
signal data_in_x14_net: std_logic_vector(8 downto 0);
signal data_in_x15_net: std_logic_vector(8 downto 0);
signal data_in_x16_net: std_logic_vector(8 downto 0);
signal data_in_x17_net: std_logic;
signal data_in_x18_net: std_logic_vector(7 downto 0);
signal data_in_x19_net: std_logic_vector(7 downto 0);
signal data_in_x1_net: std_logic_vector(17 downto 0);
signal data_in_x20_net: std_logic_vector(31 downto 0);
signal data_in_x21_net: std_logic_vector(31 downto 0);
signal data_in_x22_net: std_logic_vector(31 downto 0);
signal data_in_x23_net: std_logic_vector(4 downto 0);
signal data_in_x24_net: std_logic_vector(1 downto 0);
signal data_in_x25_net: std_logic_vector(5 downto 0);
signal data_in_x26_net: std_logic_vector(3 downto 0);
signal data_in_x27_net: std_logic_vector(31 downto 0);
signal data_in_x28_net: std_logic_vector(31 downto 0);
signal data_in_x29_net: std_logic_vector(31 downto 0);
signal data_in_x2_net: std_logic_vector(8 downto 0);
signal data_in_x3_net: std_logic_vector(3 downto 0);
signal data_in_x4_net: std_logic_vector(2 downto 0);
signal data_in_x5_net: std_logic_vector(8 downto 0);
signal data_in_x6_net: std_logic_vector(1 downto 0);
signal data_in_x7_net: std_logic;
signal data_in_x8_net: std_logic_vector(8 downto 0);
signal data_in_x9_net: std_logic_vector(8 downto 0);
signal data_out_net: std_logic_vector(17 downto 0);
signal data_out_x0_net: std_logic_vector(17 downto 0);
signal data_out_x10_net: std_logic;
signal data_out_x11_net: std_logic_vector(7 downto 0);
signal data_out_x12_net: std_logic;
signal data_out_x13_net: std_logic;
signal data_out_x14_net: std_logic;
signal data_out_x15_net: std_logic_vector(8 downto 0);
signal data_out_x16_net: std_logic_vector(8 downto 0);
signal data_out_x17_net: std_logic_vector(8 downto 0);
signal data_out_x18_net: std_logic_vector(8 downto 0);
signal data_out_x19_net: std_logic_vector(8 downto 0);
signal data_out_x1_net: std_logic;
signal data_out_x20_net: std_logic_vector(1 downto 0);
signal data_out_x21_net: std_logic_vector(31 downto 0);
signal data_out_x22_net: std_logic_vector(3 downto 0);
signal data_out_x23_net: std_logic_vector(3 downto 0);
signal data_out_x24_net: std_logic_vector(8 downto 0);
signal data_out_x25_net: std_logic_vector(8 downto 0);
signal data_out_x26_net: std_logic_vector(8 downto 0);
signal data_out_x27_net: std_logic_vector(2 downto 0);
signal data_out_x28_net: std_logic_vector(31 downto 0);
signal data_out_x29_net: std_logic_vector(31 downto 0);
signal data_out_x2_net: std_logic_vector(1 downto 0);
signal data_out_x3_net: std_logic_vector(5 downto 0);
signal data_out_x4_net: std_logic_vector(3 downto 0);
signal data_out_x5_net: std_logic_vector(4 downto 0);
signal data_out_x6_net: std_logic_vector(31 downto 0);
signal data_out_x7_net: std_logic_vector(31 downto 0);
signal data_out_x8_net: std_logic_vector(31 downto 0);
signal data_out_x9_net: std_logic_vector(7 downto 0);
signal dip_switch_net: std_logic_vector(3 downto 0);
signal dout_net: std_logic_vector(17 downto 0);
signal dout_x0_net: std_logic;
signal dout_x10_net: std_logic_vector(3 downto 0);
signal dout_x11_net: std_logic_vector(8 downto 0);
signal dout_x12_net: std_logic;
signal dout_x13_net: std_logic;
signal dout_x14_net: std_logic_vector(8 downto 0);
signal dout_x15_net: std_logic_vector(8 downto 0);
signal dout_x16_net: std_logic_vector(8 downto 0);
signal dout_x17_net: std_logic;
signal dout_x18_net: std_logic_vector(7 downto 0);
signal dout_x19_net: std_logic_vector(7 downto 0);
signal dout_x1_net: std_logic_vector(17 downto 0);
signal dout_x2_net: std_logic_vector(8 downto 0);
signal dout_x3_net: std_logic_vector(3 downto 0);
signal dout_x4_net: std_logic_vector(2 downto 0);
signal dout_x5_net: std_logic_vector(8 downto 0);
signal dout_x6_net: std_logic_vector(1 downto 0);
signal dout_x7_net: std_logic;
signal dout_x8_net: std_logic_vector(8 downto 0);
signal dout_x9_net: std_logic_vector(8 downto 0);
signal en_net: std_logic;
signal en_x0_net: std_logic;
signal en_x10_net: std_logic;
signal en_x11_net: std_logic;
signal en_x12_net: std_logic;
signal en_x13_net: std_logic;
signal en_x14_net: std_logic;
signal en_x15_net: std_logic;
signal en_x16_net: std_logic;
signal en_x17_net: std_logic;
signal en_x18_net: std_logic;
signal en_x19_net: std_logic;
signal en_x1_net: std_logic;
signal en_x20_net: std_logic;
signal en_x21_net: std_logic;
signal en_x22_net: std_logic;
signal en_x23_net: std_logic;
signal en_x2_net: std_logic;
signal en_x3_net: std_logic;
signal en_x4_net: std_logic;
signal en_x5_net: std_logic;
signal en_x6_net: std_logic;
signal en_x7_net: std_logic;
signal en_x8_net: std_logic;
signal en_x9_net: std_logic;
signal leds_net: std_logic_vector(7 downto 0);
signal plb_abus_net: std_logic_vector(31 downto 0);
signal plb_pavalid_net: std_logic;
signal plb_rnw_net: std_logic;
signal plb_wrdbus_net: std_logic_vector(31 downto 0);
signal reset_net: std_logic;
signal resetlcd_net: std_logic;
signal scl_net: std_logic;
signal sdi_net: std_logic;
signal sg_plb_addrpref_net: std_logic_vector(14 downto 0);
signal sl_addrack_net: std_logic;
signal sl_rdcomp_net: std_logic;
signal sl_rddack_net: std_logic;
signal sl_rddbus_net: std_logic_vector(31 downto 0);
signal sl_wait_net: std_logic;
signal sl_wrdack_x1: std_logic;
signal splb_rst_net: std_logic;
signal trackball_ox_net: std_logic;
signal trackball_oxn_net: std_logic;
signal trackball_oy_net: std_logic;
signal trackball_oyn_net: std_logic;
signal trackball_sel1_net: std_logic;
signal trackball_sel2_net: std_logic;
signal trackball_xscn_net: std_logic;
signal trackball_yscn_net: std_logic;
signal we_net: std_logic;
signal we_x0_net: std_logic;
signal we_x1_net: std_logic;
signal we_x2_net: std_logic;
signal we_x3_net: std_logic;
signal we_x4_net: std_logic;
begin
buttons_big_net <= buttons_big;
buttons_small_net <= buttons_small;
ce_1_sg_x21 <= ce_1;
clk_1_sg_x21 <= clk_1;
data_out_net <= data_out;
data_out_x0_net <= data_out_x0;
data_out_x1_net <= data_out_x1;
data_out_x10_net <= data_out_x10;
data_out_x11_net <= data_out_x11;
data_out_x12_net <= data_out_x12;
data_out_x13_net <= data_out_x13;
data_out_x14_net <= data_out_x14;
data_out_x15_net <= data_out_x15;
data_out_x16_net <= data_out_x16;
data_out_x17_net <= data_out_x17;
data_out_x18_net <= data_out_x18;
data_out_x19_net <= data_out_x19;
data_out_x2_net <= data_out_x2;
data_out_x20_net <= data_out_x20;
data_out_x21_net <= data_out_x21;
data_out_x22_net <= data_out_x22;
data_out_x23_net <= data_out_x23;
data_out_x24_net <= data_out_x24;
data_out_x25_net <= data_out_x25;
data_out_x26_net <= data_out_x26;
data_out_x27_net <= data_out_x27;
data_out_x28_net <= data_out_x28;
data_out_x29_net <= data_out_x29;
data_out_x3_net <= data_out_x3;
data_out_x4_net <= data_out_x4;
data_out_x5_net <= data_out_x5;
data_out_x6_net <= data_out_x6;
data_out_x7_net <= data_out_x7;
data_out_x8_net <= data_out_x8;
data_out_x9_net <= data_out_x9;
dip_switch_net <= dip_switch;
dout_net <= dout;
dout_x0_net <= dout_x0;
dout_x1_net <= dout_x1;
dout_x10_net <= dout_x10;
dout_x11_net <= dout_x11;
dout_x12_net <= dout_x12;
dout_x13_net <= dout_x13;
dout_x14_net <= dout_x14;
dout_x15_net <= dout_x15;
dout_x16_net <= dout_x16;
dout_x17_net <= dout_x17;
dout_x18_net <= dout_x18;
dout_x19_net <= dout_x19;
dout_x2_net <= dout_x2;
dout_x3_net <= dout_x3;
dout_x4_net <= dout_x4;
dout_x5_net <= dout_x5;
dout_x6_net <= dout_x6;
dout_x7_net <= dout_x7;
dout_x8_net <= dout_x8;
dout_x9_net <= dout_x9;
plb_abus_net <= plb_abus;
plb_pavalid_net <= plb_pavalid;
plb_rnw_net <= plb_rnw;
plb_wrdbus_net <= plb_wrdbus;
reset_net <= reset;
sg_plb_addrpref_net <= sg_plb_addrpref;
splb_rst_net <= splb_rst;
trackball_ox_net <= trackball_ox;
trackball_oxn_net <= trackball_oxn;
trackball_oy_net <= trackball_oy;
trackball_oyn_net <= trackball_oyn;
trackball_sel2_net <= trackball_sel2;
addr <= addr_net;
addr_x0 <= addr_x0_net;
addr_x1 <= addr_x1_net;
addr_x2 <= addr_x2_net;
addr_x3 <= addr_x3_net;
addr_x4 <= addr_x4_net;
buzzer <= buzzer_net;
cs <= cs_net;
data_in <= data_in_net;
data_in_x0 <= data_in_x0_net;
data_in_x1 <= data_in_x1_net;
data_in_x10 <= data_in_x10_net;
data_in_x11 <= data_in_x11_net;
data_in_x12 <= data_in_x12_net;
data_in_x13 <= data_in_x13_net;
data_in_x14 <= data_in_x14_net;
data_in_x15 <= data_in_x15_net;
data_in_x16 <= data_in_x16_net;
data_in_x17 <= data_in_x17_net;
data_in_x18 <= data_in_x18_net;
data_in_x19 <= data_in_x19_net;
data_in_x2 <= data_in_x2_net;
data_in_x20 <= data_in_x20_net;
data_in_x21 <= data_in_x21_net;
data_in_x22 <= data_in_x22_net;
data_in_x23 <= data_in_x23_net;
data_in_x24 <= data_in_x24_net;
data_in_x25 <= data_in_x25_net;
data_in_x26 <= data_in_x26_net;
data_in_x27 <= data_in_x27_net;
data_in_x28 <= data_in_x28_net;
data_in_x29 <= data_in_x29_net;
data_in_x3 <= data_in_x3_net;
data_in_x4 <= data_in_x4_net;
data_in_x5 <= data_in_x5_net;
data_in_x6 <= data_in_x6_net;
data_in_x7 <= data_in_x7_net;
data_in_x8 <= data_in_x8_net;
data_in_x9 <= data_in_x9_net;
en <= en_net;
en_x0 <= en_x0_net;
en_x1 <= en_x1_net;
en_x10 <= en_x10_net;
en_x11 <= en_x11_net;
en_x12 <= en_x12_net;
en_x13 <= en_x13_net;
en_x14 <= en_x14_net;
en_x15 <= en_x15_net;
en_x16 <= en_x16_net;
en_x17 <= en_x17_net;
en_x18 <= en_x18_net;
en_x19 <= en_x19_net;
en_x2 <= en_x2_net;
en_x20 <= en_x20_net;
en_x21 <= en_x21_net;
en_x22 <= en_x22_net;
en_x23 <= en_x23_net;
en_x3 <= en_x3_net;
en_x4 <= en_x4_net;
en_x5 <= en_x5_net;
en_x6 <= en_x6_net;
en_x7 <= en_x7_net;
en_x8 <= en_x8_net;
en_x9 <= en_x9_net;
leds <= leds_net;
resetlcd <= resetlcd_net;
scl <= scl_net;
sdi <= sdi_net;
sl_addrack <= sl_addrack_net;
sl_rdcomp <= sl_rdcomp_net;
sl_rddack <= sl_rddack_net;
sl_rddbus <= sl_rddbus_net;
sl_wait <= sl_wait_net;
sl_wrcomp <= sl_wrdack_x1;
sl_wrdack <= sl_wrdack_x1;
trackball_sel1 <= trackball_sel1_net;
trackball_xscn <= trackball_xscn_net;
trackball_yscn <= trackball_yscn_net;
we <= we_net;
we_x0 <= we_x0_net;
we_x1 <= we_x1_net;
we_x2 <= we_x2_net;
we_x3 <= we_x3_net;
we_x4 <= we_x4_net;
buzzer_controller_063692c849: entity work.buzzer_controller_entity_063692c849
port map (
ce_1 => ce_1_sg_x21,
clk_1 => clk_1_sg_x21,
from_register => data_out_net,
from_register1 => data_out_x0_net,
from_register2 => data_out_x1_net,
register9_x0 => buzzer_net
);
edk_processor_94deb4def9: entity work.edk_processor_entity_94deb4def9
port map (
ce_1 => ce_1_sg_x21,
clk_1 => clk_1_sg_x21,
from_register => data_out_x2_net,
from_register1 => data_out_x3_net,
from_register2 => data_out_x4_net,
from_register3 => data_out_x5_net,
plb_abus => plb_abus_net,
plb_pavalid => plb_pavalid_net,
plb_rnw => plb_rnw_net,
plb_wrdbus => plb_wrdbus_net,
sg_plb_addrpref => sg_plb_addrpref_net,
shared_memory => data_out_x6_net,
shared_memory1 => data_out_x7_net,
shared_memory2 => data_out_x8_net,
splb_rst => splb_rst_net,
to_register => dout_net,
to_register1 => dout_x0_net,
to_register10 => dout_x9_net,
to_register11 => dout_x10_net,
to_register12 => dout_x11_net,
to_register13 => dout_x12_net,
to_register14 => dout_x13_net,
to_register15 => dout_x14_net,
to_register16 => dout_x15_net,
to_register17 => dout_x16_net,
to_register18 => dout_x17_net,
to_register19 => dout_x18_net,
to_register2 => dout_x1_net,
to_register20 => dout_x19_net,
to_register3 => dout_x2_net,
to_register4 => dout_x3_net,
to_register5 => dout_x4_net,
to_register6 => dout_x5_net,
to_register7 => dout_x6_net,
to_register8 => dout_x7_net,
to_register9 => dout_x8_net,
constant5_x0 => sl_wait_net,
plb_decode_x0 => sl_addrack_net,
plb_decode_x1 => sl_rdcomp_net,
plb_decode_x2 => sl_wrdack_x1,
plb_decode_x3 => sl_rddack_net,
plb_decode_x4 => sl_rddbus_net,
plb_memmap_x0 => data_in_net,
plb_memmap_x1 => en_net,
plb_memmap_x10 => data_in_x4_net,
plb_memmap_x11 => en_x4_net,
plb_memmap_x12 => data_in_x5_net,
plb_memmap_x13 => en_x5_net,
plb_memmap_x14 => data_in_x6_net,
plb_memmap_x15 => en_x6_net,
plb_memmap_x16 => data_in_x7_net,
plb_memmap_x17 => en_x7_net,
plb_memmap_x18 => data_in_x8_net,
plb_memmap_x19 => en_x8_net,
plb_memmap_x2 => data_in_x0_net,
plb_memmap_x20 => data_in_x9_net,
plb_memmap_x21 => en_x9_net,
plb_memmap_x22 => data_in_x10_net,
plb_memmap_x23 => en_x10_net,
plb_memmap_x24 => data_in_x11_net,
plb_memmap_x25 => en_x11_net,
plb_memmap_x26 => data_in_x12_net,
plb_memmap_x27 => en_x12_net,
plb_memmap_x28 => data_in_x13_net,
plb_memmap_x29 => en_x13_net,
plb_memmap_x3 => en_x0_net,
plb_memmap_x30 => data_in_x14_net,
plb_memmap_x31 => en_x14_net,
plb_memmap_x32 => data_in_x15_net,
plb_memmap_x33 => en_x15_net,
plb_memmap_x34 => data_in_x16_net,
plb_memmap_x35 => en_x16_net,
plb_memmap_x36 => data_in_x17_net,
plb_memmap_x37 => en_x17_net,
plb_memmap_x38 => data_in_x18_net,
plb_memmap_x39 => en_x18_net,
plb_memmap_x4 => data_in_x1_net,
plb_memmap_x40 => data_in_x19_net,
plb_memmap_x41 => en_x19_net,
plb_memmap_x42 => addr_net,
plb_memmap_x43 => data_in_x20_net,
plb_memmap_x44 => we_net,
plb_memmap_x45 => addr_x0_net,
plb_memmap_x46 => data_in_x21_net,
plb_memmap_x47 => we_x0_net,
plb_memmap_x48 => addr_x1_net,
plb_memmap_x49 => data_in_x22_net,
plb_memmap_x5 => en_x1_net,
plb_memmap_x50 => we_x1_net,
plb_memmap_x6 => data_in_x2_net,
plb_memmap_x7 => en_x2_net,
plb_memmap_x8 => data_in_x3_net,
plb_memmap_x9 => en_x3_net
);
lcd_controller_e3a358fc2f: entity work.lcd_controller_entity_e3a358fc2f
port map (
ce_1 => ce_1_sg_x21,
clk_1 => clk_1_sg_x21,
from_register => data_out_x10_net,
from_register1 => data_out_x15_net,
from_register1_x0 => data_out_x24_net,
from_register2 => data_out_x16_net,
from_register2_x0 => data_out_x25_net,
from_register3 => data_out_x17_net,
from_register3_x0 => data_out_x26_net,
from_register3_x1 => data_out_x11_net,
from_register4 => data_out_x18_net,
from_register4_x0 => data_out_x27_net,
from_register4_x1 => data_out_x12_net,
from_register5 => data_out_x19_net,
from_register5_x0 => data_out_x23_net,
from_register5_x1 => data_out_x13_net,
from_register6 => data_out_x20_net,
from_register6_x0 => data_out_x14_net,
from_register7 => data_out_x22_net,
reset => reset_net,
shared_memory => data_out_x21_net,
shared_memory_x0 => data_out_x28_net,
shared_memory_x1 => data_out_x29_net,
commandrom => addr_x2_net,
commandrom_x0 => data_in_x27_net,
commandrom_x1 => we_x2_net,
datarom => addr_x3_net,
datarom_x0 => data_in_x28_net,
datarom_x1 => we_x3_net,
datarom_x2 => addr_x4_net,
datarom_x3 => data_in_x29_net,
datarom_x4 => we_x4_net,
delay_x0 => resetlcd_net,
spi => sdi_net,
spi_x0 => cs_net,
spi_x1 => scl_net
);
o_1f30dfdbf5: entity work.o_entity_1f30dfdbf5
port map (
buttons_big => buttons_big_net,
buttons_small => buttons_small_net,
ce_1 => ce_1_sg_x21,
clk_1 => clk_1_sg_x21,
dip_switch => dip_switch_net,
from_register => data_out_x9_net,
trackball_ox => trackball_ox_net,
trackball_oxn => trackball_oxn_net,
trackball_oy => trackball_oy_net,
trackball_oyn => trackball_oyn_net,
trackball_sel2 => trackball_sel2_net,
concat_x0 => data_in_x23_net,
constant2_x0 => en_x21_net,
constant4_x0 => en_x22_net,
constant6_x0 => en_x23_net,
constant_x1 => en_x20_net,
register10_x0 => trackball_xscn_net,
register11_x0 => trackball_yscn_net,
register12_x0 => trackball_sel1_net,
register3_x0 => data_in_x24_net,
register5_x0 => data_in_x25_net,
register7_x0 => data_in_x26_net,
register9_x0 => leds_net
);
end structural;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
use work.clock_pkg.all;
entity xlclkprobe is
port (clk : in std_logic;
clr : in std_logic;
ce : in std_logic;
fakeOutForXst : out std_logic);
end xlclkprobe;
architecture behavior of xlclkprobe is
begin
fakeOutForXst <= '0';
-- synopsys translate_off
work.clock_pkg.int_clk <= clk;
-- synopsys translate_on
end behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
entity xlclockdriver is
generic (
period: integer := 2;
log_2_period: integer := 0;
pipeline_regs: integer := 5;
use_bufg: integer := 0
);
port (
sysclk: in std_logic;
sysclr: in std_logic;
sysce: in std_logic;
clk: out std_logic;
clr: out std_logic;
ce: out std_logic
);
end xlclockdriver;
architecture behavior of xlclockdriver is
component bufg
port (
i: in std_logic;
o: out std_logic
);
end component;
component synth_reg_w_init
generic (
width: integer;
init_index: integer;
init_value: bit_vector;
latency: integer
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
function size_of_uint(inp: integer; power_of_2: boolean)
return integer
is
constant inp_vec: std_logic_vector(31 downto 0) :=
integer_to_std_logic_vector(inp,32, xlUnsigned);
variable result: integer;
begin
result := 32;
for i in 0 to 31 loop
if inp_vec(i) = '1' then
result := i;
end if;
end loop;
if power_of_2 then
return result;
else
return result+1;
end if;
end;
function is_power_of_2(inp: std_logic_vector)
return boolean
is
constant width: integer := inp'length;
variable vec: std_logic_vector(width - 1 downto 0);
variable single_bit_set: boolean;
variable more_than_one_bit_set: boolean;
variable result: boolean;
begin
vec := inp;
single_bit_set := false;
more_than_one_bit_set := false;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if width > 0 then
for i in 0 to width - 1 loop
if vec(i) = '1' then
if single_bit_set then
more_than_one_bit_set := true;
end if;
single_bit_set := true;
end if;
end loop;
end if;
if (single_bit_set and not(more_than_one_bit_set)) then
result := true;
else
result := false;
end if;
return result;
end;
function ce_reg_init_val(index, period : integer)
return integer
is
variable result: integer;
begin
result := 0;
if ((index mod period) = 0) then
result := 1;
end if;
return result;
end;
function remaining_pipe_regs(num_pipeline_regs, period : integer)
return integer
is
variable factor, result: integer;
begin
factor := (num_pipeline_regs / period);
result := num_pipeline_regs - (period * factor) + 1;
return result;
end;
function sg_min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
constant max_pipeline_regs : integer := 8;
constant pipe_regs : integer := 5;
constant num_pipeline_regs : integer := sg_min(pipeline_regs, max_pipeline_regs);
constant rem_pipeline_regs : integer := remaining_pipe_regs(num_pipeline_regs,period);
constant period_floor: integer := max(2, period);
constant power_of_2_counter: boolean :=
is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned));
constant cnt_width: integer :=
size_of_uint(period_floor, power_of_2_counter);
constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned);
constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned);
constant clk_for_ce_pulse_minus_regs: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector(max(0,period - rem_pipeline_regs),cnt_width, xlUnsigned);
signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0');
signal ce_vec : std_logic_vector(num_pipeline_regs downto 0);
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of ce_vec:signal is "REDUCE";
signal internal_ce: std_logic_vector(0 downto 0);
signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0);
begin
clk <= sysclk;
clr <= sysclr;
cntr_gen: process(sysclk)
begin
if sysclk'event and sysclk = '1' then
if (sysce = '1') then
if ((cnt_clr_dly(0) = '1') or (sysclr = '1')) then
clk_num <= (others => '0');
else
clk_num <= clk_num + 1;
end if;
end if;
end if;
end process;
clr_gen: process(clk_num, sysclr)
begin
if power_of_2_counter then
cnt_clr(0) <= sysclr;
else
if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1
or sysclr = '1') then
cnt_clr(0) <= '1';
else
cnt_clr(0) <= '0';
end if;
end if;
end process;
clr_reg: synth_reg_w_init
generic map (
width => 1,
init_index => 0,
init_value => b"0000",
latency => 1
)
port map (
i => cnt_clr,
ce => sysce,
clr => sysclr,
clk => sysclk,
o => cnt_clr_dly
);
pipelined_ce : if period > 1 generate
ce_gen: process(clk_num)
begin
if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then
ce_vec(num_pipeline_regs) <= '1';
else
ce_vec(num_pipeline_regs) <= '0';
end if;
end process;
ce_pipeline: for index in num_pipeline_regs downto 1 generate
ce_reg : synth_reg_w_init
generic map (
width => 1,
init_index => ce_reg_init_val(index, period),
init_value => b"0000",
latency => 1
)
port map (
i => ce_vec(index downto index),
ce => sysce,
clr => sysclr,
clk => sysclk,
o => ce_vec(index-1 downto index-1)
);
end generate;
internal_ce <= ce_vec(0 downto 0);
end generate;
use_bufg_true: if period > 1 and use_bufg = 1 generate
ce_bufg_inst: bufg
port map (
i => internal_ce(0),
o => ce
);
end generate;
use_bufg_false: if period > 1 and (use_bufg = 0) generate
ce <= internal_ce(0);
end generate;
generate_system_clk: if period = 1 generate
ce <= sysce;
end generate;
end architecture behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity xland2 is
port (
a : in std_logic;
b : in std_logic;
dout : out std_logic
);
end xland2;
architecture behavior of xland2 is
begin
dout <= a and b;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity default_clock_driver is
port (
sysce: in std_logic;
sysce_clr: in std_logic;
sysclk: in std_logic;
ce_1: out std_logic;
clk_1: out std_logic
);
end default_clock_driver;
architecture structural of default_clock_driver is
attribute syn_noprune: boolean;
attribute syn_noprune of structural : architecture is true;
attribute optimize_primitives: boolean;
attribute optimize_primitives of structural : architecture is false;
attribute dont_touch: boolean;
attribute dont_touch of structural : architecture is true;
signal sysce_clr_x0: std_logic;
signal sysce_x0: std_logic;
signal sysclk_x0: std_logic;
signal xlclockdriver_1_ce: std_logic;
signal xlclockdriver_1_clk: std_logic;
begin
sysce_x0 <= sysce;
sysce_clr_x0 <= sysce_clr;
sysclk_x0 <= sysclk;
ce_1 <= xlclockdriver_1_ce;
clk_1 <= xlclockdriver_1_clk;
xlclockdriver_1: entity work.xlclockdriver
generic map (
log_2_period => 1,
period => 1,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_1_ce,
clk => xlclockdriver_1_clk
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity user_io_board_controller_cw is
port (
buttons_big: in std_logic_vector(1 downto 0);
buttons_small: in std_logic_vector(5 downto 0);
ce: in std_logic := '1';
clk: in std_logic; -- clock period = 10.0 ns (100.0 Mhz)
dip_switch: in std_logic_vector(3 downto 0);
plb_abus: in std_logic_vector(31 downto 0);
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(31 downto 0);
reset: in std_logic;
sg_plb_addrpref: in std_logic_vector(14 downto 0);
splb_rst: in std_logic;
trackball_ox: in std_logic;
trackball_oxn: in std_logic;
trackball_oy: in std_logic;
trackball_oyn: in std_logic;
trackball_sel2: in std_logic;
buzzer: out std_logic;
cs: out std_logic;
leds: out std_logic_vector(7 downto 0);
resetlcd: out std_logic;
scl: out std_logic;
sdi: out std_logic;
sl_addrack: out std_logic;
sl_rdcomp: out std_logic;
sl_rddack: out std_logic;
sl_rddbus: out std_logic_vector(31 downto 0);
sl_wait: out std_logic;
sl_wrcomp: out std_logic;
sl_wrdack: out std_logic;
trackball_sel1: out std_logic;
trackball_xscn: out std_logic;
trackball_yscn: out std_logic
);
end user_io_board_controller_cw;
architecture structural of user_io_board_controller_cw is
component dual_port_block_memory_virtex2p_6_3_25371f622c89ba44
port (
addra: in std_logic_vector(8 downto 0);
addrb: in std_logic_vector(8 downto 0);
clka: in std_logic;
clkb: in std_logic;
dina: in std_logic_vector(31 downto 0);
dinb: in std_logic_vector(31 downto 0);
ena: in std_logic;
enb: in std_logic;
wea: in std_logic;
web: in std_logic;
douta: out std_logic_vector(31 downto 0);
doutb: out std_logic_vector(31 downto 0)
);
end component;
attribute syn_black_box: boolean;
attribute syn_black_box of dual_port_block_memory_virtex2p_6_3_25371f622c89ba44: component is true;
attribute box_type: string;
attribute box_type of dual_port_block_memory_virtex2p_6_3_25371f622c89ba44: component is "black_box";
attribute syn_noprune: boolean;
attribute optimize_primitives: boolean;
attribute dont_touch: boolean;
attribute syn_noprune of dual_port_block_memory_virtex2p_6_3_25371f622c89ba44: component is true;
attribute optimize_primitives of dual_port_block_memory_virtex2p_6_3_25371f622c89ba44: component is false;
attribute dont_touch of dual_port_block_memory_virtex2p_6_3_25371f622c89ba44: component is true;
component dual_port_block_memory_virtex2p_6_3_e98c3706f2ec2c76
port (
addra: in std_logic_vector(11 downto 0);
addrb: in std_logic_vector(11 downto 0);
clka: in std_logic;
clkb: in std_logic;
dina: in std_logic_vector(31 downto 0);
dinb: in std_logic_vector(31 downto 0);
ena: in std_logic;
enb: in std_logic;
wea: in std_logic;
web: in std_logic;
douta: out std_logic_vector(31 downto 0);
doutb: out std_logic_vector(31 downto 0)
);
end component;
attribute syn_black_box of dual_port_block_memory_virtex2p_6_3_e98c3706f2ec2c76: component is true;
attribute box_type of dual_port_block_memory_virtex2p_6_3_e98c3706f2ec2c76: component is "black_box";
attribute syn_noprune of dual_port_block_memory_virtex2p_6_3_e98c3706f2ec2c76: component is true;
attribute optimize_primitives of dual_port_block_memory_virtex2p_6_3_e98c3706f2ec2c76: component is false;
attribute dont_touch of dual_port_block_memory_virtex2p_6_3_e98c3706f2ec2c76: component is true;
component dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8
port (
addra: in std_logic_vector(7 downto 0);
addrb: in std_logic_vector(7 downto 0);
clka: in std_logic;
clkb: in std_logic;
dina: in std_logic_vector(31 downto 0);
dinb: in std_logic_vector(31 downto 0);
ena: in std_logic;
enb: in std_logic;
wea: in std_logic;
web: in std_logic;
douta: out std_logic_vector(31 downto 0);
doutb: out std_logic_vector(31 downto 0)
);
end component;
attribute syn_black_box of dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8: component is true;
attribute box_type of dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8: component is "black_box";
attribute syn_noprune of dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8: component is true;
attribute optimize_primitives of dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8: component is false;
attribute dont_touch of dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8: component is true;
component xlpersistentdff
port (
clk: in std_logic;
d: in std_logic;
q: out std_logic
);
end component;
attribute syn_black_box of xlpersistentdff: component is true;
attribute box_type of xlpersistentdff: component is "black_box";
attribute syn_noprune of xlpersistentdff: component is true;
attribute optimize_primitives of xlpersistentdff: component is false;
attribute dont_touch of xlpersistentdff: component is true;
signal Buttons_Big_reg_ce: std_logic;
signal Buttons_Small_reg_ce: std_logic;
signal Buzzer_DutyCycle_reg_ce: std_logic;
signal Buzzer_Enable_reg_ce: std_logic;
signal Buzzer_Period_reg_ce: std_logic;
signal DIP_Switch_reg_ce: std_logic;
signal LCD_BackgroundColor_reg_ce: std_logic;
signal LCD_CharacterOffset_reg_ce: std_logic;
signal LCD_CharactersSelect_reg_ce: std_logic;
signal LCD_ColSet_reg_ce: std_logic;
signal LCD_ConfigLocation_reg_ce: std_logic;
signal LCD_DividerSelect_reg_ce: std_logic;
signal LCD_FirstEnd_reg_ce: std_logic;
signal LCD_FirstStart_reg_ce: std_logic;
signal LCD_LineOffset_reg_ce: std_logic;
signal LCD_RamWrite_reg_ce: std_logic;
signal LCD_ResetLCD_reg_ce: std_logic;
signal LCD_Reset_reg_ce: std_logic;
signal LCD_RowSet_reg_ce: std_logic;
signal LCD_SecondEnd_reg_ce: std_logic;
signal LCD_SecondStart_reg_ce: std_logic;
signal LCD_Send_reg_ce: std_logic;
signal LCD_TotalCmdTransfer_reg_ce: std_logic;
signal LEDs_reg_ce: std_logic;
signal Trackball_reg_ce: std_logic;
signal addr_net: std_logic_vector(11 downto 0);
signal addr_x0_net: std_logic_vector(8 downto 0);
signal addr_x1_net: std_logic_vector(7 downto 0);
signal addr_x2_net: std_logic_vector(7 downto 0);
signal addr_x3_net: std_logic_vector(8 downto 0);
signal addr_x4_net: std_logic_vector(11 downto 0);
signal buttons_big_net: std_logic_vector(1 downto 0);
signal buttons_small_net: std_logic_vector(5 downto 0);
signal buzzer_net: std_logic;
signal ce_1_sg_x21: std_logic;
attribute MAX_FANOUT: string;
attribute MAX_FANOUT of ce_1_sg_x21: signal is "REDUCE";
signal clkNet: std_logic;
signal clk_1_sg_x21: std_logic;
signal cs_net: std_logic;
signal data_in_net: std_logic_vector(17 downto 0);
signal data_in_x0_net: std_logic;
signal data_in_x10_net: std_logic_vector(3 downto 0);
signal data_in_x11_net: std_logic_vector(8 downto 0);
signal data_in_x12_net: std_logic;
signal data_in_x13_net: std_logic;
signal data_in_x14_net: std_logic_vector(8 downto 0);
signal data_in_x15_net: std_logic_vector(8 downto 0);
signal data_in_x16_net: std_logic_vector(8 downto 0);
signal data_in_x17_net: std_logic;
signal data_in_x18_net: std_logic_vector(7 downto 0);
signal data_in_x19_net: std_logic_vector(7 downto 0);
signal data_in_x1_net: std_logic_vector(17 downto 0);
signal data_in_x20_net: std_logic_vector(31 downto 0);
signal data_in_x21_net: std_logic_vector(31 downto 0);
signal data_in_x22_net: std_logic_vector(31 downto 0);
signal data_in_x23_net: std_logic_vector(4 downto 0);
signal data_in_x24_net: std_logic_vector(1 downto 0);
signal data_in_x25_net: std_logic_vector(5 downto 0);
signal data_in_x26_net: std_logic_vector(3 downto 0);
signal data_in_x27_net: std_logic_vector(31 downto 0);
signal data_in_x28_net: std_logic_vector(31 downto 0);
signal data_in_x29_net: std_logic_vector(31 downto 0);
signal data_in_x2_net: std_logic_vector(8 downto 0);
signal data_in_x3_net: std_logic_vector(3 downto 0);
signal data_in_x4_net: std_logic_vector(2 downto 0);
signal data_in_x5_net: std_logic_vector(8 downto 0);
signal data_in_x6_net: std_logic_vector(1 downto 0);
signal data_in_x7_net: std_logic;
signal data_in_x8_net: std_logic_vector(8 downto 0);
signal data_in_x9_net: std_logic_vector(8 downto 0);
signal data_out_net: std_logic_vector(17 downto 0);
signal data_out_x0_net: std_logic_vector(17 downto 0);
signal data_out_x10_net: std_logic;
signal data_out_x11_net: std_logic_vector(7 downto 0);
signal data_out_x12_net: std_logic;
signal data_out_x13_net: std_logic;
signal data_out_x14_net: std_logic;
signal data_out_x15_net: std_logic_vector(8 downto 0);
signal data_out_x16_net: std_logic_vector(8 downto 0);
signal data_out_x17_net: std_logic_vector(8 downto 0);
signal data_out_x18_net: std_logic_vector(8 downto 0);
signal data_out_x19_net: std_logic_vector(8 downto 0);
signal data_out_x1_net: std_logic;
signal data_out_x20_net: std_logic_vector(1 downto 0);
signal data_out_x21_net: std_logic_vector(31 downto 0);
signal data_out_x22_net: std_logic_vector(3 downto 0);
signal data_out_x23_net: std_logic_vector(3 downto 0);
signal data_out_x24_net: std_logic_vector(8 downto 0);
signal data_out_x25_net: std_logic_vector(8 downto 0);
signal data_out_x26_net: std_logic_vector(8 downto 0);
signal data_out_x27_net: std_logic_vector(2 downto 0);
signal data_out_x28_net: std_logic_vector(31 downto 0);
signal data_out_x29_net: std_logic_vector(31 downto 0);
signal data_out_x2_net: std_logic_vector(1 downto 0);
signal data_out_x3_net: std_logic_vector(5 downto 0);
signal data_out_x4_net: std_logic_vector(3 downto 0);
signal data_out_x5_net: std_logic_vector(4 downto 0);
signal data_out_x6_net: std_logic_vector(31 downto 0);
signal data_out_x7_net: std_logic_vector(31 downto 0);
signal data_out_x8_net: std_logic_vector(31 downto 0);
signal data_out_x9_net: std_logic_vector(7 downto 0);
signal dip_switch_net: std_logic_vector(3 downto 0);
signal en_net: std_logic;
signal en_x0_net: std_logic;
signal en_x10_net: std_logic;
signal en_x11_net: std_logic;
signal en_x12_net: std_logic;
signal en_x13_net: std_logic;
signal en_x14_net: std_logic;
signal en_x15_net: std_logic;
signal en_x16_net: std_logic;
signal en_x17_net: std_logic;
signal en_x18_net: std_logic;
signal en_x19_net: std_logic;
signal en_x1_net: std_logic;
signal en_x20_net: std_logic;
signal en_x21_net: std_logic;
signal en_x22_net: std_logic;
signal en_x23_net: std_logic;
signal en_x2_net: std_logic;
signal en_x3_net: std_logic;
signal en_x4_net: std_logic;
signal en_x5_net: std_logic;
signal en_x6_net: std_logic;
signal en_x7_net: std_logic;
signal en_x8_net: std_logic;
signal en_x9_net: std_logic;
signal leds_net: std_logic_vector(7 downto 0);
signal persistentdff_inst_q: std_logic;
attribute syn_keep: boolean;
attribute syn_keep of persistentdff_inst_q: signal is true;
attribute keep: boolean;
attribute keep of persistentdff_inst_q: signal is true;
attribute preserve_signal: boolean;
attribute preserve_signal of persistentdff_inst_q: signal is true;
signal plb_abus_net: std_logic_vector(31 downto 0);
signal plb_pavalid_net: std_logic;
signal plb_rnw_net: std_logic;
signal plb_wrdbus_net: std_logic_vector(31 downto 0);
signal reset_net: std_logic;
signal resetlcd_net: std_logic;
signal scl_net: std_logic;
signal sdi_net: std_logic;
signal sg_plb_addrpref_net: std_logic_vector(14 downto 0);
signal sl_addrack_net: std_logic;
signal sl_rdcomp_net: std_logic;
signal sl_rddack_net: std_logic;
signal sl_rddbus_net: std_logic_vector(31 downto 0);
signal sl_wait_net: std_logic;
signal sl_wrdack_x1: std_logic;
signal sl_wrdack_x2: std_logic;
signal splb_rst_net: std_logic;
signal trackball_ox_net: std_logic;
signal trackball_oxn_net: std_logic;
signal trackball_oy_net: std_logic;
signal trackball_oyn_net: std_logic;
signal trackball_sel1_net: std_logic;
signal trackball_sel2_net: std_logic;
signal trackball_xscn_net: std_logic;
signal trackball_yscn_net: std_logic;
signal we_net: std_logic;
signal we_x0_net: std_logic;
signal we_x1_net: std_logic;
signal we_x2_net: std_logic;
signal we_x3_net: std_logic;
signal we_x4_net: std_logic;
begin
buttons_big_net <= buttons_big;
buttons_small_net <= buttons_small;
clkNet <= clk;
dip_switch_net <= dip_switch;
plb_abus_net <= plb_abus;
plb_pavalid_net <= plb_pavalid;
plb_rnw_net <= plb_rnw;
plb_wrdbus_net <= plb_wrdbus;
reset_net <= reset;
sg_plb_addrpref_net <= sg_plb_addrpref;
splb_rst_net <= splb_rst;
trackball_ox_net <= trackball_ox;
trackball_oxn_net <= trackball_oxn;
trackball_oy_net <= trackball_oy;
trackball_oyn_net <= trackball_oyn;
trackball_sel2_net <= trackball_sel2;
buzzer <= buzzer_net;
cs <= cs_net;
leds <= leds_net;
resetlcd <= resetlcd_net;
scl <= scl_net;
sdi <= sdi_net;
sl_addrack <= sl_addrack_net;
sl_rdcomp <= sl_rdcomp_net;
sl_rddack <= sl_rddack_net;
sl_rddbus <= sl_rddbus_net;
sl_wait <= sl_wait_net;
sl_wrcomp <= sl_wrdack_x2;
sl_wrdack <= sl_wrdack_x1;
trackball_sel1 <= trackball_sel1_net;
trackball_xscn <= trackball_xscn_net;
trackball_yscn <= trackball_yscn_net;
Buttons_Big_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x21_net,
dout => Buttons_Big_reg_ce
);
Buttons_Big_x0: entity work.synth_reg_w_init
generic map (
width => 2,
init_index => 2,
init_value => b"00",
latency => 1
)
port map (
ce => Buttons_Big_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x24_net,
o => data_out_x2_net
);
Buttons_Small_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x22_net,
dout => Buttons_Small_reg_ce
);
Buttons_Small_x0: entity work.synth_reg_w_init
generic map (
width => 6,
init_index => 2,
init_value => b"000000",
latency => 1
)
port map (
ce => Buttons_Small_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x25_net,
o => data_out_x3_net
);
Buzzer_DutyCycle: entity work.synth_reg_w_init
generic map (
width => 18,
init_index => 2,
init_value => b"000000000000000000",
latency => 1
)
port map (
ce => Buzzer_DutyCycle_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_net,
o => data_out_x0_net
);
Buzzer_DutyCycle_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_net,
dout => Buzzer_DutyCycle_reg_ce
);
Buzzer_Enable: entity work.synth_reg_w_init
generic map (
width => 1,
init_index => 2,
init_value => b"0",
latency => 1
)
port map (
ce => Buzzer_Enable_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i(0) => data_in_x0_net,
o(0) => data_out_x1_net
);
Buzzer_Enable_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x0_net,
dout => Buzzer_Enable_reg_ce
);
Buzzer_Period: entity work.synth_reg_w_init
generic map (
width => 18,
init_index => 2,
init_value => b"000000000000000000",
latency => 1
)
port map (
ce => Buzzer_Period_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x1_net,
o => data_out_net
);
Buzzer_Period_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x1_net,
dout => Buzzer_Period_reg_ce
);
DIP_Switch_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x23_net,
dout => DIP_Switch_reg_ce
);
DIP_Switch_x0: entity work.synth_reg_w_init
generic map (
width => 4,
init_index => 2,
init_value => b"0000",
latency => 1
)
port map (
ce => DIP_Switch_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x26_net,
o => data_out_x4_net
);
LCD_BackgroundColor: entity work.synth_reg_w_init
generic map (
width => 9,
init_index => 2,
init_value => b"000000000",
latency => 1
)
port map (
ce => LCD_BackgroundColor_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x2_net,
o => data_out_x17_net
);
LCD_BackgroundColor_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x2_net,
dout => LCD_BackgroundColor_reg_ce
);
LCD_CharacterMap: dual_port_block_memory_virtex2p_6_3_e98c3706f2ec2c76
port map (
addra => addr_x4_net,
addrb => addr_net,
clka => clk_1_sg_x21,
clkb => clk_1_sg_x21,
dina => data_in_x29_net,
dinb => data_in_x20_net,
ena => ce_1_sg_x21,
enb => ce_1_sg_x21,
wea => we_x4_net,
web => we_net,
douta => data_out_x29_net,
doutb => data_out_x6_net
);
LCD_CharacterOffset: entity work.synth_reg_w_init
generic map (
width => 4,
init_index => 2,
init_value => b"0000",
latency => 1
)
port map (
ce => LCD_CharacterOffset_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x3_net,
o => data_out_x23_net
);
LCD_CharacterOffset_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x3_net,
dout => LCD_CharacterOffset_reg_ce
);
LCD_Characters: dual_port_block_memory_virtex2p_6_3_25371f622c89ba44
port map (
addra => addr_x3_net,
addrb => addr_x0_net,
clka => clk_1_sg_x21,
clkb => clk_1_sg_x21,
dina => data_in_x28_net,
dinb => data_in_x21_net,
ena => ce_1_sg_x21,
enb => ce_1_sg_x21,
wea => we_x3_net,
web => we_x0_net,
douta => data_out_x28_net,
doutb => data_out_x7_net
);
LCD_CharactersSelect: entity work.synth_reg_w_init
generic map (
width => 3,
init_index => 2,
init_value => b"000",
latency => 1
)
port map (
ce => LCD_CharactersSelect_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x4_net,
o => data_out_x27_net
);
LCD_CharactersSelect_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x4_net,
dout => LCD_CharactersSelect_reg_ce
);
LCD_ColSet: entity work.synth_reg_w_init
generic map (
width => 9,
init_index => 2,
init_value => b"000000000",
latency => 1
)
port map (
ce => LCD_ColSet_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x5_net,
o => data_out_x24_net
);
LCD_ColSet_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x5_net,
dout => LCD_ColSet_reg_ce
);
LCD_Commands: dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8
port map (
addra => addr_x2_net,
addrb => addr_x1_net,
clka => clk_1_sg_x21,
clkb => clk_1_sg_x21,
dina => data_in_x27_net,
dinb => data_in_x22_net,
ena => ce_1_sg_x21,
enb => ce_1_sg_x21,
wea => we_x2_net,
web => we_x1_net,
douta => data_out_x21_net,
doutb => data_out_x8_net
);
LCD_ConfigLocation: entity work.synth_reg_w_init
generic map (
width => 2,
init_index => 2,
init_value => b"00",
latency => 1
)
port map (
ce => LCD_ConfigLocation_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x6_net,
o => data_out_x20_net
);
LCD_ConfigLocation_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x6_net,
dout => LCD_ConfigLocation_reg_ce
);
LCD_DividerSelect: entity work.synth_reg_w_init
generic map (
width => 1,
init_index => 2,
init_value => b"0",
latency => 1
)
port map (
ce => LCD_DividerSelect_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i(0) => data_in_x7_net,
o(0) => data_out_x12_net
);
LCD_DividerSelect_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x7_net,
dout => LCD_DividerSelect_reg_ce
);
LCD_FirstEnd: entity work.synth_reg_w_init
generic map (
width => 9,
init_index => 2,
init_value => b"000000000",
latency => 1
)
port map (
ce => LCD_FirstEnd_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x8_net,
o => data_out_x16_net
);
LCD_FirstEnd_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x8_net,
dout => LCD_FirstEnd_reg_ce
);
LCD_FirstStart: entity work.synth_reg_w_init
generic map (
width => 9,
init_index => 2,
init_value => b"000000000",
latency => 1
)
port map (
ce => LCD_FirstStart_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x9_net,
o => data_out_x15_net
);
LCD_FirstStart_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x9_net,
dout => LCD_FirstStart_reg_ce
);
LCD_LineOffset: entity work.synth_reg_w_init
generic map (
width => 4,
init_index => 2,
init_value => b"0000",
latency => 1
)
port map (
ce => LCD_LineOffset_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x10_net,
o => data_out_x22_net
);
LCD_LineOffset_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x10_net,
dout => LCD_LineOffset_reg_ce
);
LCD_RamWrite: entity work.synth_reg_w_init
generic map (
width => 9,
init_index => 2,
init_value => b"000000000",
latency => 1
)
port map (
ce => LCD_RamWrite_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x11_net,
o => data_out_x25_net
);
LCD_RamWrite_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x11_net,
dout => LCD_RamWrite_reg_ce
);
LCD_Reset: entity work.synth_reg_w_init
generic map (
width => 1,
init_index => 2,
init_value => b"0",
latency => 1
)
port map (
ce => LCD_Reset_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i(0) => data_in_x12_net,
o(0) => data_out_x10_net
);
LCD_ResetLCD: entity work.synth_reg_w_init
generic map (
width => 1,
init_index => 2,
init_value => b"0",
latency => 1
)
port map (
ce => LCD_ResetLCD_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i(0) => data_in_x13_net,
o(0) => data_out_x14_net
);
LCD_ResetLCD_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x13_net,
dout => LCD_ResetLCD_reg_ce
);
LCD_Reset_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x12_net,
dout => LCD_Reset_reg_ce
);
LCD_RowSet: entity work.synth_reg_w_init
generic map (
width => 9,
init_index => 2,
init_value => b"000000000",
latency => 1
)
port map (
ce => LCD_RowSet_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x14_net,
o => data_out_x26_net
);
LCD_RowSet_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x14_net,
dout => LCD_RowSet_reg_ce
);
LCD_SecondEnd: entity work.synth_reg_w_init
generic map (
width => 9,
init_index => 2,
init_value => b"000000000",
latency => 1
)
port map (
ce => LCD_SecondEnd_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x15_net,
o => data_out_x19_net
);
LCD_SecondEnd_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x15_net,
dout => LCD_SecondEnd_reg_ce
);
LCD_SecondStart: entity work.synth_reg_w_init
generic map (
width => 9,
init_index => 2,
init_value => b"000000000",
latency => 1
)
port map (
ce => LCD_SecondStart_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x16_net,
o => data_out_x18_net
);
LCD_SecondStart_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x16_net,
dout => LCD_SecondStart_reg_ce
);
LCD_Send: entity work.synth_reg_w_init
generic map (
width => 1,
init_index => 2,
init_value => b"0",
latency => 1
)
port map (
ce => LCD_Send_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i(0) => data_in_x17_net,
o(0) => data_out_x13_net
);
LCD_Send_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x17_net,
dout => LCD_Send_reg_ce
);
LCD_TotalCmdTransfer: entity work.synth_reg_w_init
generic map (
width => 8,
init_index => 2,
init_value => b"00000000",
latency => 1
)
port map (
ce => LCD_TotalCmdTransfer_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x18_net,
o => data_out_x11_net
);
LCD_TotalCmdTransfer_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x18_net,
dout => LCD_TotalCmdTransfer_reg_ce
);
LEDs_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x19_net,
dout => LEDs_reg_ce
);
LEDs_x0: entity work.synth_reg_w_init
generic map (
width => 8,
init_index => 2,
init_value => b"00000000",
latency => 1
)
port map (
ce => LEDs_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x19_net,
o => data_out_x9_net
);
Trackball: entity work.synth_reg_w_init
generic map (
width => 5,
init_index => 2,
init_value => b"00000",
latency => 1
)
port map (
ce => Trackball_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x23_net,
o => data_out_x5_net
);
Trackball_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x20_net,
dout => Trackball_reg_ce
);
clk_probe: entity work.xlclkprobe
port map (
ce => '1',
clk => clkNet,
clr => '0'
);
default_clock_driver_x0: entity work.default_clock_driver
port map (
sysce => '1',
sysce_clr => '0',
sysclk => clkNet,
ce_1 => ce_1_sg_x21,
clk_1 => clk_1_sg_x21
);
persistentdff_inst: xlpersistentdff
port map (
clk => clkNet,
d => persistentdff_inst_q,
q => persistentdff_inst_q
);
user_io_board_controller_x0: entity work.user_io_board_controller
port map (
buttons_big => buttons_big_net,
buttons_small => buttons_small_net,
ce_1 => ce_1_sg_x21,
clk_1 => clk_1_sg_x21,
data_out => data_out_net,
data_out_x0 => data_out_x0_net,
data_out_x1 => data_out_x1_net,
data_out_x10 => data_out_x10_net,
data_out_x11 => data_out_x11_net,
data_out_x12 => data_out_x12_net,
data_out_x13 => data_out_x13_net,
data_out_x14 => data_out_x14_net,
data_out_x15 => data_out_x15_net,
data_out_x16 => data_out_x16_net,
data_out_x17 => data_out_x17_net,
data_out_x18 => data_out_x18_net,
data_out_x19 => data_out_x19_net,
data_out_x2 => data_out_x2_net,
data_out_x20 => data_out_x20_net,
data_out_x21 => data_out_x21_net,
data_out_x22 => data_out_x22_net,
data_out_x23 => data_out_x23_net,
data_out_x24 => data_out_x24_net,
data_out_x25 => data_out_x25_net,
data_out_x26 => data_out_x26_net,
data_out_x27 => data_out_x27_net,
data_out_x28 => data_out_x28_net,
data_out_x29 => data_out_x29_net,
data_out_x3 => data_out_x3_net,
data_out_x4 => data_out_x4_net,
data_out_x5 => data_out_x5_net,
data_out_x6 => data_out_x6_net,
data_out_x7 => data_out_x7_net,
data_out_x8 => data_out_x8_net,
data_out_x9 => data_out_x9_net,
dip_switch => dip_switch_net,
dout => data_out_x0_net,
dout_x0 => data_out_x1_net,
dout_x1 => data_out_net,
dout_x10 => data_out_x22_net,
dout_x11 => data_out_x25_net,
dout_x12 => data_out_x10_net,
dout_x13 => data_out_x14_net,
dout_x14 => data_out_x26_net,
dout_x15 => data_out_x19_net,
dout_x16 => data_out_x18_net,
dout_x17 => data_out_x13_net,
dout_x18 => data_out_x11_net,
dout_x19 => data_out_x9_net,
dout_x2 => data_out_x17_net,
dout_x3 => data_out_x23_net,
dout_x4 => data_out_x27_net,
dout_x5 => data_out_x24_net,
dout_x6 => data_out_x20_net,
dout_x7 => data_out_x12_net,
dout_x8 => data_out_x16_net,
dout_x9 => data_out_x15_net,
plb_abus => plb_abus_net,
plb_pavalid => plb_pavalid_net,
plb_rnw => plb_rnw_net,
plb_wrdbus => plb_wrdbus_net,
reset => reset_net,
sg_plb_addrpref => sg_plb_addrpref_net,
splb_rst => splb_rst_net,
trackball_ox => trackball_ox_net,
trackball_oxn => trackball_oxn_net,
trackball_oy => trackball_oy_net,
trackball_oyn => trackball_oyn_net,
trackball_sel2 => trackball_sel2_net,
addr => addr_net,
addr_x0 => addr_x0_net,
addr_x1 => addr_x1_net,
addr_x2 => addr_x2_net,
addr_x3 => addr_x3_net,
addr_x4 => addr_x4_net,
buzzer => buzzer_net,
cs => cs_net,
data_in => data_in_net,
data_in_x0 => data_in_x0_net,
data_in_x1 => data_in_x1_net,
data_in_x10 => data_in_x10_net,
data_in_x11 => data_in_x11_net,
data_in_x12 => data_in_x12_net,
data_in_x13 => data_in_x13_net,
data_in_x14 => data_in_x14_net,
data_in_x15 => data_in_x15_net,
data_in_x16 => data_in_x16_net,
data_in_x17 => data_in_x17_net,
data_in_x18 => data_in_x18_net,
data_in_x19 => data_in_x19_net,
data_in_x2 => data_in_x2_net,
data_in_x20 => data_in_x20_net,
data_in_x21 => data_in_x21_net,
data_in_x22 => data_in_x22_net,
data_in_x23 => data_in_x23_net,
data_in_x24 => data_in_x24_net,
data_in_x25 => data_in_x25_net,
data_in_x26 => data_in_x26_net,
data_in_x27 => data_in_x27_net,
data_in_x28 => data_in_x28_net,
data_in_x29 => data_in_x29_net,
data_in_x3 => data_in_x3_net,
data_in_x4 => data_in_x4_net,
data_in_x5 => data_in_x5_net,
data_in_x6 => data_in_x6_net,
data_in_x7 => data_in_x7_net,
data_in_x8 => data_in_x8_net,
data_in_x9 => data_in_x9_net,
en => en_net,
en_x0 => en_x0_net,
en_x1 => en_x1_net,
en_x10 => en_x10_net,
en_x11 => en_x11_net,
en_x12 => en_x12_net,
en_x13 => en_x13_net,
en_x14 => en_x14_net,
en_x15 => en_x15_net,
en_x16 => en_x16_net,
en_x17 => en_x17_net,
en_x18 => en_x18_net,
en_x19 => en_x19_net,
en_x2 => en_x2_net,
en_x20 => en_x20_net,
en_x21 => en_x21_net,
en_x22 => en_x22_net,
en_x23 => en_x23_net,
en_x3 => en_x3_net,
en_x4 => en_x4_net,
en_x5 => en_x5_net,
en_x6 => en_x6_net,
en_x7 => en_x7_net,
en_x8 => en_x8_net,
en_x9 => en_x9_net,
leds => leds_net,
resetlcd => resetlcd_net,
scl => scl_net,
sdi => sdi_net,
sl_addrack => sl_addrack_net,
sl_rdcomp => sl_rdcomp_net,
sl_rddack => sl_rddack_net,
sl_rddbus => sl_rddbus_net,
sl_wait => sl_wait_net,
sl_wrcomp => sl_wrdack_x2,
sl_wrdack => sl_wrdack_x1,
trackball_sel1 => trackball_sel1_net,
trackball_xscn => trackball_xscn_net,
trackball_yscn => trackball_yscn_net,
we => we_net,
we_x0 => we_x0_net,
we_x1 => we_x1_net,
we_x2 => we_x2_net,
we_x3 => we_x3_net,
we_x4 => we_x4_net
);
end structural;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file adder_subtracter_virtex2p_7_0_453ed16ba8e84295.vhd when simulating
-- the core, adder_subtracter_virtex2p_7_0_453ed16ba8e84295. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY adder_subtracter_virtex2p_7_0_453ed16ba8e84295 IS
port (
A: IN std_logic_VECTOR(8 downto 0);
B: IN std_logic_VECTOR(8 downto 0);
S: OUT std_logic_VECTOR(8 downto 0));
END adder_subtracter_virtex2p_7_0_453ed16ba8e84295;
ARCHITECTURE adder_subtracter_virtex2p_7_0_453ed16ba8e84295_a OF adder_subtracter_virtex2p_7_0_453ed16ba8e84295 IS
-- synthesis translate_off
component wrapped_adder_subtracter_virtex2p_7_0_453ed16ba8e84295
port (
A: IN std_logic_VECTOR(8 downto 0);
B: IN std_logic_VECTOR(8 downto 0);
S: OUT std_logic_VECTOR(8 downto 0));
end component;
-- Configuration specification
for all : wrapped_adder_subtracter_virtex2p_7_0_453ed16ba8e84295 use entity XilinxCoreLib.C_ADDSUB_V7_0(behavioral)
generic map(
c_has_bypass_with_cin => 0,
c_a_type => 1,
c_has_sclr => 0,
c_sync_priority => 1,
c_has_aset => 0,
c_has_b_out => 0,
c_has_s => 1,
c_has_q => 0,
c_bypass_enable => 0,
c_b_constant => 0,
c_has_ovfl => 0,
c_high_bit => 8,
c_latency => 0,
c_sinit_val => "0",
c_has_bypass => 0,
c_pipe_stages => 1,
c_has_sset => 0,
c_has_ainit => 0,
c_has_a_signed => 0,
c_has_q_c_out => 0,
c_b_type => 1,
c_has_add => 0,
c_has_sinit => 0,
c_has_b_in => 0,
c_has_b_signed => 0,
c_bypass_low => 0,
c_enable_rlocs => 1,
c_b_value => "0",
c_add_mode => 0,
c_has_aclr => 0,
c_out_width => 9,
c_ainit_val => "0000",
c_low_bit => 0,
c_has_q_ovfl => 0,
c_has_q_b_out => 0,
c_has_c_out => 0,
c_b_width => 9,
c_a_width => 9,
c_sync_enable => 0,
c_has_ce => 1,
c_has_c_in => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_adder_subtracter_virtex2p_7_0_453ed16ba8e84295
port map (
A => A,
B => B,
S => S);
-- synthesis translate_on
END adder_subtracter_virtex2p_7_0_453ed16ba8e84295_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file adder_subtracter_virtex2p_7_0_7182743c9e7adf5e.vhd when simulating
-- the core, adder_subtracter_virtex2p_7_0_7182743c9e7adf5e. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY adder_subtracter_virtex2p_7_0_7182743c9e7adf5e IS
port (
A: IN std_logic_VECTOR(4 downto 0);
B: IN std_logic_VECTOR(4 downto 0);
S: OUT std_logic_VECTOR(4 downto 0));
END adder_subtracter_virtex2p_7_0_7182743c9e7adf5e;
ARCHITECTURE adder_subtracter_virtex2p_7_0_7182743c9e7adf5e_a OF adder_subtracter_virtex2p_7_0_7182743c9e7adf5e IS
-- synthesis translate_off
component wrapped_adder_subtracter_virtex2p_7_0_7182743c9e7adf5e
port (
A: IN std_logic_VECTOR(4 downto 0);
B: IN std_logic_VECTOR(4 downto 0);
S: OUT std_logic_VECTOR(4 downto 0));
end component;
-- Configuration specification
for all : wrapped_adder_subtracter_virtex2p_7_0_7182743c9e7adf5e use entity XilinxCoreLib.C_ADDSUB_V7_0(behavioral)
generic map(
c_has_bypass_with_cin => 0,
c_a_type => 1,
c_has_sclr => 0,
c_sync_priority => 1,
c_has_aset => 0,
c_has_b_out => 0,
c_has_s => 1,
c_has_q => 0,
c_bypass_enable => 0,
c_b_constant => 0,
c_has_ovfl => 0,
c_high_bit => 4,
c_latency => 0,
c_sinit_val => "0",
c_has_bypass => 0,
c_pipe_stages => 1,
c_has_sset => 0,
c_has_ainit => 0,
c_has_a_signed => 0,
c_has_q_c_out => 0,
c_b_type => 1,
c_has_add => 0,
c_has_sinit => 0,
c_has_b_in => 0,
c_has_b_signed => 0,
c_bypass_low => 0,
c_enable_rlocs => 1,
c_b_value => "0",
c_add_mode => 0,
c_has_aclr => 0,
c_out_width => 5,
c_ainit_val => "0000",
c_low_bit => 0,
c_has_q_ovfl => 0,
c_has_q_b_out => 0,
c_has_c_out => 0,
c_b_width => 5,
c_a_width => 5,
c_sync_enable => 0,
c_has_ce => 1,
c_has_c_in => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_adder_subtracter_virtex2p_7_0_7182743c9e7adf5e
port map (
A => A,
B => B,
S => S);
-- synthesis translate_on
END adder_subtracter_virtex2p_7_0_7182743c9e7adf5e_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3.vhd when simulating
-- the core, adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3 IS
port (
A: IN std_logic_VECTOR(8 downto 0);
B: IN std_logic_VECTOR(8 downto 0);
S: OUT std_logic_VECTOR(8 downto 0));
END adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3;
ARCHITECTURE adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3_a OF adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3 IS
-- synthesis translate_off
component wrapped_adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3
port (
A: IN std_logic_VECTOR(8 downto 0);
B: IN std_logic_VECTOR(8 downto 0);
S: OUT std_logic_VECTOR(8 downto 0));
end component;
-- Configuration specification
for all : wrapped_adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3 use entity XilinxCoreLib.C_ADDSUB_V7_0(behavioral)
generic map(
c_has_bypass_with_cin => 0,
c_a_type => 0,
c_has_sclr => 0,
c_sync_priority => 1,
c_has_aset => 0,
c_has_b_out => 0,
c_has_s => 1,
c_has_q => 0,
c_bypass_enable => 0,
c_b_constant => 0,
c_has_ovfl => 0,
c_high_bit => 8,
c_latency => 0,
c_sinit_val => "0",
c_has_bypass => 0,
c_pipe_stages => 1,
c_has_sset => 0,
c_has_ainit => 0,
c_has_a_signed => 0,
c_has_q_c_out => 0,
c_b_type => 0,
c_has_add => 0,
c_has_sinit => 0,
c_has_b_in => 0,
c_has_b_signed => 0,
c_bypass_low => 0,
c_enable_rlocs => 1,
c_b_value => "0",
c_add_mode => 1,
c_has_aclr => 0,
c_out_width => 9,
c_ainit_val => "0000",
c_low_bit => 0,
c_has_q_ovfl => 0,
c_has_q_b_out => 0,
c_has_c_out => 0,
c_b_width => 9,
c_a_width => 9,
c_sync_enable => 0,
c_has_ce => 1,
c_has_c_in => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3
port map (
A => A,
B => B,
S => S);
-- synthesis translate_on
END adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file binary_counter_virtex2p_7_0_23542cbcca0efa2e.vhd when simulating
-- the core, binary_counter_virtex2p_7_0_23542cbcca0efa2e. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY binary_counter_virtex2p_7_0_23542cbcca0efa2e IS
port (
Q: OUT std_logic_VECTOR(3 downto 0);
CLK: IN std_logic;
CE: IN std_logic;
SINIT: IN std_logic);
END binary_counter_virtex2p_7_0_23542cbcca0efa2e;
ARCHITECTURE binary_counter_virtex2p_7_0_23542cbcca0efa2e_a OF binary_counter_virtex2p_7_0_23542cbcca0efa2e IS
-- synthesis translate_off
component wrapped_binary_counter_virtex2p_7_0_23542cbcca0efa2e
port (
Q: OUT std_logic_VECTOR(3 downto 0);
CLK: IN std_logic;
CE: IN std_logic;
SINIT: IN std_logic);
end component;
-- Configuration specification
for all : wrapped_binary_counter_virtex2p_7_0_23542cbcca0efa2e use entity XilinxCoreLib.C_COUNTER_BINARY_V7_0(behavioral)
generic map(
c_count_mode => 0,
c_load_enable => 1,
c_has_aset => 0,
c_load_low => 0,
c_count_to => "1111111111111111",
c_sync_priority => 1,
c_has_iv => 0,
c_restrict_count => 0,
c_has_sclr => 0,
c_width => 4,
c_has_q_thresh1 => 0,
c_enable_rlocs => 0,
c_has_q_thresh0 => 0,
c_thresh1_value => "1111111111111111",
c_has_load => 0,
c_thresh_early => 1,
c_has_up => 0,
c_has_thresh1 => 0,
c_has_thresh0 => 0,
c_ainit_val => "0000",
c_has_ce => 1,
c_pipe_stages => 0,
c_has_aclr => 0,
c_sync_enable => 0,
c_has_ainit => 0,
c_sinit_val => "0000",
c_has_sset => 0,
c_has_sinit => 1,
c_count_by => "0001",
c_has_l => 0,
c_thresh0_value => "1111111111111111");
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_binary_counter_virtex2p_7_0_23542cbcca0efa2e
port map (
Q => Q,
CLK => CLK,
CE => CE,
SINIT => SINIT);
-- synthesis translate_on
END binary_counter_virtex2p_7_0_23542cbcca0efa2e_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file binary_counter_virtex2p_7_0_32a1863440903b9d.vhd when simulating
-- the core, binary_counter_virtex2p_7_0_32a1863440903b9d. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY binary_counter_virtex2p_7_0_32a1863440903b9d IS
port (
Q: OUT std_logic_VECTOR(14 downto 0);
CLK: IN std_logic;
CE: IN std_logic;
SINIT: IN std_logic);
END binary_counter_virtex2p_7_0_32a1863440903b9d;
ARCHITECTURE binary_counter_virtex2p_7_0_32a1863440903b9d_a OF binary_counter_virtex2p_7_0_32a1863440903b9d IS
-- synthesis translate_off
component wrapped_binary_counter_virtex2p_7_0_32a1863440903b9d
port (
Q: OUT std_logic_VECTOR(14 downto 0);
CLK: IN std_logic;
CE: IN std_logic;
SINIT: IN std_logic);
end component;
-- Configuration specification
for all : wrapped_binary_counter_virtex2p_7_0_32a1863440903b9d use entity XilinxCoreLib.C_COUNTER_BINARY_V7_0(behavioral)
generic map(
c_count_mode => 0,
c_load_enable => 1,
c_has_aset => 0,
c_load_low => 0,
c_count_to => "1111111111111111",
c_sync_priority => 1,
c_has_iv => 0,
c_restrict_count => 0,
c_has_sclr => 0,
c_width => 15,
c_has_q_thresh1 => 0,
c_enable_rlocs => 0,
c_has_q_thresh0 => 0,
c_thresh1_value => "1111111111111111",
c_has_load => 0,
c_thresh_early => 1,
c_has_up => 0,
c_has_thresh1 => 0,
c_has_thresh0 => 0,
c_ainit_val => "0000",
c_has_ce => 1,
c_pipe_stages => 0,
c_has_aclr => 0,
c_sync_enable => 0,
c_has_ainit => 0,
c_sinit_val => "0000",
c_has_sset => 0,
c_has_sinit => 1,
c_count_by => "0001",
c_has_l => 0,
c_thresh0_value => "1111111111111111");
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_binary_counter_virtex2p_7_0_32a1863440903b9d
port map (
Q => Q,
CLK => CLK,
CE => CE,
SINIT => SINIT);
-- synthesis translate_on
END binary_counter_virtex2p_7_0_32a1863440903b9d_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file binary_counter_virtex2p_7_0_77cea312f82499f0.vhd when simulating
-- the core, binary_counter_virtex2p_7_0_77cea312f82499f0. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY binary_counter_virtex2p_7_0_77cea312f82499f0 IS
port (
Q: OUT std_logic_VECTOR(3 downto 0);
CLK: IN std_logic;
LOAD: IN std_logic;
L: IN std_logic_VECTOR(3 downto 0);
CE: IN std_logic;
SINIT: IN std_logic);
END binary_counter_virtex2p_7_0_77cea312f82499f0;
ARCHITECTURE binary_counter_virtex2p_7_0_77cea312f82499f0_a OF binary_counter_virtex2p_7_0_77cea312f82499f0 IS
-- synthesis translate_off
component wrapped_binary_counter_virtex2p_7_0_77cea312f82499f0
port (
Q: OUT std_logic_VECTOR(3 downto 0);
CLK: IN std_logic;
LOAD: IN std_logic;
L: IN std_logic_VECTOR(3 downto 0);
CE: IN std_logic;
SINIT: IN std_logic);
end component;
-- Configuration specification
for all : wrapped_binary_counter_virtex2p_7_0_77cea312f82499f0 use entity XilinxCoreLib.C_COUNTER_BINARY_V7_0(behavioral)
generic map(
c_count_mode => 0,
c_load_enable => 1,
c_has_aset => 0,
c_load_low => 0,
c_count_to => "1111111111111111",
c_sync_priority => 1,
c_has_iv => 0,
c_restrict_count => 0,
c_has_sclr => 0,
c_width => 4,
c_has_q_thresh1 => 0,
c_enable_rlocs => 0,
c_has_q_thresh0 => 0,
c_thresh1_value => "1111111111111111",
c_has_load => 1,
c_thresh_early => 1,
c_has_up => 0,
c_has_thresh1 => 0,
c_has_thresh0 => 0,
c_ainit_val => "1111",
c_has_ce => 1,
c_pipe_stages => 0,
c_has_aclr => 0,
c_sync_enable => 0,
c_has_ainit => 0,
c_sinit_val => "1111",
c_has_sset => 0,
c_has_sinit => 1,
c_count_by => "0001",
c_has_l => 1,
c_thresh0_value => "1111111111111111");
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_binary_counter_virtex2p_7_0_77cea312f82499f0
port map (
Q => Q,
CLK => CLK,
LOAD => LOAD,
L => L,
CE => CE,
SINIT => SINIT);
-- synthesis translate_on
END binary_counter_virtex2p_7_0_77cea312f82499f0_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file binary_counter_virtex2p_7_0_950e4ab582797264.vhd when simulating
-- the core, binary_counter_virtex2p_7_0_950e4ab582797264. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY binary_counter_virtex2p_7_0_950e4ab582797264 IS
port (
Q: OUT std_logic_VECTOR(17 downto 0);
CLK: IN std_logic;
CE: IN std_logic;
SINIT: IN std_logic);
END binary_counter_virtex2p_7_0_950e4ab582797264;
ARCHITECTURE binary_counter_virtex2p_7_0_950e4ab582797264_a OF binary_counter_virtex2p_7_0_950e4ab582797264 IS
-- synthesis translate_off
component wrapped_binary_counter_virtex2p_7_0_950e4ab582797264
port (
Q: OUT std_logic_VECTOR(17 downto 0);
CLK: IN std_logic;
CE: IN std_logic;
SINIT: IN std_logic);
end component;
-- Configuration specification
for all : wrapped_binary_counter_virtex2p_7_0_950e4ab582797264 use entity XilinxCoreLib.C_COUNTER_BINARY_V7_0(behavioral)
generic map(
c_count_mode => 0,
c_load_enable => 1,
c_has_aset => 0,
c_load_low => 0,
c_count_to => "1111111111111111",
c_sync_priority => 1,
c_has_iv => 0,
c_restrict_count => 0,
c_has_sclr => 0,
c_width => 18,
c_has_q_thresh1 => 0,
c_enable_rlocs => 0,
c_has_q_thresh0 => 0,
c_thresh1_value => "1111111111111111",
c_has_load => 0,
c_thresh_early => 1,
c_has_up => 0,
c_has_thresh1 => 0,
c_has_thresh0 => 0,
c_ainit_val => "0000",
c_has_ce => 1,
c_pipe_stages => 0,
c_has_aclr => 0,
c_sync_enable => 0,
c_has_ainit => 0,
c_sinit_val => "0000",
c_has_sset => 0,
c_has_sinit => 1,
c_count_by => "0001",
c_has_l => 0,
c_thresh0_value => "1111111111111111");
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_binary_counter_virtex2p_7_0_950e4ab582797264
port map (
Q => Q,
CLK => CLK,
CE => CE,
SINIT => SINIT);
-- synthesis translate_on
END binary_counter_virtex2p_7_0_950e4ab582797264_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file binary_counter_virtex2p_7_0_a22528b4c55dc1cd.vhd when simulating
-- the core, binary_counter_virtex2p_7_0_a22528b4c55dc1cd. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY binary_counter_virtex2p_7_0_a22528b4c55dc1cd IS
port (
Q: OUT std_logic_VECTOR(13 downto 0);
CLK: IN std_logic;
CE: IN std_logic;
SINIT: IN std_logic);
END binary_counter_virtex2p_7_0_a22528b4c55dc1cd;
ARCHITECTURE binary_counter_virtex2p_7_0_a22528b4c55dc1cd_a OF binary_counter_virtex2p_7_0_a22528b4c55dc1cd IS
-- synthesis translate_off
component wrapped_binary_counter_virtex2p_7_0_a22528b4c55dc1cd
port (
Q: OUT std_logic_VECTOR(13 downto 0);
CLK: IN std_logic;
CE: IN std_logic;
SINIT: IN std_logic);
end component;
-- Configuration specification
for all : wrapped_binary_counter_virtex2p_7_0_a22528b4c55dc1cd use entity XilinxCoreLib.C_COUNTER_BINARY_V7_0(behavioral)
generic map(
c_count_mode => 0,
c_load_enable => 1,
c_has_aset => 0,
c_load_low => 0,
c_count_to => "1111111111111111",
c_sync_priority => 1,
c_has_iv => 0,
c_restrict_count => 0,
c_has_sclr => 0,
c_width => 14,
c_has_q_thresh1 => 0,
c_enable_rlocs => 0,
c_has_q_thresh0 => 0,
c_thresh1_value => "1111111111111111",
c_has_load => 0,
c_thresh_early => 1,
c_has_up => 0,
c_has_thresh1 => 0,
c_has_thresh0 => 0,
c_ainit_val => "11111111111111",
c_has_ce => 1,
c_pipe_stages => 0,
c_has_aclr => 0,
c_sync_enable => 0,
c_has_ainit => 0,
c_sinit_val => "11111111111111",
c_has_sset => 0,
c_has_sinit => 1,
c_count_by => "0001",
c_has_l => 0,
c_thresh0_value => "1111111111111111");
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_binary_counter_virtex2p_7_0_a22528b4c55dc1cd
port map (
Q => Q,
CLK => CLK,
CE => CE,
SINIT => SINIT);
-- synthesis translate_on
END binary_counter_virtex2p_7_0_a22528b4c55dc1cd_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file binary_counter_virtex2p_7_0_b0a257f5389d649a.vhd when simulating
-- the core, binary_counter_virtex2p_7_0_b0a257f5389d649a. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY binary_counter_virtex2p_7_0_b0a257f5389d649a IS
port (
Q: OUT std_logic_VECTOR(6 downto 0);
CLK: IN std_logic;
CE: IN std_logic;
SINIT: IN std_logic);
END binary_counter_virtex2p_7_0_b0a257f5389d649a;
ARCHITECTURE binary_counter_virtex2p_7_0_b0a257f5389d649a_a OF binary_counter_virtex2p_7_0_b0a257f5389d649a IS
-- synthesis translate_off
component wrapped_binary_counter_virtex2p_7_0_b0a257f5389d649a
port (
Q: OUT std_logic_VECTOR(6 downto 0);
CLK: IN std_logic;
CE: IN std_logic;
SINIT: IN std_logic);
end component;
-- Configuration specification
for all : wrapped_binary_counter_virtex2p_7_0_b0a257f5389d649a use entity XilinxCoreLib.C_COUNTER_BINARY_V7_0(behavioral)
generic map(
c_count_mode => 0,
c_load_enable => 1,
c_has_aset => 0,
c_load_low => 0,
c_count_to => "1111111111111111",
c_sync_priority => 1,
c_has_iv => 0,
c_restrict_count => 0,
c_has_sclr => 0,
c_width => 7,
c_has_q_thresh1 => 0,
c_enable_rlocs => 0,
c_has_q_thresh0 => 0,
c_thresh1_value => "1111111111111111",
c_has_load => 0,
c_thresh_early => 1,
c_has_up => 0,
c_has_thresh1 => 0,
c_has_thresh0 => 0,
c_ainit_val => "1111111",
c_has_ce => 1,
c_pipe_stages => 0,
c_has_aclr => 0,
c_sync_enable => 0,
c_has_ainit => 0,
c_sinit_val => "1111111",
c_has_sset => 0,
c_has_sinit => 1,
c_count_by => "0001",
c_has_l => 0,
c_thresh0_value => "1111111111111111");
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_binary_counter_virtex2p_7_0_b0a257f5389d649a
port map (
Q => Q,
CLK => CLK,
CE => CE,
SINIT => SINIT);
-- synthesis translate_on
END binary_counter_virtex2p_7_0_b0a257f5389d649a_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file binary_counter_virtex2p_7_0_b511f9871581ee23.vhd when simulating
-- the core, binary_counter_virtex2p_7_0_b511f9871581ee23. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY binary_counter_virtex2p_7_0_b511f9871581ee23 IS
port (
Q: OUT std_logic_VECTOR(2 downto 0);
CLK: IN std_logic;
LOAD: IN std_logic;
L: IN std_logic_VECTOR(2 downto 0);
CE: IN std_logic;
SINIT: IN std_logic);
END binary_counter_virtex2p_7_0_b511f9871581ee23;
ARCHITECTURE binary_counter_virtex2p_7_0_b511f9871581ee23_a OF binary_counter_virtex2p_7_0_b511f9871581ee23 IS
-- synthesis translate_off
component wrapped_binary_counter_virtex2p_7_0_b511f9871581ee23
port (
Q: OUT std_logic_VECTOR(2 downto 0);
CLK: IN std_logic;
LOAD: IN std_logic;
L: IN std_logic_VECTOR(2 downto 0);
CE: IN std_logic;
SINIT: IN std_logic);
end component;
-- Configuration specification
for all : wrapped_binary_counter_virtex2p_7_0_b511f9871581ee23 use entity XilinxCoreLib.C_COUNTER_BINARY_V7_0(behavioral)
generic map(
c_count_mode => 0,
c_load_enable => 1,
c_has_aset => 0,
c_load_low => 0,
c_count_to => "1111111111111111",
c_sync_priority => 1,
c_has_iv => 0,
c_restrict_count => 0,
c_has_sclr => 0,
c_width => 3,
c_has_q_thresh1 => 0,
c_enable_rlocs => 0,
c_has_q_thresh0 => 0,
c_thresh1_value => "1111111111111111",
c_has_load => 1,
c_thresh_early => 1,
c_has_up => 0,
c_has_thresh1 => 0,
c_has_thresh0 => 0,
c_ainit_val => "000",
c_has_ce => 1,
c_pipe_stages => 0,
c_has_aclr => 0,
c_sync_enable => 0,
c_has_ainit => 0,
c_sinit_val => "000",
c_has_sset => 0,
c_has_sinit => 1,
c_count_by => "001",
c_has_l => 1,
c_thresh0_value => "1111111111111111");
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_binary_counter_virtex2p_7_0_b511f9871581ee23
port map (
Q => Q,
CLK => CLK,
LOAD => LOAD,
L => L,
CE => CE,
SINIT => SINIT);
-- synthesis translate_on
END binary_counter_virtex2p_7_0_b511f9871581ee23_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file multiplier_virtex2p_10_1_817edd563258bb47.vhd when simulating
-- the core, multiplier_virtex2p_10_1_817edd563258bb47. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY multiplier_virtex2p_10_1_817edd563258bb47 IS
port (
clk: IN std_logic;
a: IN std_logic_VECTOR(17 downto 0);
b: IN std_logic_VECTOR(17 downto 0);
ce: IN std_logic;
sclr: IN std_logic;
p: OUT std_logic_VECTOR(35 downto 0));
END multiplier_virtex2p_10_1_817edd563258bb47;
ARCHITECTURE multiplier_virtex2p_10_1_817edd563258bb47_a OF multiplier_virtex2p_10_1_817edd563258bb47 IS
-- synthesis translate_off
component wrapped_multiplier_virtex2p_10_1_817edd563258bb47
port (
clk: IN std_logic;
a: IN std_logic_VECTOR(17 downto 0);
b: IN std_logic_VECTOR(17 downto 0);
ce: IN std_logic;
sclr: IN std_logic;
p: OUT std_logic_VECTOR(35 downto 0));
end component;
-- Configuration specification
for all : wrapped_multiplier_virtex2p_10_1_817edd563258bb47 use entity XilinxCoreLib.mult_gen_v10_1(behavioral)
generic map(
c_a_width => 18,
c_b_type => 1,
c_ce_overrides_sclr => 1,
c_has_sclr => 1,
c_round_pt => 0,
c_model_type => 0,
c_out_high => 35,
c_verbosity => 0,
c_mult_type => 1,
c_ccm_imp => 0,
c_latency => 1,
c_has_ce => 1,
c_has_zero_detect => 0,
c_round_output => 0,
c_optimize_goal => 1,
c_xdevicefamily => "virtex2p",
c_a_type => 1,
c_out_low => 0,
c_b_width => 18,
c_b_value => "10000001");
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_multiplier_virtex2p_10_1_817edd563258bb47
port map (
clk => clk,
a => a,
b => b,
ce => ce,
sclr => sclr,
p => p);
-- synthesis translate_on
END multiplier_virtex2p_10_1_817edd563258bb47_a;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package conv_pkg is
constant simulating : boolean := false
-- synopsys translate_off
or true
-- synopsys translate_on
;
constant xlUnsigned : integer := 1;
constant xlSigned : integer := 2;
constant xlWrap : integer := 1;
constant xlSaturate : integer := 2;
constant xlTruncate : integer := 1;
constant xlRound : integer := 2;
constant xlRoundBanker : integer := 3;
constant xlAddMode : integer := 1;
constant xlSubMode : integer := 2;
attribute black_box : boolean;
attribute syn_black_box : boolean;
attribute fpga_dont_touch: string;
attribute box_type : string;
attribute keep : string;
attribute syn_keep : boolean;
function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned;
function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector;
function std_logic_vector_to_signed(inp : std_logic_vector) return signed;
function signed_to_std_logic_vector(inp : signed) return std_logic_vector;
function unsigned_to_signed(inp : unsigned) return signed;
function signed_to_unsigned(inp : signed) return unsigned;
function pos(inp : std_logic_vector; arith : INTEGER) return boolean;
function all_same(inp: std_logic_vector) return boolean;
function all_zeros(inp: std_logic_vector) return boolean;
function is_point_five(inp: std_logic_vector) return boolean;
function all_ones(inp: std_logic_vector) return boolean;
function convert_type (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith,
quantization, overflow : INTEGER)
return std_logic_vector;
function cast (inp : std_logic_vector; old_bin_pt,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function vec_slice (inp : std_logic_vector; upper, lower : INTEGER)
return std_logic_vector;
function s2u_slice (inp : signed; upper, lower : INTEGER)
return unsigned;
function u2u_slice (inp : unsigned; upper, lower : INTEGER)
return unsigned;
function s2s_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return signed;
function u2s_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return signed;
function s2u_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return unsigned;
function u2u_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return unsigned;
function u2v_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return std_logic_vector;
function s2v_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return std_logic_vector;
function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt,
new_arith : INTEGER) return std_logic_vector;
function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt,
new_arith : INTEGER) return std_logic_vector;
function max_signed(width : INTEGER) return std_logic_vector;
function min_signed(width : INTEGER) return std_logic_vector;
function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER) return std_logic_vector;
function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER;
function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER)
return INTEGER;
function sign_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector;
function zero_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector;
function zero_ext(inp : std_logic; new_width : INTEGER)
return std_logic_vector;
function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER)
return std_logic_vector;
function align_input(inp : std_logic_vector; old_width, delta, new_arith,
new_width: INTEGER)
return std_logic_vector;
function pad_LSB(inp : std_logic_vector; new_width: integer)
return std_logic_vector;
function pad_LSB(inp : std_logic_vector; new_width, arith : integer)
return std_logic_vector;
function max(L, R: INTEGER) return INTEGER;
function min(L, R: INTEGER) return INTEGER;
function "="(left,right: STRING) return boolean;
function boolean_to_signed (inp : boolean; width: integer)
return signed;
function boolean_to_unsigned (inp : boolean; width: integer)
return unsigned;
function boolean_to_vector (inp : boolean)
return std_logic_vector;
function std_logic_to_vector (inp : std_logic)
return std_logic_vector;
function integer_to_std_logic_vector (inp : integer; width, arith : integer)
return std_logic_vector;
function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer)
return integer;
function std_logic_to_integer(constant inp : std_logic := '0')
return integer;
function bin_string_element_to_std_logic_vector (inp : string; width, index : integer)
return std_logic_vector;
function bin_string_to_std_logic_vector (inp : string)
return std_logic_vector;
function hex_string_to_std_logic_vector (inp : string; width : integer)
return std_logic_vector;
function makeZeroBinStr (width : integer) return STRING;
function and_reduce(inp: std_logic_vector) return std_logic;
-- synopsys translate_off
function is_binary_string_invalid (inp : string)
return boolean;
function is_binary_string_undefined (inp : string)
return boolean;
function is_XorU(inp : std_logic_vector)
return boolean;
function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer)
return real;
function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer)
return real;
function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer)
return std_logic_vector;
function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer)
return std_logic_vector;
constant display_precision : integer := 20;
function real_to_string (inp : real) return string;
function valid_bin_string(inp : string) return boolean;
function std_logic_vector_to_bin_string(inp : std_logic_vector) return string;
function std_logic_to_bin_string(inp : std_logic) return string;
function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer)
return string;
function real_to_bin_string(inp : real; width, bin_pt, arith : integer)
return string;
type stdlogic_to_char_t is array(std_logic) of character;
constant to_char : stdlogic_to_char_t := (
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => '-');
-- synopsys translate_on
end conv_pkg;
package body conv_pkg is
function std_logic_vector_to_unsigned(inp : std_logic_vector)
return unsigned
is
begin
return unsigned (inp);
end;
function unsigned_to_std_logic_vector(inp : unsigned)
return std_logic_vector
is
begin
return std_logic_vector(inp);
end;
function std_logic_vector_to_signed(inp : std_logic_vector)
return signed
is
begin
return signed (inp);
end;
function signed_to_std_logic_vector(inp : signed)
return std_logic_vector
is
begin
return std_logic_vector(inp);
end;
function unsigned_to_signed (inp : unsigned)
return signed
is
begin
return signed(std_logic_vector(inp));
end;
function signed_to_unsigned (inp : signed)
return unsigned
is
begin
return unsigned(std_logic_vector(inp));
end;
function pos(inp : std_logic_vector; arith : INTEGER)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
if arith = xlUnsigned then
return true;
else
if vec(width-1) = '0' then
return true;
else
return false;
end if;
end if;
return true;
end;
function max_signed(width : INTEGER)
return std_logic_vector
is
variable ones : std_logic_vector(width-2 downto 0);
variable result : std_logic_vector(width-1 downto 0);
begin
ones := (others => '1');
result(width-1) := '0';
result(width-2 downto 0) := ones;
return result;
end;
function min_signed(width : INTEGER)
return std_logic_vector
is
variable zeros : std_logic_vector(width-2 downto 0);
variable result : std_logic_vector(width-1 downto 0);
begin
zeros := (others => '0');
result(width-1) := '1';
result(width-2 downto 0) := zeros;
return result;
end;
function and_reduce(inp: std_logic_vector) return std_logic
is
variable result: std_logic;
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := vec(0);
if width > 1 then
for i in 1 to width-1 loop
result := result and vec(i);
end loop;
end if;
return result;
end;
function all_same(inp: std_logic_vector) return boolean
is
variable result: boolean;
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := true;
if width > 0 then
for i in 1 to width-1 loop
if vec(i) /= vec(0) then
result := false;
end if;
end loop;
end if;
return result;
end;
function all_zeros(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable zero : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
zero := (others => '0');
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(zero)) then
result := true;
else
result := false;
end if;
return result;
end;
function is_point_five(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (width > 1) then
if ((vec(width-1) = '1') and (all_zeros(vec(width-2 downto 0)) = true)) then
result := true;
else
result := false;
end if;
else
if (vec(width-1) = '1') then
result := true;
else
result := false;
end if;
end if;
return result;
end;
function all_ones(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable one : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
one := (others => '1');
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(one)) then
result := true;
else
result := false;
end if;
return result;
end;
function full_precision_num_width(quantization, overflow, old_width,
old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return integer
is
variable result : integer;
begin
result := old_width + 2;
return result;
end;
function quantized_num_width(quantization, overflow, old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return integer
is
variable right_of_dp, left_of_dp, result : integer;
begin
right_of_dp := max(new_bin_pt, old_bin_pt);
left_of_dp := max((new_width - new_bin_pt), (old_width - old_bin_pt));
result := (old_width + 2) + (new_bin_pt - old_bin_pt);
return result;
end;
function convert_type (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith,
quantization, overflow : INTEGER)
return std_logic_vector
is
constant fp_width : integer :=
full_precision_num_width(quantization, overflow, old_width,
old_bin_pt, old_arith, new_width,
new_bin_pt, new_arith);
constant fp_bin_pt : integer := old_bin_pt;
constant fp_arith : integer := old_arith;
variable full_precision_result : std_logic_vector(fp_width-1 downto 0);
constant q_width : integer :=
quantized_num_width(quantization, overflow, old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith);
constant q_bin_pt : integer := new_bin_pt;
constant q_arith : integer := old_arith;
variable quantized_result : std_logic_vector(q_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
result := (others => '0');
full_precision_result := cast(inp, old_bin_pt, fp_width, fp_bin_pt,
fp_arith);
if (quantization = xlRound) then
quantized_result := round_towards_inf(full_precision_result,
fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt,
q_arith);
elsif (quantization = xlRoundBanker) then
quantized_result := round_towards_even(full_precision_result,
fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt,
q_arith);
else
quantized_result := trunc(full_precision_result, fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt, q_arith);
end if;
if (overflow = xlSaturate) then
result := saturation_arith(quantized_result, q_width, q_bin_pt,
q_arith, new_width, new_bin_pt, new_arith);
else
result := wrap_arith(quantized_result, q_width, q_bin_pt, q_arith,
new_width, new_bin_pt, new_arith);
end if;
return result;
end;
function cast (inp : std_logic_vector; old_bin_pt, new_width,
new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
constant left_of_dp : integer := (new_width - new_bin_pt)
- (old_width - old_bin_pt);
constant right_of_dp : integer := (new_bin_pt - old_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable j : integer;
begin
vec := inp;
for i in new_width-1 downto 0 loop
j := i - right_of_dp;
if ( j > old_width-1) then
if (new_arith = xlUnsigned) then
result(i) := '0';
else
result(i) := vec(old_width-1);
end if;
elsif ( j >= 0) then
result(i) := vec(j);
else
result(i) := '0';
end if;
end loop;
return result;
end;
function vec_slice (inp : std_logic_vector; upper, lower : INTEGER)
return std_logic_vector
is
begin
return inp(upper downto lower);
end;
function s2u_slice (inp : signed; upper, lower : INTEGER)
return unsigned
is
begin
return unsigned(vec_slice(std_logic_vector(inp), upper, lower));
end;
function u2u_slice (inp : unsigned; upper, lower : INTEGER)
return unsigned
is
begin
return unsigned(vec_slice(std_logic_vector(inp), upper, lower));
end;
function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER)
return signed
is
begin
return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned));
end;
function s2u_cast (inp : signed; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return unsigned
is
begin
return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned));
end;
function u2s_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return signed
is
begin
return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned));
end;
function u2u_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return unsigned
is
begin
return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned));
end;
function u2v_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return std_logic_vector
is
begin
return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned);
end;
function s2v_cast (inp : signed; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return std_logic_vector
is
begin
return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned);
end;
function boolean_to_signed (inp : boolean; width : integer)
return signed
is
variable result : signed(width - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function boolean_to_unsigned (inp : boolean; width : integer)
return unsigned
is
variable result : unsigned(width - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function boolean_to_vector (inp : boolean)
return std_logic_vector
is
variable result : std_logic_vector(1 - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function std_logic_to_vector (inp : std_logic)
return std_logic_vector
is
variable result : std_logic_vector(1 - 1 downto 0);
begin
result(0) := inp;
return result;
end;
function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
result := zero_ext(vec(old_width-1 downto right_of_dp), new_width);
else
result := sign_ext(vec(old_width-1 downto right_of_dp), new_width);
end if;
else
if new_arith = xlUnsigned then
result := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
result := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
return result;
end;
function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
constant expected_new_width : integer := old_width - right_of_dp + 1;
variable vec : std_logic_vector(old_width-1 downto 0);
variable one_or_zero : std_logic_vector(new_width-1 downto 0);
variable truncated_val : std_logic_vector(new_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
truncated_val := zero_ext(vec(old_width-1 downto right_of_dp),
new_width);
else
truncated_val := sign_ext(vec(old_width-1 downto right_of_dp),
new_width);
end if;
else
if new_arith = xlUnsigned then
truncated_val := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
truncated_val := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
one_or_zero := (others => '0');
if (new_arith = xlSigned) then
if (vec(old_width-1) = '0') then
one_or_zero(0) := '1';
end if;
if (right_of_dp >= 2) and (right_of_dp <= old_width) then
if (all_zeros(vec(right_of_dp-2 downto 0)) = false) then
one_or_zero(0) := '1';
end if;
end if;
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
if vec(right_of_dp-1) = '0' then
one_or_zero(0) := '0';
end if;
else
one_or_zero(0) := '0';
end if;
else
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
one_or_zero(0) := vec(right_of_dp-1);
end if;
end if;
if new_arith = xlSigned then
result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) +
std_logic_vector_to_signed(one_or_zero));
else
result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) +
std_logic_vector_to_unsigned(one_or_zero));
end if;
return result;
end;
function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
constant expected_new_width : integer := old_width - right_of_dp + 1;
variable vec : std_logic_vector(old_width-1 downto 0);
variable one_or_zero : std_logic_vector(new_width-1 downto 0);
variable truncated_val : std_logic_vector(new_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
truncated_val := zero_ext(vec(old_width-1 downto right_of_dp),
new_width);
else
truncated_val := sign_ext(vec(old_width-1 downto right_of_dp),
new_width);
end if;
else
if new_arith = xlUnsigned then
truncated_val := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
truncated_val := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
one_or_zero := (others => '0');
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
if (is_point_five(vec(right_of_dp-1 downto 0)) = false) then
one_or_zero(0) := vec(right_of_dp-1);
else
one_or_zero(0) := vec(right_of_dp);
end if;
end if;
if new_arith = xlSigned then
result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) +
std_logic_vector_to_signed(one_or_zero));
else
result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) +
std_logic_vector_to_unsigned(one_or_zero));
end if;
return result;
end;
function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant left_of_dp : integer := (old_width - old_bin_pt) -
(new_width - new_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable overflow : boolean;
begin
vec := inp;
overflow := true;
result := (others => '0');
if (new_width >= old_width) then
overflow := false;
end if;
if ((old_arith = xlSigned and new_arith = xlSigned) and (old_width > new_width)) then
if all_same(vec(old_width-1 downto new_width-1)) then
overflow := false;
end if;
end if;
if (old_arith = xlSigned and new_arith = xlUnsigned) then
if (old_width > new_width) then
if all_zeros(vec(old_width-1 downto new_width)) then
overflow := false;
end if;
else
if (old_width = new_width) then
if (vec(new_width-1) = '0') then
overflow := false;
end if;
end if;
end if;
end if;
if (old_arith = xlUnsigned and new_arith = xlUnsigned) then
if (old_width > new_width) then
if all_zeros(vec(old_width-1 downto new_width)) then
overflow := false;
end if;
else
if (old_width = new_width) then
overflow := false;
end if;
end if;
end if;
if ((old_arith = xlUnsigned and new_arith = xlSigned) and (old_width > new_width)) then
if all_same(vec(old_width-1 downto new_width-1)) then
overflow := false;
end if;
end if;
if overflow then
if new_arith = xlSigned then
if vec(old_width-1) = '0' then
result := max_signed(new_width);
else
result := min_signed(new_width);
end if;
else
if ((old_arith = xlSigned) and vec(old_width-1) = '1') then
result := (others => '0');
else
result := (others => '1');
end if;
end if;
else
if (old_arith = xlSigned) and (new_arith = xlUnsigned) then
if (vec(old_width-1) = '1') then
vec := (others => '0');
end if;
end if;
if new_width <= old_width then
result := vec(new_width-1 downto 0);
else
if new_arith = xlUnsigned then
result := zero_ext(vec, new_width);
else
result := sign_ext(vec, new_width);
end if;
end if;
end if;
return result;
end;
function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
variable result : std_logic_vector(new_width-1 downto 0);
variable result_arith : integer;
begin
if (old_arith = xlSigned) and (new_arith = xlUnsigned) then
result_arith := xlSigned;
end if;
result := cast(inp, old_bin_pt, new_width, new_bin_pt, result_arith);
return result;
end;
function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER is
begin
return max(a_bin_pt, b_bin_pt);
end;
function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER)
return INTEGER is
begin
return max(a_width - a_bin_pt, b_width - b_bin_pt);
end;
function pad_LSB(inp : std_logic_vector; new_width: integer)
return STD_LOGIC_VECTOR
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable pos : integer;
constant pad_pos : integer := new_width - orig_width - 1;
begin
vec := inp;
pos := new_width-1;
if (new_width >= orig_width) then
for i in orig_width-1 downto 0 loop
result(pos) := vec(i);
pos := pos - 1;
end loop;
if pad_pos >= 0 then
for i in pad_pos downto 0 loop
result(i) := '0';
end loop;
end if;
end if;
return result;
end;
function sign_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if new_width >= old_width then
result(old_width-1 downto 0) := vec;
if new_width-1 >= old_width then
for i in new_width-1 downto old_width loop
result(i) := vec(old_width-1);
end loop;
end if;
else
result(new_width-1 downto 0) := vec(new_width-1 downto 0);
end if;
return result;
end;
function zero_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if new_width >= old_width then
result(old_width-1 downto 0) := vec;
if new_width-1 >= old_width then
for i in new_width-1 downto old_width loop
result(i) := '0';
end loop;
end if;
else
result(new_width-1 downto 0) := vec(new_width-1 downto 0);
end if;
return result;
end;
function zero_ext(inp : std_logic; new_width : INTEGER)
return std_logic_vector
is
variable result : std_logic_vector(new_width-1 downto 0);
begin
result(0) := inp;
for i in new_width-1 downto 1 loop
result(i) := '0';
end loop;
return result;
end;
function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER)
return std_logic_vector
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if arith = xlUnsigned then
result := zero_ext(vec, new_width);
else
result := sign_ext(vec, new_width);
end if;
return result;
end;
function pad_LSB(inp : std_logic_vector; new_width, arith: integer)
return STD_LOGIC_VECTOR
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable pos : integer;
begin
vec := inp;
pos := new_width-1;
if (arith = xlUnsigned) then
result(pos) := '0';
pos := pos - 1;
else
result(pos) := vec(orig_width-1);
pos := pos - 1;
end if;
if (new_width >= orig_width) then
for i in orig_width-1 downto 0 loop
result(pos) := vec(i);
pos := pos - 1;
end loop;
if pos >= 0 then
for i in pos downto 0 loop
result(i) := '0';
end loop;
end if;
end if;
return result;
end;
function align_input(inp : std_logic_vector; old_width, delta, new_arith,
new_width: INTEGER)
return std_logic_vector
is
variable vec : std_logic_vector(old_width-1 downto 0);
variable padded_inp : std_logic_vector((old_width + delta)-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if delta > 0 then
padded_inp := pad_LSB(vec, old_width+delta);
result := extend_MSB(padded_inp, new_width, new_arith);
else
result := extend_MSB(vec, new_width, new_arith);
end if;
return result;
end;
function max(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
function "="(left,right: STRING) return boolean is
begin
if (left'length /= right'length) then
return false;
else
test : for i in 1 to left'length loop
if left(i) /= right(i) then
return false;
end if;
end loop test;
return true;
end if;
end;
-- synopsys translate_off
function is_binary_string_invalid (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 1 to vec'length loop
if ( vec(i) = 'X' ) then
result := true;
end if;
end loop;
return result;
end;
function is_binary_string_undefined (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 1 to vec'length loop
if ( vec(i) = 'U' ) then
result := true;
end if;
end loop;
return result;
end;
function is_XorU(inp : std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 0 to width-1 loop
if (vec(i) = 'U') or (vec(i) = 'X') then
result := true;
end if;
end loop;
return result;
end;
function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer)
return real
is
variable vec : std_logic_vector(inp'length-1 downto 0);
variable result, shift_val, undefined_real : real;
variable neg_num : boolean;
begin
vec := inp;
result := 0.0;
neg_num := false;
if vec(inp'length-1) = '1' then
neg_num := true;
end if;
for i in 0 to inp'length-1 loop
if vec(i) = 'U' or vec(i) = 'X' then
return undefined_real;
end if;
if arith = xlSigned then
if neg_num then
if vec(i) = '0' then
result := result + 2.0**i;
end if;
else
if vec(i) = '1' then
result := result + 2.0**i;
end if;
end if;
else
if vec(i) = '1' then
result := result + 2.0**i;
end if;
end if;
end loop;
if arith = xlSigned then
if neg_num then
result := result + 1.0;
result := result * (-1.0);
end if;
end if;
shift_val := 2.0**(-1*bin_pt);
result := result * shift_val;
return result;
end;
function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer)
return real
is
variable result : real := 0.0;
begin
if inp = '1' then
result := 1.0;
end if;
if arith = xlSigned then
assert false
report "It doesn't make sense to convert a 1 bit number to a signed real.";
end if;
return result;
end;
-- synopsys translate_on
function integer_to_std_logic_vector (inp : integer; width, arith : integer)
return std_logic_vector
is
variable result : std_logic_vector(width-1 downto 0);
variable unsigned_val : unsigned(width-1 downto 0);
variable signed_val : signed(width-1 downto 0);
begin
if (arith = xlSigned) then
signed_val := to_signed(inp, width);
result := signed_to_std_logic_vector(signed_val);
else
unsigned_val := to_unsigned(inp, width);
result := unsigned_to_std_logic_vector(unsigned_val);
end if;
return result;
end;
function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer)
return integer
is
constant width : integer := inp'length;
variable unsigned_val : unsigned(width-1 downto 0);
variable signed_val : signed(width-1 downto 0);
variable result : integer;
begin
if (arith = xlSigned) then
signed_val := std_logic_vector_to_signed(inp);
result := to_integer(signed_val);
else
unsigned_val := std_logic_vector_to_unsigned(inp);
result := to_integer(unsigned_val);
end if;
return result;
end;
function std_logic_to_integer(constant inp : std_logic := '0')
return integer
is
begin
if inp = '1' then
return 1;
else
return 0;
end if;
end;
function makeZeroBinStr (width : integer) return STRING is
variable result : string(1 to width+3);
begin
result(1) := '0';
result(2) := 'b';
for i in 3 to width+2 loop
result(i) := '0';
end loop;
result(width+3) := '.';
return result;
end;
-- synopsys translate_off
function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer)
return std_logic_vector
is
variable result : std_logic_vector(width-1 downto 0);
begin
result := (others => '0');
return result;
end;
function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer)
return std_logic_vector
is
variable real_val : real;
variable int_val : integer;
variable result : std_logic_vector(width-1 downto 0) := (others => '0');
variable unsigned_val : unsigned(width-1 downto 0) := (others => '0');
variable signed_val : signed(width-1 downto 0) := (others => '0');
begin
real_val := inp;
int_val := integer(real_val * 2.0**(bin_pt));
if (arith = xlSigned) then
signed_val := to_signed(int_val, width);
result := signed_to_std_logic_vector(signed_val);
else
unsigned_val := to_unsigned(int_val, width);
result := unsigned_to_std_logic_vector(unsigned_val);
end if;
return result;
end;
-- synopsys translate_on
function valid_bin_string (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
begin
vec := inp;
if (vec(1) = '0' and vec(2) = 'b') then
return true;
else
return false;
end if;
end;
function hex_string_to_std_logic_vector(inp: string; width : integer)
return std_logic_vector is
constant strlen : integer := inp'LENGTH;
variable result : std_logic_vector(width-1 downto 0);
variable bitval : std_logic_vector((strlen*4)-1 downto 0);
variable posn : integer;
variable ch : character;
variable vec : string(1 to strlen);
begin
vec := inp;
result := (others => '0');
posn := (strlen*4)-1;
for i in 1 to strlen loop
ch := vec(i);
case ch is
when '0' => bitval(posn downto posn-3) := "0000";
when '1' => bitval(posn downto posn-3) := "0001";
when '2' => bitval(posn downto posn-3) := "0010";
when '3' => bitval(posn downto posn-3) := "0011";
when '4' => bitval(posn downto posn-3) := "0100";
when '5' => bitval(posn downto posn-3) := "0101";
when '6' => bitval(posn downto posn-3) := "0110";
when '7' => bitval(posn downto posn-3) := "0111";
when '8' => bitval(posn downto posn-3) := "1000";
when '9' => bitval(posn downto posn-3) := "1001";
when 'A' | 'a' => bitval(posn downto posn-3) := "1010";
when 'B' | 'b' => bitval(posn downto posn-3) := "1011";
when 'C' | 'c' => bitval(posn downto posn-3) := "1100";
when 'D' | 'd' => bitval(posn downto posn-3) := "1101";
when 'E' | 'e' => bitval(posn downto posn-3) := "1110";
when 'F' | 'f' => bitval(posn downto posn-3) := "1111";
when others => bitval(posn downto posn-3) := "XXXX";
-- synopsys translate_off
ASSERT false
REPORT "Invalid hex value" SEVERITY ERROR;
-- synopsys translate_on
end case;
posn := posn - 4;
end loop;
if (width <= strlen*4) then
result := bitval(width-1 downto 0);
else
result((strlen*4)-1 downto 0) := bitval;
end if;
return result;
end;
function bin_string_to_std_logic_vector (inp : string)
return std_logic_vector
is
variable pos : integer;
variable vec : string(1 to inp'length);
variable result : std_logic_vector(inp'length-1 downto 0);
begin
vec := inp;
pos := inp'length-1;
result := (others => '0');
for i in 1 to vec'length loop
-- synopsys translate_off
if (pos < 0) and (vec(i) = '0' or vec(i) = '1' or vec(i) = 'X' or vec(i) = 'U') then
assert false
report "Input string is larger than output std_logic_vector. Truncating output.";
return result;
end if;
-- synopsys translate_on
if vec(i) = '0' then
result(pos) := '0';
pos := pos - 1;
end if;
if vec(i) = '1' then
result(pos) := '1';
pos := pos - 1;
end if;
-- synopsys translate_off
if (vec(i) = 'X' or vec(i) = 'U') then
result(pos) := 'U';
pos := pos - 1;
end if;
-- synopsys translate_on
end loop;
return result;
end;
function bin_string_element_to_std_logic_vector (inp : string; width, index : integer)
return std_logic_vector
is
constant str_width : integer := width + 4;
constant inp_len : integer := inp'length;
constant num_elements : integer := (inp_len + 1)/str_width;
constant reverse_index : integer := (num_elements-1) - index;
variable left_pos : integer;
variable right_pos : integer;
variable vec : string(1 to inp'length);
variable result : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := (others => '0');
if (reverse_index = 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then
left_pos := 1;
right_pos := width + 3;
result := bin_string_to_std_logic_vector(vec(left_pos to right_pos));
end if;
if (reverse_index > 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then
left_pos := (reverse_index * str_width) + 1;
right_pos := left_pos + width + 2;
result := bin_string_to_std_logic_vector(vec(left_pos to right_pos));
end if;
return result;
end;
-- synopsys translate_off
function std_logic_vector_to_bin_string(inp : std_logic_vector)
return string
is
variable vec : std_logic_vector(1 to inp'length);
variable result : string(vec'range);
begin
vec := inp;
for i in vec'range loop
result(i) := to_char(vec(i));
end loop;
return result;
end;
function std_logic_to_bin_string(inp : std_logic)
return string
is
variable result : string(1 to 3);
begin
result(1) := '0';
result(2) := 'b';
result(3) := to_char(inp);
return result;
end;
function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer)
return string
is
variable width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable str_pos : integer;
variable result : string(1 to width+3);
begin
vec := inp;
str_pos := 1;
result(str_pos) := '0';
str_pos := 2;
result(str_pos) := 'b';
str_pos := 3;
for i in width-1 downto 0 loop
if (((width+3) - bin_pt) = str_pos) then
result(str_pos) := '.';
str_pos := str_pos + 1;
end if;
result(str_pos) := to_char(vec(i));
str_pos := str_pos + 1;
end loop;
if (bin_pt = 0) then
result(str_pos) := '.';
end if;
return result;
end;
function real_to_bin_string(inp : real; width, bin_pt, arith : integer)
return string
is
variable result : string(1 to width);
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := real_to_std_logic_vector(inp, width, bin_pt, arith);
result := std_logic_vector_to_bin_string(vec);
return result;
end;
function real_to_string (inp : real) return string
is
variable result : string(1 to display_precision) := (others => ' ');
begin
result(real'image(inp)'range) := real'image(inp);
return result;
end;
-- synopsys translate_on
end conv_pkg;
library IEEE;
use IEEE.std_logic_1164.all;
package clock_pkg is
-- synopsys translate_off
signal int_clk : std_logic;
-- synopsys translate_on
end clock_pkg;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity srl17e is
generic (width : integer:=16;
latency : integer :=8);
port (clk : in std_logic;
ce : in std_logic;
d : in std_logic_vector(width-1 downto 0);
q : out std_logic_vector(width-1 downto 0));
end srl17e;
architecture structural of srl17e is
component SRL16E
port (D : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
attribute syn_black_box of SRL16E : component is true;
attribute fpga_dont_touch of SRL16E : component is "true";
component FDE
port(
Q : out STD_ULOGIC;
D : in STD_ULOGIC;
C : in STD_ULOGIC;
CE : in STD_ULOGIC);
end component;
attribute syn_black_box of FDE : component is true;
attribute fpga_dont_touch of FDE : component is "true";
constant a : std_logic_vector(4 downto 0) :=
integer_to_std_logic_vector(latency-2,5,xlSigned);
signal d_delayed : std_logic_vector(width-1 downto 0);
signal srl16_out : std_logic_vector(width-1 downto 0);
begin
d_delayed <= d after 200 ps;
reg_array : for i in 0 to width-1 generate
srl16_used: if latency > 1 generate
u1 : srl16e port map(clk => clk,
d => d_delayed(i),
q => srl16_out(i),
ce => ce,
a0 => a(0),
a1 => a(1),
a2 => a(2),
a3 => a(3));
end generate;
srl16_not_used: if latency <= 1 generate
srl16_out(i) <= d_delayed(i);
end generate;
fde_used: if latency /= 0 generate
u2 : fde port map(c => clk,
d => srl16_out(i),
q => q(i),
ce => ce);
end generate;
fde_not_used: if latency = 0 generate
q(i) <= srl16_out(i);
end generate;
end generate;
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg is
generic (width : integer := 8;
latency : integer := 1);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end synth_reg;
architecture structural of synth_reg is
component srl17e
generic (width : integer:=16;
latency : integer :=8);
port (clk : in std_logic;
ce : in std_logic;
d : in std_logic_vector(width-1 downto 0);
q : out std_logic_vector(width-1 downto 0));
end component;
function calc_num_srl17es (latency : integer)
return integer
is
variable remaining_latency : integer;
variable result : integer;
begin
result := latency / 17;
remaining_latency := latency - (result * 17);
if (remaining_latency /= 0) then
result := result + 1;
end if;
return result;
end;
constant complete_num_srl17es : integer := latency / 17;
constant num_srl17es : integer := calc_num_srl17es(latency);
constant remaining_latency : integer := latency - (complete_num_srl17es * 17);
type register_array is array (num_srl17es downto 0) of
std_logic_vector(width-1 downto 0);
signal z : register_array;
begin
z(0) <= i;
complete_ones : if complete_num_srl17es > 0 generate
srl17e_array: for i in 0 to complete_num_srl17es-1 generate
delay_comp : srl17e
generic map (width => width,
latency => 17)
port map (clk => clk,
ce => ce,
d => z(i),
q => z(i+1));
end generate;
end generate;
partial_one : if remaining_latency > 0 generate
last_srl17e : srl17e
generic map (width => width,
latency => remaining_latency)
port map (clk => clk,
ce => ce,
d => z(num_srl17es-1),
q => z(num_srl17es));
end generate;
o <= z(num_srl17es);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg_reg is
generic (width : integer := 8;
latency : integer := 1);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end synth_reg_reg;
architecture behav of synth_reg_reg is
type reg_array_type is array (latency-1 downto 0) of std_logic_vector(width -1 downto 0);
signal reg_bank : reg_array_type := (others => (others => '0'));
signal reg_bank_in : reg_array_type := (others => (others => '0'));
attribute syn_allow_retiming : boolean;
attribute syn_srlstyle : string;
attribute syn_allow_retiming of reg_bank : signal is true;
attribute syn_allow_retiming of reg_bank_in : signal is true;
attribute syn_srlstyle of reg_bank : signal is "registers";
attribute syn_srlstyle of reg_bank_in : signal is "registers";
begin
latency_eq_0: if latency = 0 generate
o <= i;
end generate latency_eq_0;
latency_gt_0: if latency >= 1 generate
o <= reg_bank(latency-1);
reg_bank_in(0) <= i;
loop_gen: for idx in latency-2 downto 0 generate
reg_bank_in(idx+1) <= reg_bank(idx);
end generate loop_gen;
sync_loop: for sync_idx in latency-1 downto 0 generate
sync_proc: process (clk)
begin
if clk'event and clk = '1' then
if ce = '1' then
reg_bank(sync_idx) <= reg_bank_in(sync_idx);
end if;
end if;
end process sync_proc;
end generate sync_loop;
end generate latency_gt_0;
end behav;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity single_reg_w_init is
generic (
width: integer := 8;
init_index: integer := 0;
init_value: bit_vector := b"0000"
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end single_reg_w_init;
architecture structural of single_reg_w_init is
function build_init_const(width: integer;
init_index: integer;
init_value: bit_vector)
return std_logic_vector
is
variable result: std_logic_vector(width - 1 downto 0);
begin
if init_index = 0 then
result := (others => '0');
elsif init_index = 1 then
result := (others => '0');
result(0) := '1';
else
result := to_stdlogicvector(init_value);
end if;
return result;
end;
component fdre
port (
q: out std_ulogic;
d: in std_ulogic;
c: in std_ulogic;
ce: in std_ulogic;
r: in std_ulogic
);
end component;
attribute syn_black_box of fdre: component is true;
attribute fpga_dont_touch of fdre: component is "true";
component fdse
port (
q: out std_ulogic;
d: in std_ulogic;
c: in std_ulogic;
ce: in std_ulogic;
s: in std_ulogic
);
end component;
attribute syn_black_box of fdse: component is true;
attribute fpga_dont_touch of fdse: component is "true";
constant init_const: std_logic_vector(width - 1 downto 0)
:= build_init_const(width, init_index, init_value);
begin
fd_prim_array: for index in 0 to width - 1 generate
bit_is_0: if (init_const(index) = '0') generate
fdre_comp: fdre
port map (
c => clk,
d => i(index),
q => o(index),
ce => ce,
r => clr
);
end generate;
bit_is_1: if (init_const(index) = '1') generate
fdse_comp: fdse
port map (
c => clk,
d => i(index),
q => o(index),
ce => ce,
s => clr
);
end generate;
end generate;
end architecture structural;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg_w_init is
generic (
width: integer := 8;
init_index: integer := 0;
init_value: bit_vector := b"0000";
latency: integer := 1
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end synth_reg_w_init;
architecture structural of synth_reg_w_init is
component single_reg_w_init
generic (
width: integer := 8;
init_index: integer := 0;
init_value: bit_vector := b"0000"
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
signal dly_i: std_logic_vector((latency + 1) * width - 1 downto 0);
signal dly_clr: std_logic;
begin
latency_eq_0: if (latency = 0) generate
o <= i;
end generate;
latency_gt_0: if (latency >= 1) generate
dly_i((latency + 1) * width - 1 downto latency * width) <= i
after 200 ps;
dly_clr <= clr after 200 ps;
fd_array: for index in latency downto 1 generate
reg_comp: single_reg_w_init
generic map (
width => width,
init_index => init_index,
init_value => init_value
)
port map (
clk => clk,
i => dly_i((index + 1) * width - 1 downto index * width),
o => dly_i(index * width - 1 downto (index - 1) * width),
ce => ce,
clr => dly_clr
);
end generate;
o <= dly_i(width - 1 downto 0);
end generate;
end structural;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity convert_func_call is
generic (
din_width : integer := 16;
din_bin_pt : integer := 4;
din_arith : integer := xlUnsigned;
dout_width : integer := 8;
dout_bin_pt : integer := 2;
dout_arith : integer := xlUnsigned;
quantization : integer := xlTruncate;
overflow : integer := xlWrap);
port (
din : in std_logic_vector (din_width-1 downto 0);
result : out std_logic_vector (dout_width-1 downto 0));
end convert_func_call;
architecture behavior of convert_func_call is
begin
result <= convert_type(din, din_width, din_bin_pt, din_arith,
dout_width, dout_bin_pt, dout_arith,
quantization, overflow);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xlconvert is
generic (
din_width : integer := 16;
din_bin_pt : integer := 4;
din_arith : integer := xlUnsigned;
dout_width : integer := 8;
dout_bin_pt : integer := 2;
dout_arith : integer := xlUnsigned;
bool_conversion : integer :=0;
latency : integer := 0;
quantization : integer := xlTruncate;
overflow : integer := xlWrap);
port (
din : in std_logic_vector (din_width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
dout : out std_logic_vector (dout_width-1 downto 0));
end xlconvert;
architecture behavior of xlconvert is
component synth_reg
generic (width : integer;
latency : integer);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end component;
component convert_func_call
generic (
din_width : integer := 16;
din_bin_pt : integer := 4;
din_arith : integer := xlUnsigned;
dout_width : integer := 8;
dout_bin_pt : integer := 2;
dout_arith : integer := xlUnsigned;
quantization : integer := xlTruncate;
overflow : integer := xlWrap);
port (
din : in std_logic_vector (din_width-1 downto 0);
result : out std_logic_vector (dout_width-1 downto 0));
end component;
-- synopsys translate_off
signal real_din, real_dout : real;
-- synopsys translate_on
signal result : std_logic_vector(dout_width-1 downto 0);
begin
-- synopsys translate_off
-- synopsys translate_on
bool_conversion_generate : if (bool_conversion = 1)
generate
result <= din;
end generate;
std_conversion_generate : if (bool_conversion = 0)
generate
convert : convert_func_call
generic map (
din_width => din_width,
din_bin_pt => din_bin_pt,
din_arith => din_arith,
dout_width => dout_width,
dout_bin_pt => dout_bin_pt,
dout_arith => dout_arith,
quantization => quantization,
overflow => overflow)
port map (
din => din,
result => result);
end generate;
latency_test : if (latency > 0)
generate
reg : synth_reg
generic map ( width => dout_width,
latency => latency)
port map (i => result,
ce => ce,
clr => clr,
clk => clk,
o => dout);
end generate;
latency0 : if (latency = 0)
generate
dout <= result;
end generate latency0;
end behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library XilinxCoreLib;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xlcounter_free is
generic (
core_name0: string := "";
op_width: integer := 5;
op_arith: integer := xlSigned
);
port (
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
op: out std_logic_vector(op_width - 1 downto 0);
up: in std_logic_vector(0 downto 0) := (others => '0');
load: in std_logic_vector(0 downto 0) := (others => '0');
din: in std_logic_vector(op_width - 1 downto 0) := (others => '0');
en: in std_logic_vector(0 downto 0);
rst: in std_logic_vector(0 downto 0)
);
end xlcounter_free ;
architecture behavior of xlcounter_free is
component binary_counter_virtex2p_7_0_950e4ab582797264
port (
clk: in std_logic;
ce: in std_logic;
sinit: in std_logic;
q: out std_logic_vector(op_width - 1 downto 0)
);
end component;
attribute syn_black_box of binary_counter_virtex2p_7_0_950e4ab582797264:
component is true;
attribute fpga_dont_touch of binary_counter_virtex2p_7_0_950e4ab582797264:
component is "true";
attribute box_type of binary_counter_virtex2p_7_0_950e4ab582797264:
component is "black_box";
component binary_counter_virtex2p_7_0_b0a257f5389d649a
port (
clk: in std_logic;
ce: in std_logic;
sinit: in std_logic;
q: out std_logic_vector(op_width - 1 downto 0)
);
end component;
attribute syn_black_box of binary_counter_virtex2p_7_0_b0a257f5389d649a:
component is true;
attribute fpga_dont_touch of binary_counter_virtex2p_7_0_b0a257f5389d649a:
component is "true";
attribute box_type of binary_counter_virtex2p_7_0_b0a257f5389d649a:
component is "black_box";
component binary_counter_virtex2p_7_0_b511f9871581ee23
port (
clk: in std_logic;
ce: in std_logic;
sinit: in std_logic;
load: in std_logic;
l: in std_logic_vector(op_width - 1 downto 0);
q: out std_logic_vector(op_width - 1 downto 0)
);
end component;
attribute syn_black_box of binary_counter_virtex2p_7_0_b511f9871581ee23:
component is true;
attribute fpga_dont_touch of binary_counter_virtex2p_7_0_b511f9871581ee23:
component is "true";
attribute box_type of binary_counter_virtex2p_7_0_b511f9871581ee23:
component is "black_box";
component binary_counter_virtex2p_7_0_a22528b4c55dc1cd
port (
clk: in std_logic;
ce: in std_logic;
sinit: in std_logic;
q: out std_logic_vector(op_width - 1 downto 0)
);
end component;
attribute syn_black_box of binary_counter_virtex2p_7_0_a22528b4c55dc1cd:
component is true;
attribute fpga_dont_touch of binary_counter_virtex2p_7_0_a22528b4c55dc1cd:
component is "true";
attribute box_type of binary_counter_virtex2p_7_0_a22528b4c55dc1cd:
component is "black_box";
component binary_counter_virtex2p_7_0_77cea312f82499f0
port (
clk: in std_logic;
ce: in std_logic;
sinit: in std_logic;
load: in std_logic;
l: in std_logic_vector(op_width - 1 downto 0);
q: out std_logic_vector(op_width - 1 downto 0)
);
end component;
attribute syn_black_box of binary_counter_virtex2p_7_0_77cea312f82499f0:
component is true;
attribute fpga_dont_touch of binary_counter_virtex2p_7_0_77cea312f82499f0:
component is "true";
attribute box_type of binary_counter_virtex2p_7_0_77cea312f82499f0:
component is "black_box";
-- synopsys translate_off
constant zeroVec: std_logic_vector(op_width - 1 downto 0) := (others => '0');
constant oneVec: std_logic_vector(op_width - 1 downto 0) := (others => '1');
constant zeroStr: string(1 to op_width) :=
std_logic_vector_to_bin_string(zeroVec);
constant oneStr: string(1 to op_width) :=
std_logic_vector_to_bin_string(oneVec);
-- synopsys translate_on
signal core_sinit: std_logic;
signal core_ce: std_logic;
signal op_net: std_logic_vector(op_width - 1 downto 0);
begin
core_ce <= ce and en(0);
core_sinit <= (clr or rst(0)) and ce;
op <= op_net;
comp0: if ((core_name0 = "binary_counter_virtex2p_7_0_950e4ab582797264")) generate
core_instance0: binary_counter_virtex2p_7_0_950e4ab582797264
port map (
clk => clk,
ce => core_ce,
sinit => core_sinit,
q => op_net
);
end generate;
comp1: if ((core_name0 = "binary_counter_virtex2p_7_0_b0a257f5389d649a")) generate
core_instance1: binary_counter_virtex2p_7_0_b0a257f5389d649a
port map (
clk => clk,
ce => core_ce,
sinit => core_sinit,
q => op_net
);
end generate;
comp2: if ((core_name0 = "binary_counter_virtex2p_7_0_b511f9871581ee23")) generate
core_instance2: binary_counter_virtex2p_7_0_b511f9871581ee23
port map (
clk => clk,
ce => core_ce,
sinit => core_sinit,
load => load(0),
l => din,
q => op_net
);
end generate;
comp3: if ((core_name0 = "binary_counter_virtex2p_7_0_a22528b4c55dc1cd")) generate
core_instance3: binary_counter_virtex2p_7_0_a22528b4c55dc1cd
port map (
clk => clk,
ce => core_ce,
sinit => core_sinit,
q => op_net
);
end generate;
comp4: if ((core_name0 = "binary_counter_virtex2p_7_0_77cea312f82499f0")) generate
core_instance4: binary_counter_virtex2p_7_0_77cea312f82499f0
port map (
clk => clk,
ce => core_ce,
sinit => core_sinit,
load => load(0),
l => din,
q => op_net
);
end generate;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity inverter_e2b989a05e is
port (
ip : in std_logic_vector((1 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end inverter_e2b989a05e;
architecture behavior of inverter_e2b989a05e is
signal ip_1_26: unsigned((1 - 1) downto 0);
type array_type_op_mem_22_20 is array (0 to (1 - 1)) of unsigned((1 - 1) downto 0);
signal op_mem_22_20: array_type_op_mem_22_20 := (
0 => "0");
signal op_mem_22_20_front_din: unsigned((1 - 1) downto 0);
signal op_mem_22_20_back: unsigned((1 - 1) downto 0);
signal op_mem_22_20_push_front_pop_back_en: std_logic;
signal internal_ip_12_1_bitnot: unsigned((1 - 1) downto 0);
begin
ip_1_26 <= std_logic_vector_to_unsigned(ip);
op_mem_22_20_back <= op_mem_22_20(0);
proc_op_mem_22_20: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_22_20_push_front_pop_back_en = '1')) then
op_mem_22_20(0) <= op_mem_22_20_front_din;
end if;
end if;
end process proc_op_mem_22_20;
internal_ip_12_1_bitnot <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(ip_1_26));
op_mem_22_20_push_front_pop_back_en <= '0';
op <= unsigned_to_std_logic_vector(internal_ip_12_1_bitnot);
end behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library XilinxCoreLib;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.conv_pkg.all;
entity xlmult_v9_0 is
generic (
core_name0: string := "";
a_width: integer := 4;
a_bin_pt: integer := 2;
a_arith: integer := xlSigned;
b_width: integer := 4;
b_bin_pt: integer := 1;
b_arith: integer := xlSigned;
p_width: integer := 8;
p_bin_pt: integer := 2;
p_arith: integer := xlSigned;
rst_width: integer := 1;
rst_bin_pt: integer := 0;
rst_arith: integer := xlUnsigned;
en_width: integer := 1;
en_bin_pt: integer := 0;
en_arith: integer := xlUnsigned;
quantization: integer := xlTruncate;
overflow: integer := xlWrap;
extra_registers: integer := 0;
c_a_width: integer := 7;
c_b_width: integer := 7;
c_type: integer := 0;
c_a_type: integer := 0;
c_b_type: integer := 0;
c_pipelined: integer := 1;
c_baat: integer := 4;
multsign: integer := xlSigned;
c_output_width: integer := 16
);
port (
a: in std_logic_vector(a_width - 1 downto 0);
b: in std_logic_vector(b_width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
core_ce: in std_logic := '0';
core_clr: in std_logic := '0';
core_clk: in std_logic := '0';
rst: in std_logic_vector(rst_width - 1 downto 0);
en: in std_logic_vector(en_width - 1 downto 0);
p: out std_logic_vector(p_width - 1 downto 0)
);
end xlmult_v9_0 ;
architecture behavior of xlmult_v9_0 is
component synth_reg
generic (
width: integer := 16;
latency: integer := 5
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
component multiplier_virtex2p_10_1_817edd563258bb47
port (
b: in std_logic_vector(c_b_width - 1 downto 0);
p: out std_logic_vector(c_output_width - 1 downto 0);
clk: in std_logic;
ce: in std_logic;
sclr: in std_logic;
a: in std_logic_vector(c_a_width - 1 downto 0)
);
end component;
attribute syn_black_box of multiplier_virtex2p_10_1_817edd563258bb47:
component is true;
attribute fpga_dont_touch of multiplier_virtex2p_10_1_817edd563258bb47:
component is "true";
attribute box_type of multiplier_virtex2p_10_1_817edd563258bb47:
component is "black_box";
signal tmp_a: std_logic_vector(c_a_width - 1 downto 0);
signal conv_a: std_logic_vector(c_a_width - 1 downto 0);
signal tmp_b: std_logic_vector(c_b_width - 1 downto 0);
signal conv_b: std_logic_vector(c_b_width - 1 downto 0);
signal tmp_p: std_logic_vector(c_output_width - 1 downto 0);
signal conv_p: std_logic_vector(p_width - 1 downto 0);
-- synopsys translate_off
signal real_a, real_b, real_p: real;
-- synopsys translate_on
signal rfd: std_logic;
signal rdy: std_logic;
signal nd: std_logic;
signal internal_ce: std_logic;
signal internal_clr: std_logic;
signal internal_core_ce: std_logic;
begin
-- synopsys translate_off
-- synopsys translate_on
internal_ce <= ce and en(0);
internal_core_ce <= core_ce and en(0);
internal_clr <= (clr or rst(0)) and ce;
nd <= internal_ce;
input_process: process (a,b)
begin
tmp_a <= zero_ext(a, c_a_width);
tmp_b <= zero_ext(b, c_b_width);
end process;
output_process: process (tmp_p)
begin
conv_p <= convert_type(tmp_p, c_output_width, a_bin_pt+b_bin_pt, multsign,
p_width, p_bin_pt, p_arith, quantization, overflow);
end process;
comp0: if ((core_name0 = "multiplier_virtex2p_10_1_817edd563258bb47")) generate
core_instance0: multiplier_virtex2p_10_1_817edd563258bb47
port map (
a => tmp_a,
clk => clk,
ce => internal_ce,
sclr => internal_clr,
p => tmp_p,
b => tmp_b
);
end generate;
latency_gt_0: if (extra_registers > 0) generate
reg: synth_reg
generic map (
width => p_width,
latency => extra_registers
)
port map (
i => conv_p,
ce => internal_ce,
clr => internal_clr,
clk => clk,
o => p
);
end generate;
latency_eq_0: if (extra_registers = 0) generate
p <= conv_p;
end generate;
end architecture behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xlregister is
generic (d_width : integer := 5;
init_value : bit_vector := b"00");
port (d : in std_logic_vector (d_width-1 downto 0);
rst : in std_logic_vector(0 downto 0) := "0";
en : in std_logic_vector(0 downto 0) := "1";
ce : in std_logic;
clk : in std_logic;
q : out std_logic_vector (d_width-1 downto 0));
end xlregister;
architecture behavior of xlregister is
component synth_reg_w_init
generic (width : integer;
init_index : integer;
init_value : bit_vector;
latency : integer);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end component;
-- synopsys translate_off
signal real_d, real_q : real;
-- synopsys translate_on
signal internal_clr : std_logic;
signal internal_ce : std_logic;
begin
internal_clr <= rst(0) and ce;
internal_ce <= en(0) and ce;
synth_reg_inst : synth_reg_w_init
generic map (width => d_width,
init_index => 2,
init_value => init_value,
latency => 1)
port map (i => d,
ce => internal_ce,
clr => internal_clr,
clk => clk,
o => q);
end architecture behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity relational_4e76b03051 is
port (
a : in std_logic_vector((18 - 1) downto 0);
b : in std_logic_vector((18 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end relational_4e76b03051;
architecture behavior of relational_4e76b03051 is
signal a_1_31: unsigned((18 - 1) downto 0);
signal b_1_34: unsigned((18 - 1) downto 0);
type array_type_op_mem_32_22 is array (0 to (1 - 1)) of boolean;
signal op_mem_32_22: array_type_op_mem_32_22 := (
0 => false);
signal op_mem_32_22_front_din: boolean;
signal op_mem_32_22_back: boolean;
signal op_mem_32_22_push_front_pop_back_en: std_logic;
signal result_12_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_unsigned(a);
b_1_34 <= std_logic_vector_to_unsigned(b);
op_mem_32_22_back <= op_mem_32_22(0);
proc_op_mem_32_22: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_32_22_push_front_pop_back_en = '1')) then
op_mem_32_22(0) <= op_mem_32_22_front_din;
end if;
end if;
end process proc_op_mem_32_22;
result_12_3_rel <= a_1_31 = b_1_34;
op_mem_32_22_front_din <= result_12_3_rel;
op_mem_32_22_push_front_pop_back_en <= '1';
op <= boolean_to_vector(op_mem_32_22_back);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity relational_1433264a0c is
port (
a : in std_logic_vector((18 - 1) downto 0);
b : in std_logic_vector((18 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end relational_1433264a0c;
architecture behavior of relational_1433264a0c is
signal a_1_31: unsigned((18 - 1) downto 0);
signal b_1_34: unsigned((18 - 1) downto 0);
type array_type_op_mem_32_22 is array (0 to (1 - 1)) of boolean;
signal op_mem_32_22: array_type_op_mem_32_22 := (
0 => false);
signal op_mem_32_22_front_din: boolean;
signal op_mem_32_22_back: boolean;
signal op_mem_32_22_push_front_pop_back_en: std_logic;
signal result_22_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_unsigned(a);
b_1_34 <= std_logic_vector_to_unsigned(b);
op_mem_32_22_back <= op_mem_32_22(0);
proc_op_mem_32_22: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_32_22_push_front_pop_back_en = '1')) then
op_mem_32_22(0) <= op_mem_32_22_front_din;
end if;
end if;
end process proc_op_mem_32_22;
result_22_3_rel <= a_1_31 >= b_1_34;
op_mem_32_22_front_din <= result_22_3_rel;
op_mem_32_22_push_front_pop_back_en <= '1';
op <= boolean_to_vector(op_mem_32_22_back);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_963ed6358a is
port (
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_963ed6358a;
architecture behavior of constant_963ed6358a is
begin
op <= "0";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mcode_block_8231ed31e4 is
port (
plbrst : in std_logic_vector((1 - 1) downto 0);
plbabus : in std_logic_vector((32 - 1) downto 0);
plbpavalid : in std_logic_vector((1 - 1) downto 0);
plbrnw : in std_logic_vector((1 - 1) downto 0);
plbwrdbus : in std_logic_vector((32 - 1) downto 0);
rddata : in std_logic_vector((32 - 1) downto 0);
addrpref : in std_logic_vector((15 - 1) downto 0);
wrdbusreg : out std_logic_vector((32 - 1) downto 0);
addrack : out std_logic_vector((1 - 1) downto 0);
rdcomp : out std_logic_vector((1 - 1) downto 0);
wrdack : out std_logic_vector((1 - 1) downto 0);
bankaddr : out std_logic_vector((2 - 1) downto 0);
rnwreg : out std_logic_vector((1 - 1) downto 0);
rddack : out std_logic_vector((1 - 1) downto 0);
rddbus : out std_logic_vector((32 - 1) downto 0);
linearaddr : out std_logic_vector((13 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mcode_block_8231ed31e4;
architecture behavior of mcode_block_8231ed31e4 is
signal plbrst_2_20: unsigned((1 - 1) downto 0);
signal plbabus_2_28: unsigned((32 - 1) downto 0);
signal plbpavalid_2_37: unsigned((1 - 1) downto 0);
signal plbrnw_2_49: unsigned((1 - 1) downto 0);
signal plbwrdbus_2_57: unsigned((32 - 1) downto 0);
signal rddata_2_68: unsigned((32 - 1) downto 0);
signal addrpref_2_76: unsigned((15 - 1) downto 0);
signal plbrstreg_13_24_next: boolean;
signal plbrstreg_13_24: boolean := false;
signal plbabusreg_14_25_next: unsigned((32 - 1) downto 0);
signal plbabusreg_14_25: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal plbpavalidreg_15_28_next: boolean;
signal plbpavalidreg_15_28: boolean := false;
signal plbrnwreg_16_24_next: unsigned((1 - 1) downto 0);
signal plbrnwreg_16_24: unsigned((1 - 1) downto 0) := "0";
signal plbwrdbusreg_17_27_next: unsigned((32 - 1) downto 0);
signal plbwrdbusreg_17_27: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal avalidreg_29_23_next: boolean;
signal avalidreg_29_23: boolean := false;
signal ps1reg_40_20_next: boolean;
signal ps1reg_40_20: boolean := false;
signal psreg_48_19_next: boolean;
signal psreg_48_19: boolean := false;
type array_type_rdcompdelay_59_25 is array (0 to (3 - 1)) of unsigned((1 - 1) downto 0);
signal rdcompdelay_59_25: array_type_rdcompdelay_59_25 := (
"0",
"0",
"0");
signal rdcompdelay_59_25_front_din: unsigned((1 - 1) downto 0);
signal rdcompdelay_59_25_back: unsigned((1 - 1) downto 0);
signal rdcompdelay_59_25_push_front_pop_back_en: std_logic;
signal rdcompreg_63_23_next: unsigned((1 - 1) downto 0);
signal rdcompreg_63_23: unsigned((1 - 1) downto 0) := "0";
signal rddackreg_67_23_next: unsigned((1 - 1) downto 0);
signal rddackreg_67_23: unsigned((1 - 1) downto 0) := "0";
signal wrdackreg_71_23_next: unsigned((1 - 1) downto 0);
signal wrdackreg_71_23: unsigned((1 - 1) downto 0) := "0";
signal rddbusreg_85_23_next: unsigned((32 - 1) downto 0);
signal rddbusreg_85_23: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal bankaddr_21_1_slice: unsigned((2 - 1) downto 0);
signal linearaddr_22_1_slice: unsigned((13 - 1) downto 0);
signal addrpref_in_33_1_slice: unsigned((15 - 1) downto 0);
signal rel_34_4: boolean;
signal ps1_join_34_1: boolean;
signal ps_43_1_bit: boolean;
signal bitnot_50_49: boolean;
signal bitnot_50_73: boolean;
signal bit_50_49: boolean;
signal addrack_50_1_convert: unsigned((1 - 1) downto 0);
signal bit_56_43: unsigned((1 - 1) downto 0);
signal bitnot_73_35: unsigned((1 - 1) downto 0);
signal wrdackreg_73_1_bit: unsigned((1 - 1) downto 0);
signal rdsel_77_1_bit: unsigned((1 - 1) downto 0);
signal rel_79_4: boolean;
signal rddbus1_join_79_1: unsigned((32 - 1) downto 0);
signal plbwrdbusreg_98_1_slice: unsigned((32 - 1) downto 0);
signal plbrstreg_13_24_next_x_000000: boolean;
signal plbpavalidreg_15_28_next_x_000000: boolean;
begin
plbrst_2_20 <= std_logic_vector_to_unsigned(plbrst);
plbabus_2_28 <= std_logic_vector_to_unsigned(plbabus);
plbpavalid_2_37 <= std_logic_vector_to_unsigned(plbpavalid);
plbrnw_2_49 <= std_logic_vector_to_unsigned(plbrnw);
plbwrdbus_2_57 <= std_logic_vector_to_unsigned(plbwrdbus);
rddata_2_68 <= std_logic_vector_to_unsigned(rddata);
addrpref_2_76 <= std_logic_vector_to_unsigned(addrpref);
proc_plbrstreg_13_24: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbrstreg_13_24 <= plbrstreg_13_24_next;
end if;
end if;
end process proc_plbrstreg_13_24;
proc_plbabusreg_14_25: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbabusreg_14_25 <= plbabusreg_14_25_next;
end if;
end if;
end process proc_plbabusreg_14_25;
proc_plbpavalidreg_15_28: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbpavalidreg_15_28 <= plbpavalidreg_15_28_next;
end if;
end if;
end process proc_plbpavalidreg_15_28;
proc_plbrnwreg_16_24: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbrnwreg_16_24 <= plbrnwreg_16_24_next;
end if;
end if;
end process proc_plbrnwreg_16_24;
proc_plbwrdbusreg_17_27: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbwrdbusreg_17_27 <= plbwrdbusreg_17_27_next;
end if;
end if;
end process proc_plbwrdbusreg_17_27;
proc_avalidreg_29_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
avalidreg_29_23 <= avalidreg_29_23_next;
end if;
end if;
end process proc_avalidreg_29_23;
proc_ps1reg_40_20: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
ps1reg_40_20 <= ps1reg_40_20_next;
end if;
end if;
end process proc_ps1reg_40_20;
proc_psreg_48_19: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
psreg_48_19 <= psreg_48_19_next;
end if;
end if;
end process proc_psreg_48_19;
rdcompdelay_59_25_back <= rdcompdelay_59_25(2);
proc_rdcompdelay_59_25: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (rdcompdelay_59_25_push_front_pop_back_en = '1')) then
for i in 2 downto 1 loop
rdcompdelay_59_25(i) <= rdcompdelay_59_25(i-1);
end loop;
rdcompdelay_59_25(0) <= rdcompdelay_59_25_front_din;
end if;
end if;
end process proc_rdcompdelay_59_25;
proc_rdcompreg_63_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
rdcompreg_63_23 <= rdcompreg_63_23_next;
end if;
end if;
end process proc_rdcompreg_63_23;
proc_rddackreg_67_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
rddackreg_67_23 <= rddackreg_67_23_next;
end if;
end if;
end process proc_rddackreg_67_23;
proc_wrdackreg_71_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
wrdackreg_71_23 <= wrdackreg_71_23_next;
end if;
end if;
end process proc_wrdackreg_71_23;
proc_rddbusreg_85_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
rddbusreg_85_23 <= rddbusreg_85_23_next;
end if;
end if;
end process proc_rddbusreg_85_23;
bankaddr_21_1_slice <= u2u_slice(plbabusreg_14_25, 16, 15);
linearaddr_22_1_slice <= u2u_slice(plbabusreg_14_25, 14, 2);
addrpref_in_33_1_slice <= u2u_slice(plbabusreg_14_25, 31, 17);
rel_34_4 <= addrpref_in_33_1_slice = addrpref_2_76;
proc_if_34_1: process (rel_34_4)
is
begin
if rel_34_4 then
ps1_join_34_1 <= true;
else
ps1_join_34_1 <= false;
end if;
end process proc_if_34_1;
ps_43_1_bit <= ((boolean_to_vector(ps1_join_34_1) and boolean_to_vector(plbpavalidreg_15_28)) = "1");
bitnot_50_49 <= ((not boolean_to_vector(plbrstreg_13_24)) = "1");
bitnot_50_73 <= ((not boolean_to_vector(psreg_48_19)) = "1");
bit_50_49 <= ((boolean_to_vector(bitnot_50_49) and boolean_to_vector(ps_43_1_bit) and boolean_to_vector(bitnot_50_73)) = "1");
addrack_50_1_convert <= u2u_cast(std_logic_vector_to_unsigned(boolean_to_vector(bit_50_49)), 0, 1, 0);
bit_56_43 <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_50_1_convert) and unsigned_to_std_logic_vector(plbrnwreg_16_24));
bitnot_73_35 <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(plbrnwreg_16_24));
wrdackreg_73_1_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_50_1_convert) and unsigned_to_std_logic_vector(bitnot_73_35));
rdsel_77_1_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(rdcompdelay_59_25_back) or unsigned_to_std_logic_vector(rdcompreg_63_23));
rel_79_4 <= rdsel_77_1_bit = std_logic_vector_to_unsigned("1");
proc_if_79_1: process (rddata_2_68, rel_79_4)
is
begin
if rel_79_4 then
rddbus1_join_79_1 <= rddata_2_68;
else
rddbus1_join_79_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000");
end if;
end process proc_if_79_1;
plbwrdbusreg_98_1_slice <= u2u_slice(plbwrdbus_2_57, 31, 0);
plbrstreg_13_24_next_x_000000 <= (plbrst_2_20 /= "0");
plbrstreg_13_24_next <= plbrstreg_13_24_next_x_000000;
plbabusreg_14_25_next <= plbabus_2_28;
plbpavalidreg_15_28_next_x_000000 <= (plbpavalid_2_37 /= "0");
plbpavalidreg_15_28_next <= plbpavalidreg_15_28_next_x_000000;
plbrnwreg_16_24_next <= plbrnw_2_49;
plbwrdbusreg_17_27_next <= plbwrdbusreg_98_1_slice;
avalidreg_29_23_next <= plbpavalidreg_15_28;
ps1reg_40_20_next <= ps1_join_34_1;
psreg_48_19_next <= ps_43_1_bit;
rdcompdelay_59_25_front_din <= bit_56_43;
rdcompdelay_59_25_push_front_pop_back_en <= '1';
rdcompreg_63_23_next <= rdcompdelay_59_25_back;
rddackreg_67_23_next <= rdcompreg_63_23;
wrdackreg_71_23_next <= wrdackreg_73_1_bit;
rddbusreg_85_23_next <= rddbus1_join_79_1;
wrdbusreg <= unsigned_to_std_logic_vector(plbwrdbusreg_17_27);
addrack <= unsigned_to_std_logic_vector(addrack_50_1_convert);
rdcomp <= unsigned_to_std_logic_vector(rdcompreg_63_23);
wrdack <= unsigned_to_std_logic_vector(wrdackreg_71_23);
bankaddr <= unsigned_to_std_logic_vector(bankaddr_21_1_slice);
rnwreg <= unsigned_to_std_logic_vector(plbrnwreg_16_24);
rddack <= unsigned_to_std_logic_vector(rddackreg_67_23);
rddbus <= unsigned_to_std_logic_vector(rddbusreg_85_23);
linearaddr <= unsigned_to_std_logic_vector(linearaddr_22_1_slice);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mcode_block_66f25059c9 is
port (
wrdbus : in std_logic_vector((32 - 1) downto 0);
bankaddr : in std_logic_vector((2 - 1) downto 0);
linearaddr : in std_logic_vector((13 - 1) downto 0);
rnwreg : in std_logic_vector((1 - 1) downto 0);
addrack : in std_logic_vector((1 - 1) downto 0);
sm_buttons_big : in std_logic_vector((2 - 1) downto 0);
sm_buttons_small : in std_logic_vector((6 - 1) downto 0);
sm_dip_switch : in std_logic_vector((4 - 1) downto 0);
sm_trackball : in std_logic_vector((5 - 1) downto 0);
sm_buzzer_dutycycle : in std_logic_vector((18 - 1) downto 0);
sm_buzzer_enable : in std_logic_vector((1 - 1) downto 0);
sm_buzzer_period : in std_logic_vector((18 - 1) downto 0);
sm_lcd_backgroundcolor : in std_logic_vector((9 - 1) downto 0);
sm_lcd_characteroffset : in std_logic_vector((4 - 1) downto 0);
sm_lcd_charactersselect : in std_logic_vector((3 - 1) downto 0);
sm_lcd_colset : in std_logic_vector((9 - 1) downto 0);
sm_lcd_configlocation : in std_logic_vector((2 - 1) downto 0);
sm_lcd_dividerselect : in std_logic_vector((1 - 1) downto 0);
sm_lcd_firstend : in std_logic_vector((9 - 1) downto 0);
sm_lcd_firststart : in std_logic_vector((9 - 1) downto 0);
sm_lcd_lineoffset : in std_logic_vector((4 - 1) downto 0);
sm_lcd_ramwrite : in std_logic_vector((9 - 1) downto 0);
sm_lcd_reset : in std_logic_vector((1 - 1) downto 0);
sm_lcd_resetlcd : in std_logic_vector((1 - 1) downto 0);
sm_lcd_rowset : in std_logic_vector((9 - 1) downto 0);
sm_lcd_secondend : in std_logic_vector((9 - 1) downto 0);
sm_lcd_secondstart : in std_logic_vector((9 - 1) downto 0);
sm_lcd_send : in std_logic_vector((1 - 1) downto 0);
sm_lcd_totalcmdtransfer : in std_logic_vector((8 - 1) downto 0);
sm_leds : in std_logic_vector((8 - 1) downto 0);
sm_lcd_charactermap : in std_logic_vector((32 - 1) downto 0);
sm_lcd_characters : in std_logic_vector((32 - 1) downto 0);
sm_lcd_commands : in std_logic_vector((32 - 1) downto 0);
read_bank_out : out std_logic_vector((32 - 1) downto 0);
sm_buzzer_dutycycle_din : out std_logic_vector((18 - 1) downto 0);
sm_buzzer_dutycycle_en : out std_logic_vector((1 - 1) downto 0);
sm_buzzer_enable_din : out std_logic_vector((1 - 1) downto 0);
sm_buzzer_enable_en : out std_logic_vector((1 - 1) downto 0);
sm_buzzer_period_din : out std_logic_vector((18 - 1) downto 0);
sm_buzzer_period_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_backgroundcolor_din : out std_logic_vector((9 - 1) downto 0);
sm_lcd_backgroundcolor_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_characteroffset_din : out std_logic_vector((4 - 1) downto 0);
sm_lcd_characteroffset_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_charactersselect_din : out std_logic_vector((3 - 1) downto 0);
sm_lcd_charactersselect_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_colset_din : out std_logic_vector((9 - 1) downto 0);
sm_lcd_colset_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_configlocation_din : out std_logic_vector((2 - 1) downto 0);
sm_lcd_configlocation_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_dividerselect_din : out std_logic_vector((1 - 1) downto 0);
sm_lcd_dividerselect_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_firstend_din : out std_logic_vector((9 - 1) downto 0);
sm_lcd_firstend_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_firststart_din : out std_logic_vector((9 - 1) downto 0);
sm_lcd_firststart_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_lineoffset_din : out std_logic_vector((4 - 1) downto 0);
sm_lcd_lineoffset_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_ramwrite_din : out std_logic_vector((9 - 1) downto 0);
sm_lcd_ramwrite_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_reset_din : out std_logic_vector((1 - 1) downto 0);
sm_lcd_reset_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_resetlcd_din : out std_logic_vector((1 - 1) downto 0);
sm_lcd_resetlcd_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_rowset_din : out std_logic_vector((9 - 1) downto 0);
sm_lcd_rowset_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_secondend_din : out std_logic_vector((9 - 1) downto 0);
sm_lcd_secondend_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_secondstart_din : out std_logic_vector((9 - 1) downto 0);
sm_lcd_secondstart_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_send_din : out std_logic_vector((1 - 1) downto 0);
sm_lcd_send_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_totalcmdtransfer_din : out std_logic_vector((8 - 1) downto 0);
sm_lcd_totalcmdtransfer_en : out std_logic_vector((1 - 1) downto 0);
sm_leds_din : out std_logic_vector((8 - 1) downto 0);
sm_leds_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_charactermap_addr : out std_logic_vector((12 - 1) downto 0);
sm_lcd_charactermap_din : out std_logic_vector((32 - 1) downto 0);
sm_lcd_charactermap_we : out std_logic_vector((1 - 1) downto 0);
sm_lcd_characters_addr : out std_logic_vector((9 - 1) downto 0);
sm_lcd_characters_din : out std_logic_vector((32 - 1) downto 0);
sm_lcd_characters_we : out std_logic_vector((1 - 1) downto 0);
sm_lcd_commands_addr : out std_logic_vector((8 - 1) downto 0);
sm_lcd_commands_din : out std_logic_vector((32 - 1) downto 0);
sm_lcd_commands_we : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mcode_block_66f25059c9;
architecture behavior of mcode_block_66f25059c9 is
signal wrdbus_1_1186: unsigned((32 - 1) downto 0);
signal bankaddr_1_1194: unsigned((2 - 1) downto 0);
signal linearaddr_1_1204: unsigned((13 - 1) downto 0);
signal rnwreg_1_1216: unsigned((1 - 1) downto 0);
signal addrack_1_1224: unsigned((1 - 1) downto 0);
signal sm_buttons_big_1_1233: unsigned((2 - 1) downto 0);
signal sm_buttons_small_1_1249: unsigned((6 - 1) downto 0);
signal sm_dip_switch_1_1267: unsigned((4 - 1) downto 0);
signal sm_trackball_1_1282: unsigned((5 - 1) downto 0);
signal sm_buzzer_dutycycle_1_1296: unsigned((18 - 1) downto 0);
signal sm_buzzer_enable_1_1317: unsigned((1 - 1) downto 0);
signal sm_buzzer_period_1_1335: unsigned((18 - 1) downto 0);
signal sm_lcd_backgroundcolor_1_1353: unsigned((9 - 1) downto 0);
signal sm_lcd_characteroffset_1_1377: unsigned((4 - 1) downto 0);
signal sm_lcd_charactersselect_1_1401: unsigned((3 - 1) downto 0);
signal sm_lcd_colset_1_1426: unsigned((9 - 1) downto 0);
signal sm_lcd_configlocation_1_1441: unsigned((2 - 1) downto 0);
signal sm_lcd_dividerselect_1_1464: unsigned((1 - 1) downto 0);
signal sm_lcd_firstend_1_1486: unsigned((9 - 1) downto 0);
signal sm_lcd_firststart_1_1503: unsigned((9 - 1) downto 0);
signal sm_lcd_lineoffset_1_1522: unsigned((4 - 1) downto 0);
signal sm_lcd_ramwrite_1_1541: unsigned((9 - 1) downto 0);
signal sm_lcd_reset_1_1558: unsigned((1 - 1) downto 0);
signal sm_lcd_resetlcd_1_1572: unsigned((1 - 1) downto 0);
signal sm_lcd_rowset_1_1589: unsigned((9 - 1) downto 0);
signal sm_lcd_secondend_1_1604: unsigned((9 - 1) downto 0);
signal sm_lcd_secondstart_1_1622: unsigned((9 - 1) downto 0);
signal sm_lcd_send_1_1642: unsigned((1 - 1) downto 0);
signal sm_lcd_totalcmdtransfer_1_1655: unsigned((8 - 1) downto 0);
signal sm_leds_1_1680: unsigned((8 - 1) downto 0);
signal sm_lcd_charactermap_1_1689: unsigned((32 - 1) downto 0);
signal sm_lcd_characters_1_1710: unsigned((32 - 1) downto 0);
signal sm_lcd_commands_1_1729: unsigned((32 - 1) downto 0);
signal reg_bank_out_reg_98_30_next: unsigned((32 - 1) downto 0);
signal reg_bank_out_reg_98_30: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal ram_bank_out_reg_203_30_next: unsigned((32 - 1) downto 0);
signal ram_bank_out_reg_203_30: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal sm_lcd_charactermap_we_reg_226_40_next: boolean;
signal sm_lcd_charactermap_we_reg_226_40: boolean := false;
signal sm_lcd_characters_we_reg_245_38_next: boolean;
signal sm_lcd_characters_we_reg_245_38: boolean := false;
signal sm_lcd_commands_we_reg_264_36_next: boolean;
signal sm_lcd_commands_we_reg_264_36: boolean := false;
signal sm_lcd_charactermap_addr_reg_287_1_next: unsigned((12 - 1) downto 0);
signal sm_lcd_charactermap_addr_reg_287_1: unsigned((12 - 1) downto 0) := "000000000000";
signal sm_lcd_charactermap_addr_reg_287_1_en: std_logic;
signal sm_lcd_characters_addr_reg_295_1_next: unsigned((9 - 1) downto 0);
signal sm_lcd_characters_addr_reg_295_1: unsigned((9 - 1) downto 0) := "000000000";
signal sm_lcd_characters_addr_reg_295_1_en: std_logic;
signal sm_lcd_commands_addr_reg_303_1_next: unsigned((8 - 1) downto 0);
signal sm_lcd_commands_addr_reg_303_1: unsigned((8 - 1) downto 0) := "00000000";
signal sm_lcd_commands_addr_reg_303_1_en: std_logic;
signal read_bank_out_reg_516_31_next: unsigned((32 - 1) downto 0);
signal read_bank_out_reg_516_31: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal bankaddr_reg_519_26_next: unsigned((2 - 1) downto 0);
signal bankaddr_reg_519_26: unsigned((2 - 1) downto 0) := "00";
signal rel_101_4: boolean;
signal rel_103_8: boolean;
signal rel_105_8: boolean;
signal rel_107_8: boolean;
signal rel_109_8: boolean;
signal rel_111_8: boolean;
signal rel_113_8: boolean;
signal rel_115_8: boolean;
signal rel_117_8: boolean;
signal rel_119_8: boolean;
signal rel_121_8: boolean;
signal rel_123_8: boolean;
signal rel_125_8: boolean;
signal rel_127_8: boolean;
signal rel_129_8: boolean;
signal rel_131_8: boolean;
signal rel_133_8: boolean;
signal rel_135_8: boolean;
signal rel_137_8: boolean;
signal rel_139_8: boolean;
signal rel_141_8: boolean;
signal rel_143_8: boolean;
signal rel_145_8: boolean;
signal rel_147_8: boolean;
signal rel_149_8: boolean;
signal reg_bank_out_reg_join_101_1: unsigned((32 - 1) downto 0);
signal opcode_160_1_concat: unsigned((17 - 1) downto 0);
signal slice_164_51: unsigned((1 - 1) downto 0);
signal sm_lcd_charactermap_sel_value_164_1_concat: unsigned((1 - 1) downto 0);
signal rel_168_4: boolean;
signal sm_lcd_charactermap_sel_join_168_1: boolean;
signal slice_176_49: unsigned((4 - 1) downto 0);
signal sm_lcd_characters_sel_value_176_1_concat: unsigned((4 - 1) downto 0);
signal rel_180_4: boolean;
signal sm_lcd_characters_sel_join_180_1: boolean;
signal slice_188_47: unsigned((5 - 1) downto 0);
signal sm_lcd_commands_sel_value_188_1_concat: unsigned((5 - 1) downto 0);
signal rel_192_4: boolean;
signal sm_lcd_commands_sel_join_192_1: boolean;
signal ram_bank_out_reg_join_205_1: unsigned((32 - 1) downto 0);
signal slice_214_44: unsigned((32 - 1) downto 0);
signal slice_217_42: unsigned((32 - 1) downto 0);
signal slice_220_40: unsigned((32 - 1) downto 0);
signal slice_231_46: unsigned((1 - 1) downto 0);
signal opcode_sm_lcd_charactermap_228_1_concat: unsigned((5 - 1) downto 0);
signal rel_235_4: boolean;
signal sm_lcd_charactermap_we_reg_join_235_1: boolean;
signal slice_250_46: unsigned((4 - 1) downto 0);
signal opcode_sm_lcd_characters_247_1_concat: unsigned((8 - 1) downto 0);
signal rel_254_4: boolean;
signal sm_lcd_characters_we_reg_join_254_1: boolean;
signal slice_269_46: unsigned((5 - 1) downto 0);
signal opcode_sm_lcd_commands_266_1_concat: unsigned((9 - 1) downto 0);
signal rel_273_4: boolean;
signal sm_lcd_commands_we_reg_join_273_1: boolean;
signal sm_lcd_charactermap_addr_reg_290_5_slice: unsigned((13 - 1) downto 0);
signal rel_289_4: boolean;
signal sm_lcd_charactermap_addr_reg_join_289_1: unsigned((13 - 1) downto 0);
signal sm_lcd_charactermap_addr_reg_join_289_1_en: std_logic;
signal sm_lcd_characters_addr_reg_298_5_slice: unsigned((10 - 1) downto 0);
signal rel_297_4: boolean;
signal sm_lcd_characters_addr_reg_join_297_1: unsigned((10 - 1) downto 0);
signal sm_lcd_characters_addr_reg_join_297_1_en: std_logic;
signal sm_lcd_commands_addr_reg_306_5_slice: unsigned((9 - 1) downto 0);
signal rel_305_4: boolean;
signal sm_lcd_commands_addr_reg_join_305_1: unsigned((9 - 1) downto 0);
signal sm_lcd_commands_addr_reg_join_305_1_en: std_logic;
signal rel_316_4: boolean;
signal sm_buzzer_dutycycle_en_join_316_1: boolean;
signal rel_322_4: boolean;
signal sm_buzzer_enable_en_join_322_1: boolean;
signal rel_328_4: boolean;
signal sm_buzzer_period_en_join_328_1: boolean;
signal rel_334_4: boolean;
signal sm_lcd_backgroundcolor_en_join_334_1: boolean;
signal rel_340_4: boolean;
signal sm_lcd_characteroffset_en_join_340_1: boolean;
signal rel_346_4: boolean;
signal sm_lcd_charactersselect_en_join_346_1: boolean;
signal rel_352_4: boolean;
signal sm_lcd_colset_en_join_352_1: boolean;
signal rel_358_4: boolean;
signal sm_lcd_configlocation_en_join_358_1: boolean;
signal rel_364_4: boolean;
signal sm_lcd_dividerselect_en_join_364_1: boolean;
signal rel_370_4: boolean;
signal sm_lcd_firstend_en_join_370_1: boolean;
signal rel_376_4: boolean;
signal sm_lcd_firststart_en_join_376_1: boolean;
signal rel_382_4: boolean;
signal sm_lcd_lineoffset_en_join_382_1: boolean;
signal rel_388_4: boolean;
signal sm_lcd_ramwrite_en_join_388_1: boolean;
signal rel_394_4: boolean;
signal sm_lcd_reset_en_join_394_1: boolean;
signal rel_400_4: boolean;
signal sm_lcd_resetlcd_en_join_400_1: boolean;
signal rel_406_4: boolean;
signal sm_lcd_rowset_en_join_406_1: boolean;
signal rel_412_4: boolean;
signal sm_lcd_secondend_en_join_412_1: boolean;
signal rel_418_4: boolean;
signal sm_lcd_secondstart_en_join_418_1: boolean;
signal rel_424_4: boolean;
signal sm_lcd_send_en_join_424_1: boolean;
signal rel_430_4: boolean;
signal sm_lcd_totalcmdtransfer_en_join_430_1: boolean;
signal rel_436_4: boolean;
signal sm_leds_en_join_436_1: boolean;
signal slice_451_44: unsigned((18 - 1) downto 0);
signal slice_454_41: unsigned((1 - 1) downto 0);
signal slice_457_41: unsigned((18 - 1) downto 0);
signal slice_460_47: unsigned((9 - 1) downto 0);
signal slice_463_47: unsigned((4 - 1) downto 0);
signal slice_466_48: unsigned((3 - 1) downto 0);
signal slice_469_38: unsigned((9 - 1) downto 0);
signal slice_472_46: unsigned((2 - 1) downto 0);
signal slice_475_45: unsigned((1 - 1) downto 0);
signal slice_478_40: unsigned((9 - 1) downto 0);
signal slice_481_42: unsigned((9 - 1) downto 0);
signal slice_484_42: unsigned((4 - 1) downto 0);
signal slice_487_40: unsigned((9 - 1) downto 0);
signal slice_490_37: unsigned((1 - 1) downto 0);
signal slice_493_40: unsigned((1 - 1) downto 0);
signal slice_496_38: unsigned((9 - 1) downto 0);
signal slice_499_41: unsigned((9 - 1) downto 0);
signal slice_502_43: unsigned((9 - 1) downto 0);
signal slice_505_36: unsigned((1 - 1) downto 0);
signal slice_508_48: unsigned((8 - 1) downto 0);
signal slice_511_32: unsigned((8 - 1) downto 0);
signal rel_521_4: boolean;
signal rel_524_8: boolean;
signal rel_527_8: boolean;
signal rel_530_8: boolean;
signal read_bank_out_reg_join_521_1: unsigned((32 - 1) downto 0);
signal cast_sm_lcd_charactermap_addr_reg_287_1_next: unsigned((12 - 1) downto 0);
signal cast_sm_lcd_characters_addr_reg_295_1_next: unsigned((9 - 1) downto 0);
signal cast_sm_lcd_commands_addr_reg_303_1_next: unsigned((8 - 1) downto 0);
begin
wrdbus_1_1186 <= std_logic_vector_to_unsigned(wrdbus);
bankaddr_1_1194 <= std_logic_vector_to_unsigned(bankaddr);
linearaddr_1_1204 <= std_logic_vector_to_unsigned(linearaddr);
rnwreg_1_1216 <= std_logic_vector_to_unsigned(rnwreg);
addrack_1_1224 <= std_logic_vector_to_unsigned(addrack);
sm_buttons_big_1_1233 <= std_logic_vector_to_unsigned(sm_buttons_big);
sm_buttons_small_1_1249 <= std_logic_vector_to_unsigned(sm_buttons_small);
sm_dip_switch_1_1267 <= std_logic_vector_to_unsigned(sm_dip_switch);
sm_trackball_1_1282 <= std_logic_vector_to_unsigned(sm_trackball);
sm_buzzer_dutycycle_1_1296 <= std_logic_vector_to_unsigned(sm_buzzer_dutycycle);
sm_buzzer_enable_1_1317 <= std_logic_vector_to_unsigned(sm_buzzer_enable);
sm_buzzer_period_1_1335 <= std_logic_vector_to_unsigned(sm_buzzer_period);
sm_lcd_backgroundcolor_1_1353 <= std_logic_vector_to_unsigned(sm_lcd_backgroundcolor);
sm_lcd_characteroffset_1_1377 <= std_logic_vector_to_unsigned(sm_lcd_characteroffset);
sm_lcd_charactersselect_1_1401 <= std_logic_vector_to_unsigned(sm_lcd_charactersselect);
sm_lcd_colset_1_1426 <= std_logic_vector_to_unsigned(sm_lcd_colset);
sm_lcd_configlocation_1_1441 <= std_logic_vector_to_unsigned(sm_lcd_configlocation);
sm_lcd_dividerselect_1_1464 <= std_logic_vector_to_unsigned(sm_lcd_dividerselect);
sm_lcd_firstend_1_1486 <= std_logic_vector_to_unsigned(sm_lcd_firstend);
sm_lcd_firststart_1_1503 <= std_logic_vector_to_unsigned(sm_lcd_firststart);
sm_lcd_lineoffset_1_1522 <= std_logic_vector_to_unsigned(sm_lcd_lineoffset);
sm_lcd_ramwrite_1_1541 <= std_logic_vector_to_unsigned(sm_lcd_ramwrite);
sm_lcd_reset_1_1558 <= std_logic_vector_to_unsigned(sm_lcd_reset);
sm_lcd_resetlcd_1_1572 <= std_logic_vector_to_unsigned(sm_lcd_resetlcd);
sm_lcd_rowset_1_1589 <= std_logic_vector_to_unsigned(sm_lcd_rowset);
sm_lcd_secondend_1_1604 <= std_logic_vector_to_unsigned(sm_lcd_secondend);
sm_lcd_secondstart_1_1622 <= std_logic_vector_to_unsigned(sm_lcd_secondstart);
sm_lcd_send_1_1642 <= std_logic_vector_to_unsigned(sm_lcd_send);
sm_lcd_totalcmdtransfer_1_1655 <= std_logic_vector_to_unsigned(sm_lcd_totalcmdtransfer);
sm_leds_1_1680 <= std_logic_vector_to_unsigned(sm_leds);
sm_lcd_charactermap_1_1689 <= std_logic_vector_to_unsigned(sm_lcd_charactermap);
sm_lcd_characters_1_1710 <= std_logic_vector_to_unsigned(sm_lcd_characters);
sm_lcd_commands_1_1729 <= std_logic_vector_to_unsigned(sm_lcd_commands);
proc_reg_bank_out_reg_98_30: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
reg_bank_out_reg_98_30 <= reg_bank_out_reg_98_30_next;
end if;
end if;
end process proc_reg_bank_out_reg_98_30;
proc_ram_bank_out_reg_203_30: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
ram_bank_out_reg_203_30 <= ram_bank_out_reg_203_30_next;
end if;
end if;
end process proc_ram_bank_out_reg_203_30;
proc_sm_lcd_charactermap_we_reg_226_40: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
sm_lcd_charactermap_we_reg_226_40 <= sm_lcd_charactermap_we_reg_226_40_next;
end if;
end if;
end process proc_sm_lcd_charactermap_we_reg_226_40;
proc_sm_lcd_characters_we_reg_245_38: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
sm_lcd_characters_we_reg_245_38 <= sm_lcd_characters_we_reg_245_38_next;
end if;
end if;
end process proc_sm_lcd_characters_we_reg_245_38;
proc_sm_lcd_commands_we_reg_264_36: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
sm_lcd_commands_we_reg_264_36 <= sm_lcd_commands_we_reg_264_36_next;
end if;
end if;
end process proc_sm_lcd_commands_we_reg_264_36;
proc_sm_lcd_charactermap_addr_reg_287_1: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (sm_lcd_charactermap_addr_reg_287_1_en = '1')) then
sm_lcd_charactermap_addr_reg_287_1 <= sm_lcd_charactermap_addr_reg_287_1_next;
end if;
end if;
end process proc_sm_lcd_charactermap_addr_reg_287_1;
proc_sm_lcd_characters_addr_reg_295_1: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (sm_lcd_characters_addr_reg_295_1_en = '1')) then
sm_lcd_characters_addr_reg_295_1 <= sm_lcd_characters_addr_reg_295_1_next;
end if;
end if;
end process proc_sm_lcd_characters_addr_reg_295_1;
proc_sm_lcd_commands_addr_reg_303_1: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (sm_lcd_commands_addr_reg_303_1_en = '1')) then
sm_lcd_commands_addr_reg_303_1 <= sm_lcd_commands_addr_reg_303_1_next;
end if;
end if;
end process proc_sm_lcd_commands_addr_reg_303_1;
proc_read_bank_out_reg_516_31: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
read_bank_out_reg_516_31 <= read_bank_out_reg_516_31_next;
end if;
end if;
end process proc_read_bank_out_reg_516_31;
proc_bankaddr_reg_519_26: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
bankaddr_reg_519_26 <= bankaddr_reg_519_26_next;
end if;
end if;
end process proc_bankaddr_reg_519_26;
rel_101_4 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000010101");
rel_103_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000010110");
rel_105_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000010111");
rel_107_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000011000");
rel_109_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000000000");
rel_111_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000000001");
rel_113_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000000010");
rel_115_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000000011");
rel_117_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000000100");
rel_119_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000000101");
rel_121_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000000110");
rel_123_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000000111");
rel_125_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000001000");
rel_127_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000001001");
rel_129_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000001010");
rel_131_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000001011");
rel_133_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000001100");
rel_135_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000001101");
rel_137_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000001110");
rel_139_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000001111");
rel_141_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000010000");
rel_143_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000010001");
rel_145_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000010010");
rel_147_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000010011");
rel_149_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000010100");
proc_if_101_1: process (reg_bank_out_reg_98_30, rel_101_4, rel_103_8, rel_105_8, rel_107_8, rel_109_8, rel_111_8, rel_113_8, rel_115_8, rel_117_8, rel_119_8, rel_121_8, rel_123_8, rel_125_8, rel_127_8, rel_129_8, rel_131_8, rel_133_8, rel_135_8, rel_137_8, rel_139_8, rel_141_8, rel_143_8, rel_145_8, rel_147_8, rel_149_8, sm_buttons_big_1_1233, sm_buttons_small_1_1249, sm_buzzer_dutycycle_1_1296, sm_buzzer_enable_1_1317, sm_buzzer_period_1_1335, sm_dip_switch_1_1267, sm_lcd_backgroundcolor_1_1353, sm_lcd_characteroffset_1_1377, sm_lcd_charactersselect_1_1401, sm_lcd_colset_1_1426, sm_lcd_configlocation_1_1441, sm_lcd_dividerselect_1_1464, sm_lcd_firstend_1_1486, sm_lcd_firststart_1_1503, sm_lcd_lineoffset_1_1522, sm_lcd_ramwrite_1_1541, sm_lcd_reset_1_1558, sm_lcd_resetlcd_1_1572, sm_lcd_rowset_1_1589, sm_lcd_secondend_1_1604, sm_lcd_secondstart_1_1622, sm_lcd_send_1_1642, sm_lcd_totalcmdtransfer_1_1655, sm_leds_1_1680, sm_trackball_1_1282)
is
begin
if rel_101_4 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_buttons_big_1_1233, 0, 32, 0);
elsif rel_103_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_buttons_small_1_1249, 0, 32, 0);
elsif rel_105_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_dip_switch_1_1267, 0, 32, 0);
elsif rel_107_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_trackball_1_1282, 0, 32, 0);
elsif rel_109_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_buzzer_dutycycle_1_1296, 0, 32, 0);
elsif rel_111_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_buzzer_enable_1_1317, 0, 32, 0);
elsif rel_113_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_buzzer_period_1_1335, 0, 32, 0);
elsif rel_115_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_backgroundcolor_1_1353, 0, 32, 0);
elsif rel_117_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_characteroffset_1_1377, 0, 32, 0);
elsif rel_119_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_charactersselect_1_1401, 0, 32, 0);
elsif rel_121_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_colset_1_1426, 0, 32, 0);
elsif rel_123_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_configlocation_1_1441, 0, 32, 0);
elsif rel_125_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_dividerselect_1_1464, 0, 32, 0);
elsif rel_127_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_firstend_1_1486, 0, 32, 0);
elsif rel_129_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_firststart_1_1503, 0, 32, 0);
elsif rel_131_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_lineoffset_1_1522, 0, 32, 0);
elsif rel_133_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_ramwrite_1_1541, 0, 32, 0);
elsif rel_135_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_reset_1_1558, 0, 32, 0);
elsif rel_137_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_resetlcd_1_1572, 0, 32, 0);
elsif rel_139_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_rowset_1_1589, 0, 32, 0);
elsif rel_141_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_secondend_1_1604, 0, 32, 0);
elsif rel_143_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_secondstart_1_1622, 0, 32, 0);
elsif rel_145_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_send_1_1642, 0, 32, 0);
elsif rel_147_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_totalcmdtransfer_1_1655, 0, 32, 0);
elsif rel_149_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_leds_1_1680, 0, 32, 0);
else
reg_bank_out_reg_join_101_1 <= reg_bank_out_reg_98_30;
end if;
end process proc_if_101_1;
opcode_160_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_1_1224) & unsigned_to_std_logic_vector(rnwreg_1_1216) & unsigned_to_std_logic_vector(bankaddr_1_1194) & unsigned_to_std_logic_vector(linearaddr_1_1204));
slice_164_51 <= u2u_slice(linearaddr_1_1204, 12, 12);
sm_lcd_charactermap_sel_value_164_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(slice_164_51));
rel_168_4 <= sm_lcd_charactermap_sel_value_164_1_concat = std_logic_vector_to_unsigned("0");
proc_if_168_1: process (rel_168_4)
is
begin
if rel_168_4 then
sm_lcd_charactermap_sel_join_168_1 <= true;
else
sm_lcd_charactermap_sel_join_168_1 <= false;
end if;
end process proc_if_168_1;
slice_176_49 <= u2u_slice(linearaddr_1_1204, 12, 9);
sm_lcd_characters_sel_value_176_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(slice_176_49));
rel_180_4 <= sm_lcd_characters_sel_value_176_1_concat = std_logic_vector_to_unsigned("1000");
proc_if_180_1: process (rel_180_4)
is
begin
if rel_180_4 then
sm_lcd_characters_sel_join_180_1 <= true;
else
sm_lcd_characters_sel_join_180_1 <= false;
end if;
end process proc_if_180_1;
slice_188_47 <= u2u_slice(linearaddr_1_1204, 12, 8);
sm_lcd_commands_sel_value_188_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(slice_188_47));
rel_192_4 <= sm_lcd_commands_sel_value_188_1_concat = std_logic_vector_to_unsigned("10010");
proc_if_192_1: process (rel_192_4)
is
begin
if rel_192_4 then
sm_lcd_commands_sel_join_192_1 <= true;
else
sm_lcd_commands_sel_join_192_1 <= false;
end if;
end process proc_if_192_1;
proc_if_205_1: process (ram_bank_out_reg_203_30, sm_lcd_charactermap_1_1689, sm_lcd_charactermap_sel_join_168_1, sm_lcd_characters_1_1710, sm_lcd_characters_sel_join_180_1, sm_lcd_commands_1_1729, sm_lcd_commands_sel_join_192_1)
is
begin
if sm_lcd_charactermap_sel_join_168_1 then
ram_bank_out_reg_join_205_1 <= sm_lcd_charactermap_1_1689;
elsif sm_lcd_characters_sel_join_180_1 then
ram_bank_out_reg_join_205_1 <= sm_lcd_characters_1_1710;
elsif sm_lcd_commands_sel_join_192_1 then
ram_bank_out_reg_join_205_1 <= sm_lcd_commands_1_1729;
else
ram_bank_out_reg_join_205_1 <= ram_bank_out_reg_203_30;
end if;
end process proc_if_205_1;
slice_214_44 <= u2u_slice(wrdbus_1_1186, 31, 0);
slice_217_42 <= u2u_slice(wrdbus_1_1186, 31, 0);
slice_220_40 <= u2u_slice(wrdbus_1_1186, 31, 0);
slice_231_46 <= u2u_slice(linearaddr_1_1204, 12, 12);
opcode_sm_lcd_charactermap_228_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_1_1224) & unsigned_to_std_logic_vector(rnwreg_1_1216) & unsigned_to_std_logic_vector(bankaddr_1_1194) & unsigned_to_std_logic_vector(slice_231_46));
rel_235_4 <= opcode_sm_lcd_charactermap_228_1_concat = std_logic_vector_to_unsigned("10000");
proc_if_235_1: process (rel_235_4)
is
begin
if rel_235_4 then
sm_lcd_charactermap_we_reg_join_235_1 <= true;
else
sm_lcd_charactermap_we_reg_join_235_1 <= false;
end if;
end process proc_if_235_1;
slice_250_46 <= u2u_slice(linearaddr_1_1204, 12, 9);
opcode_sm_lcd_characters_247_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_1_1224) & unsigned_to_std_logic_vector(rnwreg_1_1216) & unsigned_to_std_logic_vector(bankaddr_1_1194) & unsigned_to_std_logic_vector(slice_250_46));
rel_254_4 <= opcode_sm_lcd_characters_247_1_concat = std_logic_vector_to_unsigned("10001000");
proc_if_254_1: process (rel_254_4)
is
begin
if rel_254_4 then
sm_lcd_characters_we_reg_join_254_1 <= true;
else
sm_lcd_characters_we_reg_join_254_1 <= false;
end if;
end process proc_if_254_1;
slice_269_46 <= u2u_slice(linearaddr_1_1204, 12, 8);
opcode_sm_lcd_commands_266_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_1_1224) & unsigned_to_std_logic_vector(rnwreg_1_1216) & unsigned_to_std_logic_vector(bankaddr_1_1194) & unsigned_to_std_logic_vector(slice_269_46));
rel_273_4 <= opcode_sm_lcd_commands_266_1_concat = std_logic_vector_to_unsigned("100010010");
proc_if_273_1: process (rel_273_4)
is
begin
if rel_273_4 then
sm_lcd_commands_we_reg_join_273_1 <= true;
else
sm_lcd_commands_we_reg_join_273_1 <= false;
end if;
end process proc_if_273_1;
sm_lcd_charactermap_addr_reg_290_5_slice <= u2u_slice(linearaddr_1_1204, 12, 0);
rel_289_4 <= addrack_1_1224 = std_logic_vector_to_unsigned("1");
proc_if_289_1: process (rel_289_4, sm_lcd_charactermap_addr_reg_290_5_slice)
is
begin
if rel_289_4 then
sm_lcd_charactermap_addr_reg_join_289_1_en <= '1';
else
sm_lcd_charactermap_addr_reg_join_289_1_en <= '0';
end if;
sm_lcd_charactermap_addr_reg_join_289_1 <= sm_lcd_charactermap_addr_reg_290_5_slice;
end process proc_if_289_1;
sm_lcd_characters_addr_reg_298_5_slice <= u2u_slice(linearaddr_1_1204, 9, 0);
rel_297_4 <= addrack_1_1224 = std_logic_vector_to_unsigned("1");
proc_if_297_1: process (rel_297_4, sm_lcd_characters_addr_reg_298_5_slice)
is
begin
if rel_297_4 then
sm_lcd_characters_addr_reg_join_297_1_en <= '1';
else
sm_lcd_characters_addr_reg_join_297_1_en <= '0';
end if;
sm_lcd_characters_addr_reg_join_297_1 <= sm_lcd_characters_addr_reg_298_5_slice;
end process proc_if_297_1;
sm_lcd_commands_addr_reg_306_5_slice <= u2u_slice(linearaddr_1_1204, 8, 0);
rel_305_4 <= addrack_1_1224 = std_logic_vector_to_unsigned("1");
proc_if_305_1: process (rel_305_4, sm_lcd_commands_addr_reg_306_5_slice)
is
begin
if rel_305_4 then
sm_lcd_commands_addr_reg_join_305_1_en <= '1';
else
sm_lcd_commands_addr_reg_join_305_1_en <= '0';
end if;
sm_lcd_commands_addr_reg_join_305_1 <= sm_lcd_commands_addr_reg_306_5_slice;
end process proc_if_305_1;
rel_316_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000000000");
proc_if_316_1: process (rel_316_4)
is
begin
if rel_316_4 then
sm_buzzer_dutycycle_en_join_316_1 <= true;
else
sm_buzzer_dutycycle_en_join_316_1 <= false;
end if;
end process proc_if_316_1;
rel_322_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000000001");
proc_if_322_1: process (rel_322_4)
is
begin
if rel_322_4 then
sm_buzzer_enable_en_join_322_1 <= true;
else
sm_buzzer_enable_en_join_322_1 <= false;
end if;
end process proc_if_322_1;
rel_328_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000000010");
proc_if_328_1: process (rel_328_4)
is
begin
if rel_328_4 then
sm_buzzer_period_en_join_328_1 <= true;
else
sm_buzzer_period_en_join_328_1 <= false;
end if;
end process proc_if_328_1;
rel_334_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000000011");
proc_if_334_1: process (rel_334_4)
is
begin
if rel_334_4 then
sm_lcd_backgroundcolor_en_join_334_1 <= true;
else
sm_lcd_backgroundcolor_en_join_334_1 <= false;
end if;
end process proc_if_334_1;
rel_340_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000000100");
proc_if_340_1: process (rel_340_4)
is
begin
if rel_340_4 then
sm_lcd_characteroffset_en_join_340_1 <= true;
else
sm_lcd_characteroffset_en_join_340_1 <= false;
end if;
end process proc_if_340_1;
rel_346_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000000101");
proc_if_346_1: process (rel_346_4)
is
begin
if rel_346_4 then
sm_lcd_charactersselect_en_join_346_1 <= true;
else
sm_lcd_charactersselect_en_join_346_1 <= false;
end if;
end process proc_if_346_1;
rel_352_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000000110");
proc_if_352_1: process (rel_352_4)
is
begin
if rel_352_4 then
sm_lcd_colset_en_join_352_1 <= true;
else
sm_lcd_colset_en_join_352_1 <= false;
end if;
end process proc_if_352_1;
rel_358_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000000111");
proc_if_358_1: process (rel_358_4)
is
begin
if rel_358_4 then
sm_lcd_configlocation_en_join_358_1 <= true;
else
sm_lcd_configlocation_en_join_358_1 <= false;
end if;
end process proc_if_358_1;
rel_364_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000001000");
proc_if_364_1: process (rel_364_4)
is
begin
if rel_364_4 then
sm_lcd_dividerselect_en_join_364_1 <= true;
else
sm_lcd_dividerselect_en_join_364_1 <= false;
end if;
end process proc_if_364_1;
rel_370_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000001001");
proc_if_370_1: process (rel_370_4)
is
begin
if rel_370_4 then
sm_lcd_firstend_en_join_370_1 <= true;
else
sm_lcd_firstend_en_join_370_1 <= false;
end if;
end process proc_if_370_1;
rel_376_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000001010");
proc_if_376_1: process (rel_376_4)
is
begin
if rel_376_4 then
sm_lcd_firststart_en_join_376_1 <= true;
else
sm_lcd_firststart_en_join_376_1 <= false;
end if;
end process proc_if_376_1;
rel_382_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000001011");
proc_if_382_1: process (rel_382_4)
is
begin
if rel_382_4 then
sm_lcd_lineoffset_en_join_382_1 <= true;
else
sm_lcd_lineoffset_en_join_382_1 <= false;
end if;
end process proc_if_382_1;
rel_388_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000001100");
proc_if_388_1: process (rel_388_4)
is
begin
if rel_388_4 then
sm_lcd_ramwrite_en_join_388_1 <= true;
else
sm_lcd_ramwrite_en_join_388_1 <= false;
end if;
end process proc_if_388_1;
rel_394_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000001101");
proc_if_394_1: process (rel_394_4)
is
begin
if rel_394_4 then
sm_lcd_reset_en_join_394_1 <= true;
else
sm_lcd_reset_en_join_394_1 <= false;
end if;
end process proc_if_394_1;
rel_400_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000001110");
proc_if_400_1: process (rel_400_4)
is
begin
if rel_400_4 then
sm_lcd_resetlcd_en_join_400_1 <= true;
else
sm_lcd_resetlcd_en_join_400_1 <= false;
end if;
end process proc_if_400_1;
rel_406_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000001111");
proc_if_406_1: process (rel_406_4)
is
begin
if rel_406_4 then
sm_lcd_rowset_en_join_406_1 <= true;
else
sm_lcd_rowset_en_join_406_1 <= false;
end if;
end process proc_if_406_1;
rel_412_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000010000");
proc_if_412_1: process (rel_412_4)
is
begin
if rel_412_4 then
sm_lcd_secondend_en_join_412_1 <= true;
else
sm_lcd_secondend_en_join_412_1 <= false;
end if;
end process proc_if_412_1;
rel_418_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000010001");
proc_if_418_1: process (rel_418_4)
is
begin
if rel_418_4 then
sm_lcd_secondstart_en_join_418_1 <= true;
else
sm_lcd_secondstart_en_join_418_1 <= false;
end if;
end process proc_if_418_1;
rel_424_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000010010");
proc_if_424_1: process (rel_424_4)
is
begin
if rel_424_4 then
sm_lcd_send_en_join_424_1 <= true;
else
sm_lcd_send_en_join_424_1 <= false;
end if;
end process proc_if_424_1;
rel_430_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000010011");
proc_if_430_1: process (rel_430_4)
is
begin
if rel_430_4 then
sm_lcd_totalcmdtransfer_en_join_430_1 <= true;
else
sm_lcd_totalcmdtransfer_en_join_430_1 <= false;
end if;
end process proc_if_430_1;
rel_436_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000010100");
proc_if_436_1: process (rel_436_4)
is
begin
if rel_436_4 then
sm_leds_en_join_436_1 <= true;
else
sm_leds_en_join_436_1 <= false;
end if;
end process proc_if_436_1;
slice_451_44 <= u2u_slice(wrdbus_1_1186, 17, 0);
slice_454_41 <= u2u_slice(wrdbus_1_1186, 0, 0);
slice_457_41 <= u2u_slice(wrdbus_1_1186, 17, 0);
slice_460_47 <= u2u_slice(wrdbus_1_1186, 8, 0);
slice_463_47 <= u2u_slice(wrdbus_1_1186, 3, 0);
slice_466_48 <= u2u_slice(wrdbus_1_1186, 2, 0);
slice_469_38 <= u2u_slice(wrdbus_1_1186, 8, 0);
slice_472_46 <= u2u_slice(wrdbus_1_1186, 1, 0);
slice_475_45 <= u2u_slice(wrdbus_1_1186, 0, 0);
slice_478_40 <= u2u_slice(wrdbus_1_1186, 8, 0);
slice_481_42 <= u2u_slice(wrdbus_1_1186, 8, 0);
slice_484_42 <= u2u_slice(wrdbus_1_1186, 3, 0);
slice_487_40 <= u2u_slice(wrdbus_1_1186, 8, 0);
slice_490_37 <= u2u_slice(wrdbus_1_1186, 0, 0);
slice_493_40 <= u2u_slice(wrdbus_1_1186, 0, 0);
slice_496_38 <= u2u_slice(wrdbus_1_1186, 8, 0);
slice_499_41 <= u2u_slice(wrdbus_1_1186, 8, 0);
slice_502_43 <= u2u_slice(wrdbus_1_1186, 8, 0);
slice_505_36 <= u2u_slice(wrdbus_1_1186, 0, 0);
slice_508_48 <= u2u_slice(wrdbus_1_1186, 7, 0);
slice_511_32 <= u2u_slice(wrdbus_1_1186, 7, 0);
rel_521_4 <= bankaddr_reg_519_26 = std_logic_vector_to_unsigned("00");
rel_524_8 <= bankaddr_reg_519_26 = std_logic_vector_to_unsigned("01");
rel_527_8 <= bankaddr_reg_519_26 = std_logic_vector_to_unsigned("10");
rel_530_8 <= bankaddr_reg_519_26 = std_logic_vector_to_unsigned("11");
proc_if_521_1: process (ram_bank_out_reg_203_30, read_bank_out_reg_516_31, reg_bank_out_reg_98_30, rel_521_4, rel_524_8, rel_527_8, rel_530_8)
is
begin
if rel_521_4 then
read_bank_out_reg_join_521_1 <= ram_bank_out_reg_203_30;
elsif rel_524_8 then
read_bank_out_reg_join_521_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000");
elsif rel_527_8 then
read_bank_out_reg_join_521_1 <= reg_bank_out_reg_98_30;
elsif rel_530_8 then
read_bank_out_reg_join_521_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000");
else
read_bank_out_reg_join_521_1 <= read_bank_out_reg_516_31;
end if;
end process proc_if_521_1;
reg_bank_out_reg_98_30_next <= reg_bank_out_reg_join_101_1;
ram_bank_out_reg_203_30_next <= ram_bank_out_reg_join_205_1;
sm_lcd_charactermap_we_reg_226_40_next <= sm_lcd_charactermap_we_reg_join_235_1;
sm_lcd_characters_we_reg_245_38_next <= sm_lcd_characters_we_reg_join_254_1;
sm_lcd_commands_we_reg_264_36_next <= sm_lcd_commands_we_reg_join_273_1;
cast_sm_lcd_charactermap_addr_reg_287_1_next <= u2u_cast(sm_lcd_charactermap_addr_reg_join_289_1, 0, 12, 0);
sm_lcd_charactermap_addr_reg_287_1_next <= cast_sm_lcd_charactermap_addr_reg_287_1_next;
sm_lcd_charactermap_addr_reg_287_1_en <= sm_lcd_charactermap_addr_reg_join_289_1_en;
cast_sm_lcd_characters_addr_reg_295_1_next <= u2u_cast(sm_lcd_characters_addr_reg_join_297_1, 0, 9, 0);
sm_lcd_characters_addr_reg_295_1_next <= cast_sm_lcd_characters_addr_reg_295_1_next;
sm_lcd_characters_addr_reg_295_1_en <= sm_lcd_characters_addr_reg_join_297_1_en;
cast_sm_lcd_commands_addr_reg_303_1_next <= u2u_cast(sm_lcd_commands_addr_reg_join_305_1, 0, 8, 0);
sm_lcd_commands_addr_reg_303_1_next <= cast_sm_lcd_commands_addr_reg_303_1_next;
sm_lcd_commands_addr_reg_303_1_en <= sm_lcd_commands_addr_reg_join_305_1_en;
read_bank_out_reg_516_31_next <= read_bank_out_reg_join_521_1;
bankaddr_reg_519_26_next <= bankaddr_1_1194;
read_bank_out <= unsigned_to_std_logic_vector(read_bank_out_reg_516_31);
sm_buzzer_dutycycle_din <= unsigned_to_std_logic_vector(slice_451_44);
sm_buzzer_dutycycle_en <= boolean_to_vector(sm_buzzer_dutycycle_en_join_316_1);
sm_buzzer_enable_din <= unsigned_to_std_logic_vector(slice_454_41);
sm_buzzer_enable_en <= boolean_to_vector(sm_buzzer_enable_en_join_322_1);
sm_buzzer_period_din <= unsigned_to_std_logic_vector(slice_457_41);
sm_buzzer_period_en <= boolean_to_vector(sm_buzzer_period_en_join_328_1);
sm_lcd_backgroundcolor_din <= unsigned_to_std_logic_vector(slice_460_47);
sm_lcd_backgroundcolor_en <= boolean_to_vector(sm_lcd_backgroundcolor_en_join_334_1);
sm_lcd_characteroffset_din <= unsigned_to_std_logic_vector(slice_463_47);
sm_lcd_characteroffset_en <= boolean_to_vector(sm_lcd_characteroffset_en_join_340_1);
sm_lcd_charactersselect_din <= unsigned_to_std_logic_vector(slice_466_48);
sm_lcd_charactersselect_en <= boolean_to_vector(sm_lcd_charactersselect_en_join_346_1);
sm_lcd_colset_din <= unsigned_to_std_logic_vector(slice_469_38);
sm_lcd_colset_en <= boolean_to_vector(sm_lcd_colset_en_join_352_1);
sm_lcd_configlocation_din <= unsigned_to_std_logic_vector(slice_472_46);
sm_lcd_configlocation_en <= boolean_to_vector(sm_lcd_configlocation_en_join_358_1);
sm_lcd_dividerselect_din <= unsigned_to_std_logic_vector(slice_475_45);
sm_lcd_dividerselect_en <= boolean_to_vector(sm_lcd_dividerselect_en_join_364_1);
sm_lcd_firstend_din <= unsigned_to_std_logic_vector(slice_478_40);
sm_lcd_firstend_en <= boolean_to_vector(sm_lcd_firstend_en_join_370_1);
sm_lcd_firststart_din <= unsigned_to_std_logic_vector(slice_481_42);
sm_lcd_firststart_en <= boolean_to_vector(sm_lcd_firststart_en_join_376_1);
sm_lcd_lineoffset_din <= unsigned_to_std_logic_vector(slice_484_42);
sm_lcd_lineoffset_en <= boolean_to_vector(sm_lcd_lineoffset_en_join_382_1);
sm_lcd_ramwrite_din <= unsigned_to_std_logic_vector(slice_487_40);
sm_lcd_ramwrite_en <= boolean_to_vector(sm_lcd_ramwrite_en_join_388_1);
sm_lcd_reset_din <= unsigned_to_std_logic_vector(slice_490_37);
sm_lcd_reset_en <= boolean_to_vector(sm_lcd_reset_en_join_394_1);
sm_lcd_resetlcd_din <= unsigned_to_std_logic_vector(slice_493_40);
sm_lcd_resetlcd_en <= boolean_to_vector(sm_lcd_resetlcd_en_join_400_1);
sm_lcd_rowset_din <= unsigned_to_std_logic_vector(slice_496_38);
sm_lcd_rowset_en <= boolean_to_vector(sm_lcd_rowset_en_join_406_1);
sm_lcd_secondend_din <= unsigned_to_std_logic_vector(slice_499_41);
sm_lcd_secondend_en <= boolean_to_vector(sm_lcd_secondend_en_join_412_1);
sm_lcd_secondstart_din <= unsigned_to_std_logic_vector(slice_502_43);
sm_lcd_secondstart_en <= boolean_to_vector(sm_lcd_secondstart_en_join_418_1);
sm_lcd_send_din <= unsigned_to_std_logic_vector(slice_505_36);
sm_lcd_send_en <= boolean_to_vector(sm_lcd_send_en_join_424_1);
sm_lcd_totalcmdtransfer_din <= unsigned_to_std_logic_vector(slice_508_48);
sm_lcd_totalcmdtransfer_en <= boolean_to_vector(sm_lcd_totalcmdtransfer_en_join_430_1);
sm_leds_din <= unsigned_to_std_logic_vector(slice_511_32);
sm_leds_en <= boolean_to_vector(sm_leds_en_join_436_1);
sm_lcd_charactermap_addr <= unsigned_to_std_logic_vector(sm_lcd_charactermap_addr_reg_287_1);
sm_lcd_charactermap_din <= unsigned_to_std_logic_vector(slice_214_44);
sm_lcd_charactermap_we <= boolean_to_vector(sm_lcd_charactermap_we_reg_226_40);
sm_lcd_characters_addr <= unsigned_to_std_logic_vector(sm_lcd_characters_addr_reg_295_1);
sm_lcd_characters_din <= unsigned_to_std_logic_vector(slice_217_42);
sm_lcd_characters_we <= boolean_to_vector(sm_lcd_characters_we_reg_245_38);
sm_lcd_commands_addr <= unsigned_to_std_logic_vector(sm_lcd_commands_addr_reg_303_1);
sm_lcd_commands_din <= unsigned_to_std_logic_vector(slice_220_40);
sm_lcd_commands_we <= boolean_to_vector(sm_lcd_commands_we_reg_264_36);
end behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xldelay is
generic(width : integer := -1;
latency : integer := -1;
reg_retiming : integer := 0);
port(d : in std_logic_vector (width-1 downto 0);
ce : in std_logic;
clk : in std_logic;
en : in std_logic;
q : out std_logic_vector (width-1 downto 0));
end xldelay;
architecture behavior of xldelay is
component synth_reg
generic (width : integer;
latency : integer);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end component;
component synth_reg_reg
generic (width : integer;
latency : integer);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end component;
signal internal_ce : std_logic;
begin
internal_ce <= ce and en;
srl_delay: if (reg_retiming = 0) or (latency < 1) generate
synth_reg_srl_inst : synth_reg
generic map (
width => width,
latency => latency)
port map (
i => d,
ce => internal_ce,
clr => '0',
clk => clk,
o => q);
end generate srl_delay;
reg_delay: if (reg_retiming = 1) and (latency >= 1) generate
synth_reg_reg_inst : synth_reg_reg
generic map (
width => width,
latency => latency)
port map (
i => d,
ce => internal_ce,
clr => '0',
clk => clk,
o => q);
end generate reg_delay;
end architecture behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity logical_4ad38e8aed is
port (
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
d2 : in std_logic_vector((1 - 1) downto 0);
d3 : in std_logic_vector((1 - 1) downto 0);
d4 : in std_logic_vector((1 - 1) downto 0);
d5 : in std_logic_vector((1 - 1) downto 0);
d6 : in std_logic_vector((1 - 1) downto 0);
d7 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end logical_4ad38e8aed;
architecture behavior of logical_4ad38e8aed is
signal d0_1_24: std_logic_vector((1 - 1) downto 0);
signal d1_1_27: std_logic_vector((1 - 1) downto 0);
signal d2_1_30: std_logic_vector((1 - 1) downto 0);
signal d3_1_33: std_logic_vector((1 - 1) downto 0);
signal d4_1_36: std_logic_vector((1 - 1) downto 0);
signal d5_1_39: std_logic_vector((1 - 1) downto 0);
signal d6_1_42: std_logic_vector((1 - 1) downto 0);
signal d7_1_45: std_logic_vector((1 - 1) downto 0);
signal fully_2_1_bit: std_logic_vector((1 - 1) downto 0);
begin
d0_1_24 <= d0;
d1_1_27 <= d1;
d2_1_30 <= d2;
d3_1_33 <= d3;
d4_1_36 <= d4;
d5_1_39 <= d5;
d6_1_42 <= d6;
d7_1_45 <= d7;
fully_2_1_bit <= d0_1_24 or d1_1_27 or d2_1_30 or d3_1_33 or d4_1_36 or d5_1_39 or d6_1_42 or d7_1_45;
y <= fully_2_1_bit;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_2b3acb49f4 is
port (
in0 : in std_logic_vector((1 - 1) downto 0);
in1 : in std_logic_vector((1 - 1) downto 0);
in2 : in std_logic_vector((1 - 1) downto 0);
in3 : in std_logic_vector((1 - 1) downto 0);
in4 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((5 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end concat_2b3acb49f4;
architecture behavior of concat_2b3acb49f4 is
signal in0_1_23: unsigned((1 - 1) downto 0);
signal in1_1_27: unsigned((1 - 1) downto 0);
signal in2_1_31: unsigned((1 - 1) downto 0);
signal in3_1_35: unsigned((1 - 1) downto 0);
signal in4_1_39: unsigned((1 - 1) downto 0);
signal y_2_1_concat: unsigned((5 - 1) downto 0);
begin
in0_1_23 <= std_logic_vector_to_unsigned(in0);
in1_1_27 <= std_logic_vector_to_unsigned(in1);
in2_1_31 <= std_logic_vector_to_unsigned(in2);
in3_1_35 <= std_logic_vector_to_unsigned(in3);
in4_1_39 <= std_logic_vector_to_unsigned(in4);
y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & unsigned_to_std_logic_vector(in2_1_31) & unsigned_to_std_logic_vector(in3_1_35) & unsigned_to_std_logic_vector(in4_1_39));
y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_6293007044 is
port (
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_6293007044;
architecture behavior of constant_6293007044 is
begin
op <= "1";
end behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.conv_pkg.all;
entity xlslice is
generic (
new_msb : integer := 9;
new_lsb : integer := 1;
x_width : integer := 16;
y_width : integer := 8);
port (
x : in std_logic_vector (x_width-1 downto 0);
y : out std_logic_vector (y_width-1 downto 0));
end xlslice;
architecture behavior of xlslice is
begin
y <= x(new_msb downto new_lsb);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_37567836aa is
port (
op : out std_logic_vector((32 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_37567836aa;
architecture behavior of constant_37567836aa is
begin
op <= "00000000000000000000000000000000";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_2c45f290ed is
port (
sel : in std_logic_vector((1 - 1) downto 0);
d0 : in std_logic_vector((16 - 1) downto 0);
d1 : in std_logic_vector((16 - 1) downto 0);
y : out std_logic_vector((16 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_2c45f290ed;
architecture behavior of mux_2c45f290ed is
signal sel_1_20: std_logic_vector((1 - 1) downto 0);
signal d0_1_24: std_logic_vector((16 - 1) downto 0);
signal d1_1_27: std_logic_vector((16 - 1) downto 0);
signal unregy_join_6_1: std_logic_vector((16 - 1) downto 0);
begin
sel_1_20 <= sel;
d0_1_24 <= d0;
d1_1_27 <= d1;
proc_switch_6_1: process (d0_1_24, d1_1_27, sel_1_20)
is
begin
case sel_1_20 is
when "0" =>
unregy_join_6_1 <= d0_1_24;
when others =>
unregy_join_6_1 <= d1_1_27;
end case;
end process proc_switch_6_1;
y <= unregy_join_6_1;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity logical_b1e9d7c303 is
port (
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end logical_b1e9d7c303;
architecture behavior of logical_b1e9d7c303 is
signal d0_1_24: std_logic_vector((1 - 1) downto 0);
signal d1_1_27: std_logic_vector((1 - 1) downto 0);
signal bit_2_26: std_logic_vector((1 - 1) downto 0);
signal fully_2_1_bitnot: std_logic_vector((1 - 1) downto 0);
begin
d0_1_24 <= d0;
d1_1_27 <= d1;
bit_2_26 <= d0_1_24 or d1_1_27;
fully_2_1_bitnot <= not bit_2_26;
y <= fully_2_1_bitnot;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity accum_2cb0e56e96 is
port (
b : in std_logic_vector((1 - 1) downto 0);
rst : in std_logic_vector((1 - 1) downto 0);
en : in std_logic_vector((1 - 1) downto 0);
q : out std_logic_vector((7 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end accum_2cb0e56e96;
architecture behavior of accum_2cb0e56e96 is
signal b_17_24: unsigned((1 - 1) downto 0);
signal rst_17_27: boolean;
signal en_17_32: boolean;
signal accum_reg_41_23: unsigned((7 - 1) downto 0) := "0000000";
signal accum_reg_41_23_rst: std_logic;
signal accum_reg_41_23_en: std_logic;
signal cast_51_42: unsigned((7 - 1) downto 0);
signal accum_reg_join_47_1: unsigned((8 - 1) downto 0);
signal accum_reg_join_47_1_en: std_logic;
signal accum_reg_join_47_1_rst: std_logic;
begin
b_17_24 <= std_logic_vector_to_unsigned(b);
rst_17_27 <= ((rst) = "1");
en_17_32 <= ((en) = "1");
proc_accum_reg_41_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (accum_reg_41_23_rst = '1')) then
accum_reg_41_23 <= "0000000";
elsif ((ce = '1') and (accum_reg_41_23_en = '1')) then
accum_reg_41_23 <= accum_reg_41_23 + cast_51_42;
end if;
end if;
end process proc_accum_reg_41_23;
cast_51_42 <= u2u_cast(b_17_24, 0, 7, 0);
proc_if_47_1: process (accum_reg_41_23, cast_51_42, en_17_32, rst_17_27)
is
begin
if rst_17_27 then
accum_reg_join_47_1_rst <= '1';
elsif en_17_32 then
accum_reg_join_47_1_rst <= '0';
else
accum_reg_join_47_1_rst <= '0';
end if;
if en_17_32 then
accum_reg_join_47_1_en <= '1';
else
accum_reg_join_47_1_en <= '0';
end if;
end process proc_if_47_1;
accum_reg_41_23_rst <= accum_reg_join_47_1_rst;
accum_reg_41_23_en <= accum_reg_join_47_1_en;
q <= unsigned_to_std_logic_vector(accum_reg_41_23);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity accum_be45dd0aa2 is
port (
b : in std_logic_vector((1 - 1) downto 0);
rst : in std_logic_vector((1 - 1) downto 0);
q : out std_logic_vector((4 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end accum_be45dd0aa2;
architecture behavior of accum_be45dd0aa2 is
signal b_17_24: unsigned((1 - 1) downto 0);
signal rst_17_27: boolean;
signal accum_reg_41_23: unsigned((4 - 1) downto 0) := "0000";
signal accum_reg_41_23_rst: std_logic;
signal cast_51_42: unsigned((4 - 1) downto 0);
signal accum_reg_join_47_1: unsigned((5 - 1) downto 0);
signal accum_reg_join_47_1_rst: std_logic;
begin
b_17_24 <= std_logic_vector_to_unsigned(b);
rst_17_27 <= ((rst) = "1");
proc_accum_reg_41_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (accum_reg_41_23_rst = '1')) then
accum_reg_41_23 <= "0000";
elsif (ce = '1') then
accum_reg_41_23 <= accum_reg_41_23 + cast_51_42;
end if;
end if;
end process proc_accum_reg_41_23;
cast_51_42 <= u2u_cast(b_17_24, 0, 4, 0);
proc_if_47_1: process (accum_reg_41_23, cast_51_42, rst_17_27)
is
begin
if rst_17_27 then
accum_reg_join_47_1_rst <= '1';
else
accum_reg_join_47_1_rst <= '0';
end if;
end process proc_if_47_1;
accum_reg_41_23_rst <= accum_reg_join_47_1_rst;
q <= unsigned_to_std_logic_vector(accum_reg_41_23);
end behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library XilinxCoreLib;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.conv_pkg.all;
entity xladdsub is
generic (
core_name0: string := "";
a_width: integer := 16;
a_bin_pt: integer := 4;
a_arith: integer := xlUnsigned;
c_in_width: integer := 16;
c_in_bin_pt: integer := 4;
c_in_arith: integer := xlUnsigned;
c_out_width: integer := 16;
c_out_bin_pt: integer := 4;
c_out_arith: integer := xlUnsigned;
b_width: integer := 8;
b_bin_pt: integer := 2;
b_arith: integer := xlUnsigned;
s_width: integer := 17;
s_bin_pt: integer := 4;
s_arith: integer := xlUnsigned;
rst_width: integer := 1;
rst_bin_pt: integer := 0;
rst_arith: integer := xlUnsigned;
en_width: integer := 1;
en_bin_pt: integer := 0;
en_arith: integer := xlUnsigned;
full_s_width: integer := 17;
full_s_arith: integer := xlUnsigned;
mode: integer := xlAddMode;
extra_registers: integer := 0;
latency: integer := 0;
quantization: integer := xlTruncate;
overflow: integer := xlWrap;
c_latency: integer := 0;
c_output_width: integer := 17;
c_has_q : integer := 1;
c_has_s : integer := 0;
c_has_c_out : integer := 0;
c_has_q_c_out : integer := 0;
c_has_b_out : integer := 0;
c_has_q_b_out : integer := 0;
c_has_q_ovfl : integer := 0;
c_has_ovfl : integer := 0
);
port (
a: in std_logic_vector(a_width - 1 downto 0);
b: in std_logic_vector(b_width - 1 downto 0);
c_in : in std_logic_vector (0 downto 0) := "0";
ce: in std_logic;
clr: in std_logic := '0';
clk: in std_logic;
rst: in std_logic_vector(rst_width - 1 downto 0) := "0";
en: in std_logic_vector(en_width - 1 downto 0) := "1";
c_out : out std_logic_vector (0 downto 0);
s: out std_logic_vector(s_width - 1 downto 0)
);
end xladdsub ;
architecture behavior of xladdsub is
component synth_reg
generic (
width: integer := 16;
latency: integer := 5
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
function format_input(inp: std_logic_vector; old_width, delta, new_arith,
new_width: integer)
return std_logic_vector
is
variable vec: std_logic_vector(old_width-1 downto 0);
variable padded_inp: std_logic_vector((old_width + delta)-1 downto 0);
variable result: std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if delta > 0 then
padded_inp := pad_LSB(vec, old_width+delta);
result := extend_MSB(padded_inp, new_width, new_arith);
else
result := extend_MSB(vec, new_width, new_arith);
end if;
return result;
end;
constant full_s_bin_pt: integer := fractional_bits(a_bin_pt, b_bin_pt);
constant full_a_width: integer := full_s_width;
constant full_b_width: integer := full_s_width;
signal full_a: std_logic_vector(full_a_width - 1 downto 0);
signal full_b: std_logic_vector(full_b_width - 1 downto 0);
signal core_s: std_logic_vector(full_s_width - 1 downto 0);
signal conv_s: std_logic_vector(s_width - 1 downto 0);
signal temp_cout : std_logic;
signal internal_clr: std_logic;
signal internal_ce: std_logic;
signal extra_reg_ce: std_logic;
signal override: std_logic;
signal logic1: std_logic_vector(0 downto 0);
component adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3
port (
a: in std_logic_vector( 9 - 1 downto 0);
s: out std_logic_vector(c_output_width - 1 downto 0);
b: in std_logic_vector(9 - 1 downto 0)
);
end component;
attribute syn_black_box of adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3:
component is true;
attribute fpga_dont_touch of adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3:
component is "true";
attribute box_type of adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3:
component is "black_box";
component adder_subtracter_virtex2p_7_0_453ed16ba8e84295
port (
a: in std_logic_vector( 9 - 1 downto 0);
s: out std_logic_vector(c_output_width - 1 downto 0);
b: in std_logic_vector(9 - 1 downto 0)
);
end component;
attribute syn_black_box of adder_subtracter_virtex2p_7_0_453ed16ba8e84295:
component is true;
attribute fpga_dont_touch of adder_subtracter_virtex2p_7_0_453ed16ba8e84295:
component is "true";
attribute box_type of adder_subtracter_virtex2p_7_0_453ed16ba8e84295:
component is "black_box";
component adder_subtracter_virtex2p_7_0_7182743c9e7adf5e
port (
a: in std_logic_vector( 5 - 1 downto 0);
s: out std_logic_vector(c_output_width - 1 downto 0);
b: in std_logic_vector(5 - 1 downto 0)
);
end component;
attribute syn_black_box of adder_subtracter_virtex2p_7_0_7182743c9e7adf5e:
component is true;
attribute fpga_dont_touch of adder_subtracter_virtex2p_7_0_7182743c9e7adf5e:
component is "true";
attribute box_type of adder_subtracter_virtex2p_7_0_7182743c9e7adf5e:
component is "black_box";
begin
internal_clr <= (clr or (rst(0))) and ce;
internal_ce <= ce and en(0);
logic1(0) <= '1';
addsub_process: process(a, b, core_s)
begin
full_a <= format_input(a, a_width, b_bin_pt - a_bin_pt, a_arith,
full_a_width);
full_b <= format_input(b, b_width, a_bin_pt - b_bin_pt, b_arith,
full_b_width);
conv_s <= convert_type(core_s, full_s_width, full_s_bin_pt, full_s_arith,
s_width, s_bin_pt, s_arith, quantization, overflow);
end process addsub_process;
comp0: if ((core_name0 = "adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3")) generate
core_instance0: adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3
port map (
a => full_a,
s => core_s,
b => full_b
);
end generate;
comp1: if ((core_name0 = "adder_subtracter_virtex2p_7_0_453ed16ba8e84295")) generate
core_instance1: adder_subtracter_virtex2p_7_0_453ed16ba8e84295
port map (
a => full_a,
s => core_s,
b => full_b
);
end generate;
comp2: if ((core_name0 = "adder_subtracter_virtex2p_7_0_7182743c9e7adf5e")) generate
core_instance2: adder_subtracter_virtex2p_7_0_7182743c9e7adf5e
port map (
a => full_a,
s => core_s,
b => full_b
);
end generate;
latency_test: if (extra_registers > 0) generate
override_test: if (c_latency > 1) generate
override_pipe: synth_reg
generic map (
width => 1,
latency => c_latency)
port map (
i => logic1,
ce => internal_ce,
clr => internal_clr,
clk => clk,
o(0) => override);
extra_reg_ce <= ce and en(0) and override;
end generate override_test;
no_override: if (c_latency = 0) or (c_latency = 1) generate
extra_reg_ce <= ce and en(0);
end generate no_override;
extra_reg: synth_reg
generic map (
width => s_width,
latency => extra_registers
)
port map (
i => conv_s,
ce => extra_reg_ce,
clr => internal_clr,
clk => clk,
o => s
);
cout_test : if((c_has_c_out = 1) or
(c_has_b_out = 1) or
(c_has_q_c_out = 1) or
(c_has_q_b_out = 1)) generate
c_out_extra_reg: synth_reg
generic map (
width => 1,
latency => extra_registers
)
port map (
i(0) => temp_cout,
ce => extra_reg_ce,
clr => internal_clr,
clk => clk,
o => c_out
);
end generate cout_test;
end generate;
latency_s: if ((latency = 0) or (extra_registers = 0)) generate
s <= conv_s;
end generate latency_s;
latency0: if ( ((latency = 0) or (extra_registers = 0)) and
((c_has_b_out = 1) or
(c_has_q_c_out = 1) or
(c_has_c_out = 1) or
(c_has_q_b_out = 1))) generate
c_out(0) <= temp_cout;
end generate latency0;
tie_dangling_cout: if ((c_has_c_out = 0) and
(c_has_b_out = 0) and
(c_has_q_c_out = 0) and
(c_has_q_b_out = 0)) generate
c_out <= "0";
end generate tie_dangling_cout;
end architecture behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_f62149b02a is
port (
in0 : in std_logic_vector((2 - 1) downto 0);
in1 : in std_logic_vector((7 - 1) downto 0);
y : out std_logic_vector((9 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end concat_f62149b02a;
architecture behavior of concat_f62149b02a is
signal in0_1_23: unsigned((2 - 1) downto 0);
signal in1_1_27: unsigned((7 - 1) downto 0);
signal y_2_1_concat: unsigned((9 - 1) downto 0);
begin
in0_1_23 <= std_logic_vector_to_unsigned(in0);
in1_1_27 <= std_logic_vector_to_unsigned(in1);
y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27));
y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_1ece14600f is
port (
in0 : in std_logic_vector((1 - 1) downto 0);
in1 : in std_logic_vector((8 - 1) downto 0);
y : out std_logic_vector((9 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end concat_1ece14600f;
architecture behavior of concat_1ece14600f is
signal in0_1_23: unsigned((1 - 1) downto 0);
signal in1_1_27: unsigned((8 - 1) downto 0);
signal y_2_1_concat: unsigned((9 - 1) downto 0);
begin
in0_1_23 <= std_logic_vector_to_unsigned(in0);
in1_1_27 <= std_logic_vector_to_unsigned(in1);
y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27));
y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_443ed96427 is
port (
op : out std_logic_vector((9 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_443ed96427;
architecture behavior of constant_443ed96427 is
begin
op <= "101011100";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_145086465d is
port (
op : out std_logic_vector((4 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_145086465d;
architecture behavior of constant_145086465d is
begin
op <= "1000";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_fb9f6d3796 is
port (
op : out std_logic_vector((9 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_fb9f6d3796;
architecture behavior of constant_fb9f6d3796 is
begin
op <= "100010101";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_09a4afb2ee is
port (
op : out std_logic_vector((9 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_09a4afb2ee;
architecture behavior of constant_09a4afb2ee is
begin
op <= "101110101";
end behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library XilinxCoreLib;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity xlcounter_limit is
generic (
core_name0: string := "";
op_width: integer := 5;
op_arith: integer := xlSigned;
cnt_63_48: integer:= 0;
cnt_47_32: integer:= 0;
cnt_31_16: integer:= 0;
cnt_15_0: integer:= 0;
count_limited: integer := 0
);
port (
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
op: out std_logic_vector(op_width - 1 downto 0);
up: in std_logic_vector(0 downto 0) := (others => '0');
en: in std_logic_vector(0 downto 0);
rst: in std_logic_vector(0 downto 0)
);
end xlcounter_limit ;
architecture behavior of xlcounter_limit is
signal high_cnt_to: std_logic_vector(31 downto 0);
signal low_cnt_to: std_logic_vector(31 downto 0);
signal cnt_to: std_logic_vector(63 downto 0);
signal core_sinit, op_thresh0, core_ce: std_logic;
signal rst_overrides_en: std_logic;
signal op_net: std_logic_vector(op_width - 1 downto 0);
-- synopsys translate_off
signal real_op : real;
-- synopsys translate_on
function equals(op, cnt_to : std_logic_vector; width, arith : integer)
return std_logic
is
variable signed_op, signed_cnt_to : signed (width - 1 downto 0);
variable unsigned_op, unsigned_cnt_to : unsigned (width - 1 downto 0);
variable result : std_logic;
begin
-- synopsys translate_off
if ((is_XorU(op)) or (is_XorU(cnt_to)) ) then
result := '0';
return result;
end if;
-- synopsys translate_on
if (op = cnt_to) then
result := '1';
else
result := '0';
end if;
return result;
end;
component binary_counter_virtex2p_7_0_32a1863440903b9d
port (
clk: in std_logic;
ce: in std_logic;
sinit: in std_logic;
q: out std_logic_vector(op_width - 1 downto 0)
);
end component;
attribute syn_black_box of binary_counter_virtex2p_7_0_32a1863440903b9d:
component is true;
attribute fpga_dont_touch of binary_counter_virtex2p_7_0_32a1863440903b9d:
component is "true";
attribute box_type of binary_counter_virtex2p_7_0_32a1863440903b9d:
component is "black_box";
component binary_counter_virtex2p_7_0_23542cbcca0efa2e
port (
clk: in std_logic;
ce: in std_logic;
sinit: in std_logic;
q: out std_logic_vector(op_width - 1 downto 0)
);
end component;
attribute syn_black_box of binary_counter_virtex2p_7_0_23542cbcca0efa2e:
component is true;
attribute fpga_dont_touch of binary_counter_virtex2p_7_0_23542cbcca0efa2e:
component is "true";
attribute box_type of binary_counter_virtex2p_7_0_23542cbcca0efa2e:
component is "black_box";
-- synopsys translate_off
constant zeroVec : std_logic_vector(op_width - 1 downto 0) := (others => '0');
constant oneVec : std_logic_vector(op_width - 1 downto 0) := (others => '1');
constant zeroStr : string(1 to op_width) :=
std_logic_vector_to_bin_string(zeroVec);
constant oneStr : string(1 to op_width) :=
std_logic_vector_to_bin_string(oneVec);
-- synopsys translate_on
begin
-- synopsys translate_off
-- synopsys translate_on
cnt_to(63 downto 48) <= integer_to_std_logic_vector(cnt_63_48, 16, op_arith);
cnt_to(47 downto 32) <= integer_to_std_logic_vector(cnt_47_32, 16, op_arith);
cnt_to(31 downto 16) <= integer_to_std_logic_vector(cnt_31_16, 16, op_arith);
cnt_to(15 downto 0) <= integer_to_std_logic_vector(cnt_15_0, 16, op_arith);
op <= op_net;
core_ce <= ce and en(0);
rst_overrides_en <= rst(0) or en(0);
limit : if (count_limited = 1) generate
eq_cnt_to : process (op_net, cnt_to)
begin
op_thresh0 <= equals(op_net, cnt_to(op_width - 1 downto 0),
op_width, op_arith);
end process;
core_sinit <= (op_thresh0 or clr or rst(0)) and ce and rst_overrides_en;
end generate;
no_limit : if (count_limited = 0) generate
core_sinit <= (clr or rst(0)) and ce and rst_overrides_en;
end generate;
comp0: if ((core_name0 = "binary_counter_virtex2p_7_0_32a1863440903b9d")) generate
core_instance0: binary_counter_virtex2p_7_0_32a1863440903b9d
port map (
clk => clk,
ce => core_ce,
sinit => core_sinit,
q => op_net
);
end generate;
comp1: if ((core_name0 = "binary_counter_virtex2p_7_0_23542cbcca0efa2e")) generate
core_instance1: binary_counter_virtex2p_7_0_23542cbcca0efa2e
port map (
clk => clk,
ce => core_ce,
sinit => core_sinit,
q => op_net
);
end generate;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity inverter_e5b38cca3b is
port (
ip : in std_logic_vector((1 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end inverter_e5b38cca3b;
architecture behavior of inverter_e5b38cca3b is
signal ip_1_26: boolean;
type array_type_op_mem_22_20 is array (0 to (1 - 1)) of boolean;
signal op_mem_22_20: array_type_op_mem_22_20 := (
0 => false);
signal op_mem_22_20_front_din: boolean;
signal op_mem_22_20_back: boolean;
signal op_mem_22_20_push_front_pop_back_en: std_logic;
signal internal_ip_12_1_bitnot: boolean;
begin
ip_1_26 <= ((ip) = "1");
op_mem_22_20_back <= op_mem_22_20(0);
proc_op_mem_22_20: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_22_20_push_front_pop_back_en = '1')) then
op_mem_22_20(0) <= op_mem_22_20_front_din;
end if;
end if;
end process proc_op_mem_22_20;
internal_ip_12_1_bitnot <= ((not boolean_to_vector(ip_1_26)) = "1");
op_mem_22_20_push_front_pop_back_en <= '0';
op <= boolean_to_vector(internal_ip_12_1_bitnot);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity logical_aacf6e1b0e is
port (
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end logical_aacf6e1b0e;
architecture behavior of logical_aacf6e1b0e is
signal d0_1_24: std_logic;
signal d1_1_27: std_logic;
signal fully_2_1_bit: std_logic;
begin
d0_1_24 <= d0(0);
d1_1_27 <= d1(0);
fully_2_1_bit <= d0_1_24 or d1_1_27;
y <= std_logic_to_vector(fully_2_1_bit);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity logical_80f90b97d0 is
port (
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end logical_80f90b97d0;
architecture behavior of logical_80f90b97d0 is
signal d0_1_24: std_logic;
signal d1_1_27: std_logic;
signal fully_2_1_bit: std_logic;
begin
d0_1_24 <= d0(0);
d1_1_27 <= d1(0);
fully_2_1_bit <= d0_1_24 and d1_1_27;
y <= std_logic_to_vector(fully_2_1_bit);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_d99e59b6d4 is
port (
sel : in std_logic_vector((1 - 1) downto 0);
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_d99e59b6d4;
architecture behavior of mux_d99e59b6d4 is
signal sel_1_20: std_logic;
signal d0_1_24: std_logic;
signal d1_1_27: std_logic;
signal sel_internal_2_1_convert: std_logic_vector((1 - 1) downto 0);
signal unregy_join_6_1: std_logic;
begin
sel_1_20 <= sel(0);
d0_1_24 <= d0(0);
d1_1_27 <= d1(0);
sel_internal_2_1_convert <= cast(std_logic_to_vector(sel_1_20), 0, 1, 0, xlUnsigned);
proc_switch_6_1: process (d0_1_24, d1_1_27, sel_internal_2_1_convert)
is
begin
case sel_internal_2_1_convert is
when "0" =>
unregy_join_6_1 <= d0_1_24;
when others =>
unregy_join_6_1 <= d1_1_27;
end case;
end process proc_switch_6_1;
y <= std_logic_to_vector(unregy_join_6_1);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_1f00a411aa is
port (
sel : in std_logic_vector((4 - 1) downto 0);
d0 : in std_logic_vector((9 - 1) downto 0);
d1 : in std_logic_vector((9 - 1) downto 0);
d2 : in std_logic_vector((9 - 1) downto 0);
d3 : in std_logic_vector((9 - 1) downto 0);
d4 : in std_logic_vector((9 - 1) downto 0);
d5 : in std_logic_vector((9 - 1) downto 0);
d6 : in std_logic_vector((9 - 1) downto 0);
d7 : in std_logic_vector((9 - 1) downto 0);
d8 : in std_logic_vector((9 - 1) downto 0);
y : out std_logic_vector((9 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_1f00a411aa;
architecture behavior of mux_1f00a411aa is
signal sel_1_20: std_logic_vector((4 - 1) downto 0);
signal d0_1_24: std_logic_vector((9 - 1) downto 0);
signal d1_1_27: std_logic_vector((9 - 1) downto 0);
signal d2_1_30: std_logic_vector((9 - 1) downto 0);
signal d3_1_33: std_logic_vector((9 - 1) downto 0);
signal d4_1_36: std_logic_vector((9 - 1) downto 0);
signal d5_1_39: std_logic_vector((9 - 1) downto 0);
signal d6_1_42: std_logic_vector((9 - 1) downto 0);
signal d7_1_45: std_logic_vector((9 - 1) downto 0);
signal d8_1_48: std_logic_vector((9 - 1) downto 0);
signal unregy_join_6_1: std_logic_vector((9 - 1) downto 0);
begin
sel_1_20 <= sel;
d0_1_24 <= d0;
d1_1_27 <= d1;
d2_1_30 <= d2;
d3_1_33 <= d3;
d4_1_36 <= d4;
d5_1_39 <= d5;
d6_1_42 <= d6;
d7_1_45 <= d7;
d8_1_48 <= d8;
proc_switch_6_1: process (d0_1_24, d1_1_27, d2_1_30, d3_1_33, d4_1_36, d5_1_39, d6_1_42, d7_1_45, d8_1_48, sel_1_20)
is
begin
case sel_1_20 is
when "0000" =>
unregy_join_6_1 <= d0_1_24;
when "0001" =>
unregy_join_6_1 <= d1_1_27;
when "0010" =>
unregy_join_6_1 <= d2_1_30;
when "0011" =>
unregy_join_6_1 <= d3_1_33;
when "0100" =>
unregy_join_6_1 <= d4_1_36;
when "0101" =>
unregy_join_6_1 <= d5_1_39;
when "0110" =>
unregy_join_6_1 <= d6_1_42;
when "0111" =>
unregy_join_6_1 <= d7_1_45;
when others =>
unregy_join_6_1 <= d8_1_48;
end case;
end process proc_switch_6_1;
y <= unregy_join_6_1;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity relational_92c392c8b6 is
port (
a : in std_logic_vector((7 - 1) downto 0);
b : in std_logic_vector((9 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end relational_92c392c8b6;
architecture behavior of relational_92c392c8b6 is
signal a_1_31: unsigned((7 - 1) downto 0);
signal b_1_34: signed((9 - 1) downto 0);
type array_type_op_mem_32_22 is array (0 to (1 - 1)) of boolean;
signal op_mem_32_22: array_type_op_mem_32_22 := (
0 => false);
signal op_mem_32_22_front_din: boolean;
signal op_mem_32_22_back: boolean;
signal op_mem_32_22_push_front_pop_back_en: std_logic;
signal cast_20_12: signed((9 - 1) downto 0);
signal result_20_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_unsigned(a);
b_1_34 <= std_logic_vector_to_signed(b);
op_mem_32_22_back <= op_mem_32_22(0);
proc_op_mem_32_22: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_32_22_push_front_pop_back_en = '1')) then
op_mem_32_22(0) <= op_mem_32_22_front_din;
end if;
end if;
end process proc_op_mem_32_22;
cast_20_12 <= u2s_cast(a_1_31, 0, 9, 0);
result_20_3_rel <= cast_20_12 <= b_1_34;
op_mem_32_22_front_din <= result_20_3_rel;
op_mem_32_22_push_front_pop_back_en <= '1';
op <= boolean_to_vector(op_mem_32_22_back);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity relational_fb96203f91 is
port (
a : in std_logic_vector((4 - 1) downto 0);
b : in std_logic_vector((4 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end relational_fb96203f91;
architecture behavior of relational_fb96203f91 is
signal a_1_31: unsigned((4 - 1) downto 0);
signal b_1_34: unsigned((4 - 1) downto 0);
signal result_16_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_unsigned(a);
b_1_34 <= std_logic_vector_to_unsigned(b);
result_16_3_rel <= a_1_31 < b_1_34;
op <= boolean_to_vector(result_16_3_rel);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_998e20a1ca is
port (
sel : in std_logic_vector((2 - 1) downto 0);
d0 : in std_logic_vector((8 - 1) downto 0);
d1 : in std_logic_vector((8 - 1) downto 0);
d2 : in std_logic_vector((8 - 1) downto 0);
d3 : in std_logic_vector((8 - 1) downto 0);
y : out std_logic_vector((8 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_998e20a1ca;
architecture behavior of mux_998e20a1ca is
signal sel_1_20: std_logic_vector((2 - 1) downto 0);
signal d0_1_24: std_logic_vector((8 - 1) downto 0);
signal d1_1_27: std_logic_vector((8 - 1) downto 0);
signal d2_1_30: std_logic_vector((8 - 1) downto 0);
signal d3_1_33: std_logic_vector((8 - 1) downto 0);
signal unregy_join_6_1: std_logic_vector((8 - 1) downto 0);
begin
sel_1_20 <= sel;
d0_1_24 <= d0;
d1_1_27 <= d1;
d2_1_30 <= d2;
d3_1_33 <= d3;
proc_switch_6_1: process (d0_1_24, d1_1_27, d2_1_30, d3_1_33, sel_1_20)
is
begin
case sel_1_20 is
when "00" =>
unregy_join_6_1 <= d0_1_24;
when "01" =>
unregy_join_6_1 <= d1_1_27;
when "10" =>
unregy_join_6_1 <= d2_1_30;
when others =>
unregy_join_6_1 <= d3_1_33;
end case;
end process proc_switch_6_1;
y <= unregy_join_6_1;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_32864ba5d6 is
port (
in0 : in std_logic_vector((4 - 1) downto 0);
in1 : in std_logic_vector((3 - 1) downto 0);
y : out std_logic_vector((7 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end concat_32864ba5d6;
architecture behavior of concat_32864ba5d6 is
signal in0_1_23: unsigned((4 - 1) downto 0);
signal in1_1_27: unsigned((3 - 1) downto 0);
signal y_2_1_concat: unsigned((7 - 1) downto 0);
begin
in0_1_23 <= std_logic_vector_to_unsigned(in0);
in1_1_27 <= std_logic_vector_to_unsigned(in1);
y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27));
y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_822933f89b is
port (
op : out std_logic_vector((3 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_822933f89b;
architecture behavior of constant_822933f89b is
begin
op <= "000";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_21d4a28b7e is
port (
op : out std_logic_vector((8 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_21d4a28b7e;
architecture behavior of constant_21d4a28b7e is
begin
op <= "00000011";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_b940b9054a is
port (
op : out std_logic_vector((8 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_b940b9054a;
architecture behavior of constant_b940b9054a is
begin
op <= "00001010";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_78218439f3 is
port (
in0 : in std_logic_vector((3 - 1) downto 0);
in1 : in std_logic_vector((4 - 1) downto 0);
in2 : in std_logic_vector((4 - 1) downto 0);
y : out std_logic_vector((11 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end concat_78218439f3;
architecture behavior of concat_78218439f3 is
signal in0_1_23: unsigned((3 - 1) downto 0);
signal in1_1_27: unsigned((4 - 1) downto 0);
signal in2_1_31: unsigned((4 - 1) downto 0);
signal y_2_1_concat: unsigned((11 - 1) downto 0);
begin
in0_1_23 <= std_logic_vector_to_unsigned(in0);
in1_1_27 <= std_logic_vector_to_unsigned(in1);
in2_1_31 <= std_logic_vector_to_unsigned(in2);
y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & unsigned_to_std_logic_vector(in2_1_31));
y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_25ab81b400 is
port (
in0 : in std_logic_vector((8 - 1) downto 0);
in1 : in std_logic_vector((6 - 1) downto 0);
y : out std_logic_vector((14 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end concat_25ab81b400;
architecture behavior of concat_25ab81b400 is
signal in0_1_23: unsigned((8 - 1) downto 0);
signal in1_1_27: unsigned((6 - 1) downto 0);
signal y_2_1_concat: unsigned((14 - 1) downto 0);
begin
in0_1_23 <= std_logic_vector_to_unsigned(in0);
in1_1_27 <= std_logic_vector_to_unsigned(in1);
y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27));
y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_e6f5ee726b is
port (
in0 : in std_logic_vector((1 - 1) downto 0);
in1 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((2 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end concat_e6f5ee726b;
architecture behavior of concat_e6f5ee726b is
signal in0_1_23: unsigned((1 - 1) downto 0);
signal in1_1_27: unsigned((1 - 1) downto 0);
signal y_2_1_concat: unsigned((2 - 1) downto 0);
begin
in0_1_23 <= std_logic_vector_to_unsigned(in0);
in1_1_27 <= std_logic_vector_to_unsigned(in1);
y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27));
y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_469094441c is
port (
op : out std_logic_vector((3 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_469094441c;
architecture behavior of constant_469094441c is
begin
op <= "100";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_a1c496ea88 is
port (
op : out std_logic_vector((3 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_a1c496ea88;
architecture behavior of constant_a1c496ea88 is
begin
op <= "001";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_2ec2057ae3 is
port (
sel : in std_logic_vector((2 - 1) downto 0);
d0 : in std_logic_vector((3 - 1) downto 0);
d1 : in std_logic_vector((3 - 1) downto 0);
d2 : in std_logic_vector((3 - 1) downto 0);
d3 : in std_logic_vector((3 - 1) downto 0);
y : out std_logic_vector((3 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_2ec2057ae3;
architecture behavior of mux_2ec2057ae3 is
signal sel_1_20: std_logic_vector((2 - 1) downto 0);
signal d0_1_24: std_logic_vector((3 - 1) downto 0);
signal d1_1_27: std_logic_vector((3 - 1) downto 0);
signal d2_1_30: std_logic_vector((3 - 1) downto 0);
signal d3_1_33: std_logic_vector((3 - 1) downto 0);
signal unregy_join_6_1: std_logic_vector((3 - 1) downto 0);
begin
sel_1_20 <= sel;
d0_1_24 <= d0;
d1_1_27 <= d1;
d2_1_30 <= d2;
d3_1_33 <= d3;
proc_switch_6_1: process (d0_1_24, d1_1_27, d2_1_30, d3_1_33, sel_1_20)
is
begin
case sel_1_20 is
when "00" =>
unregy_join_6_1 <= d0_1_24;
when "01" =>
unregy_join_6_1 <= d1_1_27;
when "10" =>
unregy_join_6_1 <= d2_1_30;
when others =>
unregy_join_6_1 <= d3_1_33;
end case;
end process proc_switch_6_1;
y <= unregy_join_6_1;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_7586447000 is
port (
sel : in std_logic_vector((3 - 1) downto 0);
d0 : in std_logic_vector((9 - 1) downto 0);
d1 : in std_logic_vector((9 - 1) downto 0);
d2 : in std_logic_vector((9 - 1) downto 0);
d3 : in std_logic_vector((9 - 1) downto 0);
d4 : in std_logic_vector((9 - 1) downto 0);
d5 : in std_logic_vector((9 - 1) downto 0);
d6 : in std_logic_vector((9 - 1) downto 0);
d7 : in std_logic_vector((9 - 1) downto 0);
y : out std_logic_vector((9 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_7586447000;
architecture behavior of mux_7586447000 is
signal sel_1_20: std_logic_vector((3 - 1) downto 0);
signal d0_1_24: std_logic_vector((9 - 1) downto 0);
signal d1_1_27: std_logic_vector((9 - 1) downto 0);
signal d2_1_30: std_logic_vector((9 - 1) downto 0);
signal d3_1_33: std_logic_vector((9 - 1) downto 0);
signal d4_1_36: std_logic_vector((9 - 1) downto 0);
signal d5_1_39: std_logic_vector((9 - 1) downto 0);
signal d6_1_42: std_logic_vector((9 - 1) downto 0);
signal d7_1_45: std_logic_vector((9 - 1) downto 0);
signal unregy_join_6_1: std_logic_vector((9 - 1) downto 0);
begin
sel_1_20 <= sel;
d0_1_24 <= d0;
d1_1_27 <= d1;
d2_1_30 <= d2;
d3_1_33 <= d3;
d4_1_36 <= d4;
d5_1_39 <= d5;
d6_1_42 <= d6;
d7_1_45 <= d7;
proc_switch_6_1: process (d0_1_24, d1_1_27, d2_1_30, d3_1_33, d4_1_36, d5_1_39, d6_1_42, d7_1_45, sel_1_20)
is
begin
case sel_1_20 is
when "000" =>
unregy_join_6_1 <= d0_1_24;
when "001" =>
unregy_join_6_1 <= d1_1_27;
when "010" =>
unregy_join_6_1 <= d2_1_30;
when "011" =>
unregy_join_6_1 <= d3_1_33;
when "100" =>
unregy_join_6_1 <= d4_1_36;
when "101" =>
unregy_join_6_1 <= d5_1_39;
when "110" =>
unregy_join_6_1 <= d6_1_42;
when others =>
unregy_join_6_1 <= d7_1_45;
end case;
end process proc_switch_6_1;
y <= unregy_join_6_1;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity relational_f7cb2b0c31 is
port (
a : in std_logic_vector((6 - 1) downto 0);
b : in std_logic_vector((1 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end relational_f7cb2b0c31;
architecture behavior of relational_f7cb2b0c31 is
signal a_1_31: unsigned((6 - 1) downto 0);
signal b_1_34: unsigned((1 - 1) downto 0);
signal cast_12_17: unsigned((6 - 1) downto 0);
signal result_12_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_unsigned(a);
b_1_34 <= std_logic_vector_to_unsigned(b);
cast_12_17 <= u2u_cast(b_1_34, 0, 6, 0);
result_12_3_rel <= a_1_31 = cast_12_17;
op <= boolean_to_vector(result_12_3_rel);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity relational_ee03197e2c is
port (
a : in std_logic_vector((4 - 1) downto 0);
b : in std_logic_vector((1 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end relational_ee03197e2c;
architecture behavior of relational_ee03197e2c is
signal a_1_31: unsigned((4 - 1) downto 0);
signal b_1_34: unsigned((1 - 1) downto 0);
signal cast_12_17: unsigned((4 - 1) downto 0);
signal result_12_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_unsigned(a);
b_1_34 <= std_logic_vector_to_unsigned(b);
cast_12_17 <= u2u_cast(b_1_34, 0, 4, 0);
result_12_3_rel <= a_1_31 = cast_12_17;
op <= boolean_to_vector(result_12_3_rel);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity relational_04b069dd89 is
port (
a : in std_logic_vector((3 - 1) downto 0);
b : in std_logic_vector((1 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end relational_04b069dd89;
architecture behavior of relational_04b069dd89 is
signal a_1_31: unsigned((3 - 1) downto 0);
signal b_1_34: unsigned((1 - 1) downto 0);
signal cast_12_17: unsigned((3 - 1) downto 0);
signal result_12_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_unsigned(a);
b_1_34 <= std_logic_vector_to_unsigned(b);
cast_12_17 <= u2u_cast(b_1_34, 0, 3, 0);
result_12_3_rel <= a_1_31 = cast_12_17;
op <= boolean_to_vector(result_12_3_rel);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_8e3eece8f2 is
port (
sel : in std_logic_vector((4 - 1) downto 0);
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
d2 : in std_logic_vector((1 - 1) downto 0);
d3 : in std_logic_vector((1 - 1) downto 0);
d4 : in std_logic_vector((1 - 1) downto 0);
d5 : in std_logic_vector((1 - 1) downto 0);
d6 : in std_logic_vector((1 - 1) downto 0);
d7 : in std_logic_vector((1 - 1) downto 0);
d8 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_8e3eece8f2;
architecture behavior of mux_8e3eece8f2 is
signal sel_1_20: std_logic_vector((4 - 1) downto 0);
signal d0_1_24: std_logic_vector((1 - 1) downto 0);
signal d1_1_27: std_logic_vector((1 - 1) downto 0);
signal d2_1_30: std_logic_vector((1 - 1) downto 0);
signal d3_1_33: std_logic_vector((1 - 1) downto 0);
signal d4_1_36: std_logic_vector((1 - 1) downto 0);
signal d5_1_39: std_logic_vector((1 - 1) downto 0);
signal d6_1_42: std_logic_vector((1 - 1) downto 0);
signal d7_1_45: std_logic_vector((1 - 1) downto 0);
signal d8_1_48: std_logic_vector((1 - 1) downto 0);
type array_type_pipe_30_22 is array (0 to (1 - 1)) of std_logic_vector((1 - 1) downto 0);
signal pipe_30_22: array_type_pipe_30_22 := (
0 => "0");
signal pipe_30_22_front_din: std_logic_vector((1 - 1) downto 0);
signal pipe_30_22_back: std_logic_vector((1 - 1) downto 0);
signal pipe_30_22_push_front_pop_back_en: std_logic;
signal unregy_join_6_1: std_logic_vector((1 - 1) downto 0);
begin
sel_1_20 <= sel;
d0_1_24 <= d0;
d1_1_27 <= d1;
d2_1_30 <= d2;
d3_1_33 <= d3;
d4_1_36 <= d4;
d5_1_39 <= d5;
d6_1_42 <= d6;
d7_1_45 <= d7;
d8_1_48 <= d8;
pipe_30_22_back <= pipe_30_22(0);
proc_pipe_30_22: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (pipe_30_22_push_front_pop_back_en = '1')) then
pipe_30_22(0) <= pipe_30_22_front_din;
end if;
end if;
end process proc_pipe_30_22;
proc_switch_6_1: process (d0_1_24, d1_1_27, d2_1_30, d3_1_33, d4_1_36, d5_1_39, d6_1_42, d7_1_45, d8_1_48, sel_1_20)
is
begin
case sel_1_20 is
when "0000" =>
unregy_join_6_1 <= d0_1_24;
when "0001" =>
unregy_join_6_1 <= d1_1_27;
when "0010" =>
unregy_join_6_1 <= d2_1_30;
when "0011" =>
unregy_join_6_1 <= d3_1_33;
when "0100" =>
unregy_join_6_1 <= d4_1_36;
when "0101" =>
unregy_join_6_1 <= d5_1_39;
when "0110" =>
unregy_join_6_1 <= d6_1_42;
when "0111" =>
unregy_join_6_1 <= d7_1_45;
when others =>
unregy_join_6_1 <= d8_1_48;
end case;
end process proc_switch_6_1;
pipe_30_22_front_din <= unregy_join_6_1;
pipe_30_22_push_front_pop_back_en <= '1';
y <= pipe_30_22_back;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity logical_938d99ac11 is
port (
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end logical_938d99ac11;
architecture behavior of logical_938d99ac11 is
signal d0_1_24: std_logic_vector((1 - 1) downto 0);
signal d1_1_27: std_logic_vector((1 - 1) downto 0);
signal fully_2_1_bit: std_logic_vector((1 - 1) downto 0);
begin
d0_1_24 <= d0;
d1_1_27 <= d1;
fully_2_1_bit <= d0_1_24 and d1_1_27;
y <= fully_2_1_bit;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_06590e4008 is
port (
op : out std_logic_vector((4 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_06590e4008;
architecture behavior of constant_06590e4008 is
begin
op <= "1111";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_112ed141f4 is
port (
sel : in std_logic_vector((1 - 1) downto 0);
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_112ed141f4;
architecture behavior of mux_112ed141f4 is
signal sel_1_20: std_logic;
signal d0_1_24: std_logic_vector((1 - 1) downto 0);
signal d1_1_27: std_logic_vector((1 - 1) downto 0);
signal sel_internal_2_1_convert: std_logic_vector((1 - 1) downto 0);
signal unregy_join_6_1: std_logic_vector((1 - 1) downto 0);
begin
sel_1_20 <= sel(0);
d0_1_24 <= d0;
d1_1_27 <= d1;
sel_internal_2_1_convert <= cast(std_logic_to_vector(sel_1_20), 0, 1, 0, xlUnsigned);
proc_switch_6_1: process (d0_1_24, d1_1_27, sel_internal_2_1_convert)
is
begin
case sel_internal_2_1_convert is
when "0" =>
unregy_join_6_1 <= d0_1_24;
when others =>
unregy_join_6_1 <= d1_1_27;
end case;
end process proc_switch_6_1;
y <= unregy_join_6_1;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity logical_3e1f051fb7 is
port (
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end logical_3e1f051fb7;
architecture behavior of logical_3e1f051fb7 is
signal d0_1_24: std_logic_vector((1 - 1) downto 0);
signal d1_1_27: std_logic_vector((1 - 1) downto 0);
signal fully_2_1_bit: std_logic_vector((1 - 1) downto 0);
begin
d0_1_24 <= d0;
d1_1_27 <= d1;
fully_2_1_bit <= d0_1_24 or d1_1_27;
y <= fully_2_1_bit;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_791081a00e is
port (
sel : in std_logic_vector((1 - 1) downto 0);
d0 : in std_logic_vector((9 - 1) downto 0);
d1 : in std_logic_vector((9 - 1) downto 0);
y : out std_logic_vector((9 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_791081a00e;
architecture behavior of mux_791081a00e is
signal sel_1_20: std_logic;
signal d0_1_24: std_logic_vector((9 - 1) downto 0);
signal d1_1_27: std_logic_vector((9 - 1) downto 0);
signal sel_internal_2_1_convert: std_logic_vector((1 - 1) downto 0);
signal unregy_join_6_1: std_logic_vector((9 - 1) downto 0);
begin
sel_1_20 <= sel(0);
d0_1_24 <= d0;
d1_1_27 <= d1;
sel_internal_2_1_convert <= cast(std_logic_to_vector(sel_1_20), 0, 1, 0, xlUnsigned);
proc_switch_6_1: process (d0_1_24, d1_1_27, sel_internal_2_1_convert)
is
begin
case sel_internal_2_1_convert is
when "0" =>
unregy_join_6_1 <= d0_1_24;
when others =>
unregy_join_6_1 <= d1_1_27;
end case;
end process proc_switch_6_1;
y <= unregy_join_6_1;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/Buzzer Controller"
entity buzzer_controller_entity_063692c849 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
from_register: in std_logic_vector(17 downto 0);
from_register1: in std_logic_vector(17 downto 0);
from_register2: in std_logic;
register9_x0: out std_logic
);
end buzzer_controller_entity_063692c849;
architecture structural of buzzer_controller_entity_063692c849 is
signal ce_1_sg_x0: std_logic;
signal clk_1_sg_x0: std_logic;
signal convert_dout_net: std_logic;
signal counter_op_net: std_logic_vector(17 downto 0);
signal from_register1_data_out_net_x0: std_logic_vector(17 downto 0);
signal from_register2_data_out_net_x0: std_logic;
signal from_register_data_out_net_x0: std_logic_vector(17 downto 0);
signal inverter_op_net: std_logic;
signal mult_p_net: std_logic_vector(17 downto 0);
signal register8_q_net: std_logic;
signal register9_q_net_x0: std_logic;
signal relational1_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_1_sg_x0 <= ce_1;
clk_1_sg_x0 <= clk_1;
from_register_data_out_net_x0 <= from_register;
from_register1_data_out_net_x0 <= from_register1;
from_register2_data_out_net_x0 <= from_register2;
register9_x0 <= register9_q_net_x0;
convert: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din(0) => inverter_op_net,
dout(0) => convert_dout_net
);
counter: entity work.xlcounter_free
generic map (
core_name0 => "binary_counter_virtex2p_7_0_950e4ab582797264",
op_arith => xlUnsigned,
op_width => 18
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
en => "1",
rst(0) => relational_op_net,
op => counter_op_net
);
inverter: entity work.inverter_e2b989a05e
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
ip(0) => from_register2_data_out_net_x0,
op(0) => inverter_op_net
);
mult: entity work.xlmult_v9_0
generic map (
a_arith => xlUnsigned,
a_bin_pt => 0,
a_width => 18,
b_arith => xlUnsigned,
b_bin_pt => 18,
b_width => 18,
c_a_type => 1,
c_a_width => 18,
c_b_type => 1,
c_b_width => 18,
c_baat => 18,
c_output_width => 36,
c_type => 1,
core_name0 => "multiplier_virtex2p_10_1_817edd563258bb47",
extra_registers => 0,
multsign => 1,
overflow => 1,
p_arith => xlUnsigned,
p_bin_pt => 0,
p_width => 18,
quantization => 1
)
port map (
a => from_register_data_out_net_x0,
b => from_register1_data_out_net_x0,
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
core_ce => ce_1_sg_x0,
core_clk => clk_1_sg_x0,
core_clr => '1',
en => "1",
rst => "0",
p => mult_p_net
);
register8: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d(0) => relational1_op_net,
en => "1",
rst(0) => convert_dout_net,
q(0) => register8_q_net
);
register9: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d(0) => register8_q_net,
en => "1",
rst => "0",
q(0) => register9_q_net_x0
);
relational: entity work.relational_4e76b03051
port map (
a => counter_op_net,
b => from_register_data_out_net_x0,
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_1433264a0c
port map (
a => counter_op_net,
b => mult_p_net,
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
op(0) => relational1_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/EDK Processor"
entity edk_processor_entity_94deb4def9 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
from_register: in std_logic_vector(1 downto 0);
from_register1: in std_logic_vector(5 downto 0);
from_register2: in std_logic_vector(3 downto 0);
from_register3: in std_logic_vector(4 downto 0);
plb_abus: in std_logic_vector(31 downto 0);
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(31 downto 0);
sg_plb_addrpref: in std_logic_vector(14 downto 0);
shared_memory: in std_logic_vector(31 downto 0);
shared_memory1: in std_logic_vector(31 downto 0);
shared_memory2: in std_logic_vector(31 downto 0);
splb_rst: in std_logic;
to_register: in std_logic_vector(17 downto 0);
to_register1: in std_logic;
to_register10: in std_logic_vector(8 downto 0);
to_register11: in std_logic_vector(3 downto 0);
to_register12: in std_logic_vector(8 downto 0);
to_register13: in std_logic;
to_register14: in std_logic;
to_register15: in std_logic_vector(8 downto 0);
to_register16: in std_logic_vector(8 downto 0);
to_register17: in std_logic_vector(8 downto 0);
to_register18: in std_logic;
to_register19: in std_logic_vector(7 downto 0);
to_register2: in std_logic_vector(17 downto 0);
to_register20: in std_logic_vector(7 downto 0);
to_register3: in std_logic_vector(8 downto 0);
to_register4: in std_logic_vector(3 downto 0);
to_register5: in std_logic_vector(2 downto 0);
to_register6: in std_logic_vector(8 downto 0);
to_register7: in std_logic_vector(1 downto 0);
to_register8: in std_logic;
to_register9: in std_logic_vector(8 downto 0);
constant5_x0: out std_logic;
plb_decode_x0: out std_logic;
plb_decode_x1: out std_logic;
plb_decode_x2: out std_logic;
plb_decode_x3: out std_logic;
plb_decode_x4: out std_logic_vector(31 downto 0);
plb_memmap_x0: out std_logic_vector(17 downto 0);
plb_memmap_x1: out std_logic;
plb_memmap_x10: out std_logic_vector(2 downto 0);
plb_memmap_x11: out std_logic;
plb_memmap_x12: out std_logic_vector(8 downto 0);
plb_memmap_x13: out std_logic;
plb_memmap_x14: out std_logic_vector(1 downto 0);
plb_memmap_x15: out std_logic;
plb_memmap_x16: out std_logic;
plb_memmap_x17: out std_logic;
plb_memmap_x18: out std_logic_vector(8 downto 0);
plb_memmap_x19: out std_logic;
plb_memmap_x2: out std_logic;
plb_memmap_x20: out std_logic_vector(8 downto 0);
plb_memmap_x21: out std_logic;
plb_memmap_x22: out std_logic_vector(3 downto 0);
plb_memmap_x23: out std_logic;
plb_memmap_x24: out std_logic_vector(8 downto 0);
plb_memmap_x25: out std_logic;
plb_memmap_x26: out std_logic;
plb_memmap_x27: out std_logic;
plb_memmap_x28: out std_logic;
plb_memmap_x29: out std_logic;
plb_memmap_x3: out std_logic;
plb_memmap_x30: out std_logic_vector(8 downto 0);
plb_memmap_x31: out std_logic;
plb_memmap_x32: out std_logic_vector(8 downto 0);
plb_memmap_x33: out std_logic;
plb_memmap_x34: out std_logic_vector(8 downto 0);
plb_memmap_x35: out std_logic;
plb_memmap_x36: out std_logic;
plb_memmap_x37: out std_logic;
plb_memmap_x38: out std_logic_vector(7 downto 0);
plb_memmap_x39: out std_logic;
plb_memmap_x4: out std_logic_vector(17 downto 0);
plb_memmap_x40: out std_logic_vector(7 downto 0);
plb_memmap_x41: out std_logic;
plb_memmap_x42: out std_logic_vector(11 downto 0);
plb_memmap_x43: out std_logic_vector(31 downto 0);
plb_memmap_x44: out std_logic;
plb_memmap_x45: out std_logic_vector(8 downto 0);
plb_memmap_x46: out std_logic_vector(31 downto 0);
plb_memmap_x47: out std_logic;
plb_memmap_x48: out std_logic_vector(7 downto 0);
plb_memmap_x49: out std_logic_vector(31 downto 0);
plb_memmap_x5: out std_logic;
plb_memmap_x50: out std_logic;
plb_memmap_x6: out std_logic_vector(8 downto 0);
plb_memmap_x7: out std_logic;
plb_memmap_x8: out std_logic_vector(3 downto 0);
plb_memmap_x9: out std_logic
);
end edk_processor_entity_94deb4def9;
architecture structural of edk_processor_entity_94deb4def9 is
signal bankaddr: std_logic_vector(1 downto 0);
signal buttons_big_dout_x0: std_logic_vector(1 downto 0);
signal buttons_small_dout_x0: std_logic_vector(5 downto 0);
signal buzzer_dutycycle_din_x0: std_logic_vector(17 downto 0);
signal buzzer_dutycycle_dout_x0: std_logic_vector(17 downto 0);
signal buzzer_dutycycle_en_x0: std_logic;
signal buzzer_enable_din_x0: std_logic;
signal buzzer_enable_dout_x0: std_logic;
signal buzzer_enable_en_x0: std_logic;
signal buzzer_period_din_x0: std_logic_vector(17 downto 0);
signal buzzer_period_dout_x0: std_logic_vector(17 downto 0);
signal buzzer_period_en_x0: std_logic;
signal ce_1_sg_x1: std_logic;
signal clk_1_sg_x1: std_logic;
signal dip_switch_dout_x0: std_logic_vector(3 downto 0);
signal lcd_backgroundcolor_din_x0: std_logic_vector(8 downto 0);
signal lcd_backgroundcolor_dout_x0: std_logic_vector(8 downto 0);
signal lcd_backgroundcolor_en_x0: std_logic;
signal lcd_charactermap_addr_x0: std_logic_vector(11 downto 0);
signal lcd_charactermap_din_x0: std_logic_vector(31 downto 0);
signal lcd_charactermap_dout_x0: std_logic_vector(31 downto 0);
signal lcd_charactermap_we_x0: std_logic;
signal lcd_characteroffset_din_x0: std_logic_vector(3 downto 0);
signal lcd_characteroffset_dout_x0: std_logic_vector(3 downto 0);
signal lcd_characteroffset_en_x0: std_logic;
signal lcd_characters_addr_x0: std_logic_vector(8 downto 0);
signal lcd_characters_din_x0: std_logic_vector(31 downto 0);
signal lcd_characters_dout_x0: std_logic_vector(31 downto 0);
signal lcd_characters_we_x0: std_logic;
signal lcd_charactersselect_din_x0: std_logic_vector(2 downto 0);
signal lcd_charactersselect_dout_x0: std_logic_vector(2 downto 0);
signal lcd_charactersselect_en_x0: std_logic;
signal lcd_colset_din_x0: std_logic_vector(8 downto 0);
signal lcd_colset_dout_x0: std_logic_vector(8 downto 0);
signal lcd_colset_en_x0: std_logic;
signal lcd_commands_addr_x0: std_logic_vector(7 downto 0);
signal lcd_commands_din_x0: std_logic_vector(31 downto 0);
signal lcd_commands_dout_x0: std_logic_vector(31 downto 0);
signal lcd_commands_we_x0: std_logic;
signal lcd_configlocation_din_x0: std_logic_vector(1 downto 0);
signal lcd_configlocation_dout_x0: std_logic_vector(1 downto 0);
signal lcd_configlocation_en_x0: std_logic;
signal lcd_dividerselect_din_x0: std_logic;
signal lcd_dividerselect_dout_x0: std_logic;
signal lcd_dividerselect_en_x0: std_logic;
signal lcd_firstend_din_x0: std_logic_vector(8 downto 0);
signal lcd_firstend_dout_x0: std_logic_vector(8 downto 0);
signal lcd_firstend_en_x0: std_logic;
signal lcd_firststart_din_x0: std_logic_vector(8 downto 0);
signal lcd_firststart_dout_x0: std_logic_vector(8 downto 0);
signal lcd_firststart_en_x0: std_logic;
signal lcd_lineoffset_din_x0: std_logic_vector(3 downto 0);
signal lcd_lineoffset_dout_x0: std_logic_vector(3 downto 0);
signal lcd_lineoffset_en_x0: std_logic;
signal lcd_ramwrite_din_x0: std_logic_vector(8 downto 0);
signal lcd_ramwrite_dout_x0: std_logic_vector(8 downto 0);
signal lcd_ramwrite_en_x0: std_logic;
signal lcd_reset_din_x0: std_logic;
signal lcd_reset_dout_x0: std_logic;
signal lcd_reset_en_x0: std_logic;
signal lcd_resetlcd_din_x0: std_logic;
signal lcd_resetlcd_dout_x0: std_logic;
signal lcd_resetlcd_en_x0: std_logic;
signal lcd_rowset_din_x0: std_logic_vector(8 downto 0);
signal lcd_rowset_dout_x0: std_logic_vector(8 downto 0);
signal lcd_rowset_en_x0: std_logic;
signal lcd_secondend_din_x0: std_logic_vector(8 downto 0);
signal lcd_secondend_dout_x0: std_logic_vector(8 downto 0);
signal lcd_secondend_en_x0: std_logic;
signal lcd_secondstart_din_x0: std_logic_vector(8 downto 0);
signal lcd_secondstart_dout_x0: std_logic_vector(8 downto 0);
signal lcd_secondstart_en_x0: std_logic;
signal lcd_send_din_x0: std_logic;
signal lcd_send_dout_x0: std_logic;
signal lcd_send_en_x0: std_logic;
signal lcd_totalcmdtransfer_din_x0: std_logic_vector(7 downto 0);
signal lcd_totalcmdtransfer_dout_x0: std_logic_vector(7 downto 0);
signal lcd_totalcmdtransfer_en_x0: std_logic;
signal leds_din_x0: std_logic_vector(7 downto 0);
signal leds_dout_x0: std_logic_vector(7 downto 0);
signal leds_en_x0: std_logic;
signal linearaddr: std_logic_vector(12 downto 0);
signal plb_abus_net_x0: std_logic_vector(31 downto 0);
signal plb_pavalid_net_x0: std_logic;
signal plb_rnw_net_x0: std_logic;
signal plb_wrdbus_net_x0: std_logic_vector(31 downto 0);
signal rddata: std_logic_vector(31 downto 0);
signal rnwreg: std_logic;
signal sg_plb_addrpref_net_x0: std_logic_vector(14 downto 0);
signal sl_addrack_x0: std_logic;
signal sl_rdcomp_x0: std_logic;
signal sl_rddack_x0: std_logic;
signal sl_rddbus_x0: std_logic_vector(31 downto 0);
signal sl_wait_x0: std_logic;
signal sl_wrdack_x0: std_logic;
signal splb_rst_net_x0: std_logic;
signal trackball_dout_x0: std_logic_vector(4 downto 0);
signal wrdbusreg: std_logic_vector(31 downto 0);
begin
ce_1_sg_x1 <= ce_1;
clk_1_sg_x1 <= clk_1;
buttons_big_dout_x0 <= from_register;
buttons_small_dout_x0 <= from_register1;
dip_switch_dout_x0 <= from_register2;
trackball_dout_x0 <= from_register3;
plb_abus_net_x0 <= plb_abus;
plb_pavalid_net_x0 <= plb_pavalid;
plb_rnw_net_x0 <= plb_rnw;
plb_wrdbus_net_x0 <= plb_wrdbus;
sg_plb_addrpref_net_x0 <= sg_plb_addrpref;
lcd_charactermap_dout_x0 <= shared_memory;
lcd_characters_dout_x0 <= shared_memory1;
lcd_commands_dout_x0 <= shared_memory2;
splb_rst_net_x0 <= splb_rst;
buzzer_dutycycle_dout_x0 <= to_register;
buzzer_enable_dout_x0 <= to_register1;
lcd_firststart_dout_x0 <= to_register10;
lcd_lineoffset_dout_x0 <= to_register11;
lcd_ramwrite_dout_x0 <= to_register12;
lcd_reset_dout_x0 <= to_register13;
lcd_resetlcd_dout_x0 <= to_register14;
lcd_rowset_dout_x0 <= to_register15;
lcd_secondend_dout_x0 <= to_register16;
lcd_secondstart_dout_x0 <= to_register17;
lcd_send_dout_x0 <= to_register18;
lcd_totalcmdtransfer_dout_x0 <= to_register19;
buzzer_period_dout_x0 <= to_register2;
leds_dout_x0 <= to_register20;
lcd_backgroundcolor_dout_x0 <= to_register3;
lcd_characteroffset_dout_x0 <= to_register4;
lcd_charactersselect_dout_x0 <= to_register5;
lcd_colset_dout_x0 <= to_register6;
lcd_configlocation_dout_x0 <= to_register7;
lcd_dividerselect_dout_x0 <= to_register8;
lcd_firstend_dout_x0 <= to_register9;
constant5_x0 <= sl_wait_x0;
plb_decode_x0 <= sl_addrack_x0;
plb_decode_x1 <= sl_rdcomp_x0;
plb_decode_x2 <= sl_wrdack_x0;
plb_decode_x3 <= sl_rddack_x0;
plb_decode_x4 <= sl_rddbus_x0;
plb_memmap_x0 <= buzzer_dutycycle_din_x0;
plb_memmap_x1 <= buzzer_dutycycle_en_x0;
plb_memmap_x10 <= lcd_charactersselect_din_x0;
plb_memmap_x11 <= lcd_charactersselect_en_x0;
plb_memmap_x12 <= lcd_colset_din_x0;
plb_memmap_x13 <= lcd_colset_en_x0;
plb_memmap_x14 <= lcd_configlocation_din_x0;
plb_memmap_x15 <= lcd_configlocation_en_x0;
plb_memmap_x16 <= lcd_dividerselect_din_x0;
plb_memmap_x17 <= lcd_dividerselect_en_x0;
plb_memmap_x18 <= lcd_firstend_din_x0;
plb_memmap_x19 <= lcd_firstend_en_x0;
plb_memmap_x2 <= buzzer_enable_din_x0;
plb_memmap_x20 <= lcd_firststart_din_x0;
plb_memmap_x21 <= lcd_firststart_en_x0;
plb_memmap_x22 <= lcd_lineoffset_din_x0;
plb_memmap_x23 <= lcd_lineoffset_en_x0;
plb_memmap_x24 <= lcd_ramwrite_din_x0;
plb_memmap_x25 <= lcd_ramwrite_en_x0;
plb_memmap_x26 <= lcd_reset_din_x0;
plb_memmap_x27 <= lcd_reset_en_x0;
plb_memmap_x28 <= lcd_resetlcd_din_x0;
plb_memmap_x29 <= lcd_resetlcd_en_x0;
plb_memmap_x3 <= buzzer_enable_en_x0;
plb_memmap_x30 <= lcd_rowset_din_x0;
plb_memmap_x31 <= lcd_rowset_en_x0;
plb_memmap_x32 <= lcd_secondend_din_x0;
plb_memmap_x33 <= lcd_secondend_en_x0;
plb_memmap_x34 <= lcd_secondstart_din_x0;
plb_memmap_x35 <= lcd_secondstart_en_x0;
plb_memmap_x36 <= lcd_send_din_x0;
plb_memmap_x37 <= lcd_send_en_x0;
plb_memmap_x38 <= lcd_totalcmdtransfer_din_x0;
plb_memmap_x39 <= lcd_totalcmdtransfer_en_x0;
plb_memmap_x4 <= buzzer_period_din_x0;
plb_memmap_x40 <= leds_din_x0;
plb_memmap_x41 <= leds_en_x0;
plb_memmap_x42 <= lcd_charactermap_addr_x0;
plb_memmap_x43 <= lcd_charactermap_din_x0;
plb_memmap_x44 <= lcd_charactermap_we_x0;
plb_memmap_x45 <= lcd_characters_addr_x0;
plb_memmap_x46 <= lcd_characters_din_x0;
plb_memmap_x47 <= lcd_characters_we_x0;
plb_memmap_x48 <= lcd_commands_addr_x0;
plb_memmap_x49 <= lcd_commands_din_x0;
plb_memmap_x5 <= buzzer_period_en_x0;
plb_memmap_x50 <= lcd_commands_we_x0;
plb_memmap_x6 <= lcd_backgroundcolor_din_x0;
plb_memmap_x7 <= lcd_backgroundcolor_en_x0;
plb_memmap_x8 <= lcd_characteroffset_din_x0;
plb_memmap_x9 <= lcd_characteroffset_en_x0;
constant5: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => sl_wait_x0
);
plb_decode: entity work.mcode_block_8231ed31e4
port map (
addrpref => sg_plb_addrpref_net_x0,
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
plbabus => plb_abus_net_x0,
plbpavalid(0) => plb_pavalid_net_x0,
plbrnw(0) => plb_rnw_net_x0,
plbrst(0) => splb_rst_net_x0,
plbwrdbus => plb_wrdbus_net_x0,
rddata => rddata,
addrack(0) => sl_addrack_x0,
bankaddr => bankaddr,
linearaddr => linearaddr,
rdcomp(0) => sl_rdcomp_x0,
rddack(0) => sl_rddack_x0,
rddbus => sl_rddbus_x0,
rnwreg(0) => rnwreg,
wrdack(0) => sl_wrdack_x0,
wrdbusreg => wrdbusreg
);
plb_memmap: entity work.mcode_block_66f25059c9
port map (
addrack(0) => sl_addrack_x0,
bankaddr => bankaddr,
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
linearaddr => linearaddr,
rnwreg(0) => rnwreg,
sm_buttons_big => buttons_big_dout_x0,
sm_buttons_small => buttons_small_dout_x0,
sm_buzzer_dutycycle => buzzer_dutycycle_dout_x0,
sm_buzzer_enable(0) => buzzer_enable_dout_x0,
sm_buzzer_period => buzzer_period_dout_x0,
sm_dip_switch => dip_switch_dout_x0,
sm_lcd_backgroundcolor => lcd_backgroundcolor_dout_x0,
sm_lcd_charactermap => lcd_charactermap_dout_x0,
sm_lcd_characteroffset => lcd_characteroffset_dout_x0,
sm_lcd_characters => lcd_characters_dout_x0,
sm_lcd_charactersselect => lcd_charactersselect_dout_x0,
sm_lcd_colset => lcd_colset_dout_x0,
sm_lcd_commands => lcd_commands_dout_x0,
sm_lcd_configlocation => lcd_configlocation_dout_x0,
sm_lcd_dividerselect(0) => lcd_dividerselect_dout_x0,
sm_lcd_firstend => lcd_firstend_dout_x0,
sm_lcd_firststart => lcd_firststart_dout_x0,
sm_lcd_lineoffset => lcd_lineoffset_dout_x0,
sm_lcd_ramwrite => lcd_ramwrite_dout_x0,
sm_lcd_reset(0) => lcd_reset_dout_x0,
sm_lcd_resetlcd(0) => lcd_resetlcd_dout_x0,
sm_lcd_rowset => lcd_rowset_dout_x0,
sm_lcd_secondend => lcd_secondend_dout_x0,
sm_lcd_secondstart => lcd_secondstart_dout_x0,
sm_lcd_send(0) => lcd_send_dout_x0,
sm_lcd_totalcmdtransfer => lcd_totalcmdtransfer_dout_x0,
sm_leds => leds_dout_x0,
sm_trackball => trackball_dout_x0,
wrdbus => wrdbusreg,
read_bank_out => rddata,
sm_buzzer_dutycycle_din => buzzer_dutycycle_din_x0,
sm_buzzer_dutycycle_en(0) => buzzer_dutycycle_en_x0,
sm_buzzer_enable_din(0) => buzzer_enable_din_x0,
sm_buzzer_enable_en(0) => buzzer_enable_en_x0,
sm_buzzer_period_din => buzzer_period_din_x0,
sm_buzzer_period_en(0) => buzzer_period_en_x0,
sm_lcd_backgroundcolor_din => lcd_backgroundcolor_din_x0,
sm_lcd_backgroundcolor_en(0) => lcd_backgroundcolor_en_x0,
sm_lcd_charactermap_addr => lcd_charactermap_addr_x0,
sm_lcd_charactermap_din => lcd_charactermap_din_x0,
sm_lcd_charactermap_we(0) => lcd_charactermap_we_x0,
sm_lcd_characteroffset_din => lcd_characteroffset_din_x0,
sm_lcd_characteroffset_en(0) => lcd_characteroffset_en_x0,
sm_lcd_characters_addr => lcd_characters_addr_x0,
sm_lcd_characters_din => lcd_characters_din_x0,
sm_lcd_characters_we(0) => lcd_characters_we_x0,
sm_lcd_charactersselect_din => lcd_charactersselect_din_x0,
sm_lcd_charactersselect_en(0) => lcd_charactersselect_en_x0,
sm_lcd_colset_din => lcd_colset_din_x0,
sm_lcd_colset_en(0) => lcd_colset_en_x0,
sm_lcd_commands_addr => lcd_commands_addr_x0,
sm_lcd_commands_din => lcd_commands_din_x0,
sm_lcd_commands_we(0) => lcd_commands_we_x0,
sm_lcd_configlocation_din => lcd_configlocation_din_x0,
sm_lcd_configlocation_en(0) => lcd_configlocation_en_x0,
sm_lcd_dividerselect_din(0) => lcd_dividerselect_din_x0,
sm_lcd_dividerselect_en(0) => lcd_dividerselect_en_x0,
sm_lcd_firstend_din => lcd_firstend_din_x0,
sm_lcd_firstend_en(0) => lcd_firstend_en_x0,
sm_lcd_firststart_din => lcd_firststart_din_x0,
sm_lcd_firststart_en(0) => lcd_firststart_en_x0,
sm_lcd_lineoffset_din => lcd_lineoffset_din_x0,
sm_lcd_lineoffset_en(0) => lcd_lineoffset_en_x0,
sm_lcd_ramwrite_din => lcd_ramwrite_din_x0,
sm_lcd_ramwrite_en(0) => lcd_ramwrite_en_x0,
sm_lcd_reset_din(0) => lcd_reset_din_x0,
sm_lcd_reset_en(0) => lcd_reset_en_x0,
sm_lcd_resetlcd_din(0) => lcd_resetlcd_din_x0,
sm_lcd_resetlcd_en(0) => lcd_resetlcd_en_x0,
sm_lcd_rowset_din => lcd_rowset_din_x0,
sm_lcd_rowset_en(0) => lcd_rowset_en_x0,
sm_lcd_secondend_din => lcd_secondend_din_x0,
sm_lcd_secondend_en(0) => lcd_secondend_en_x0,
sm_lcd_secondstart_din => lcd_secondstart_din_x0,
sm_lcd_secondstart_en(0) => lcd_secondstart_en_x0,
sm_lcd_send_din(0) => lcd_send_din_x0,
sm_lcd_send_en(0) => lcd_send_en_x0,
sm_lcd_totalcmdtransfer_din => lcd_totalcmdtransfer_din_x0,
sm_lcd_totalcmdtransfer_en(0) => lcd_totalcmdtransfer_en_x0,
sm_leds_din => leds_din_x0,
sm_leds_en(0) => leds_en_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/Interactive I/O/8xDebounce"
entity x8xdebounce_entity_bf5cd80880 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
d: in std_logic;
q: out std_logic
);
end x8xdebounce_entity_bf5cd80880;
architecture structural of x8xdebounce_entity_bf5cd80880 is
signal ce_1_sg_x2: std_logic;
signal clk_1_sg_x2: std_logic;
signal delay1_q_net: std_logic;
signal delay2_q_net: std_logic;
signal delay3_q_net: std_logic;
signal delay4_q_net: std_logic;
signal delay5_q_net: std_logic;
signal delay6_q_net: std_logic;
signal delay_q_net: std_logic;
signal logical_y_net_x0: std_logic;
signal trackball_sel2_net_x0: std_logic;
begin
ce_1_sg_x2 <= ce_1;
clk_1_sg_x2 <= clk_1;
trackball_sel2_net_x0 <= d;
q <= logical_y_net_x0;
delay: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x2,
clk => clk_1_sg_x2,
d(0) => trackball_sel2_net_x0,
en => '1',
q(0) => delay_q_net
);
delay1: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x2,
clk => clk_1_sg_x2,
d(0) => delay_q_net,
en => '1',
q(0) => delay1_q_net
);
delay2: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x2,
clk => clk_1_sg_x2,
d(0) => delay1_q_net,
en => '1',
q(0) => delay2_q_net
);
delay3: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x2,
clk => clk_1_sg_x2,
d(0) => delay2_q_net,
en => '1',
q(0) => delay3_q_net
);
delay4: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x2,
clk => clk_1_sg_x2,
d(0) => delay3_q_net,
en => '1',
q(0) => delay4_q_net
);
delay5: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x2,
clk => clk_1_sg_x2,
d(0) => delay4_q_net,
en => '1',
q(0) => delay5_q_net
);
delay6: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x2,
clk => clk_1_sg_x2,
d(0) => delay5_q_net,
en => '1',
q(0) => delay6_q_net
);
logical: entity work.logical_4ad38e8aed
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => trackball_sel2_net_x0,
d1(0) => delay_q_net,
d2(0) => delay1_q_net,
d3(0) => delay2_q_net,
d4(0) => delay3_q_net,
d5(0) => delay4_q_net,
d6(0) => delay5_q_net,
d7(0) => delay6_q_net,
y(0) => logical_y_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/Interactive I/O"
entity o_entity_1f30dfdbf5 is
port (
buttons_big: in std_logic_vector(1 downto 0);
buttons_small: in std_logic_vector(5 downto 0);
ce_1: in std_logic;
clk_1: in std_logic;
dip_switch: in std_logic_vector(3 downto 0);
from_register: in std_logic_vector(7 downto 0);
trackball_ox: in std_logic;
trackball_oxn: in std_logic;
trackball_oy: in std_logic;
trackball_oyn: in std_logic;
trackball_sel2: in std_logic;
concat_x0: out std_logic_vector(4 downto 0);
constant2_x0: out std_logic;
constant4_x0: out std_logic;
constant6_x0: out std_logic;
constant_x1: out std_logic;
register10_x0: out std_logic;
register11_x0: out std_logic;
register12_x0: out std_logic;
register3_x0: out std_logic_vector(1 downto 0);
register5_x0: out std_logic_vector(5 downto 0);
register7_x0: out std_logic_vector(3 downto 0);
register9_x0: out std_logic_vector(7 downto 0)
);
end o_entity_1f30dfdbf5;
architecture structural of o_entity_1f30dfdbf5 is
signal buttons_big_net_x0: std_logic_vector(1 downto 0);
signal buttons_small_net_x0: std_logic_vector(5 downto 0);
signal ce_1_sg_x7: std_logic;
signal clk_1_sg_x7: std_logic;
signal concat_y_net_x0: std_logic_vector(4 downto 0);
signal constant13_op_net: std_logic;
signal constant2_op_net_x0: std_logic;
signal constant4_op_net_x0: std_logic;
signal constant6_op_net_x0: std_logic;
signal constant_op_net_x0: std_logic;
signal dip_switch_net_x0: std_logic_vector(3 downto 0);
signal from_register_data_out_net_x0: std_logic_vector(7 downto 0);
signal logical_y_net_x0: std_logic;
signal logical_y_net_x1: std_logic;
signal logical_y_net_x2: std_logic;
signal logical_y_net_x3: std_logic;
signal logical_y_net_x4: std_logic;
signal register10_q_net_x0: std_logic;
signal register11_q_net_x0: std_logic;
signal register12_q_net_x0: std_logic;
signal register13_q_net: std_logic;
signal register14_q_net: std_logic;
signal register15_q_net: std_logic;
signal register16_q_net: std_logic;
signal register17_q_net: std_logic;
signal register18_q_net: std_logic;
signal register19_q_net: std_logic;
signal register1_q_net: std_logic;
signal register20_q_net: std_logic;
signal register2_q_net: std_logic_vector(1 downto 0);
signal register3_q_net_x0: std_logic_vector(1 downto 0);
signal register4_q_net: std_logic_vector(5 downto 0);
signal register5_q_net_x0: std_logic_vector(5 downto 0);
signal register6_q_net: std_logic_vector(3 downto 0);
signal register7_q_net_x0: std_logic_vector(3 downto 0);
signal register8_q_net: std_logic_vector(7 downto 0);
signal register9_q_net_x0: std_logic_vector(7 downto 0);
signal register_q_net: std_logic;
signal trackball_ox_net_x1: std_logic;
signal trackball_oxn_net_x1: std_logic;
signal trackball_oy_net_x1: std_logic;
signal trackball_oyn_net_x1: std_logic;
signal trackball_sel2_net_x1: std_logic;
begin
buttons_big_net_x0 <= buttons_big;
buttons_small_net_x0 <= buttons_small;
ce_1_sg_x7 <= ce_1;
clk_1_sg_x7 <= clk_1;
dip_switch_net_x0 <= dip_switch;
from_register_data_out_net_x0 <= from_register;
trackball_ox_net_x1 <= trackball_ox;
trackball_oxn_net_x1 <= trackball_oxn;
trackball_oy_net_x1 <= trackball_oy;
trackball_oyn_net_x1 <= trackball_oyn;
trackball_sel2_net_x1 <= trackball_sel2;
concat_x0 <= concat_y_net_x0;
constant2_x0 <= constant2_op_net_x0;
constant4_x0 <= constant4_op_net_x0;
constant6_x0 <= constant6_op_net_x0;
constant_x1 <= constant_op_net_x0;
register10_x0 <= register10_q_net_x0;
register11_x0 <= register11_q_net_x0;
register12_x0 <= register12_q_net_x0;
register3_x0 <= register3_q_net_x0;
register5_x0 <= register5_q_net_x0;
register7_x0 <= register7_q_net_x0;
register9_x0 <= register9_q_net_x0;
concat: entity work.concat_2b3acb49f4
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => register20_q_net,
in1(0) => register1_q_net,
in2(0) => register14_q_net,
in3(0) => register16_q_net,
in4(0) => register18_q_net,
y => concat_y_net_x0
);
constant13: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant13_op_net
);
constant2: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant2_op_net_x0
);
constant4: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant4_op_net_x0
);
constant6: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant6_op_net_x0
);
constant_x0: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant_op_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => register_q_net,
en => "1",
rst => "0",
q(0) => register1_q_net
);
register10: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => constant13_op_net,
en => "1",
rst => "0",
q(0) => register10_q_net_x0
);
register11: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => constant13_op_net,
en => "1",
rst => "0",
q(0) => register11_q_net_x0
);
register12: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => constant13_op_net,
en => "1",
rst => "0",
q(0) => register12_q_net_x0
);
register13: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => logical_y_net_x2,
en => "1",
rst => "0",
q(0) => register13_q_net
);
register14: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => register13_q_net,
en => "1",
rst => "0",
q(0) => register14_q_net
);
register15: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => logical_y_net_x3,
en => "1",
rst => "0",
q(0) => register15_q_net
);
register16: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => register15_q_net,
en => "1",
rst => "0",
q(0) => register16_q_net
);
register17: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => logical_y_net_x4,
en => "1",
rst => "0",
q(0) => register17_q_net
);
register18: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => register17_q_net,
en => "1",
rst => "0",
q(0) => register18_q_net
);
register19: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => logical_y_net_x0,
en => "1",
rst => "0",
q(0) => register19_q_net
);
register2: entity work.xlregister
generic map (
d_width => 2,
init_value => b"00"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d => buttons_big_net_x0,
en => "1",
rst => "0",
q => register2_q_net
);
register20: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => register19_q_net,
en => "1",
rst => "0",
q(0) => register20_q_net
);
register3: entity work.xlregister
generic map (
d_width => 2,
init_value => b"00"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d => register2_q_net,
en => "1",
rst => "0",
q => register3_q_net_x0
);
register4: entity work.xlregister
generic map (
d_width => 6,
init_value => b"000000"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d => buttons_small_net_x0,
en => "1",
rst => "0",
q => register4_q_net
);
register5: entity work.xlregister
generic map (
d_width => 6,
init_value => b"000000"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d => register4_q_net,
en => "1",
rst => "0",
q => register5_q_net_x0
);
register6: entity work.xlregister
generic map (
d_width => 4,
init_value => b"0000"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d => dip_switch_net_x0,
en => "1",
rst => "0",
q => register6_q_net
);
register7: entity work.xlregister
generic map (
d_width => 4,
init_value => b"0000"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d => register6_q_net,
en => "1",
rst => "0",
q => register7_q_net_x0
);
register8: entity work.xlregister
generic map (
d_width => 8,
init_value => b"00000000"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d => from_register_data_out_net_x0,
en => "1",
rst => "0",
q => register8_q_net
);
register9: entity work.xlregister
generic map (
d_width => 8,
init_value => b"00000000"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d => register8_q_net,
en => "1",
rst => "0",
q => register9_q_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => logical_y_net_x1,
en => "1",
rst => "0",
q(0) => register_q_net
);
x8xdebounce1_e364c4890f: entity work.x8xdebounce_entity_bf5cd80880
port map (
ce_1 => ce_1_sg_x7,
clk_1 => clk_1_sg_x7,
d => trackball_ox_net_x1,
q => logical_y_net_x1
);
x8xdebounce2_5537837997: entity work.x8xdebounce_entity_bf5cd80880
port map (
ce_1 => ce_1_sg_x7,
clk_1 => clk_1_sg_x7,
d => trackball_oxn_net_x1,
q => logical_y_net_x2
);
x8xdebounce3_1e40372202: entity work.x8xdebounce_entity_bf5cd80880
port map (
ce_1 => ce_1_sg_x7,
clk_1 => clk_1_sg_x7,
d => trackball_oy_net_x1,
q => logical_y_net_x3
);
x8xdebounce4_7911ba4284: entity work.x8xdebounce_entity_bf5cd80880
port map (
ce_1 => ce_1_sg_x7,
clk_1 => clk_1_sg_x7,
d => trackball_oyn_net_x1,
q => logical_y_net_x4
);
x8xdebounce_bf5cd80880: entity work.x8xdebounce_entity_bf5cd80880
port map (
ce_1 => ce_1_sg_x7,
clk_1 => clk_1_sg_x7,
d => trackball_sel2_net_x1,
q => logical_y_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller/CommandROM/Command Memory"
entity command_memory_entity_ca978db4f0 is
port (
addr_9b: in std_logic_vector(8 downto 0);
shared_memory: in std_logic_vector(31 downto 0);
constant1_x0: out std_logic;
constant_x1: out std_logic_vector(31 downto 0);
data_16b: out std_logic_vector(15 downto 0);
x8msb_x0: out std_logic_vector(7 downto 0)
);
end command_memory_entity_ca978db4f0;
architecture structural of command_memory_entity_ca978db4f0 is
signal concat_y_net_x0: std_logic_vector(8 downto 0);
signal constant1_op_net_x0: std_logic;
signal constant_op_net_x0: std_logic_vector(31 downto 0);
signal lsb_y_net: std_logic;
signal mux_y_net_x0: std_logic_vector(15 downto 0);
signal shared_memory_data_out_net_x0: std_logic_vector(31 downto 0);
signal x16lsb_y_net: std_logic_vector(15 downto 0);
signal x16msb_y_net: std_logic_vector(15 downto 0);
signal x8msb_y_net_x0: std_logic_vector(7 downto 0);
begin
concat_y_net_x0 <= addr_9b;
shared_memory_data_out_net_x0 <= shared_memory;
constant1_x0 <= constant1_op_net_x0;
constant_x1 <= constant_op_net_x0;
data_16b <= mux_y_net_x0;
x8msb_x0 <= x8msb_y_net_x0;
constant1: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant1_op_net_x0
);
constant_x0: entity work.constant_37567836aa
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant_op_net_x0
);
lsb: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 0,
x_width => 9,
y_width => 1
)
port map (
x => concat_y_net_x0,
y(0) => lsb_y_net
);
mux: entity work.mux_2c45f290ed
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => x16lsb_y_net,
d1 => x16msb_y_net,
sel(0) => lsb_y_net,
y => mux_y_net_x0
);
x16lsb: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 15,
x_width => 32,
y_width => 16
)
port map (
x => shared_memory_data_out_net_x0,
y => x16lsb_y_net
);
x16msb: entity work.xlslice
generic map (
new_lsb => 16,
new_msb => 31,
x_width => 32,
y_width => 16
)
port map (
x => shared_memory_data_out_net_x0,
y => x16msb_y_net
);
x8msb: entity work.xlslice
generic map (
new_lsb => 1,
new_msb => 8,
x_width => 9,
y_width => 8
)
port map (
x => concat_y_net_x0,
y => x8msb_y_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller/CommandROM/Neg Edge Detector"
entity neg_edge_detector_entity_b797592ea5 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
input_signal: in std_logic;
rising_edge: out std_logic
);
end neg_edge_detector_entity_b797592ea5;
architecture structural of neg_edge_detector_entity_b797592ea5 is
signal ce_1_sg_x8: std_logic;
signal clk_1_sg_x8: std_logic;
signal delay_q_net: std_logic;
signal inverter_op_net: std_logic;
signal logical_y_net_x0: std_logic;
signal slice4_y_net_x0: std_logic;
begin
ce_1_sg_x8 <= ce_1;
clk_1_sg_x8 <= clk_1;
slice4_y_net_x0 <= input_signal;
rising_edge <= logical_y_net_x0;
delay: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x8,
clk => clk_1_sg_x8,
d(0) => inverter_op_net,
en => '1',
q(0) => delay_q_net
);
inverter: entity work.inverter_e2b989a05e
port map (
ce => ce_1_sg_x8,
clk => clk_1_sg_x8,
clr => '0',
ip(0) => slice4_y_net_x0,
op(0) => inverter_op_net
);
logical: entity work.logical_b1e9d7c303
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => slice4_y_net_x0,
d1(0) => delay_q_net,
y(0) => logical_y_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller/CommandROM"
entity commandrom_entity_b68e0d97b7 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
from_register1: in std_logic_vector(8 downto 0);
from_register2: in std_logic_vector(8 downto 0);
from_register3: in std_logic_vector(8 downto 0);
from_register4: in std_logic_vector(8 downto 0);
from_register5: in std_logic_vector(8 downto 0);
from_register6: in std_logic_vector(1 downto 0);
reset: in std_logic;
sendcmds: in std_logic;
shared_memory: in std_logic_vector(31 downto 0);
totalnoofcmds: in std_logic_vector(7 downto 0);
transferdone: in std_logic;
cmdsdone: out std_logic;
command_memory: out std_logic_vector(7 downto 0);
command_memory_x0: out std_logic_vector(31 downto 0);
command_memory_x1: out std_logic;
datatosend: out std_logic_vector(8 downto 0);
starttransfer: out std_logic
);
end commandrom_entity_b68e0d97b7;
architecture structural of commandrom_entity_b68e0d97b7 is
signal accumulator1_q_net: std_logic_vector(3 downto 0);
signal accumulator_q_net: std_logic_vector(6 downto 0);
signal addsub_s_net: std_logic_vector(8 downto 0);
signal ce_1_sg_x9: std_logic;
signal clk_1_sg_x9: std_logic;
signal concat2_y_net_x0: std_logic_vector(8 downto 0);
signal concat_y_net_x0: std_logic_vector(8 downto 0);
signal constant11_op_net: std_logic_vector(8 downto 0);
signal constant1_op_net_x1: std_logic;
signal constant2_op_net: std_logic;
signal constant3_op_net: std_logic;
signal constant4_op_net: std_logic_vector(3 downto 0);
signal constant5_op_net: std_logic_vector(8 downto 0);
signal constant6_op_net: std_logic_vector(8 downto 0);
signal constant_op_net_x1: std_logic_vector(31 downto 0);
signal convert1_dout_net: std_logic;
signal convert1_dout_net_x2: std_logic;
signal convert1_dout_net_x3: std_logic;
signal convert2_dout_net: std_logic;
signal convert_dout_net: std_logic;
signal counter1_op_net: std_logic_vector(14 downto 0);
signal counter_op_net: std_logic_vector(6 downto 0);
signal delay_q_net: std_logic;
signal from_register1_data_out_net_x0: std_logic_vector(8 downto 0);
signal from_register2_data_out_net_x0: std_logic_vector(8 downto 0);
signal from_register3_data_out_net_x1: std_logic_vector(8 downto 0);
signal from_register3_data_out_net_x2: std_logic_vector(7 downto 0);
signal from_register4_data_out_net_x0: std_logic_vector(8 downto 0);
signal from_register5_data_out_net_x0: std_logic_vector(8 downto 0);
signal from_register6_data_out_net_x0: std_logic_vector(1 downto 0);
signal inverter1_op_net: std_logic;
signal inverter2_op_net: std_logic;
signal logical1_y_net: std_logic;
signal logical2_y_net: std_logic;
signal logical3_y_net: std_logic;
signal logical_y_net: std_logic;
signal logical_y_net_x0: std_logic;
signal logical_y_net_x2: std_logic;
signal mux1_y_net: std_logic;
signal mux2_y_net_x0: std_logic;
signal mux3_y_net: std_logic_vector(8 downto 0);
signal mux_y_net_x0: std_logic_vector(15 downto 0);
signal register_q_net_x0: std_logic;
signal relational1_op_net: std_logic;
signal relational_op_net: std_logic;
signal shared_memory_data_out_net_x1: std_logic_vector(31 downto 0);
signal slice2_y_net: std_logic_vector(7 downto 0);
signal slice3_y_net: std_logic;
signal slice4_y_net_x0: std_logic;
signal slice5_y_net: std_logic_vector(8 downto 0);
signal x8msb_y_net_x1: std_logic_vector(7 downto 0);
begin
ce_1_sg_x9 <= ce_1;
clk_1_sg_x9 <= clk_1;
from_register1_data_out_net_x0 <= from_register1;
from_register2_data_out_net_x0 <= from_register2;
from_register3_data_out_net_x1 <= from_register3;
from_register4_data_out_net_x0 <= from_register4;
from_register5_data_out_net_x0 <= from_register5;
from_register6_data_out_net_x0 <= from_register6;
convert1_dout_net_x2 <= reset;
logical_y_net_x2 <= sendcmds;
shared_memory_data_out_net_x1 <= shared_memory;
from_register3_data_out_net_x2 <= totalnoofcmds;
convert1_dout_net_x3 <= transferdone;
cmdsdone <= register_q_net_x0;
command_memory <= x8msb_y_net_x1;
command_memory_x0 <= constant_op_net_x1;
command_memory_x1 <= constant1_op_net_x1;
datatosend <= concat2_y_net_x0;
starttransfer <= mux2_y_net_x0;
accumulator: entity work.accum_2cb0e56e96
port map (
b(0) => convert_dout_net,
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
clr => '0',
en(0) => logical1_y_net,
rst(0) => logical_y_net_x2,
q => accumulator_q_net
);
accumulator1: entity work.accum_be45dd0aa2
port map (
b(0) => convert1_dout_net,
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
clr => '0',
rst(0) => convert1_dout_net_x2,
q => accumulator1_q_net
);
addsub: entity work.xladdsub
generic map (
a_arith => xlUnsigned,
a_bin_pt => 0,
a_width => 8,
b_arith => xlUnsigned,
b_bin_pt => 0,
b_width => 1,
c_has_b_out => 0,
c_has_c_out => 0,
c_has_q => 0,
c_has_q_b_out => 0,
c_has_q_c_out => 0,
c_has_s => 1,
c_latency => 0,
c_output_width => 9,
core_name0 => "adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 9,
latency => 0,
mode => 2,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 0,
s_width => 9
)
port map (
a => from_register3_data_out_net_x2,
b(0) => constant3_op_net,
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
clr => '0',
en => "1",
s => addsub_s_net
);
command_memory_ca978db4f0: entity work.command_memory_entity_ca978db4f0
port map (
addr_9b => concat_y_net_x0,
shared_memory => shared_memory_data_out_net_x1,
constant1_x0 => constant1_op_net_x1,
constant_x1 => constant_op_net_x1,
data_16b => mux_y_net_x0,
x8msb_x0 => x8msb_y_net_x1
);
concat: entity work.concat_f62149b02a
port map (
ce => '0',
clk => '0',
clr => '0',
in0 => from_register6_data_out_net_x0,
in1 => counter_op_net,
y => concat_y_net_x0
);
concat2: entity work.concat_1ece14600f
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => inverter1_op_net,
in1 => slice2_y_net,
y => concat2_y_net_x0
);
constant11: entity work.constant_443ed96427
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant11_op_net
);
constant2: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant2_op_net
);
constant3: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant3_op_net
);
constant4: entity work.constant_145086465d
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant4_op_net
);
constant5: entity work.constant_fb9f6d3796
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant5_op_net
);
constant6: entity work.constant_09a4afb2ee
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant6_op_net
);
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din(0) => delay_q_net,
dout(0) => convert_dout_net
);
convert1: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din(0) => logical3_y_net,
dout(0) => convert1_dout_net
);
convert2: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 5,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
clr => '0',
din(0) => logical_y_net_x0,
dout(0) => convert2_dout_net
);
counter: entity work.xlcounter_free
generic map (
core_name0 => "binary_counter_virtex2p_7_0_b0a257f5389d649a",
op_arith => xlUnsigned,
op_width => 7
)
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
clr => '0',
en(0) => logical_y_net,
rst(0) => convert1_dout_net_x2,
op => counter_op_net
);
counter1: entity work.xlcounter_limit
generic map (
cnt_15_0 => 17435,
cnt_31_16 => 0,
cnt_47_32 => 0,
cnt_63_48 => 0,
core_name0 => "binary_counter_virtex2p_7_0_32a1863440903b9d",
count_limited => 1,
op_arith => xlUnsigned,
op_width => 15
)
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
clr => '0',
en(0) => logical2_y_net,
rst(0) => convert1_dout_net_x2,
op => counter1_op_net
);
delay: entity work.xldelay
generic map (
latency => 4,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
d(0) => logical_y_net,
en => '1',
q(0) => delay_q_net
);
inverter1: entity work.inverter_e2b989a05e
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
clr => '0',
ip(0) => slice3_y_net,
op(0) => inverter1_op_net
);
inverter2: entity work.inverter_e5b38cca3b
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
clr => '0',
ip(0) => relational_op_net,
op(0) => inverter2_op_net
);
logical: entity work.logical_aacf6e1b0e
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => logical_y_net_x2,
d1(0) => convert1_dout_net_x3,
y(0) => logical_y_net
);
logical1: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => delay_q_net,
d1(0) => relational_op_net,
y(0) => logical1_y_net
);
logical2: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => inverter2_op_net,
d1(0) => convert1_dout_net_x3,
y(0) => logical2_y_net
);
logical3: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => relational1_op_net,
d1(0) => logical2_y_net,
y(0) => logical3_y_net
);
mux1: entity work.mux_d99e59b6d4
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => constant2_op_net,
d1(0) => delay_q_net,
sel(0) => relational_op_net,
y(0) => mux1_y_net
);
mux2: entity work.mux_d99e59b6d4
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => mux1_y_net,
d1(0) => delay_q_net,
sel(0) => inverter2_op_net,
y(0) => mux2_y_net_x0
);
mux3: entity work.mux_1f00a411aa
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => slice5_y_net,
d1 => constant5_op_net,
d2 => from_register1_data_out_net_x0,
d3 => from_register2_data_out_net_x0,
d4 => constant6_op_net,
d5 => from_register4_data_out_net_x0,
d6 => from_register5_data_out_net_x0,
d7 => constant11_op_net,
d8 => from_register3_data_out_net_x1,
sel => accumulator1_q_net,
y => mux3_y_net
);
neg_edge_detector_b797592ea5: entity work.neg_edge_detector_entity_b797592ea5
port map (
ce_1 => ce_1_sg_x9,
clk_1 => clk_1_sg_x9,
input_signal => slice4_y_net_x0,
rising_edge => logical_y_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
d(0) => convert2_dout_net,
en(0) => convert2_dout_net,
rst(0) => convert1_dout_net_x2,
q(0) => register_q_net_x0
);
relational: entity work.relational_92c392c8b6
port map (
a => accumulator_q_net,
b => addsub_s_net,
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_fb96203f91
port map (
a => accumulator1_q_net,
b => constant4_op_net,
ce => '0',
clk => '0',
clr => '0',
op(0) => relational1_op_net
);
slice2: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 7,
x_width => 9,
y_width => 8
)
port map (
x => mux3_y_net,
y => slice2_y_net
);
slice3: entity work.xlslice
generic map (
new_lsb => 8,
new_msb => 8,
x_width => 9,
y_width => 1
)
port map (
x => mux3_y_net,
y(0) => slice3_y_net
);
slice4: entity work.xlslice
generic map (
new_lsb => 14,
new_msb => 14,
x_width => 15,
y_width => 1
)
port map (
x => counter1_op_net,
y(0) => slice4_y_net_x0
);
slice5: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 8,
x_width => 16,
y_width => 9
)
port map (
x => mux_y_net_x0,
y => slice5_y_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller/DataROM/Character Buffer Shared Memory"
entity character_buffer_shared_memory_entity_1eeb1f8786 is
port (
addr_11b: in std_logic_vector(10 downto 0);
shared_memory: in std_logic_vector(31 downto 0);
constant1_x0: out std_logic;
constant_x1: out std_logic_vector(31 downto 0);
data_8b: out std_logic_vector(7 downto 0);
x9msb_x0: out std_logic_vector(8 downto 0)
);
end character_buffer_shared_memory_entity_1eeb1f8786;
architecture structural of character_buffer_shared_memory_entity_1eeb1f8786 is
signal concat1_y_net_x0: std_logic_vector(10 downto 0);
signal constant1_op_net_x0: std_logic;
signal constant_op_net_x0: std_logic_vector(31 downto 0);
signal mux_y_net_x0: std_logic_vector(7 downto 0);
signal shared_memory_data_out_net_x0: std_logic_vector(31 downto 0);
signal x2lsb_y_net: std_logic_vector(1 downto 0);
signal x8lsb_0_y_net: std_logic_vector(7 downto 0);
signal x8lsb_16_y_net: std_logic_vector(7 downto 0);
signal x8lsb_24_y_net: std_logic_vector(7 downto 0);
signal x8lsb_8_y_net: std_logic_vector(7 downto 0);
signal x9msb_y_net_x0: std_logic_vector(8 downto 0);
begin
concat1_y_net_x0 <= addr_11b;
shared_memory_data_out_net_x0 <= shared_memory;
constant1_x0 <= constant1_op_net_x0;
constant_x1 <= constant_op_net_x0;
data_8b <= mux_y_net_x0;
x9msb_x0 <= x9msb_y_net_x0;
constant1: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant1_op_net_x0
);
constant_x0: entity work.constant_37567836aa
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant_op_net_x0
);
mux: entity work.mux_998e20a1ca
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => x8lsb_24_y_net,
d1 => x8lsb_16_y_net,
d2 => x8lsb_8_y_net,
d3 => x8lsb_0_y_net,
sel => x2lsb_y_net,
y => mux_y_net_x0
);
x2lsb: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 1,
x_width => 11,
y_width => 2
)
port map (
x => concat1_y_net_x0,
y => x2lsb_y_net
);
x8lsb_0: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 7,
x_width => 32,
y_width => 8
)
port map (
x => shared_memory_data_out_net_x0,
y => x8lsb_0_y_net
);
x8lsb_16: entity work.xlslice
generic map (
new_lsb => 16,
new_msb => 23,
x_width => 32,
y_width => 8
)
port map (
x => shared_memory_data_out_net_x0,
y => x8lsb_16_y_net
);
x8lsb_24: entity work.xlslice
generic map (
new_lsb => 24,
new_msb => 31,
x_width => 32,
y_width => 8
)
port map (
x => shared_memory_data_out_net_x0,
y => x8lsb_24_y_net
);
x8lsb_8: entity work.xlslice
generic map (
new_lsb => 8,
new_msb => 15,
x_width => 32,
y_width => 8
)
port map (
x => shared_memory_data_out_net_x0,
y => x8lsb_8_y_net
);
x9msb: entity work.xlslice
generic map (
new_lsb => 2,
new_msb => 10,
x_width => 11,
y_width => 9
)
port map (
x => concat1_y_net_x0,
y => x9msb_y_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller/DataROM/Character Map Shared Memory"
entity character_map_shared_memory_entity_e504c38a5b is
port (
addr_14b: in std_logic_vector(13 downto 0);
shared_memory: in std_logic_vector(31 downto 0);
constant1_x0: out std_logic;
constant_x1: out std_logic_vector(31 downto 0);
data_8b: out std_logic_vector(7 downto 0);
x12msb_x0: out std_logic_vector(11 downto 0)
);
end character_map_shared_memory_entity_e504c38a5b;
architecture structural of character_map_shared_memory_entity_e504c38a5b is
signal concat_y_net_x0: std_logic_vector(13 downto 0);
signal constant1_op_net_x0: std_logic;
signal constant_op_net_x0: std_logic_vector(31 downto 0);
signal mux_y_net_x0: std_logic_vector(7 downto 0);
signal shared_memory_data_out_net_x0: std_logic_vector(31 downto 0);
signal x12msb_y_net_x0: std_logic_vector(11 downto 0);
signal x2lsb_y_net: std_logic_vector(1 downto 0);
signal x8lsb_0_y_net: std_logic_vector(7 downto 0);
signal x8lsb_16_y_net: std_logic_vector(7 downto 0);
signal x8lsb_24_y_net: std_logic_vector(7 downto 0);
signal x8lsb_8_y_net: std_logic_vector(7 downto 0);
begin
concat_y_net_x0 <= addr_14b;
shared_memory_data_out_net_x0 <= shared_memory;
constant1_x0 <= constant1_op_net_x0;
constant_x1 <= constant_op_net_x0;
data_8b <= mux_y_net_x0;
x12msb_x0 <= x12msb_y_net_x0;
constant1: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant1_op_net_x0
);
constant_x0: entity work.constant_37567836aa
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant_op_net_x0
);
mux: entity work.mux_998e20a1ca
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => x8lsb_24_y_net,
d1 => x8lsb_16_y_net,
d2 => x8lsb_8_y_net,
d3 => x8lsb_0_y_net,
sel => x2lsb_y_net,
y => mux_y_net_x0
);
x12msb: entity work.xlslice
generic map (
new_lsb => 2,
new_msb => 13,
x_width => 14,
y_width => 12
)
port map (
x => concat_y_net_x0,
y => x12msb_y_net_x0
);
x2lsb: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 1,
x_width => 14,
y_width => 2
)
port map (
x => concat_y_net_x0,
y => x2lsb_y_net
);
x8lsb_0: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 7,
x_width => 32,
y_width => 8
)
port map (
x => shared_memory_data_out_net_x0,
y => x8lsb_0_y_net
);
x8lsb_16: entity work.xlslice
generic map (
new_lsb => 16,
new_msb => 23,
x_width => 32,
y_width => 8
)
port map (
x => shared_memory_data_out_net_x0,
y => x8lsb_16_y_net
);
x8lsb_24: entity work.xlslice
generic map (
new_lsb => 24,
new_msb => 31,
x_width => 32,
y_width => 8
)
port map (
x => shared_memory_data_out_net_x0,
y => x8lsb_24_y_net
);
x8lsb_8: entity work.xlslice
generic map (
new_lsb => 8,
new_msb => 15,
x_width => 32,
y_width => 8
)
port map (
x => shared_memory_data_out_net_x0,
y => x8lsb_8_y_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller/DataROM/Pos Edge Detector"
entity pos_edge_detector_entity_90ec5fccc3 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
input_signal: in std_logic;
rising_edge: out std_logic
);
end pos_edge_detector_entity_90ec5fccc3;
architecture structural of pos_edge_detector_entity_90ec5fccc3 is
signal ce_1_sg_x10: std_logic;
signal clk_1_sg_x10: std_logic;
signal delay_q_net: std_logic;
signal inverter_op_net: std_logic;
signal logical_y_net_x0: std_logic;
signal relational_op_net_x0: std_logic;
begin
ce_1_sg_x10 <= ce_1;
clk_1_sg_x10 <= clk_1;
relational_op_net_x0 <= input_signal;
rising_edge <= logical_y_net_x0;
delay: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x10,
clk => clk_1_sg_x10,
d(0) => inverter_op_net,
en => '1',
q(0) => delay_q_net
);
inverter: entity work.inverter_e5b38cca3b
port map (
ce => ce_1_sg_x10,
clk => clk_1_sg_x10,
clr => '0',
ip(0) => relational_op_net_x0,
op(0) => inverter_op_net
);
logical: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => relational_op_net_x0,
d1(0) => delay_q_net,
y(0) => logical_y_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller/DataROM/Subsystem"
entity subsystem_entity_8d430c7bea is
port (
ce_1: in std_logic;
clk_1: in std_logic;
not0: in std_logic;
transferdone: in std_logic;
x6bitval: in std_logic;
out1: out std_logic
);
end subsystem_entity_8d430c7bea;
architecture structural of subsystem_entity_8d430c7bea is
signal ce_1_sg_x11: std_logic;
signal clk_1_sg_x11: std_logic;
signal delay_q_net: std_logic;
signal inverter2_op_net_x0: std_logic;
signal logical1_y_net: std_logic;
signal logical2_y_net: std_logic;
signal logical3_y_net_x0: std_logic;
signal logical_y_net_x0: std_logic;
signal relational_op_net_x1: std_logic;
begin
ce_1_sg_x11 <= ce_1;
clk_1_sg_x11 <= clk_1;
inverter2_op_net_x0 <= not0;
logical_y_net_x0 <= transferdone;
relational_op_net_x1 <= x6bitval;
out1 <= logical3_y_net_x0;
delay: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x11,
clk => clk_1_sg_x11,
d(0) => logical_y_net_x0,
en => '1',
q(0) => delay_q_net
);
logical1: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => inverter2_op_net_x0,
d1(0) => delay_q_net,
y(0) => logical1_y_net
);
logical2: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => relational_op_net_x1,
d1(0) => delay_q_net,
y(0) => logical2_y_net
);
logical3: entity work.logical_aacf6e1b0e
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => logical2_y_net,
d1(0) => logical1_y_net,
y(0) => logical3_y_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller/DataROM/Subsystem1"
entity subsystem1_entity_a91e11b915 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
x4bits: in std_logic_vector(3 downto 0);
end_x0: out std_logic_vector(8 downto 0);
start: out std_logic_vector(8 downto 0)
);
end subsystem1_entity_a91e11b915;
architecture structural of subsystem1_entity_a91e11b915 is
signal addsub1_s_net_x0: std_logic_vector(8 downto 0);
signal addsub_s_net_x0: std_logic_vector(8 downto 0);
signal ce_1_sg_x12: std_logic;
signal clk_1_sg_x12: std_logic;
signal concat6_y_net: std_logic_vector(6 downto 0);
signal constant1_op_net: std_logic_vector(7 downto 0);
signal constant2_op_net: std_logic_vector(7 downto 0);
signal constant_op_net: std_logic_vector(2 downto 0);
signal slice10_y_net_x0: std_logic_vector(3 downto 0);
begin
ce_1_sg_x12 <= ce_1;
clk_1_sg_x12 <= clk_1;
slice10_y_net_x0 <= x4bits;
end_x0 <= addsub1_s_net_x0;
start <= addsub_s_net_x0;
addsub: entity work.xladdsub
generic map (
a_arith => xlUnsigned,
a_bin_pt => 0,
a_width => 7,
b_arith => xlUnsigned,
b_bin_pt => 0,
b_width => 8,
c_has_b_out => 0,
c_has_c_out => 0,
c_has_q => 0,
c_has_q_b_out => 0,
c_has_q_c_out => 0,
c_has_s => 1,
c_latency => 0,
c_output_width => 9,
core_name0 => "adder_subtracter_virtex2p_7_0_453ed16ba8e84295",
extra_registers => 0,
full_s_arith => 1,
full_s_width => 9,
latency => 0,
mode => 1,
overflow => 1,
quantization => 1,
s_arith => xlUnsigned,
s_bin_pt => 0,
s_width => 9
)
port map (
a => concat6_y_net,
b => constant1_op_net,
ce => ce_1_sg_x12,
clk => clk_1_sg_x12,
clr => '0',
en => "1",
s => addsub_s_net_x0
);
addsub1: entity work.xladdsub
generic map (
a_arith => xlUnsigned,
a_bin_pt => 0,
a_width => 7,
b_arith => xlUnsigned,
b_bin_pt => 0,
b_width => 8,
c_has_b_out => 0,
c_has_c_out => 0,
c_has_q => 0,
c_has_q_b_out => 0,
c_has_q_c_out => 0,
c_has_s => 1,
c_latency => 0,
c_output_width => 9,
core_name0 => "adder_subtracter_virtex2p_7_0_453ed16ba8e84295",
extra_registers => 0,
full_s_arith => 1,
full_s_width => 9,
latency => 0,
mode => 1,
overflow => 1,
quantization => 1,
s_arith => xlUnsigned,
s_bin_pt => 0,
s_width => 9
)
port map (
a => concat6_y_net,
b => constant2_op_net,
ce => ce_1_sg_x12,
clk => clk_1_sg_x12,
clr => '0',
en => "1",
s => addsub1_s_net_x0
);
concat6: entity work.concat_32864ba5d6
port map (
ce => '0',
clk => '0',
clr => '0',
in0 => slice10_y_net_x0,
in1 => constant_op_net,
y => concat6_y_net
);
constant1: entity work.constant_21d4a28b7e
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant1_op_net
);
constant2: entity work.constant_b940b9054a
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant2_op_net
);
constant_x0: entity work.constant_822933f89b
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller/DataROM"
entity datarom_entity_fd2cd392cc is
port (
ce_1: in std_logic;
clk_1: in std_logic;
cmdsdone: in std_logic;
from_register1: in std_logic_vector(8 downto 0);
from_register2: in std_logic_vector(8 downto 0);
from_register3: in std_logic_vector(8 downto 0);
from_register4: in std_logic_vector(2 downto 0);
from_register5: in std_logic_vector(3 downto 0);
from_register7: in std_logic_vector(3 downto 0);
reset: in std_logic;
shared_memory: in std_logic_vector(31 downto 0);
shared_memory_x0: in std_logic_vector(31 downto 0);
transferdone: in std_logic;
character_buffer_shared_memory: out std_logic_vector(8 downto 0);
character_buffer_shared_memory_x0: out std_logic_vector(31 downto 0);
character_buffer_shared_memory_x1: out std_logic;
character_map_shared_memory: out std_logic_vector(11 downto 0);
character_map_shared_memory_x0: out std_logic_vector(31 downto 0);
character_map_shared_memory_x1: out std_logic;
data: out std_logic_vector(8 downto 0);
starttransfer: out std_logic
);
end datarom_entity_fd2cd392cc;
architecture structural of datarom_entity_fd2cd392cc is
signal addsub1_s_net: std_logic_vector(3 downto 0);
signal addsub1_s_net_x0: std_logic_vector(8 downto 0);
signal addsub1_s_net_x1: std_logic_vector(8 downto 0);
signal addsub2_s_net: std_logic_vector(3 downto 0);
signal addsub_s_net_x0: std_logic_vector(8 downto 0);
signal addsub_s_net_x1: std_logic_vector(8 downto 0);
signal ce_1_sg_x14: std_logic;
signal clk_1_sg_x14: std_logic;
signal concat1_y_net_x0: std_logic_vector(10 downto 0);
signal concat3_y_net: std_logic_vector(1 downto 0);
signal concat4_y_net_x0: std_logic_vector(8 downto 0);
signal concat5_y_net: std_logic_vector(8 downto 0);
signal concat_y_net_x0: std_logic_vector(13 downto 0);
signal constant10_op_net: std_logic;
signal constant1_op_net_x2: std_logic;
signal constant1_op_net_x3: std_logic;
signal constant4_op_net: std_logic;
signal constant5_op_net: std_logic;
signal constant6_op_net: std_logic_vector(2 downto 0);
signal constant7_op_net: std_logic_vector(2 downto 0);
signal constant8_op_net: std_logic_vector(2 downto 0);
signal constant9_op_net: std_logic;
signal constant_op_net_x2: std_logic_vector(31 downto 0);
signal constant_op_net_x3: std_logic_vector(31 downto 0);
signal convert1_dout_net: std_logic;
signal convert1_dout_net_x4: std_logic;
signal convert1_dout_net_x5: std_logic;
signal convert_dout_net: std_logic;
signal counter1_op_net: std_logic_vector(13 downto 0);
signal counter_op_net: std_logic_vector(2 downto 0);
signal delay_q_net_x0: std_logic;
signal from_register1_data_out_net_x0: std_logic_vector(8 downto 0);
signal from_register2_data_out_net_x0: std_logic_vector(8 downto 0);
signal from_register3_data_out_net_x0: std_logic_vector(8 downto 0);
signal from_register4_data_out_net_x0: std_logic_vector(2 downto 0);
signal from_register5_data_out_net_x0: std_logic_vector(3 downto 0);
signal from_register7_data_out_net_x0: std_logic_vector(3 downto 0);
signal inverter2_op_net_x0: std_logic;
signal inverter3_op_net: std_logic;
signal logical1_y_net: std_logic;
signal logical3_y_net_x0: std_logic;
signal logical_y_net_x0: std_logic;
signal logical_y_net_x1: std_logic;
signal mux2_y_net: std_logic_vector(2 downto 0);
signal mux3_y_net: std_logic_vector(8 downto 0);
signal mux_y_net_x0: std_logic_vector(7 downto 0);
signal mux_y_net_x1: std_logic_vector(7 downto 0);
signal register_q_net: std_logic_vector(5 downto 0);
signal register_q_net_x1: std_logic;
signal relational1_op_net: std_logic;
signal relational2_op_net: std_logic;
signal relational_op_net_x1: std_logic;
signal shared_memory_data_out_net_x2: std_logic_vector(31 downto 0);
signal shared_memory_data_out_net_x3: std_logic_vector(31 downto 0);
signal slice10_y_net_x0: std_logic_vector(3 downto 0);
signal slice11_y_net_x0: std_logic_vector(3 downto 0);
signal slice4_y_net: std_logic_vector(7 downto 0);
signal slice5_y_net: std_logic_vector(5 downto 0);
signal slice6_y_net: std_logic_vector(5 downto 0);
signal slice7_y_net: std_logic_vector(3 downto 0);
signal slice8_y_net: std_logic_vector(7 downto 0);
signal slice9_y_net: std_logic;
signal x12msb_y_net_x1: std_logic_vector(11 downto 0);
signal x4lsb_y_net: std_logic_vector(3 downto 0);
signal x4msb_y_net: std_logic_vector(3 downto 0);
signal x9msb_y_net_x1: std_logic_vector(8 downto 0);
begin
ce_1_sg_x14 <= ce_1;
clk_1_sg_x14 <= clk_1;
register_q_net_x1 <= cmdsdone;
from_register1_data_out_net_x0 <= from_register1;
from_register2_data_out_net_x0 <= from_register2;
from_register3_data_out_net_x0 <= from_register3;
from_register4_data_out_net_x0 <= from_register4;
from_register5_data_out_net_x0 <= from_register5;
from_register7_data_out_net_x0 <= from_register7;
convert1_dout_net_x4 <= reset;
shared_memory_data_out_net_x2 <= shared_memory;
shared_memory_data_out_net_x3 <= shared_memory_x0;
convert1_dout_net_x5 <= transferdone;
character_buffer_shared_memory <= x9msb_y_net_x1;
character_buffer_shared_memory_x0 <= constant_op_net_x2;
character_buffer_shared_memory_x1 <= constant1_op_net_x2;
character_map_shared_memory <= x12msb_y_net_x1;
character_map_shared_memory_x0 <= constant_op_net_x3;
character_map_shared_memory_x1 <= constant1_op_net_x3;
data <= concat4_y_net_x0;
starttransfer <= delay_q_net_x0;
addsub1: entity work.xladdsub
generic map (
a_arith => xlUnsigned,
a_bin_pt => 0,
a_width => 4,
b_arith => xlUnsigned,
b_bin_pt => 0,
b_width => 4,
c_has_b_out => 0,
c_has_c_out => 0,
c_has_q => 0,
c_has_q_b_out => 0,
c_has_q_c_out => 0,
c_has_s => 1,
c_latency => 0,
c_output_width => 5,
core_name0 => "adder_subtracter_virtex2p_7_0_7182743c9e7adf5e",
extra_registers => 0,
full_s_arith => 1,
full_s_width => 5,
latency => 0,
mode => 1,
overflow => 1,
quantization => 1,
s_arith => xlUnsigned,
s_bin_pt => 0,
s_width => 4
)
port map (
a => from_register7_data_out_net_x0,
b => x4msb_y_net,
ce => ce_1_sg_x14,
clk => clk_1_sg_x14,
clr => '0',
en => "1",
s => addsub1_s_net
);
addsub2: entity work.xladdsub
generic map (
a_arith => xlUnsigned,
a_bin_pt => 0,
a_width => 4,
b_arith => xlUnsigned,
b_bin_pt => 0,
b_width => 4,
c_has_b_out => 0,
c_has_c_out => 0,
c_has_q => 0,
c_has_q_b_out => 0,
c_has_q_c_out => 0,
c_has_s => 1,
c_latency => 0,
c_output_width => 5,
core_name0 => "adder_subtracter_virtex2p_7_0_7182743c9e7adf5e",
extra_registers => 0,
full_s_arith => 1,
full_s_width => 5,
latency => 0,
mode => 1,
overflow => 1,
quantization => 1,
s_arith => xlUnsigned,
s_bin_pt => 0,
s_width => 4
)
port map (
a => x4lsb_y_net,
b => from_register5_data_out_net_x0,
ce => ce_1_sg_x14,
clk => clk_1_sg_x14,
clr => '0',
en => "1",
s => addsub2_s_net
);
character_buffer_shared_memory_1eeb1f8786: entity work.character_buffer_shared_memory_entity_1eeb1f8786
port map (
addr_11b => concat1_y_net_x0,
shared_memory => shared_memory_data_out_net_x2,
constant1_x0 => constant1_op_net_x2,
constant_x1 => constant_op_net_x2,
data_8b => mux_y_net_x0,
x9msb_x0 => x9msb_y_net_x1
);
character_map_shared_memory_e504c38a5b: entity work.character_map_shared_memory_entity_e504c38a5b
port map (
addr_14b => concat_y_net_x0,
shared_memory => shared_memory_data_out_net_x3,
constant1_x0 => constant1_op_net_x3,
constant_x1 => constant_op_net_x3,
data_8b => mux_y_net_x1,
x12msb_x0 => x12msb_y_net_x1
);
concat: entity work.concat_25ab81b400
port map (
ce => '0',
clk => '0',
clr => '0',
in0 => mux_y_net_x0,
in1 => register_q_net,
y => concat_y_net_x0
);
concat1: entity work.concat_78218439f3
port map (
ce => '0',
clk => '0',
clr => '0',
in0 => from_register4_data_out_net_x0,
in1 => addsub1_s_net,
in2 => addsub2_s_net,
y => concat1_y_net_x0
);
concat3: entity work.concat_e6f5ee726b
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => convert_dout_net,
in1(0) => convert1_dout_net,
y => concat3_y_net
);
concat4: entity work.concat_1ece14600f
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => inverter3_op_net,
in1 => slice8_y_net,
y => concat4_y_net_x0
);
concat5: entity work.concat_1ece14600f
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => constant10_op_net,
in1 => mux_y_net_x1,
y => concat5_y_net
);
constant10: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant10_op_net
);
constant4: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant4_op_net
);
constant5: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant5_op_net
);
constant6: entity work.constant_822933f89b
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant6_op_net
);
constant7: entity work.constant_469094441c
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant7_op_net
);
constant8: entity work.constant_a1c496ea88
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant8_op_net
);
constant9: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant9_op_net
);
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din(0) => relational_op_net_x1,
dout(0) => convert_dout_net
);
convert1: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din(0) => relational1_op_net,
dout(0) => convert1_dout_net
);
counter: entity work.xlcounter_free
generic map (
core_name0 => "binary_counter_virtex2p_7_0_b511f9871581ee23",
op_arith => xlUnsigned,
op_width => 3
)
port map (
ce => ce_1_sg_x14,
clk => clk_1_sg_x14,
clr => '0',
din => mux2_y_net,
en(0) => logical3_y_net_x0,
load(0) => logical_y_net_x1,
rst => "0",
op => counter_op_net
);
counter1: entity work.xlcounter_free
generic map (
core_name0 => "binary_counter_virtex2p_7_0_a22528b4c55dc1cd",
op_arith => xlUnsigned,
op_width => 14
)
port map (
ce => ce_1_sg_x14,
clk => clk_1_sg_x14,
clr => '0',
en(0) => logical1_y_net,
rst(0) => convert1_dout_net_x4,
op => counter1_op_net
);
delay: entity work.xldelay
generic map (
latency => 4,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x14,
clk => clk_1_sg_x14,
d(0) => logical_y_net_x0,
en => '1',
q(0) => delay_q_net_x0
);
inverter2: entity work.inverter_e5b38cca3b
port map (
ce => ce_1_sg_x14,
clk => clk_1_sg_x14,
clr => '0',
ip(0) => relational2_op_net,
op(0) => inverter2_op_net_x0
);
inverter3: entity work.inverter_e2b989a05e
port map (
ce => ce_1_sg_x14,
clk => clk_1_sg_x14,
clr => '0',
ip(0) => slice9_y_net,
op(0) => inverter3_op_net
);
logical: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => convert1_dout_net_x5,
d1(0) => register_q_net_x1,
y(0) => logical_y_net_x0
);
logical1: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => relational2_op_net,
d1(0) => logical_y_net_x0,
y(0) => logical1_y_net
);
mux2: entity work.mux_2ec2057ae3
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => constant6_op_net,
d1 => constant6_op_net,
d2 => constant7_op_net,
d3 => constant8_op_net,
sel => concat3_y_net,
y => mux2_y_net
);
mux3: entity work.mux_7586447000
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => concat5_y_net,
d1 => from_register3_data_out_net_x0,
d2 => addsub_s_net_x0,
d3 => addsub1_s_net_x0,
d4 => from_register1_data_out_net_x0,
d5 => addsub_s_net_x1,
d6 => addsub1_s_net_x1,
d7 => from_register2_data_out_net_x0,
sel => counter_op_net,
y => mux3_y_net
);
pos_edge_detector_90ec5fccc3: entity work.pos_edge_detector_entity_90ec5fccc3
port map (
ce_1 => ce_1_sg_x14,
clk_1 => clk_1_sg_x14,
input_signal => relational_op_net_x1,
rising_edge => logical_y_net_x1
);
register_x0: entity work.xlregister
generic map (
d_width => 6,
init_value => b"000000"
)
port map (
ce => ce_1_sg_x14,
clk => clk_1_sg_x14,
d => slice5_y_net,
en => "1",
rst => "0",
q => register_q_net
);
relational: entity work.relational_f7cb2b0c31
port map (
a => slice6_y_net,
b(0) => constant4_op_net,
ce => '0',
clk => '0',
clr => '0',
op(0) => relational_op_net_x1
);
relational1: entity work.relational_ee03197e2c
port map (
a => slice7_y_net,
b(0) => constant5_op_net,
ce => '0',
clk => '0',
clr => '0',
op(0) => relational1_op_net
);
relational2: entity work.relational_04b069dd89
port map (
a => counter_op_net,
b(0) => constant9_op_net,
ce => '0',
clk => '0',
clr => '0',
op(0) => relational2_op_net
);
slice10: entity work.xlslice
generic map (
new_lsb => 10,
new_msb => 13,
x_width => 14,
y_width => 4
)
port map (
x => counter1_op_net,
y => slice10_y_net_x0
);
slice11: entity work.xlslice
generic map (
new_lsb => 6,
new_msb => 9,
x_width => 14,
y_width => 4
)
port map (
x => counter1_op_net,
y => slice11_y_net_x0
);
slice4: entity work.xlslice
generic map (
new_lsb => 6,
new_msb => 13,
x_width => 14,
y_width => 8
)
port map (
x => counter1_op_net,
y => slice4_y_net
);
slice5: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 5,
x_width => 14,
y_width => 6
)
port map (
x => counter1_op_net,
y => slice5_y_net
);
slice6: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 5,
x_width => 14,
y_width => 6
)
port map (
x => counter1_op_net,
y => slice6_y_net
);
slice7: entity work.xlslice
generic map (
new_lsb => 6,
new_msb => 9,
x_width => 14,
y_width => 4
)
port map (
x => counter1_op_net,
y => slice7_y_net
);
slice8: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 7,
x_width => 9,
y_width => 8
)
port map (
x => mux3_y_net,
y => slice8_y_net
);
slice9: entity work.xlslice
generic map (
new_lsb => 8,
new_msb => 8,
x_width => 9,
y_width => 1
)
port map (
x => mux3_y_net,
y(0) => slice9_y_net
);
subsystem1_a91e11b915: entity work.subsystem1_entity_a91e11b915
port map (
ce_1 => ce_1_sg_x14,
clk_1 => clk_1_sg_x14,
x4bits => slice10_y_net_x0,
end_x0 => addsub1_s_net_x0,
start => addsub_s_net_x0
);
subsystem2_4e1ae86655: entity work.subsystem1_entity_a91e11b915
port map (
ce_1 => ce_1_sg_x14,
clk_1 => clk_1_sg_x14,
x4bits => slice11_y_net_x0,
end_x0 => addsub1_s_net_x1,
start => addsub_s_net_x1
);
subsystem_8d430c7bea: entity work.subsystem_entity_8d430c7bea
port map (
ce_1 => ce_1_sg_x14,
clk_1 => clk_1_sg_x14,
not0 => inverter2_op_net_x0,
transferdone => logical_y_net_x0,
x6bitval => relational_op_net_x1,
out1 => logical3_y_net_x0
);
x4lsb: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 3,
x_width => 8,
y_width => 4
)
port map (
x => slice4_y_net,
y => x4lsb_y_net
);
x4msb: entity work.xlslice
generic map (
new_lsb => 4,
new_msb => 7,
x_width => 8,
y_width => 4
)
port map (
x => slice4_y_net,
y => x4msb_y_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller/SPI/Data_Latch"
entity data_latch_entity_d697580f4e is
port (
bit_select: in std_logic_vector(3 downto 0);
ce_1: in std_logic;
clk_1: in std_logic;
data_to_transmit: in std_logic_vector(8 downto 0);
latchdata: in std_logic;
reset: in std_logic;
spi_data: out std_logic
);
end data_latch_entity_d697580f4e;
architecture structural of data_latch_entity_d697580f4e is
signal ce_1_sg_x16: std_logic;
signal clk_1_sg_x16: std_logic;
signal convert1_dout_net_x5: std_logic;
signal counter_op_net_x0: std_logic_vector(3 downto 0);
signal mux1_y_net_x0: std_logic;
signal mux_y_net_x1: std_logic_vector(8 downto 0);
signal mux_y_net_x2: std_logic;
signal register_q_net: std_logic_vector(8 downto 0);
signal slice1_y_net: std_logic;
signal slice2_y_net: std_logic;
signal slice3_y_net: std_logic;
signal slice4_y_net: std_logic;
signal slice5_y_net: std_logic;
signal slice6_y_net: std_logic;
signal slice7_y_net: std_logic;
signal slice8_y_net: std_logic;
signal slice_y_net: std_logic;
begin
counter_op_net_x0 <= bit_select;
ce_1_sg_x16 <= ce_1;
clk_1_sg_x16 <= clk_1;
mux_y_net_x1 <= data_to_transmit;
mux1_y_net_x0 <= latchdata;
convert1_dout_net_x5 <= reset;
spi_data <= mux_y_net_x2;
mux: entity work.mux_8e3eece8f2
port map (
ce => ce_1_sg_x16,
clk => clk_1_sg_x16,
clr => '0',
d0(0) => slice_y_net,
d1(0) => slice1_y_net,
d2(0) => slice2_y_net,
d3(0) => slice3_y_net,
d4(0) => slice4_y_net,
d5(0) => slice5_y_net,
d6(0) => slice6_y_net,
d7(0) => slice7_y_net,
d8(0) => slice8_y_net,
sel => counter_op_net_x0,
y(0) => mux_y_net_x2
);
register_x0: entity work.xlregister
generic map (
d_width => 9,
init_value => b"000000000"
)
port map (
ce => ce_1_sg_x16,
clk => clk_1_sg_x16,
d => mux_y_net_x1,
en(0) => mux1_y_net_x0,
rst(0) => convert1_dout_net_x5,
q => register_q_net
);
slice: entity work.xlslice
generic map (
new_lsb => 8,
new_msb => 8,
x_width => 9,
y_width => 1
)
port map (
x => register_q_net,
y(0) => slice_y_net
);
slice1: entity work.xlslice
generic map (
new_lsb => 7,
new_msb => 7,
x_width => 9,
y_width => 1
)
port map (
x => register_q_net,
y(0) => slice1_y_net
);
slice2: entity work.xlslice
generic map (
new_lsb => 6,
new_msb => 6,
x_width => 9,
y_width => 1
)
port map (
x => register_q_net,
y(0) => slice2_y_net
);
slice3: entity work.xlslice
generic map (
new_lsb => 5,
new_msb => 5,
x_width => 9,
y_width => 1
)
port map (
x => register_q_net,
y(0) => slice3_y_net
);
slice4: entity work.xlslice
generic map (
new_lsb => 4,
new_msb => 4,
x_width => 9,
y_width => 1
)
port map (
x => register_q_net,
y(0) => slice4_y_net
);
slice5: entity work.xlslice
generic map (
new_lsb => 3,
new_msb => 3,
x_width => 9,
y_width => 1
)
port map (
x => register_q_net,
y(0) => slice5_y_net
);
slice6: entity work.xlslice
generic map (
new_lsb => 2,
new_msb => 2,
x_width => 9,
y_width => 1
)
port map (
x => register_q_net,
y(0) => slice6_y_net
);
slice7: entity work.xlslice
generic map (
new_lsb => 1,
new_msb => 1,
x_width => 9,
y_width => 1
)
port map (
x => register_q_net,
y(0) => slice7_y_net
);
slice8: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 0,
x_width => 9,
y_width => 1
)
port map (
x => register_q_net,
y(0) => slice8_y_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller/SPI/Pos Edge Detector"
entity pos_edge_detector_entity_ac86c1f1ba is
port (
ce_1: in std_logic;
clk_1: in std_logic;
input_signal: in std_logic;
rising_edge: out std_logic
);
end pos_edge_detector_entity_ac86c1f1ba;
architecture structural of pos_edge_detector_entity_ac86c1f1ba is
signal ce_1_sg_x17: std_logic;
signal clk_1_sg_x17: std_logic;
signal delay_q_net: std_logic;
signal inverter_op_net: std_logic;
signal logical_y_net_x0: std_logic;
signal mux_y_net_x0: std_logic;
begin
ce_1_sg_x17 <= ce_1;
clk_1_sg_x17 <= clk_1;
mux_y_net_x0 <= input_signal;
rising_edge <= logical_y_net_x0;
delay: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x17,
clk => clk_1_sg_x17,
d(0) => inverter_op_net,
en => '1',
q(0) => delay_q_net
);
inverter: entity work.inverter_e2b989a05e
port map (
ce => ce_1_sg_x17,
clk => clk_1_sg_x17,
clr => '0',
ip(0) => mux_y_net_x0,
op(0) => inverter_op_net
);
logical: entity work.logical_938d99ac11
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => mux_y_net_x0,
d1(0) => delay_q_net,
y(0) => logical_y_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller/SPI"
entity spi_entity_fd37afb7f3 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
data_to_transfer: in std_logic_vector(8 downto 0);
dividerselect: in std_logic;
reset: in std_logic;
send: in std_logic;
cs: out std_logic;
data: out std_logic;
done: out std_logic;
scl: out std_logic
);
end spi_entity_fd37afb7f3;
architecture structural of spi_entity_fd37afb7f3 is
signal ce_1_sg_x19: std_logic;
signal clk_1_sg_x19: std_logic;
signal constant_op_net: std_logic_vector(3 downto 0);
signal convert1_dout_net_x7: std_logic;
signal convert1_dout_net_x8: std_logic;
signal convert_dout_net_x0: std_logic;
signal convert_dout_net_x1: std_logic;
signal counter1_op_net: std_logic_vector(3 downto 0);
signal counter_op_net_x0: std_logic_vector(3 downto 0);
signal delay1_q_net: std_logic;
signal delay_q_net: std_logic;
signal inverter1_op_net_x0: std_logic;
signal inverter_op_net_x0: std_logic;
signal logical_y_net: std_logic;
signal logical_y_net_x0: std_logic;
signal logical_y_net_x1: std_logic;
signal mux1_y_net: std_logic;
signal mux1_y_net_x1: std_logic;
signal mux_y_net_x3: std_logic_vector(8 downto 0);
signal mux_y_net_x4: std_logic;
signal mux_y_net_x5: std_logic;
signal register_q_net: std_logic;
signal slice1_y_net: std_logic;
signal slice2_y_net: std_logic;
signal slice_y_net: std_logic;
begin
ce_1_sg_x19 <= ce_1;
clk_1_sg_x19 <= clk_1;
mux_y_net_x3 <= data_to_transfer;
convert_dout_net_x1 <= dividerselect;
convert1_dout_net_x7 <= reset;
mux1_y_net_x1 <= send;
cs <= inverter_op_net_x0;
data <= mux_y_net_x4;
done <= convert1_dout_net_x8;
scl <= mux_y_net_x5;
constant_x0: entity work.constant_06590e4008
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant_op_net
);
convert: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din(0) => mux1_y_net,
dout(0) => convert_dout_net_x0
);
convert1: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din(0) => logical_y_net_x1,
dout(0) => convert1_dout_net_x8
);
counter: entity work.xlcounter_limit
generic map (
cnt_15_0 => 8,
cnt_31_16 => 0,
cnt_47_32 => 0,
cnt_63_48 => 0,
core_name0 => "binary_counter_virtex2p_7_0_23542cbcca0efa2e",
count_limited => 1,
op_arith => xlUnsigned,
op_width => 4
)
port map (
ce => ce_1_sg_x19,
clk => clk_1_sg_x19,
clr => '0',
en(0) => convert_dout_net_x0,
rst(0) => convert1_dout_net_x7,
op => counter_op_net_x0
);
counter1: entity work.xlcounter_free
generic map (
core_name0 => "binary_counter_virtex2p_7_0_77cea312f82499f0",
op_arith => xlUnsigned,
op_width => 4
)
port map (
ce => ce_1_sg_x19,
clk => clk_1_sg_x19,
clr => '0',
din => constant_op_net,
en(0) => register_q_net,
load(0) => convert1_dout_net_x8,
rst(0) => convert1_dout_net_x7,
op => counter1_op_net
);
data_latch_d697580f4e: entity work.data_latch_entity_d697580f4e
port map (
bit_select => counter_op_net_x0,
ce_1 => ce_1_sg_x19,
clk_1 => clk_1_sg_x19,
data_to_transmit => mux_y_net_x3,
latchdata => mux1_y_net_x1,
reset => convert1_dout_net_x7,
spi_data => mux_y_net_x4
);
delay: entity work.xldelay
generic map (
latency => 2,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x19,
clk => clk_1_sg_x19,
d(0) => logical_y_net_x0,
en => '1',
q(0) => delay_q_net
);
delay1: entity work.xldelay
generic map (
latency => 6,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x19,
clk => clk_1_sg_x19,
d(0) => logical_y_net_x0,
en => '1',
q(0) => delay1_q_net
);
inverter: entity work.inverter_e5b38cca3b
port map (
ce => ce_1_sg_x19,
clk => clk_1_sg_x19,
clr => '0',
ip(0) => register_q_net,
op(0) => inverter_op_net_x0
);
inverter1: entity work.inverter_e2b989a05e
port map (
ce => ce_1_sg_x19,
clk => clk_1_sg_x19,
clr => '0',
ip(0) => slice1_y_net,
op(0) => inverter1_op_net_x0
);
logical: entity work.logical_aacf6e1b0e
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => convert1_dout_net_x8,
d1(0) => mux1_y_net_x1,
y(0) => logical_y_net
);
mux: entity work.mux_112ed141f4
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => slice_y_net,
d1(0) => slice2_y_net,
sel(0) => convert_dout_net_x1,
y(0) => mux_y_net_x5
);
mux1: entity work.mux_112ed141f4
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => delay_q_net,
d1(0) => delay1_q_net,
sel(0) => convert_dout_net_x1,
y(0) => mux1_y_net
);
pos_edge_detector2_d448638b52: entity work.pos_edge_detector_entity_ac86c1f1ba
port map (
ce_1 => ce_1_sg_x19,
clk_1 => clk_1_sg_x19,
input_signal => inverter1_op_net_x0,
rising_edge => logical_y_net_x1
);
pos_edge_detector_ac86c1f1ba: entity work.pos_edge_detector_entity_ac86c1f1ba
port map (
ce_1 => ce_1_sg_x19,
clk_1 => clk_1_sg_x19,
input_signal => mux_y_net_x5,
rising_edge => logical_y_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x19,
clk => clk_1_sg_x19,
d(0) => mux1_y_net_x1,
en(0) => logical_y_net,
rst(0) => convert1_dout_net_x7,
q(0) => register_q_net
);
slice: entity work.xlslice
generic map (
new_lsb => 2,
new_msb => 2,
x_width => 4,
y_width => 1
)
port map (
x => counter1_op_net,
y(0) => slice_y_net
);
slice1: entity work.xlslice
generic map (
new_lsb => 3,
new_msb => 3,
x_width => 4,
y_width => 1
)
port map (
x => counter_op_net_x0,
y(0) => slice1_y_net
);
slice2: entity work.xlslice
generic map (
new_lsb => 3,
new_msb => 3,
x_width => 4,
y_width => 1
)
port map (
x => counter1_op_net,
y(0) => slice2_y_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller"
entity lcd_controller_entity_e3a358fc2f is
port (
ce_1: in std_logic;
clk_1: in std_logic;
from_register: in std_logic;
from_register1: in std_logic_vector(8 downto 0);
from_register1_x0: in std_logic_vector(8 downto 0);
from_register2: in std_logic_vector(8 downto 0);
from_register2_x0: in std_logic_vector(8 downto 0);
from_register3: in std_logic_vector(8 downto 0);
from_register3_x0: in std_logic_vector(8 downto 0);
from_register3_x1: in std_logic_vector(7 downto 0);
from_register4: in std_logic_vector(8 downto 0);
from_register4_x0: in std_logic_vector(2 downto 0);
from_register4_x1: in std_logic;
from_register5: in std_logic_vector(8 downto 0);
from_register5_x0: in std_logic_vector(3 downto 0);
from_register5_x1: in std_logic;
from_register6: in std_logic_vector(1 downto 0);
from_register6_x0: in std_logic;
from_register7: in std_logic_vector(3 downto 0);
reset: in std_logic;
shared_memory: in std_logic_vector(31 downto 0);
shared_memory_x0: in std_logic_vector(31 downto 0);
shared_memory_x1: in std_logic_vector(31 downto 0);
commandrom: out std_logic_vector(7 downto 0);
commandrom_x0: out std_logic_vector(31 downto 0);
commandrom_x1: out std_logic;
datarom: out std_logic_vector(8 downto 0);
datarom_x0: out std_logic_vector(31 downto 0);
datarom_x1: out std_logic;
datarom_x2: out std_logic_vector(11 downto 0);
datarom_x3: out std_logic_vector(31 downto 0);
datarom_x4: out std_logic;
delay_x0: out std_logic;
spi: out std_logic;
spi_x0: out std_logic;
spi_x1: out std_logic
);
end lcd_controller_entity_e3a358fc2f;
architecture structural of lcd_controller_entity_e3a358fc2f is
signal ce_1_sg_x20: std_logic;
signal clk_1_sg_x20: std_logic;
signal concat2_y_net_x0: std_logic_vector(8 downto 0);
signal concat4_y_net_x0: std_logic_vector(8 downto 0);
signal constant1_op_net_x4: std_logic;
signal constant1_op_net_x5: std_logic;
signal constant1_op_net_x6: std_logic;
signal constant_op_net_x4: std_logic_vector(31 downto 0);
signal constant_op_net_x5: std_logic_vector(31 downto 0);
signal constant_op_net_x6: std_logic_vector(31 downto 0);
signal convert1_dout_net_x7: std_logic;
signal convert1_dout_net_x8: std_logic;
signal convert2_dout_net_x0: std_logic;
signal convert_dout_net_x1: std_logic;
signal delay_q_net_x0: std_logic;
signal delay_q_net_x1: std_logic;
signal from_register1_data_out_net_x2: std_logic_vector(8 downto 0);
signal from_register1_data_out_net_x3: std_logic_vector(8 downto 0);
signal from_register2_data_out_net_x2: std_logic_vector(8 downto 0);
signal from_register2_data_out_net_x3: std_logic_vector(8 downto 0);
signal from_register3_data_out_net_x3: std_logic_vector(8 downto 0);
signal from_register3_data_out_net_x4: std_logic_vector(8 downto 0);
signal from_register3_data_out_net_x5: std_logic_vector(7 downto 0);
signal from_register4_data_out_net_x2: std_logic_vector(8 downto 0);
signal from_register4_data_out_net_x3: std_logic_vector(2 downto 0);
signal from_register4_data_out_net_x4: std_logic;
signal from_register5_data_out_net_x2: std_logic_vector(8 downto 0);
signal from_register5_data_out_net_x3: std_logic_vector(3 downto 0);
signal from_register5_data_out_net_x4: std_logic;
signal from_register6_data_out_net_x1: std_logic_vector(1 downto 0);
signal from_register6_data_out_net_x2: std_logic;
signal from_register7_data_out_net_x1: std_logic_vector(3 downto 0);
signal from_register_data_out_net_x0: std_logic;
signal inverter_op_net_x1: std_logic;
signal logical1_y_net: std_logic;
signal logical_y_net_x3: std_logic;
signal mux1_y_net_x1: std_logic;
signal mux2_y_net_x0: std_logic;
signal mux_y_net_x3: std_logic_vector(8 downto 0);
signal mux_y_net_x6: std_logic;
signal mux_y_net_x7: std_logic;
signal register_q_net_x1: std_logic;
signal reset_net_x0: std_logic;
signal shared_memory_data_out_net_x4: std_logic_vector(31 downto 0);
signal shared_memory_data_out_net_x5: std_logic_vector(31 downto 0);
signal shared_memory_data_out_net_x6: std_logic_vector(31 downto 0);
signal x12msb_y_net_x2: std_logic_vector(11 downto 0);
signal x8msb_y_net_x2: std_logic_vector(7 downto 0);
signal x9msb_y_net_x2: std_logic_vector(8 downto 0);
begin
ce_1_sg_x20 <= ce_1;
clk_1_sg_x20 <= clk_1;
from_register_data_out_net_x0 <= from_register;
from_register1_data_out_net_x2 <= from_register1;
from_register1_data_out_net_x3 <= from_register1_x0;
from_register2_data_out_net_x2 <= from_register2;
from_register2_data_out_net_x3 <= from_register2_x0;
from_register3_data_out_net_x3 <= from_register3;
from_register3_data_out_net_x4 <= from_register3_x0;
from_register3_data_out_net_x5 <= from_register3_x1;
from_register4_data_out_net_x2 <= from_register4;
from_register4_data_out_net_x3 <= from_register4_x0;
from_register4_data_out_net_x4 <= from_register4_x1;
from_register5_data_out_net_x2 <= from_register5;
from_register5_data_out_net_x3 <= from_register5_x0;
from_register5_data_out_net_x4 <= from_register5_x1;
from_register6_data_out_net_x1 <= from_register6;
from_register6_data_out_net_x2 <= from_register6_x0;
from_register7_data_out_net_x1 <= from_register7;
reset_net_x0 <= reset;
shared_memory_data_out_net_x4 <= shared_memory;
shared_memory_data_out_net_x5 <= shared_memory_x0;
shared_memory_data_out_net_x6 <= shared_memory_x1;
commandrom <= x8msb_y_net_x2;
commandrom_x0 <= constant_op_net_x4;
commandrom_x1 <= constant1_op_net_x4;
datarom <= x9msb_y_net_x2;
datarom_x0 <= constant_op_net_x5;
datarom_x1 <= constant1_op_net_x5;
datarom_x2 <= x12msb_y_net_x2;
datarom_x3 <= constant_op_net_x6;
datarom_x4 <= constant1_op_net_x6;
delay_x0 <= delay_q_net_x1;
spi <= mux_y_net_x6;
spi_x0 <= inverter_op_net_x1;
spi_x1 <= mux_y_net_x7;
commandrom_b68e0d97b7: entity work.commandrom_entity_b68e0d97b7
port map (
ce_1 => ce_1_sg_x20,
clk_1 => clk_1_sg_x20,
from_register1 => from_register1_data_out_net_x2,
from_register2 => from_register2_data_out_net_x2,
from_register3 => from_register3_data_out_net_x3,
from_register4 => from_register4_data_out_net_x2,
from_register5 => from_register5_data_out_net_x2,
from_register6 => from_register6_data_out_net_x1,
reset => convert1_dout_net_x7,
sendcmds => logical_y_net_x3,
shared_memory => shared_memory_data_out_net_x4,
totalnoofcmds => from_register3_data_out_net_x5,
transferdone => convert1_dout_net_x8,
cmdsdone => register_q_net_x1,
command_memory => x8msb_y_net_x2,
command_memory_x0 => constant_op_net_x4,
command_memory_x1 => constant1_op_net_x4,
datatosend => concat2_y_net_x0,
starttransfer => mux2_y_net_x0
);
convert: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din(0) => from_register4_data_out_net_x4,
dout(0) => convert_dout_net_x1
);
convert1: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din(0) => logical1_y_net,
dout(0) => convert1_dout_net_x7
);
convert2: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din(0) => from_register5_data_out_net_x4,
dout(0) => convert2_dout_net_x0
);
datarom_fd2cd392cc: entity work.datarom_entity_fd2cd392cc
port map (
ce_1 => ce_1_sg_x20,
clk_1 => clk_1_sg_x20,
cmdsdone => register_q_net_x1,
from_register1 => from_register1_data_out_net_x3,
from_register2 => from_register2_data_out_net_x3,
from_register3 => from_register3_data_out_net_x4,
from_register4 => from_register4_data_out_net_x3,
from_register5 => from_register5_data_out_net_x3,
from_register7 => from_register7_data_out_net_x1,
reset => convert1_dout_net_x7,
shared_memory => shared_memory_data_out_net_x5,
shared_memory_x0 => shared_memory_data_out_net_x6,
transferdone => convert1_dout_net_x8,
character_buffer_shared_memory => x9msb_y_net_x2,
character_buffer_shared_memory_x0 => constant_op_net_x5,
character_buffer_shared_memory_x1 => constant1_op_net_x5,
character_map_shared_memory => x12msb_y_net_x2,
character_map_shared_memory_x0 => constant_op_net_x6,
character_map_shared_memory_x1 => constant1_op_net_x6,
data => concat4_y_net_x0,
starttransfer => delay_q_net_x0
);
delay: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x20,
clk => clk_1_sg_x20,
d(0) => from_register6_data_out_net_x2,
en => '1',
q(0) => delay_q_net_x1
);
logical1: entity work.logical_3e1f051fb7
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => reset_net_x0,
d1(0) => from_register_data_out_net_x0,
y(0) => logical1_y_net
);
mux: entity work.mux_791081a00e
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => concat2_y_net_x0,
d1 => concat4_y_net_x0,
sel(0) => register_q_net_x1,
y => mux_y_net_x3
);
mux1: entity work.mux_d99e59b6d4
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => mux2_y_net_x0,
d1(0) => delay_q_net_x0,
sel(0) => register_q_net_x1,
y(0) => mux1_y_net_x1
);
pos_edge_detector_63345fcb1c: entity work.pos_edge_detector_entity_90ec5fccc3
port map (
ce_1 => ce_1_sg_x20,
clk_1 => clk_1_sg_x20,
input_signal => convert2_dout_net_x0,
rising_edge => logical_y_net_x3
);
spi_fd37afb7f3: entity work.spi_entity_fd37afb7f3
port map (
ce_1 => ce_1_sg_x20,
clk_1 => clk_1_sg_x20,
data_to_transfer => mux_y_net_x3,
dividerselect => convert_dout_net_x1,
reset => convert1_dout_net_x7,
send => mux1_y_net_x1,
cs => inverter_op_net_x1,
data => mux_y_net_x6,
done => convert1_dout_net_x8,
scl => mux_y_net_x7
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller"
entity user_io_board_controller is
port (
buttons_big: in std_logic_vector(1 downto 0);
buttons_small: in std_logic_vector(5 downto 0);
ce_1: in std_logic;
clk_1: in std_logic;
data_out: in std_logic_vector(17 downto 0);
data_out_x0: in std_logic_vector(17 downto 0);
data_out_x1: in std_logic;
data_out_x10: in std_logic;
data_out_x11: in std_logic_vector(7 downto 0);
data_out_x12: in std_logic;
data_out_x13: in std_logic;
data_out_x14: in std_logic;
data_out_x15: in std_logic_vector(8 downto 0);
data_out_x16: in std_logic_vector(8 downto 0);
data_out_x17: in std_logic_vector(8 downto 0);
data_out_x18: in std_logic_vector(8 downto 0);
data_out_x19: in std_logic_vector(8 downto 0);
data_out_x2: in std_logic_vector(1 downto 0);
data_out_x20: in std_logic_vector(1 downto 0);
data_out_x21: in std_logic_vector(31 downto 0);
data_out_x22: in std_logic_vector(3 downto 0);
data_out_x23: in std_logic_vector(3 downto 0);
data_out_x24: in std_logic_vector(8 downto 0);
data_out_x25: in std_logic_vector(8 downto 0);
data_out_x26: in std_logic_vector(8 downto 0);
data_out_x27: in std_logic_vector(2 downto 0);
data_out_x28: in std_logic_vector(31 downto 0);
data_out_x29: in std_logic_vector(31 downto 0);
data_out_x3: in std_logic_vector(5 downto 0);
data_out_x4: in std_logic_vector(3 downto 0);
data_out_x5: in std_logic_vector(4 downto 0);
data_out_x6: in std_logic_vector(31 downto 0);
data_out_x7: in std_logic_vector(31 downto 0);
data_out_x8: in std_logic_vector(31 downto 0);
data_out_x9: in std_logic_vector(7 downto 0);
dip_switch: in std_logic_vector(3 downto 0);
dout: in std_logic_vector(17 downto 0);
dout_x0: in std_logic;
dout_x1: in std_logic_vector(17 downto 0);
dout_x10: in std_logic_vector(3 downto 0);
dout_x11: in std_logic_vector(8 downto 0);
dout_x12: in std_logic;
dout_x13: in std_logic;
dout_x14: in std_logic_vector(8 downto 0);
dout_x15: in std_logic_vector(8 downto 0);
dout_x16: in std_logic_vector(8 downto 0);
dout_x17: in std_logic;
dout_x18: in std_logic_vector(7 downto 0);
dout_x19: in std_logic_vector(7 downto 0);
dout_x2: in std_logic_vector(8 downto 0);
dout_x3: in std_logic_vector(3 downto 0);
dout_x4: in std_logic_vector(2 downto 0);
dout_x5: in std_logic_vector(8 downto 0);
dout_x6: in std_logic_vector(1 downto 0);
dout_x7: in std_logic;
dout_x8: in std_logic_vector(8 downto 0);
dout_x9: in std_logic_vector(8 downto 0);
plb_abus: in std_logic_vector(31 downto 0);
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(31 downto 0);
reset: in std_logic;
sg_plb_addrpref: in std_logic_vector(14 downto 0);
splb_rst: in std_logic;
trackball_ox: in std_logic;
trackball_oxn: in std_logic;
trackball_oy: in std_logic;
trackball_oyn: in std_logic;
trackball_sel2: in std_logic;
addr: out std_logic_vector(11 downto 0);
addr_x0: out std_logic_vector(8 downto 0);
addr_x1: out std_logic_vector(7 downto 0);
addr_x2: out std_logic_vector(7 downto 0);
addr_x3: out std_logic_vector(8 downto 0);
addr_x4: out std_logic_vector(11 downto 0);
buzzer: out std_logic;
cs: out std_logic;
data_in: out std_logic_vector(17 downto 0);
data_in_x0: out std_logic;
data_in_x1: out std_logic_vector(17 downto 0);
data_in_x10: out std_logic_vector(3 downto 0);
data_in_x11: out std_logic_vector(8 downto 0);
data_in_x12: out std_logic;
data_in_x13: out std_logic;
data_in_x14: out std_logic_vector(8 downto 0);
data_in_x15: out std_logic_vector(8 downto 0);
data_in_x16: out std_logic_vector(8 downto 0);
data_in_x17: out std_logic;
data_in_x18: out std_logic_vector(7 downto 0);
data_in_x19: out std_logic_vector(7 downto 0);
data_in_x2: out std_logic_vector(8 downto 0);
data_in_x20: out std_logic_vector(31 downto 0);
data_in_x21: out std_logic_vector(31 downto 0);
data_in_x22: out std_logic_vector(31 downto 0);
data_in_x23: out std_logic_vector(4 downto 0);
data_in_x24: out std_logic_vector(1 downto 0);
data_in_x25: out std_logic_vector(5 downto 0);
data_in_x26: out std_logic_vector(3 downto 0);
data_in_x27: out std_logic_vector(31 downto 0);
data_in_x28: out std_logic_vector(31 downto 0);
data_in_x29: out std_logic_vector(31 downto 0);
data_in_x3: out std_logic_vector(3 downto 0);
data_in_x4: out std_logic_vector(2 downto 0);
data_in_x5: out std_logic_vector(8 downto 0);
data_in_x6: out std_logic_vector(1 downto 0);
data_in_x7: out std_logic;
data_in_x8: out std_logic_vector(8 downto 0);
data_in_x9: out std_logic_vector(8 downto 0);
en: out std_logic;
en_x0: out std_logic;
en_x1: out std_logic;
en_x10: out std_logic;
en_x11: out std_logic;
en_x12: out std_logic;
en_x13: out std_logic;
en_x14: out std_logic;
en_x15: out std_logic;
en_x16: out std_logic;
en_x17: out std_logic;
en_x18: out std_logic;
en_x19: out std_logic;
en_x2: out std_logic;
en_x20: out std_logic;
en_x21: out std_logic;
en_x22: out std_logic;
en_x23: out std_logic;
en_x3: out std_logic;
en_x4: out std_logic;
en_x5: out std_logic;
en_x6: out std_logic;
en_x7: out std_logic;
en_x8: out std_logic;
en_x9: out std_logic;
leds: out std_logic_vector(7 downto 0);
resetlcd: out std_logic;
scl: out std_logic;
sdi: out std_logic;
sl_addrack: out std_logic;
sl_rdcomp: out std_logic;
sl_rddack: out std_logic;
sl_rddbus: out std_logic_vector(31 downto 0);
sl_wait: out std_logic;
sl_wrcomp: out std_logic;
sl_wrdack: out std_logic;
trackball_sel1: out std_logic;
trackball_xscn: out std_logic;
trackball_yscn: out std_logic;
we: out std_logic;
we_x0: out std_logic;
we_x1: out std_logic;
we_x2: out std_logic;
we_x3: out std_logic;
we_x4: out std_logic
);
end user_io_board_controller;
architecture structural of user_io_board_controller is
signal addr_net: std_logic_vector(11 downto 0);
signal addr_x0_net: std_logic_vector(8 downto 0);
signal addr_x1_net: std_logic_vector(7 downto 0);
signal addr_x2_net: std_logic_vector(7 downto 0);
signal addr_x3_net: std_logic_vector(8 downto 0);
signal addr_x4_net: std_logic_vector(11 downto 0);
signal buttons_big_net: std_logic_vector(1 downto 0);
signal buttons_small_net: std_logic_vector(5 downto 0);
signal buzzer_net: std_logic;
signal ce_1_sg_x21: std_logic;
signal clk_1_sg_x21: std_logic;
signal cs_net: std_logic;
signal data_in_net: std_logic_vector(17 downto 0);
signal data_in_x0_net: std_logic;
signal data_in_x10_net: std_logic_vector(3 downto 0);
signal data_in_x11_net: std_logic_vector(8 downto 0);
signal data_in_x12_net: std_logic;
signal data_in_x13_net: std_logic;
signal data_in_x14_net: std_logic_vector(8 downto 0);
signal data_in_x15_net: std_logic_vector(8 downto 0);
signal data_in_x16_net: std_logic_vector(8 downto 0);
signal data_in_x17_net: std_logic;
signal data_in_x18_net: std_logic_vector(7 downto 0);
signal data_in_x19_net: std_logic_vector(7 downto 0);
signal data_in_x1_net: std_logic_vector(17 downto 0);
signal data_in_x20_net: std_logic_vector(31 downto 0);
signal data_in_x21_net: std_logic_vector(31 downto 0);
signal data_in_x22_net: std_logic_vector(31 downto 0);
signal data_in_x23_net: std_logic_vector(4 downto 0);
signal data_in_x24_net: std_logic_vector(1 downto 0);
signal data_in_x25_net: std_logic_vector(5 downto 0);
signal data_in_x26_net: std_logic_vector(3 downto 0);
signal data_in_x27_net: std_logic_vector(31 downto 0);
signal data_in_x28_net: std_logic_vector(31 downto 0);
signal data_in_x29_net: std_logic_vector(31 downto 0);
signal data_in_x2_net: std_logic_vector(8 downto 0);
signal data_in_x3_net: std_logic_vector(3 downto 0);
signal data_in_x4_net: std_logic_vector(2 downto 0);
signal data_in_x5_net: std_logic_vector(8 downto 0);
signal data_in_x6_net: std_logic_vector(1 downto 0);
signal data_in_x7_net: std_logic;
signal data_in_x8_net: std_logic_vector(8 downto 0);
signal data_in_x9_net: std_logic_vector(8 downto 0);
signal data_out_net: std_logic_vector(17 downto 0);
signal data_out_x0_net: std_logic_vector(17 downto 0);
signal data_out_x10_net: std_logic;
signal data_out_x11_net: std_logic_vector(7 downto 0);
signal data_out_x12_net: std_logic;
signal data_out_x13_net: std_logic;
signal data_out_x14_net: std_logic;
signal data_out_x15_net: std_logic_vector(8 downto 0);
signal data_out_x16_net: std_logic_vector(8 downto 0);
signal data_out_x17_net: std_logic_vector(8 downto 0);
signal data_out_x18_net: std_logic_vector(8 downto 0);
signal data_out_x19_net: std_logic_vector(8 downto 0);
signal data_out_x1_net: std_logic;
signal data_out_x20_net: std_logic_vector(1 downto 0);
signal data_out_x21_net: std_logic_vector(31 downto 0);
signal data_out_x22_net: std_logic_vector(3 downto 0);
signal data_out_x23_net: std_logic_vector(3 downto 0);
signal data_out_x24_net: std_logic_vector(8 downto 0);
signal data_out_x25_net: std_logic_vector(8 downto 0);
signal data_out_x26_net: std_logic_vector(8 downto 0);
signal data_out_x27_net: std_logic_vector(2 downto 0);
signal data_out_x28_net: std_logic_vector(31 downto 0);
signal data_out_x29_net: std_logic_vector(31 downto 0);
signal data_out_x2_net: std_logic_vector(1 downto 0);
signal data_out_x3_net: std_logic_vector(5 downto 0);
signal data_out_x4_net: std_logic_vector(3 downto 0);
signal data_out_x5_net: std_logic_vector(4 downto 0);
signal data_out_x6_net: std_logic_vector(31 downto 0);
signal data_out_x7_net: std_logic_vector(31 downto 0);
signal data_out_x8_net: std_logic_vector(31 downto 0);
signal data_out_x9_net: std_logic_vector(7 downto 0);
signal dip_switch_net: std_logic_vector(3 downto 0);
signal dout_net: std_logic_vector(17 downto 0);
signal dout_x0_net: std_logic;
signal dout_x10_net: std_logic_vector(3 downto 0);
signal dout_x11_net: std_logic_vector(8 downto 0);
signal dout_x12_net: std_logic;
signal dout_x13_net: std_logic;
signal dout_x14_net: std_logic_vector(8 downto 0);
signal dout_x15_net: std_logic_vector(8 downto 0);
signal dout_x16_net: std_logic_vector(8 downto 0);
signal dout_x17_net: std_logic;
signal dout_x18_net: std_logic_vector(7 downto 0);
signal dout_x19_net: std_logic_vector(7 downto 0);
signal dout_x1_net: std_logic_vector(17 downto 0);
signal dout_x2_net: std_logic_vector(8 downto 0);
signal dout_x3_net: std_logic_vector(3 downto 0);
signal dout_x4_net: std_logic_vector(2 downto 0);
signal dout_x5_net: std_logic_vector(8 downto 0);
signal dout_x6_net: std_logic_vector(1 downto 0);
signal dout_x7_net: std_logic;
signal dout_x8_net: std_logic_vector(8 downto 0);
signal dout_x9_net: std_logic_vector(8 downto 0);
signal en_net: std_logic;
signal en_x0_net: std_logic;
signal en_x10_net: std_logic;
signal en_x11_net: std_logic;
signal en_x12_net: std_logic;
signal en_x13_net: std_logic;
signal en_x14_net: std_logic;
signal en_x15_net: std_logic;
signal en_x16_net: std_logic;
signal en_x17_net: std_logic;
signal en_x18_net: std_logic;
signal en_x19_net: std_logic;
signal en_x1_net: std_logic;
signal en_x20_net: std_logic;
signal en_x21_net: std_logic;
signal en_x22_net: std_logic;
signal en_x23_net: std_logic;
signal en_x2_net: std_logic;
signal en_x3_net: std_logic;
signal en_x4_net: std_logic;
signal en_x5_net: std_logic;
signal en_x6_net: std_logic;
signal en_x7_net: std_logic;
signal en_x8_net: std_logic;
signal en_x9_net: std_logic;
signal leds_net: std_logic_vector(7 downto 0);
signal plb_abus_net: std_logic_vector(31 downto 0);
signal plb_pavalid_net: std_logic;
signal plb_rnw_net: std_logic;
signal plb_wrdbus_net: std_logic_vector(31 downto 0);
signal reset_net: std_logic;
signal resetlcd_net: std_logic;
signal scl_net: std_logic;
signal sdi_net: std_logic;
signal sg_plb_addrpref_net: std_logic_vector(14 downto 0);
signal sl_addrack_net: std_logic;
signal sl_rdcomp_net: std_logic;
signal sl_rddack_net: std_logic;
signal sl_rddbus_net: std_logic_vector(31 downto 0);
signal sl_wait_net: std_logic;
signal sl_wrdack_x1: std_logic;
signal splb_rst_net: std_logic;
signal trackball_ox_net: std_logic;
signal trackball_oxn_net: std_logic;
signal trackball_oy_net: std_logic;
signal trackball_oyn_net: std_logic;
signal trackball_sel1_net: std_logic;
signal trackball_sel2_net: std_logic;
signal trackball_xscn_net: std_logic;
signal trackball_yscn_net: std_logic;
signal we_net: std_logic;
signal we_x0_net: std_logic;
signal we_x1_net: std_logic;
signal we_x2_net: std_logic;
signal we_x3_net: std_logic;
signal we_x4_net: std_logic;
begin
buttons_big_net <= buttons_big;
buttons_small_net <= buttons_small;
ce_1_sg_x21 <= ce_1;
clk_1_sg_x21 <= clk_1;
data_out_net <= data_out;
data_out_x0_net <= data_out_x0;
data_out_x1_net <= data_out_x1;
data_out_x10_net <= data_out_x10;
data_out_x11_net <= data_out_x11;
data_out_x12_net <= data_out_x12;
data_out_x13_net <= data_out_x13;
data_out_x14_net <= data_out_x14;
data_out_x15_net <= data_out_x15;
data_out_x16_net <= data_out_x16;
data_out_x17_net <= data_out_x17;
data_out_x18_net <= data_out_x18;
data_out_x19_net <= data_out_x19;
data_out_x2_net <= data_out_x2;
data_out_x20_net <= data_out_x20;
data_out_x21_net <= data_out_x21;
data_out_x22_net <= data_out_x22;
data_out_x23_net <= data_out_x23;
data_out_x24_net <= data_out_x24;
data_out_x25_net <= data_out_x25;
data_out_x26_net <= data_out_x26;
data_out_x27_net <= data_out_x27;
data_out_x28_net <= data_out_x28;
data_out_x29_net <= data_out_x29;
data_out_x3_net <= data_out_x3;
data_out_x4_net <= data_out_x4;
data_out_x5_net <= data_out_x5;
data_out_x6_net <= data_out_x6;
data_out_x7_net <= data_out_x7;
data_out_x8_net <= data_out_x8;
data_out_x9_net <= data_out_x9;
dip_switch_net <= dip_switch;
dout_net <= dout;
dout_x0_net <= dout_x0;
dout_x1_net <= dout_x1;
dout_x10_net <= dout_x10;
dout_x11_net <= dout_x11;
dout_x12_net <= dout_x12;
dout_x13_net <= dout_x13;
dout_x14_net <= dout_x14;
dout_x15_net <= dout_x15;
dout_x16_net <= dout_x16;
dout_x17_net <= dout_x17;
dout_x18_net <= dout_x18;
dout_x19_net <= dout_x19;
dout_x2_net <= dout_x2;
dout_x3_net <= dout_x3;
dout_x4_net <= dout_x4;
dout_x5_net <= dout_x5;
dout_x6_net <= dout_x6;
dout_x7_net <= dout_x7;
dout_x8_net <= dout_x8;
dout_x9_net <= dout_x9;
plb_abus_net <= plb_abus;
plb_pavalid_net <= plb_pavalid;
plb_rnw_net <= plb_rnw;
plb_wrdbus_net <= plb_wrdbus;
reset_net <= reset;
sg_plb_addrpref_net <= sg_plb_addrpref;
splb_rst_net <= splb_rst;
trackball_ox_net <= trackball_ox;
trackball_oxn_net <= trackball_oxn;
trackball_oy_net <= trackball_oy;
trackball_oyn_net <= trackball_oyn;
trackball_sel2_net <= trackball_sel2;
addr <= addr_net;
addr_x0 <= addr_x0_net;
addr_x1 <= addr_x1_net;
addr_x2 <= addr_x2_net;
addr_x3 <= addr_x3_net;
addr_x4 <= addr_x4_net;
buzzer <= buzzer_net;
cs <= cs_net;
data_in <= data_in_net;
data_in_x0 <= data_in_x0_net;
data_in_x1 <= data_in_x1_net;
data_in_x10 <= data_in_x10_net;
data_in_x11 <= data_in_x11_net;
data_in_x12 <= data_in_x12_net;
data_in_x13 <= data_in_x13_net;
data_in_x14 <= data_in_x14_net;
data_in_x15 <= data_in_x15_net;
data_in_x16 <= data_in_x16_net;
data_in_x17 <= data_in_x17_net;
data_in_x18 <= data_in_x18_net;
data_in_x19 <= data_in_x19_net;
data_in_x2 <= data_in_x2_net;
data_in_x20 <= data_in_x20_net;
data_in_x21 <= data_in_x21_net;
data_in_x22 <= data_in_x22_net;
data_in_x23 <= data_in_x23_net;
data_in_x24 <= data_in_x24_net;
data_in_x25 <= data_in_x25_net;
data_in_x26 <= data_in_x26_net;
data_in_x27 <= data_in_x27_net;
data_in_x28 <= data_in_x28_net;
data_in_x29 <= data_in_x29_net;
data_in_x3 <= data_in_x3_net;
data_in_x4 <= data_in_x4_net;
data_in_x5 <= data_in_x5_net;
data_in_x6 <= data_in_x6_net;
data_in_x7 <= data_in_x7_net;
data_in_x8 <= data_in_x8_net;
data_in_x9 <= data_in_x9_net;
en <= en_net;
en_x0 <= en_x0_net;
en_x1 <= en_x1_net;
en_x10 <= en_x10_net;
en_x11 <= en_x11_net;
en_x12 <= en_x12_net;
en_x13 <= en_x13_net;
en_x14 <= en_x14_net;
en_x15 <= en_x15_net;
en_x16 <= en_x16_net;
en_x17 <= en_x17_net;
en_x18 <= en_x18_net;
en_x19 <= en_x19_net;
en_x2 <= en_x2_net;
en_x20 <= en_x20_net;
en_x21 <= en_x21_net;
en_x22 <= en_x22_net;
en_x23 <= en_x23_net;
en_x3 <= en_x3_net;
en_x4 <= en_x4_net;
en_x5 <= en_x5_net;
en_x6 <= en_x6_net;
en_x7 <= en_x7_net;
en_x8 <= en_x8_net;
en_x9 <= en_x9_net;
leds <= leds_net;
resetlcd <= resetlcd_net;
scl <= scl_net;
sdi <= sdi_net;
sl_addrack <= sl_addrack_net;
sl_rdcomp <= sl_rdcomp_net;
sl_rddack <= sl_rddack_net;
sl_rddbus <= sl_rddbus_net;
sl_wait <= sl_wait_net;
sl_wrcomp <= sl_wrdack_x1;
sl_wrdack <= sl_wrdack_x1;
trackball_sel1 <= trackball_sel1_net;
trackball_xscn <= trackball_xscn_net;
trackball_yscn <= trackball_yscn_net;
we <= we_net;
we_x0 <= we_x0_net;
we_x1 <= we_x1_net;
we_x2 <= we_x2_net;
we_x3 <= we_x3_net;
we_x4 <= we_x4_net;
buzzer_controller_063692c849: entity work.buzzer_controller_entity_063692c849
port map (
ce_1 => ce_1_sg_x21,
clk_1 => clk_1_sg_x21,
from_register => data_out_net,
from_register1 => data_out_x0_net,
from_register2 => data_out_x1_net,
register9_x0 => buzzer_net
);
edk_processor_94deb4def9: entity work.edk_processor_entity_94deb4def9
port map (
ce_1 => ce_1_sg_x21,
clk_1 => clk_1_sg_x21,
from_register => data_out_x2_net,
from_register1 => data_out_x3_net,
from_register2 => data_out_x4_net,
from_register3 => data_out_x5_net,
plb_abus => plb_abus_net,
plb_pavalid => plb_pavalid_net,
plb_rnw => plb_rnw_net,
plb_wrdbus => plb_wrdbus_net,
sg_plb_addrpref => sg_plb_addrpref_net,
shared_memory => data_out_x6_net,
shared_memory1 => data_out_x7_net,
shared_memory2 => data_out_x8_net,
splb_rst => splb_rst_net,
to_register => dout_net,
to_register1 => dout_x0_net,
to_register10 => dout_x9_net,
to_register11 => dout_x10_net,
to_register12 => dout_x11_net,
to_register13 => dout_x12_net,
to_register14 => dout_x13_net,
to_register15 => dout_x14_net,
to_register16 => dout_x15_net,
to_register17 => dout_x16_net,
to_register18 => dout_x17_net,
to_register19 => dout_x18_net,
to_register2 => dout_x1_net,
to_register20 => dout_x19_net,
to_register3 => dout_x2_net,
to_register4 => dout_x3_net,
to_register5 => dout_x4_net,
to_register6 => dout_x5_net,
to_register7 => dout_x6_net,
to_register8 => dout_x7_net,
to_register9 => dout_x8_net,
constant5_x0 => sl_wait_net,
plb_decode_x0 => sl_addrack_net,
plb_decode_x1 => sl_rdcomp_net,
plb_decode_x2 => sl_wrdack_x1,
plb_decode_x3 => sl_rddack_net,
plb_decode_x4 => sl_rddbus_net,
plb_memmap_x0 => data_in_net,
plb_memmap_x1 => en_net,
plb_memmap_x10 => data_in_x4_net,
plb_memmap_x11 => en_x4_net,
plb_memmap_x12 => data_in_x5_net,
plb_memmap_x13 => en_x5_net,
plb_memmap_x14 => data_in_x6_net,
plb_memmap_x15 => en_x6_net,
plb_memmap_x16 => data_in_x7_net,
plb_memmap_x17 => en_x7_net,
plb_memmap_x18 => data_in_x8_net,
plb_memmap_x19 => en_x8_net,
plb_memmap_x2 => data_in_x0_net,
plb_memmap_x20 => data_in_x9_net,
plb_memmap_x21 => en_x9_net,
plb_memmap_x22 => data_in_x10_net,
plb_memmap_x23 => en_x10_net,
plb_memmap_x24 => data_in_x11_net,
plb_memmap_x25 => en_x11_net,
plb_memmap_x26 => data_in_x12_net,
plb_memmap_x27 => en_x12_net,
plb_memmap_x28 => data_in_x13_net,
plb_memmap_x29 => en_x13_net,
plb_memmap_x3 => en_x0_net,
plb_memmap_x30 => data_in_x14_net,
plb_memmap_x31 => en_x14_net,
plb_memmap_x32 => data_in_x15_net,
plb_memmap_x33 => en_x15_net,
plb_memmap_x34 => data_in_x16_net,
plb_memmap_x35 => en_x16_net,
plb_memmap_x36 => data_in_x17_net,
plb_memmap_x37 => en_x17_net,
plb_memmap_x38 => data_in_x18_net,
plb_memmap_x39 => en_x18_net,
plb_memmap_x4 => data_in_x1_net,
plb_memmap_x40 => data_in_x19_net,
plb_memmap_x41 => en_x19_net,
plb_memmap_x42 => addr_net,
plb_memmap_x43 => data_in_x20_net,
plb_memmap_x44 => we_net,
plb_memmap_x45 => addr_x0_net,
plb_memmap_x46 => data_in_x21_net,
plb_memmap_x47 => we_x0_net,
plb_memmap_x48 => addr_x1_net,
plb_memmap_x49 => data_in_x22_net,
plb_memmap_x5 => en_x1_net,
plb_memmap_x50 => we_x1_net,
plb_memmap_x6 => data_in_x2_net,
plb_memmap_x7 => en_x2_net,
plb_memmap_x8 => data_in_x3_net,
plb_memmap_x9 => en_x3_net
);
lcd_controller_e3a358fc2f: entity work.lcd_controller_entity_e3a358fc2f
port map (
ce_1 => ce_1_sg_x21,
clk_1 => clk_1_sg_x21,
from_register => data_out_x10_net,
from_register1 => data_out_x15_net,
from_register1_x0 => data_out_x24_net,
from_register2 => data_out_x16_net,
from_register2_x0 => data_out_x25_net,
from_register3 => data_out_x17_net,
from_register3_x0 => data_out_x26_net,
from_register3_x1 => data_out_x11_net,
from_register4 => data_out_x18_net,
from_register4_x0 => data_out_x27_net,
from_register4_x1 => data_out_x12_net,
from_register5 => data_out_x19_net,
from_register5_x0 => data_out_x23_net,
from_register5_x1 => data_out_x13_net,
from_register6 => data_out_x20_net,
from_register6_x0 => data_out_x14_net,
from_register7 => data_out_x22_net,
reset => reset_net,
shared_memory => data_out_x21_net,
shared_memory_x0 => data_out_x28_net,
shared_memory_x1 => data_out_x29_net,
commandrom => addr_x2_net,
commandrom_x0 => data_in_x27_net,
commandrom_x1 => we_x2_net,
datarom => addr_x3_net,
datarom_x0 => data_in_x28_net,
datarom_x1 => we_x3_net,
datarom_x2 => addr_x4_net,
datarom_x3 => data_in_x29_net,
datarom_x4 => we_x4_net,
delay_x0 => resetlcd_net,
spi => sdi_net,
spi_x0 => cs_net,
spi_x1 => scl_net
);
o_1f30dfdbf5: entity work.o_entity_1f30dfdbf5
port map (
buttons_big => buttons_big_net,
buttons_small => buttons_small_net,
ce_1 => ce_1_sg_x21,
clk_1 => clk_1_sg_x21,
dip_switch => dip_switch_net,
from_register => data_out_x9_net,
trackball_ox => trackball_ox_net,
trackball_oxn => trackball_oxn_net,
trackball_oy => trackball_oy_net,
trackball_oyn => trackball_oyn_net,
trackball_sel2 => trackball_sel2_net,
concat_x0 => data_in_x23_net,
constant2_x0 => en_x21_net,
constant4_x0 => en_x22_net,
constant6_x0 => en_x23_net,
constant_x1 => en_x20_net,
register10_x0 => trackball_xscn_net,
register11_x0 => trackball_yscn_net,
register12_x0 => trackball_sel1_net,
register3_x0 => data_in_x24_net,
register5_x0 => data_in_x25_net,
register7_x0 => data_in_x26_net,
register9_x0 => leds_net
);
end structural;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
use work.clock_pkg.all;
entity xlclkprobe is
port (clk : in std_logic;
clr : in std_logic;
ce : in std_logic;
fakeOutForXst : out std_logic);
end xlclkprobe;
architecture behavior of xlclkprobe is
begin
fakeOutForXst <= '0';
-- synopsys translate_off
work.clock_pkg.int_clk <= clk;
-- synopsys translate_on
end behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
entity xlclockdriver is
generic (
period: integer := 2;
log_2_period: integer := 0;
pipeline_regs: integer := 5;
use_bufg: integer := 0
);
port (
sysclk: in std_logic;
sysclr: in std_logic;
sysce: in std_logic;
clk: out std_logic;
clr: out std_logic;
ce: out std_logic
);
end xlclockdriver;
architecture behavior of xlclockdriver is
component bufg
port (
i: in std_logic;
o: out std_logic
);
end component;
component synth_reg_w_init
generic (
width: integer;
init_index: integer;
init_value: bit_vector;
latency: integer
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
function size_of_uint(inp: integer; power_of_2: boolean)
return integer
is
constant inp_vec: std_logic_vector(31 downto 0) :=
integer_to_std_logic_vector(inp,32, xlUnsigned);
variable result: integer;
begin
result := 32;
for i in 0 to 31 loop
if inp_vec(i) = '1' then
result := i;
end if;
end loop;
if power_of_2 then
return result;
else
return result+1;
end if;
end;
function is_power_of_2(inp: std_logic_vector)
return boolean
is
constant width: integer := inp'length;
variable vec: std_logic_vector(width - 1 downto 0);
variable single_bit_set: boolean;
variable more_than_one_bit_set: boolean;
variable result: boolean;
begin
vec := inp;
single_bit_set := false;
more_than_one_bit_set := false;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if width > 0 then
for i in 0 to width - 1 loop
if vec(i) = '1' then
if single_bit_set then
more_than_one_bit_set := true;
end if;
single_bit_set := true;
end if;
end loop;
end if;
if (single_bit_set and not(more_than_one_bit_set)) then
result := true;
else
result := false;
end if;
return result;
end;
function ce_reg_init_val(index, period : integer)
return integer
is
variable result: integer;
begin
result := 0;
if ((index mod period) = 0) then
result := 1;
end if;
return result;
end;
function remaining_pipe_regs(num_pipeline_regs, period : integer)
return integer
is
variable factor, result: integer;
begin
factor := (num_pipeline_regs / period);
result := num_pipeline_regs - (period * factor) + 1;
return result;
end;
function sg_min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
constant max_pipeline_regs : integer := 8;
constant pipe_regs : integer := 5;
constant num_pipeline_regs : integer := sg_min(pipeline_regs, max_pipeline_regs);
constant rem_pipeline_regs : integer := remaining_pipe_regs(num_pipeline_regs,period);
constant period_floor: integer := max(2, period);
constant power_of_2_counter: boolean :=
is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned));
constant cnt_width: integer :=
size_of_uint(period_floor, power_of_2_counter);
constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned);
constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned);
constant clk_for_ce_pulse_minus_regs: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector(max(0,period - rem_pipeline_regs),cnt_width, xlUnsigned);
signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0');
signal ce_vec : std_logic_vector(num_pipeline_regs downto 0);
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of ce_vec:signal is "REDUCE";
signal internal_ce: std_logic_vector(0 downto 0);
signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0);
begin
clk <= sysclk;
clr <= sysclr;
cntr_gen: process(sysclk)
begin
if sysclk'event and sysclk = '1' then
if (sysce = '1') then
if ((cnt_clr_dly(0) = '1') or (sysclr = '1')) then
clk_num <= (others => '0');
else
clk_num <= clk_num + 1;
end if;
end if;
end if;
end process;
clr_gen: process(clk_num, sysclr)
begin
if power_of_2_counter then
cnt_clr(0) <= sysclr;
else
if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1
or sysclr = '1') then
cnt_clr(0) <= '1';
else
cnt_clr(0) <= '0';
end if;
end if;
end process;
clr_reg: synth_reg_w_init
generic map (
width => 1,
init_index => 0,
init_value => b"0000",
latency => 1
)
port map (
i => cnt_clr,
ce => sysce,
clr => sysclr,
clk => sysclk,
o => cnt_clr_dly
);
pipelined_ce : if period > 1 generate
ce_gen: process(clk_num)
begin
if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then
ce_vec(num_pipeline_regs) <= '1';
else
ce_vec(num_pipeline_regs) <= '0';
end if;
end process;
ce_pipeline: for index in num_pipeline_regs downto 1 generate
ce_reg : synth_reg_w_init
generic map (
width => 1,
init_index => ce_reg_init_val(index, period),
init_value => b"0000",
latency => 1
)
port map (
i => ce_vec(index downto index),
ce => sysce,
clr => sysclr,
clk => sysclk,
o => ce_vec(index-1 downto index-1)
);
end generate;
internal_ce <= ce_vec(0 downto 0);
end generate;
use_bufg_true: if period > 1 and use_bufg = 1 generate
ce_bufg_inst: bufg
port map (
i => internal_ce(0),
o => ce
);
end generate;
use_bufg_false: if period > 1 and (use_bufg = 0) generate
ce <= internal_ce(0);
end generate;
generate_system_clk: if period = 1 generate
ce <= sysce;
end generate;
end architecture behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity xland2 is
port (
a : in std_logic;
b : in std_logic;
dout : out std_logic
);
end xland2;
architecture behavior of xland2 is
begin
dout <= a and b;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity default_clock_driver is
port (
sysce: in std_logic;
sysce_clr: in std_logic;
sysclk: in std_logic;
ce_1: out std_logic;
clk_1: out std_logic
);
end default_clock_driver;
architecture structural of default_clock_driver is
attribute syn_noprune: boolean;
attribute syn_noprune of structural : architecture is true;
attribute optimize_primitives: boolean;
attribute optimize_primitives of structural : architecture is false;
attribute dont_touch: boolean;
attribute dont_touch of structural : architecture is true;
signal sysce_clr_x0: std_logic;
signal sysce_x0: std_logic;
signal sysclk_x0: std_logic;
signal xlclockdriver_1_ce: std_logic;
signal xlclockdriver_1_clk: std_logic;
begin
sysce_x0 <= sysce;
sysce_clr_x0 <= sysce_clr;
sysclk_x0 <= sysclk;
ce_1 <= xlclockdriver_1_ce;
clk_1 <= xlclockdriver_1_clk;
xlclockdriver_1: entity work.xlclockdriver
generic map (
log_2_period => 1,
period => 1,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_1_ce,
clk => xlclockdriver_1_clk
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity user_io_board_controller_cw is
port (
buttons_big: in std_logic_vector(1 downto 0);
buttons_small: in std_logic_vector(5 downto 0);
ce: in std_logic := '1';
clk: in std_logic; -- clock period = 10.0 ns (100.0 Mhz)
dip_switch: in std_logic_vector(3 downto 0);
plb_abus: in std_logic_vector(31 downto 0);
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(31 downto 0);
reset: in std_logic;
sg_plb_addrpref: in std_logic_vector(14 downto 0);
splb_rst: in std_logic;
trackball_ox: in std_logic;
trackball_oxn: in std_logic;
trackball_oy: in std_logic;
trackball_oyn: in std_logic;
trackball_sel2: in std_logic;
buzzer: out std_logic;
cs: out std_logic;
leds: out std_logic_vector(7 downto 0);
resetlcd: out std_logic;
scl: out std_logic;
sdi: out std_logic;
sl_addrack: out std_logic;
sl_rdcomp: out std_logic;
sl_rddack: out std_logic;
sl_rddbus: out std_logic_vector(31 downto 0);
sl_wait: out std_logic;
sl_wrcomp: out std_logic;
sl_wrdack: out std_logic;
trackball_sel1: out std_logic;
trackball_xscn: out std_logic;
trackball_yscn: out std_logic
);
end user_io_board_controller_cw;
architecture structural of user_io_board_controller_cw is
component dual_port_block_memory_virtex2p_6_3_25371f622c89ba44
port (
addra: in std_logic_vector(8 downto 0);
addrb: in std_logic_vector(8 downto 0);
clka: in std_logic;
clkb: in std_logic;
dina: in std_logic_vector(31 downto 0);
dinb: in std_logic_vector(31 downto 0);
ena: in std_logic;
enb: in std_logic;
wea: in std_logic;
web: in std_logic;
douta: out std_logic_vector(31 downto 0);
doutb: out std_logic_vector(31 downto 0)
);
end component;
attribute syn_black_box: boolean;
attribute syn_black_box of dual_port_block_memory_virtex2p_6_3_25371f622c89ba44: component is true;
attribute box_type: string;
attribute box_type of dual_port_block_memory_virtex2p_6_3_25371f622c89ba44: component is "black_box";
attribute syn_noprune: boolean;
attribute optimize_primitives: boolean;
attribute dont_touch: boolean;
attribute syn_noprune of dual_port_block_memory_virtex2p_6_3_25371f622c89ba44: component is true;
attribute optimize_primitives of dual_port_block_memory_virtex2p_6_3_25371f622c89ba44: component is false;
attribute dont_touch of dual_port_block_memory_virtex2p_6_3_25371f622c89ba44: component is true;
component dual_port_block_memory_virtex2p_6_3_e98c3706f2ec2c76
port (
addra: in std_logic_vector(11 downto 0);
addrb: in std_logic_vector(11 downto 0);
clka: in std_logic;
clkb: in std_logic;
dina: in std_logic_vector(31 downto 0);
dinb: in std_logic_vector(31 downto 0);
ena: in std_logic;
enb: in std_logic;
wea: in std_logic;
web: in std_logic;
douta: out std_logic_vector(31 downto 0);
doutb: out std_logic_vector(31 downto 0)
);
end component;
attribute syn_black_box of dual_port_block_memory_virtex2p_6_3_e98c3706f2ec2c76: component is true;
attribute box_type of dual_port_block_memory_virtex2p_6_3_e98c3706f2ec2c76: component is "black_box";
attribute syn_noprune of dual_port_block_memory_virtex2p_6_3_e98c3706f2ec2c76: component is true;
attribute optimize_primitives of dual_port_block_memory_virtex2p_6_3_e98c3706f2ec2c76: component is false;
attribute dont_touch of dual_port_block_memory_virtex2p_6_3_e98c3706f2ec2c76: component is true;
component dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8
port (
addra: in std_logic_vector(7 downto 0);
addrb: in std_logic_vector(7 downto 0);
clka: in std_logic;
clkb: in std_logic;
dina: in std_logic_vector(31 downto 0);
dinb: in std_logic_vector(31 downto 0);
ena: in std_logic;
enb: in std_logic;
wea: in std_logic;
web: in std_logic;
douta: out std_logic_vector(31 downto 0);
doutb: out std_logic_vector(31 downto 0)
);
end component;
attribute syn_black_box of dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8: component is true;
attribute box_type of dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8: component is "black_box";
attribute syn_noprune of dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8: component is true;
attribute optimize_primitives of dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8: component is false;
attribute dont_touch of dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8: component is true;
component xlpersistentdff
port (
clk: in std_logic;
d: in std_logic;
q: out std_logic
);
end component;
attribute syn_black_box of xlpersistentdff: component is true;
attribute box_type of xlpersistentdff: component is "black_box";
attribute syn_noprune of xlpersistentdff: component is true;
attribute optimize_primitives of xlpersistentdff: component is false;
attribute dont_touch of xlpersistentdff: component is true;
signal Buttons_Big_reg_ce: std_logic;
signal Buttons_Small_reg_ce: std_logic;
signal Buzzer_DutyCycle_reg_ce: std_logic;
signal Buzzer_Enable_reg_ce: std_logic;
signal Buzzer_Period_reg_ce: std_logic;
signal DIP_Switch_reg_ce: std_logic;
signal LCD_BackgroundColor_reg_ce: std_logic;
signal LCD_CharacterOffset_reg_ce: std_logic;
signal LCD_CharactersSelect_reg_ce: std_logic;
signal LCD_ColSet_reg_ce: std_logic;
signal LCD_ConfigLocation_reg_ce: std_logic;
signal LCD_DividerSelect_reg_ce: std_logic;
signal LCD_FirstEnd_reg_ce: std_logic;
signal LCD_FirstStart_reg_ce: std_logic;
signal LCD_LineOffset_reg_ce: std_logic;
signal LCD_RamWrite_reg_ce: std_logic;
signal LCD_ResetLCD_reg_ce: std_logic;
signal LCD_Reset_reg_ce: std_logic;
signal LCD_RowSet_reg_ce: std_logic;
signal LCD_SecondEnd_reg_ce: std_logic;
signal LCD_SecondStart_reg_ce: std_logic;
signal LCD_Send_reg_ce: std_logic;
signal LCD_TotalCmdTransfer_reg_ce: std_logic;
signal LEDs_reg_ce: std_logic;
signal Trackball_reg_ce: std_logic;
signal addr_net: std_logic_vector(11 downto 0);
signal addr_x0_net: std_logic_vector(8 downto 0);
signal addr_x1_net: std_logic_vector(7 downto 0);
signal addr_x2_net: std_logic_vector(7 downto 0);
signal addr_x3_net: std_logic_vector(8 downto 0);
signal addr_x4_net: std_logic_vector(11 downto 0);
signal buttons_big_net: std_logic_vector(1 downto 0);
signal buttons_small_net: std_logic_vector(5 downto 0);
signal buzzer_net: std_logic;
signal ce_1_sg_x21: std_logic;
attribute MAX_FANOUT: string;
attribute MAX_FANOUT of ce_1_sg_x21: signal is "REDUCE";
signal clkNet: std_logic;
signal clk_1_sg_x21: std_logic;
signal cs_net: std_logic;
signal data_in_net: std_logic_vector(17 downto 0);
signal data_in_x0_net: std_logic;
signal data_in_x10_net: std_logic_vector(3 downto 0);
signal data_in_x11_net: std_logic_vector(8 downto 0);
signal data_in_x12_net: std_logic;
signal data_in_x13_net: std_logic;
signal data_in_x14_net: std_logic_vector(8 downto 0);
signal data_in_x15_net: std_logic_vector(8 downto 0);
signal data_in_x16_net: std_logic_vector(8 downto 0);
signal data_in_x17_net: std_logic;
signal data_in_x18_net: std_logic_vector(7 downto 0);
signal data_in_x19_net: std_logic_vector(7 downto 0);
signal data_in_x1_net: std_logic_vector(17 downto 0);
signal data_in_x20_net: std_logic_vector(31 downto 0);
signal data_in_x21_net: std_logic_vector(31 downto 0);
signal data_in_x22_net: std_logic_vector(31 downto 0);
signal data_in_x23_net: std_logic_vector(4 downto 0);
signal data_in_x24_net: std_logic_vector(1 downto 0);
signal data_in_x25_net: std_logic_vector(5 downto 0);
signal data_in_x26_net: std_logic_vector(3 downto 0);
signal data_in_x27_net: std_logic_vector(31 downto 0);
signal data_in_x28_net: std_logic_vector(31 downto 0);
signal data_in_x29_net: std_logic_vector(31 downto 0);
signal data_in_x2_net: std_logic_vector(8 downto 0);
signal data_in_x3_net: std_logic_vector(3 downto 0);
signal data_in_x4_net: std_logic_vector(2 downto 0);
signal data_in_x5_net: std_logic_vector(8 downto 0);
signal data_in_x6_net: std_logic_vector(1 downto 0);
signal data_in_x7_net: std_logic;
signal data_in_x8_net: std_logic_vector(8 downto 0);
signal data_in_x9_net: std_logic_vector(8 downto 0);
signal data_out_net: std_logic_vector(17 downto 0);
signal data_out_x0_net: std_logic_vector(17 downto 0);
signal data_out_x10_net: std_logic;
signal data_out_x11_net: std_logic_vector(7 downto 0);
signal data_out_x12_net: std_logic;
signal data_out_x13_net: std_logic;
signal data_out_x14_net: std_logic;
signal data_out_x15_net: std_logic_vector(8 downto 0);
signal data_out_x16_net: std_logic_vector(8 downto 0);
signal data_out_x17_net: std_logic_vector(8 downto 0);
signal data_out_x18_net: std_logic_vector(8 downto 0);
signal data_out_x19_net: std_logic_vector(8 downto 0);
signal data_out_x1_net: std_logic;
signal data_out_x20_net: std_logic_vector(1 downto 0);
signal data_out_x21_net: std_logic_vector(31 downto 0);
signal data_out_x22_net: std_logic_vector(3 downto 0);
signal data_out_x23_net: std_logic_vector(3 downto 0);
signal data_out_x24_net: std_logic_vector(8 downto 0);
signal data_out_x25_net: std_logic_vector(8 downto 0);
signal data_out_x26_net: std_logic_vector(8 downto 0);
signal data_out_x27_net: std_logic_vector(2 downto 0);
signal data_out_x28_net: std_logic_vector(31 downto 0);
signal data_out_x29_net: std_logic_vector(31 downto 0);
signal data_out_x2_net: std_logic_vector(1 downto 0);
signal data_out_x3_net: std_logic_vector(5 downto 0);
signal data_out_x4_net: std_logic_vector(3 downto 0);
signal data_out_x5_net: std_logic_vector(4 downto 0);
signal data_out_x6_net: std_logic_vector(31 downto 0);
signal data_out_x7_net: std_logic_vector(31 downto 0);
signal data_out_x8_net: std_logic_vector(31 downto 0);
signal data_out_x9_net: std_logic_vector(7 downto 0);
signal dip_switch_net: std_logic_vector(3 downto 0);
signal en_net: std_logic;
signal en_x0_net: std_logic;
signal en_x10_net: std_logic;
signal en_x11_net: std_logic;
signal en_x12_net: std_logic;
signal en_x13_net: std_logic;
signal en_x14_net: std_logic;
signal en_x15_net: std_logic;
signal en_x16_net: std_logic;
signal en_x17_net: std_logic;
signal en_x18_net: std_logic;
signal en_x19_net: std_logic;
signal en_x1_net: std_logic;
signal en_x20_net: std_logic;
signal en_x21_net: std_logic;
signal en_x22_net: std_logic;
signal en_x23_net: std_logic;
signal en_x2_net: std_logic;
signal en_x3_net: std_logic;
signal en_x4_net: std_logic;
signal en_x5_net: std_logic;
signal en_x6_net: std_logic;
signal en_x7_net: std_logic;
signal en_x8_net: std_logic;
signal en_x9_net: std_logic;
signal leds_net: std_logic_vector(7 downto 0);
signal persistentdff_inst_q: std_logic;
attribute syn_keep: boolean;
attribute syn_keep of persistentdff_inst_q: signal is true;
attribute keep: boolean;
attribute keep of persistentdff_inst_q: signal is true;
attribute preserve_signal: boolean;
attribute preserve_signal of persistentdff_inst_q: signal is true;
signal plb_abus_net: std_logic_vector(31 downto 0);
signal plb_pavalid_net: std_logic;
signal plb_rnw_net: std_logic;
signal plb_wrdbus_net: std_logic_vector(31 downto 0);
signal reset_net: std_logic;
signal resetlcd_net: std_logic;
signal scl_net: std_logic;
signal sdi_net: std_logic;
signal sg_plb_addrpref_net: std_logic_vector(14 downto 0);
signal sl_addrack_net: std_logic;
signal sl_rdcomp_net: std_logic;
signal sl_rddack_net: std_logic;
signal sl_rddbus_net: std_logic_vector(31 downto 0);
signal sl_wait_net: std_logic;
signal sl_wrdack_x1: std_logic;
signal sl_wrdack_x2: std_logic;
signal splb_rst_net: std_logic;
signal trackball_ox_net: std_logic;
signal trackball_oxn_net: std_logic;
signal trackball_oy_net: std_logic;
signal trackball_oyn_net: std_logic;
signal trackball_sel1_net: std_logic;
signal trackball_sel2_net: std_logic;
signal trackball_xscn_net: std_logic;
signal trackball_yscn_net: std_logic;
signal we_net: std_logic;
signal we_x0_net: std_logic;
signal we_x1_net: std_logic;
signal we_x2_net: std_logic;
signal we_x3_net: std_logic;
signal we_x4_net: std_logic;
begin
buttons_big_net <= buttons_big;
buttons_small_net <= buttons_small;
clkNet <= clk;
dip_switch_net <= dip_switch;
plb_abus_net <= plb_abus;
plb_pavalid_net <= plb_pavalid;
plb_rnw_net <= plb_rnw;
plb_wrdbus_net <= plb_wrdbus;
reset_net <= reset;
sg_plb_addrpref_net <= sg_plb_addrpref;
splb_rst_net <= splb_rst;
trackball_ox_net <= trackball_ox;
trackball_oxn_net <= trackball_oxn;
trackball_oy_net <= trackball_oy;
trackball_oyn_net <= trackball_oyn;
trackball_sel2_net <= trackball_sel2;
buzzer <= buzzer_net;
cs <= cs_net;
leds <= leds_net;
resetlcd <= resetlcd_net;
scl <= scl_net;
sdi <= sdi_net;
sl_addrack <= sl_addrack_net;
sl_rdcomp <= sl_rdcomp_net;
sl_rddack <= sl_rddack_net;
sl_rddbus <= sl_rddbus_net;
sl_wait <= sl_wait_net;
sl_wrcomp <= sl_wrdack_x2;
sl_wrdack <= sl_wrdack_x1;
trackball_sel1 <= trackball_sel1_net;
trackball_xscn <= trackball_xscn_net;
trackball_yscn <= trackball_yscn_net;
Buttons_Big_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x21_net,
dout => Buttons_Big_reg_ce
);
Buttons_Big_x0: entity work.synth_reg_w_init
generic map (
width => 2,
init_index => 2,
init_value => b"00",
latency => 1
)
port map (
ce => Buttons_Big_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x24_net,
o => data_out_x2_net
);
Buttons_Small_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x22_net,
dout => Buttons_Small_reg_ce
);
Buttons_Small_x0: entity work.synth_reg_w_init
generic map (
width => 6,
init_index => 2,
init_value => b"000000",
latency => 1
)
port map (
ce => Buttons_Small_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x25_net,
o => data_out_x3_net
);
Buzzer_DutyCycle: entity work.synth_reg_w_init
generic map (
width => 18,
init_index => 2,
init_value => b"000000000000000000",
latency => 1
)
port map (
ce => Buzzer_DutyCycle_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_net,
o => data_out_x0_net
);
Buzzer_DutyCycle_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_net,
dout => Buzzer_DutyCycle_reg_ce
);
Buzzer_Enable: entity work.synth_reg_w_init
generic map (
width => 1,
init_index => 2,
init_value => b"0",
latency => 1
)
port map (
ce => Buzzer_Enable_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i(0) => data_in_x0_net,
o(0) => data_out_x1_net
);
Buzzer_Enable_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x0_net,
dout => Buzzer_Enable_reg_ce
);
Buzzer_Period: entity work.synth_reg_w_init
generic map (
width => 18,
init_index => 2,
init_value => b"000000000000000000",
latency => 1
)
port map (
ce => Buzzer_Period_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x1_net,
o => data_out_net
);
Buzzer_Period_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x1_net,
dout => Buzzer_Period_reg_ce
);
DIP_Switch_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x23_net,
dout => DIP_Switch_reg_ce
);
DIP_Switch_x0: entity work.synth_reg_w_init
generic map (
width => 4,
init_index => 2,
init_value => b"0000",
latency => 1
)
port map (
ce => DIP_Switch_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x26_net,
o => data_out_x4_net
);
LCD_BackgroundColor: entity work.synth_reg_w_init
generic map (
width => 9,
init_index => 2,
init_value => b"000000000",
latency => 1
)
port map (
ce => LCD_BackgroundColor_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x2_net,
o => data_out_x17_net
);
LCD_BackgroundColor_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x2_net,
dout => LCD_BackgroundColor_reg_ce
);
LCD_CharacterMap: dual_port_block_memory_virtex2p_6_3_e98c3706f2ec2c76
port map (
addra => addr_x4_net,
addrb => addr_net,
clka => clk_1_sg_x21,
clkb => clk_1_sg_x21,
dina => data_in_x29_net,
dinb => data_in_x20_net,
ena => ce_1_sg_x21,
enb => ce_1_sg_x21,
wea => we_x4_net,
web => we_net,
douta => data_out_x29_net,
doutb => data_out_x6_net
);
LCD_CharacterOffset: entity work.synth_reg_w_init
generic map (
width => 4,
init_index => 2,
init_value => b"0000",
latency => 1
)
port map (
ce => LCD_CharacterOffset_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x3_net,
o => data_out_x23_net
);
LCD_CharacterOffset_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x3_net,
dout => LCD_CharacterOffset_reg_ce
);
LCD_Characters: dual_port_block_memory_virtex2p_6_3_25371f622c89ba44
port map (
addra => addr_x3_net,
addrb => addr_x0_net,
clka => clk_1_sg_x21,
clkb => clk_1_sg_x21,
dina => data_in_x28_net,
dinb => data_in_x21_net,
ena => ce_1_sg_x21,
enb => ce_1_sg_x21,
wea => we_x3_net,
web => we_x0_net,
douta => data_out_x28_net,
doutb => data_out_x7_net
);
LCD_CharactersSelect: entity work.synth_reg_w_init
generic map (
width => 3,
init_index => 2,
init_value => b"000",
latency => 1
)
port map (
ce => LCD_CharactersSelect_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x4_net,
o => data_out_x27_net
);
LCD_CharactersSelect_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x4_net,
dout => LCD_CharactersSelect_reg_ce
);
LCD_ColSet: entity work.synth_reg_w_init
generic map (
width => 9,
init_index => 2,
init_value => b"000000000",
latency => 1
)
port map (
ce => LCD_ColSet_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x5_net,
o => data_out_x24_net
);
LCD_ColSet_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x5_net,
dout => LCD_ColSet_reg_ce
);
LCD_Commands: dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8
port map (
addra => addr_x2_net,
addrb => addr_x1_net,
clka => clk_1_sg_x21,
clkb => clk_1_sg_x21,
dina => data_in_x27_net,
dinb => data_in_x22_net,
ena => ce_1_sg_x21,
enb => ce_1_sg_x21,
wea => we_x2_net,
web => we_x1_net,
douta => data_out_x21_net,
doutb => data_out_x8_net
);
LCD_ConfigLocation: entity work.synth_reg_w_init
generic map (
width => 2,
init_index => 2,
init_value => b"00",
latency => 1
)
port map (
ce => LCD_ConfigLocation_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x6_net,
o => data_out_x20_net
);
LCD_ConfigLocation_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x6_net,
dout => LCD_ConfigLocation_reg_ce
);
LCD_DividerSelect: entity work.synth_reg_w_init
generic map (
width => 1,
init_index => 2,
init_value => b"0",
latency => 1
)
port map (
ce => LCD_DividerSelect_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i(0) => data_in_x7_net,
o(0) => data_out_x12_net
);
LCD_DividerSelect_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x7_net,
dout => LCD_DividerSelect_reg_ce
);
LCD_FirstEnd: entity work.synth_reg_w_init
generic map (
width => 9,
init_index => 2,
init_value => b"000000000",
latency => 1
)
port map (
ce => LCD_FirstEnd_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x8_net,
o => data_out_x16_net
);
LCD_FirstEnd_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x8_net,
dout => LCD_FirstEnd_reg_ce
);
LCD_FirstStart: entity work.synth_reg_w_init
generic map (
width => 9,
init_index => 2,
init_value => b"000000000",
latency => 1
)
port map (
ce => LCD_FirstStart_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x9_net,
o => data_out_x15_net
);
LCD_FirstStart_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x9_net,
dout => LCD_FirstStart_reg_ce
);
LCD_LineOffset: entity work.synth_reg_w_init
generic map (
width => 4,
init_index => 2,
init_value => b"0000",
latency => 1
)
port map (
ce => LCD_LineOffset_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x10_net,
o => data_out_x22_net
);
LCD_LineOffset_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x10_net,
dout => LCD_LineOffset_reg_ce
);
LCD_RamWrite: entity work.synth_reg_w_init
generic map (
width => 9,
init_index => 2,
init_value => b"000000000",
latency => 1
)
port map (
ce => LCD_RamWrite_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x11_net,
o => data_out_x25_net
);
LCD_RamWrite_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x11_net,
dout => LCD_RamWrite_reg_ce
);
LCD_Reset: entity work.synth_reg_w_init
generic map (
width => 1,
init_index => 2,
init_value => b"0",
latency => 1
)
port map (
ce => LCD_Reset_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i(0) => data_in_x12_net,
o(0) => data_out_x10_net
);
LCD_ResetLCD: entity work.synth_reg_w_init
generic map (
width => 1,
init_index => 2,
init_value => b"0",
latency => 1
)
port map (
ce => LCD_ResetLCD_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i(0) => data_in_x13_net,
o(0) => data_out_x14_net
);
LCD_ResetLCD_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x13_net,
dout => LCD_ResetLCD_reg_ce
);
LCD_Reset_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x12_net,
dout => LCD_Reset_reg_ce
);
LCD_RowSet: entity work.synth_reg_w_init
generic map (
width => 9,
init_index => 2,
init_value => b"000000000",
latency => 1
)
port map (
ce => LCD_RowSet_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x14_net,
o => data_out_x26_net
);
LCD_RowSet_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x14_net,
dout => LCD_RowSet_reg_ce
);
LCD_SecondEnd: entity work.synth_reg_w_init
generic map (
width => 9,
init_index => 2,
init_value => b"000000000",
latency => 1
)
port map (
ce => LCD_SecondEnd_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x15_net,
o => data_out_x19_net
);
LCD_SecondEnd_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x15_net,
dout => LCD_SecondEnd_reg_ce
);
LCD_SecondStart: entity work.synth_reg_w_init
generic map (
width => 9,
init_index => 2,
init_value => b"000000000",
latency => 1
)
port map (
ce => LCD_SecondStart_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x16_net,
o => data_out_x18_net
);
LCD_SecondStart_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x16_net,
dout => LCD_SecondStart_reg_ce
);
LCD_Send: entity work.synth_reg_w_init
generic map (
width => 1,
init_index => 2,
init_value => b"0",
latency => 1
)
port map (
ce => LCD_Send_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i(0) => data_in_x17_net,
o(0) => data_out_x13_net
);
LCD_Send_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x17_net,
dout => LCD_Send_reg_ce
);
LCD_TotalCmdTransfer: entity work.synth_reg_w_init
generic map (
width => 8,
init_index => 2,
init_value => b"00000000",
latency => 1
)
port map (
ce => LCD_TotalCmdTransfer_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x18_net,
o => data_out_x11_net
);
LCD_TotalCmdTransfer_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x18_net,
dout => LCD_TotalCmdTransfer_reg_ce
);
LEDs_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x19_net,
dout => LEDs_reg_ce
);
LEDs_x0: entity work.synth_reg_w_init
generic map (
width => 8,
init_index => 2,
init_value => b"00000000",
latency => 1
)
port map (
ce => LEDs_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x19_net,
o => data_out_x9_net
);
Trackball: entity work.synth_reg_w_init
generic map (
width => 5,
init_index => 2,
init_value => b"00000",
latency => 1
)
port map (
ce => Trackball_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x23_net,
o => data_out_x5_net
);
Trackball_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x20_net,
dout => Trackball_reg_ce
);
clk_probe: entity work.xlclkprobe
port map (
ce => '1',
clk => clkNet,
clr => '0'
);
default_clock_driver_x0: entity work.default_clock_driver
port map (
sysce => '1',
sysce_clr => '0',
sysclk => clkNet,
ce_1 => ce_1_sg_x21,
clk_1 => clk_1_sg_x21
);
persistentdff_inst: xlpersistentdff
port map (
clk => clkNet,
d => persistentdff_inst_q,
q => persistentdff_inst_q
);
user_io_board_controller_x0: entity work.user_io_board_controller
port map (
buttons_big => buttons_big_net,
buttons_small => buttons_small_net,
ce_1 => ce_1_sg_x21,
clk_1 => clk_1_sg_x21,
data_out => data_out_net,
data_out_x0 => data_out_x0_net,
data_out_x1 => data_out_x1_net,
data_out_x10 => data_out_x10_net,
data_out_x11 => data_out_x11_net,
data_out_x12 => data_out_x12_net,
data_out_x13 => data_out_x13_net,
data_out_x14 => data_out_x14_net,
data_out_x15 => data_out_x15_net,
data_out_x16 => data_out_x16_net,
data_out_x17 => data_out_x17_net,
data_out_x18 => data_out_x18_net,
data_out_x19 => data_out_x19_net,
data_out_x2 => data_out_x2_net,
data_out_x20 => data_out_x20_net,
data_out_x21 => data_out_x21_net,
data_out_x22 => data_out_x22_net,
data_out_x23 => data_out_x23_net,
data_out_x24 => data_out_x24_net,
data_out_x25 => data_out_x25_net,
data_out_x26 => data_out_x26_net,
data_out_x27 => data_out_x27_net,
data_out_x28 => data_out_x28_net,
data_out_x29 => data_out_x29_net,
data_out_x3 => data_out_x3_net,
data_out_x4 => data_out_x4_net,
data_out_x5 => data_out_x5_net,
data_out_x6 => data_out_x6_net,
data_out_x7 => data_out_x7_net,
data_out_x8 => data_out_x8_net,
data_out_x9 => data_out_x9_net,
dip_switch => dip_switch_net,
dout => data_out_x0_net,
dout_x0 => data_out_x1_net,
dout_x1 => data_out_net,
dout_x10 => data_out_x22_net,
dout_x11 => data_out_x25_net,
dout_x12 => data_out_x10_net,
dout_x13 => data_out_x14_net,
dout_x14 => data_out_x26_net,
dout_x15 => data_out_x19_net,
dout_x16 => data_out_x18_net,
dout_x17 => data_out_x13_net,
dout_x18 => data_out_x11_net,
dout_x19 => data_out_x9_net,
dout_x2 => data_out_x17_net,
dout_x3 => data_out_x23_net,
dout_x4 => data_out_x27_net,
dout_x5 => data_out_x24_net,
dout_x6 => data_out_x20_net,
dout_x7 => data_out_x12_net,
dout_x8 => data_out_x16_net,
dout_x9 => data_out_x15_net,
plb_abus => plb_abus_net,
plb_pavalid => plb_pavalid_net,
plb_rnw => plb_rnw_net,
plb_wrdbus => plb_wrdbus_net,
reset => reset_net,
sg_plb_addrpref => sg_plb_addrpref_net,
splb_rst => splb_rst_net,
trackball_ox => trackball_ox_net,
trackball_oxn => trackball_oxn_net,
trackball_oy => trackball_oy_net,
trackball_oyn => trackball_oyn_net,
trackball_sel2 => trackball_sel2_net,
addr => addr_net,
addr_x0 => addr_x0_net,
addr_x1 => addr_x1_net,
addr_x2 => addr_x2_net,
addr_x3 => addr_x3_net,
addr_x4 => addr_x4_net,
buzzer => buzzer_net,
cs => cs_net,
data_in => data_in_net,
data_in_x0 => data_in_x0_net,
data_in_x1 => data_in_x1_net,
data_in_x10 => data_in_x10_net,
data_in_x11 => data_in_x11_net,
data_in_x12 => data_in_x12_net,
data_in_x13 => data_in_x13_net,
data_in_x14 => data_in_x14_net,
data_in_x15 => data_in_x15_net,
data_in_x16 => data_in_x16_net,
data_in_x17 => data_in_x17_net,
data_in_x18 => data_in_x18_net,
data_in_x19 => data_in_x19_net,
data_in_x2 => data_in_x2_net,
data_in_x20 => data_in_x20_net,
data_in_x21 => data_in_x21_net,
data_in_x22 => data_in_x22_net,
data_in_x23 => data_in_x23_net,
data_in_x24 => data_in_x24_net,
data_in_x25 => data_in_x25_net,
data_in_x26 => data_in_x26_net,
data_in_x27 => data_in_x27_net,
data_in_x28 => data_in_x28_net,
data_in_x29 => data_in_x29_net,
data_in_x3 => data_in_x3_net,
data_in_x4 => data_in_x4_net,
data_in_x5 => data_in_x5_net,
data_in_x6 => data_in_x6_net,
data_in_x7 => data_in_x7_net,
data_in_x8 => data_in_x8_net,
data_in_x9 => data_in_x9_net,
en => en_net,
en_x0 => en_x0_net,
en_x1 => en_x1_net,
en_x10 => en_x10_net,
en_x11 => en_x11_net,
en_x12 => en_x12_net,
en_x13 => en_x13_net,
en_x14 => en_x14_net,
en_x15 => en_x15_net,
en_x16 => en_x16_net,
en_x17 => en_x17_net,
en_x18 => en_x18_net,
en_x19 => en_x19_net,
en_x2 => en_x2_net,
en_x20 => en_x20_net,
en_x21 => en_x21_net,
en_x22 => en_x22_net,
en_x23 => en_x23_net,
en_x3 => en_x3_net,
en_x4 => en_x4_net,
en_x5 => en_x5_net,
en_x6 => en_x6_net,
en_x7 => en_x7_net,
en_x8 => en_x8_net,
en_x9 => en_x9_net,
leds => leds_net,
resetlcd => resetlcd_net,
scl => scl_net,
sdi => sdi_net,
sl_addrack => sl_addrack_net,
sl_rdcomp => sl_rdcomp_net,
sl_rddack => sl_rddack_net,
sl_rddbus => sl_rddbus_net,
sl_wait => sl_wait_net,
sl_wrcomp => sl_wrdack_x2,
sl_wrdack => sl_wrdack_x1,
trackball_sel1 => trackball_sel1_net,
trackball_xscn => trackball_xscn_net,
trackball_yscn => trackball_yscn_net,
we => we_net,
we_x0 => we_x0_net,
we_x1 => we_x1_net,
we_x2 => we_x2_net,
we_x3 => we_x3_net,
we_x4 => we_x4_net
);
end structural;
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 07-05-2016
-- Module Name: p4-2.vhd
--------------------------------------------------------------------------------
-- next state logic for a FSM
process (state, a, b, c, d, e)
begin
case state is
when IDLE =>
if a = '0' then
next_state <= INITIAL;
-- preventing from transparent latch creation
else
next_state <= IDLE;
end if;
when INITIAL =>
if a = '1' then
next_state <= ERROR_FLAG;
else
next_state <= SCANNING;
end if;
when SCANNING =>
if b = '1' then
next_state <= LOCKED;
elsif b = '0' then
if c = '0' then
next_state <= TIME_OUT;
else
next_state <= RELEASE;
end if;
-- following statement never happening ...
else
next_state <= CAPTURE;
end if;
when CAPTURE =>
next_state <= ...
when LOCKED =>
next_state <= ...
when TIME_OUT =>
next_state <= ...
when RELEASE =>
next_state <= ...
when ERROR_FLAG =>
next_state <= some_function(a, d, e);
end case;
end process;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: DMA_READ_QUEUE_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity DMA_READ_QUEUE_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(64-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(5-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(64-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(5-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(5-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end DMA_READ_QUEUE_top_wrapper;
architecture xilinx of DMA_READ_QUEUE_top_wrapper is
SIGNAL clk_i : std_logic;
component DMA_READ_QUEUE_top is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : DMA_READ_QUEUE_top
PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
--!
--! @file: exercise5_10.vhd
--! @brief: arithmetic circuit with integer
--! @author: Antonio Gutierrez
--! @date: 2013-10-23
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity mini_alu is
generic (N: integer := 3;);
port (
a, b: in integer range -2**(N-1) to 2**(N-1)-1;
cin: in integer range 0 to 1;
opcode: in integer range 0 to 7;
y: out integer range -2**(N-1) to 2**(N-1)-1;
end entity mini_alu;
--------------------------------------
architecture circuit of mini_alu is
signal a_sig, b_sig: signed(N-1 downto 0);
signal a_unsig, b_unsig: unsigned(N-1 downto 0);
signal y_sig: signed(N-1 downto 0);
signal y_unsig: unsigned(N-1 downto 0);
begin
a_sig <= to_signed(a, a_sig'length);
b_sig <= to_signed(b, b_sig'length);
a_unsig <= to_unsigned(a, a_unsig'length);
b_unsig <= to_unsigned(b, b_unsig'length);
-- signed
with opcode(1 downto 0) select
y_sig <= a_sig + b_sig when 0,
a_sig - b_sig when 1.
b_sig - a_sig when 2,
a_sig + b_sig + cin when others;
-- unsigned
with opcode(1 downto 0) select
y_unsig <= a_unsig + b_unsig when 0,
a_unsig - b_unsig when 1.
b_unsig - a_unsig when 2,
a_unsig + b_unsig + cin when others;
-- mux
with opcode(2) select
y <= y_unsig when 0,
y_sig when others;
end architecture circuit;
--------------------------------------
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.VHDL_lib.all;
entity spi is
port(
clk: in std_logic;
data: in std_logic_vector(31 downto 0);
ready: out std_logic;
valid: in std_logic;
clatch: out std_logic;
cclk: out std_logic;
cdata: out std_logic
);
end spi;
architecture Behavioral of spi is
type states is (idle,deliver); --type of state machine.
signal state : states;
signal payload : std_logic_vector(31 downto 0);
signal index: integer := 0;
signal cclkb: std_logic;
begin
clk_div1: clk_div generic map( div=>2000 ) port map( input=> clk, output=> cclkb);
cclk <= cclkb;
process(cclkb)
begin
if(cclkb'event and cclkb = '0')then
case state is
when idle=>
clatch <= '1';
ready <= '1';
if(valid = '1')then
state <= deliver;
payload <= data;
index <= 0;
end if;
when deliver=>
clatch <= '0';
ready <= '0';
cdata <= payload(31-index);
index <= index + 1;
if( index = 31 )then
state <= idle;
end if;
end case;
end if;
end process;
end Behavioral;
|
-- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
-- Configuration for using the testbench in post-synthesis simulation
-- Start work.post_synthesis_spartan6 in your simulator of choice
configuration post_synthesis_spartan6 of ethernet_mac_tb is
for behavioral
for all : test_instance
use entity work.test_wrapper_spartan6;
end for;
end for;
end configuration; |
-- Projeto MasterMind
-- Diogo Daniel Soares Ferreira e Eduardo Reis Silva
library IEEE;
use IEEE.std_LOGIC_1164.all;
entity Counter9999Tb is
end Counter9999Tb;
-- Teste unitário para contador de 0 a 9999.
architecture Stimulus of Counter9999Tb is
signal s_clk, s_reset, s_enable : std_logic;
signal s_count0, s_count1, s_count2, s_count3 : std_logic_vector(3 downto 0);
begin
counter_str: entity work.Counter9999(Behavioral)
port map(clk => s_clk,
reset => s_reset,
enable => s_enable,
count0 => s_count0,
count1 => s_count1,
count2 => s_count2,
count3 => s_count3);
clk_proc: process
begin
s_clk <= '0';
wait for 1 ns;
s_clk <= '1';
wait for 1 ns;
end process;
stim_proc: process
begin
s_enable <= '1';
s_reset <= '0';
wait for 100 ns;
end process;
end Stimulus; |
package pkg is
generic ( gen: natural );
constant test: natural:=gen;
end package;
package body pkg is
end pkg;
package mygpkg is new work.pkg generic map ( gen => 17 );
|
package pkg is
generic ( gen: natural );
constant test: natural:=gen;
end package;
package body pkg is
end pkg;
package mygpkg is new work.pkg generic map ( gen => 17 );
|
entity implicit1 is
end entity;
architecture test of implicit1 is
signal x : natural;
begin
x <= 1 after 1 ns,
2 after 2 ns,
3 after 3 ns;
process is
begin
assert x = 0;
assert x'delayed = 0;
wait for 1 ns;
assert x = 1;
assert x'delayed = 0;
wait for 0 ns;
assert x'delayed = 1;
assert x'delayed(1 ns) = 0;
wait for 1 ns;
assert x'delayed = 1;
assert x'delayed(1 ns) = 1;
wait;
end process;
end architecture;
|
entity implicit1 is
end entity;
architecture test of implicit1 is
signal x : natural;
begin
x <= 1 after 1 ns,
2 after 2 ns,
3 after 3 ns;
process is
begin
assert x = 0;
assert x'delayed = 0;
wait for 1 ns;
assert x = 1;
assert x'delayed = 0;
wait for 0 ns;
assert x'delayed = 1;
assert x'delayed(1 ns) = 0;
wait for 1 ns;
assert x'delayed = 1;
assert x'delayed(1 ns) = 1;
wait;
end process;
end architecture;
|
entity implicit1 is
end entity;
architecture test of implicit1 is
signal x : natural;
begin
x <= 1 after 1 ns,
2 after 2 ns,
3 after 3 ns;
process is
begin
assert x = 0;
assert x'delayed = 0;
wait for 1 ns;
assert x = 1;
assert x'delayed = 0;
wait for 0 ns;
assert x'delayed = 1;
assert x'delayed(1 ns) = 0;
wait for 1 ns;
assert x'delayed = 1;
assert x'delayed(1 ns) = 1;
wait;
end process;
end architecture;
|
entity implicit1 is
end entity;
architecture test of implicit1 is
signal x : natural;
begin
x <= 1 after 1 ns,
2 after 2 ns,
3 after 3 ns;
process is
begin
assert x = 0;
assert x'delayed = 0;
wait for 1 ns;
assert x = 1;
assert x'delayed = 0;
wait for 0 ns;
assert x'delayed = 1;
assert x'delayed(1 ns) = 0;
wait for 1 ns;
assert x'delayed = 1;
assert x'delayed(1 ns) = 1;
wait;
end process;
end architecture;
|
entity implicit1 is
end entity;
architecture test of implicit1 is
signal x : natural;
begin
x <= 1 after 1 ns,
2 after 2 ns,
3 after 3 ns;
process is
begin
assert x = 0;
assert x'delayed = 0;
wait for 1 ns;
assert x = 1;
assert x'delayed = 0;
wait for 0 ns;
assert x'delayed = 1;
assert x'delayed(1 ns) = 0;
wait for 1 ns;
assert x'delayed = 1;
assert x'delayed(1 ns) = 1;
wait;
end process;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GNWZPLIVXS is
generic ( widthB : natural := 8;
widthA : natural := 16);
port(
a : in std_logic_vector((widthA)-1 downto 0);
aclr : in std_logic;
b : in std_logic_vector((widthB)-1 downto 0);
clock : in std_logic;
output : out std_logic_vector((widthA+widthB)-1 downto 0));
end entity;
architecture rtl of alt_dspbuilder_bus_concat_GNWZPLIVXS is
Begin
output <= a & b;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GNWZPLIVXS is
generic ( widthB : natural := 8;
widthA : natural := 16);
port(
a : in std_logic_vector((widthA)-1 downto 0);
aclr : in std_logic;
b : in std_logic_vector((widthB)-1 downto 0);
clock : in std_logic;
output : out std_logic_vector((widthA+widthB)-1 downto 0));
end entity;
architecture rtl of alt_dspbuilder_bus_concat_GNWZPLIVXS is
Begin
output <= a & b;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GNWZPLIVXS is
generic ( widthB : natural := 8;
widthA : natural := 16);
port(
a : in std_logic_vector((widthA)-1 downto 0);
aclr : in std_logic;
b : in std_logic_vector((widthB)-1 downto 0);
clock : in std_logic;
output : out std_logic_vector((widthA+widthB)-1 downto 0));
end entity;
architecture rtl of alt_dspbuilder_bus_concat_GNWZPLIVXS is
Begin
output <= a & b;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GNWZPLIVXS is
generic ( widthB : natural := 8;
widthA : natural := 16);
port(
a : in std_logic_vector((widthA)-1 downto 0);
aclr : in std_logic;
b : in std_logic_vector((widthB)-1 downto 0);
clock : in std_logic;
output : out std_logic_vector((widthA+widthB)-1 downto 0));
end entity;
architecture rtl of alt_dspbuilder_bus_concat_GNWZPLIVXS is
Begin
output <= a & b;
end architecture; |
library ieee;
use ieee.std_logic_1164.all;
entity init is
port (o : out std_logic);
end init;
architecture behav of init is
begin
o <= '0';
end behav;
library ieee;
use ieee.std_logic_1164.all;
entity forgen02 is
port (a : out std_logic_vector (7 downto 0));
end;
architecture behav of forgen02 is
-- constant c : std_logic_vector (7 downto 0) := x"a1";
begin
gen: for i in a'range generate
inst: entity work.init
port map (o => a(i));
end generate;
end behav;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: umcpads_gen
-- File: umcpads_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: UMC pad wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package umcpads is
-- input pad
component ICMT3V port( A : in std_logic; Z : out std_logic); end component;
-- input pad with pull-up
component ICMT3VPU port( A : in std_logic; Z : out std_logic); end component;
-- input pad with pull-down
component ICMT3VPD port( A : in std_logic; Z : out std_logic); end component;
-- schmitt input pad
component ISTRT3V port( A : in std_logic; Z : out std_logic); end component;
-- output pads
component OCM3V4 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V12 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V24 port( Z : out std_logic; A : in std_logic); end component;
-- tri-state output pads
component OCMTR4 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR12 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR24 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
-- bidirectional pads
component BICM3V4 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V12 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V24 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.ICMT3V;
use umc18.ICMT3VPU;
use umc18.ICMT3VPD;
use umc18.ISTRT3V;
-- pragma translate_on
entity umc_inpad is
generic (level : integer := 0; voltage : integer := 0; filter : integer := 0);
port (pad : in std_logic; o : out std_logic);
end;
architecture rtl of umc_inpad is
component ICMT3V port( A : in std_logic; Z : out std_logic); end component;
component ICMT3VPU port( A : in std_logic; Z : out std_logic); end component;
component ICMT3VPD port( A : in std_logic; Z : out std_logic); end component;
component ISTRT3V port( A : in std_logic; Z : out std_logic); end component;
begin
norm : if filter = 0 generate
ip : ICMT3V port map (a => pad, z => o);
end generate;
pu : if filter = pullup generate
ip : ICMT3VPU port map (a => pad, z => o);
end generate;
pd : if filter = pulldown generate
ip : ICMT3VPD port map (a => pad, z => o);
end generate;
sch : if filter = schmitt generate
ip : ISTRT3V port map (a => pad, z => o);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.BICM3V4;
use umc18.BICM3V12;
use umc18.BICM3V24;
-- pragma translate_on
entity umc_iopad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end ;
architecture rtl of umc_iopad is
component BICM3V4 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V12 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V24 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
begin
f4 : if (strength <= 4) generate
op : BICM3V4 port map (a => i, en => en, io => pad, z => o);
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : BICM3V12 port map (a => i, en => en, io => pad, z => o);
end generate;
f24 : if (strength > 16) generate
op : BICM3V24 port map (a => i, en => en, io => pad, z => o);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.OCM3V4;
use umc18.OCM3V12;
use umc18.OCM3V24;
-- pragma translate_on
entity umc_outpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end ;
architecture rtl of umc_outpad is
component OCM3V4 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V12 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V24 port( Z : out std_logic; A : in std_logic); end component;
begin
f4 : if (strength <= 4) generate
op : OCM3V4 port map (a => i, z => pad);
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : OCM3V12 port map (a => i, z => pad);
end generate;
f24 : if (strength > 12) generate
op : OCM3V24 port map (a => i, z => pad);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.OCMTR4;
use umc18.OCMTR12;
use umc18.OCMTR24;
-- pragma translate_on
entity umc_toutpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end ;
architecture rtl of umc_toutpad is
component OCMTR4 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR12 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR24 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
begin
f4 : if (strength <= 4) generate
op : OCMTR4 port map (a => i, en => en, z => pad);
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : OCMTR12 port map (a => i, en => en, z => pad);
end generate;
f24 : if (strength > 12) generate
op : OCMTR24 port map (a => i, en => en, z => pad);
end generate;
end;
library umc18;
-- pragma translate_off
use umc18.LVDS_Driver;
use umc18.LVDS_Receiver;
use umc18.LVDS_Biasmodule;
-- pragma translate_on
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity umc_lvds_combo is
generic (voltage : integer := 0; width : integer := 1);
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
odval, osval, en : in std_logic_vector(0 to width-1);
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
idval, isval : out std_logic_vector(0 to width-1);
lvdsref : in std_logic);
end ;
architecture rtl of umc_lvds_combo is
component LVDS_Driver port ( A, Vref, HI : in std_logic; Z, ZN : out std_logic); end component;
component LVDS_Receiver port ( A, AN : in std_logic; Z : out std_logic); end component;
component LVDS_Biasmodule port ( RefR : in std_logic; Vref, HI : out std_logic); end component;
signal vref, hi : std_logic;
begin
lvds_bias: LVDS_Biasmodule port map (lvdsref, vref, hi);
swloop : for i in 0 to width-1 generate
spw_rxd_pad : LVDS_Receiver port map (idpadp(i), idpadn(i), idval(i));
spw_rxs_pad : LVDS_Receiver port map (ispadp(i), ispadn(i), isval(i));
spw_txd_pad : LVDS_Driver port map (odval(i), vref, hi, odpadp(i), odpadn(i));
spw_txs_pad : LVDS_Driver port map (osval(i), vref, hi, ospadp(i), ospadn(i));
end generate;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2cmst_gen
-- File: i2cmst_gen.vhd
-- Author: Jan Andersson - Aeroflex Gaisler
-- Contact: [email protected]
-- Description: Generic I2CMST, see i2cmst.vhd
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.i2c.all;
entity i2cmst_gen is
generic (
oepol : integer range 0 to 1 := 0; -- output enable polarity
filter : integer range 2 to 512 := 2; -- filter bit size
dynfilt : integer range 0 to 1 := 0);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
prdata : out std_logic_vector(31 downto 0);
irq : out std_logic;
-- I2C signals
--i2ci : in i2c_in_type;
i2ci_scl : in std_ulogic;
i2ci_sda : in std_ulogic;
--i2co : out i2c_out_type
i2co_scl : out std_ulogic;
i2co_scloen : out std_ulogic;
i2co_sda : out std_ulogic;
i2co_sdaoen : out std_ulogic;
i2co_enable : out std_ulogic
);
end entity i2cmst_gen;
architecture rtl of i2cmst_gen is
-- APB signals
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_type;
-- I2C signals
signal i2ci : i2c_in_type;
signal i2co : i2c_out_type;
begin
apbi.psel(0) <= psel;
apbi.psel(1 to NAPBSLV-1) <= (others => '0');
apbi.penable <= penable;
apbi.paddr <= paddr;
apbi.pwrite <= pwrite;
apbi.pwdata <= pwdata;
apbi.pirq <= (others => '0');
apbi.testen <= '0';
apbi.testrst <= '0';
apbi.scanen <= '0';
apbi.testoen <= '0';
prdata <= apbo.prdata;
irq <= apbo.pirq(0);
i2ci.scl <= i2ci_scl;
i2ci.sda <= i2ci_sda;
i2co_scl <= i2co.scl;
i2co_scloen <= i2co.scloen;
i2co_sda <= i2co.sda;
i2co_sdaoen <= i2co.sdaoen;
i2co_enable <= i2co.enable;
i2c0 : i2cmst
generic map (pindex => 0, paddr => 0, pmask => 0, pirq => 0,
oepol => oepol, filter => filter, dynfilt => dynfilt)
port map (rstn, clk, apbi, apbo, i2ci, i2co);
end architecture rtl;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rawUVCfifo_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.rawUVCfifo_pkg.ALL;
ENTITY rawUVCfifo_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF rawUVCfifo_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:rawUVCfifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rawUVCfifo_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.rawUVCfifo_pkg.ALL;
ENTITY rawUVCfifo_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF rawUVCfifo_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:rawUVCfifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rawUVCfifo_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.rawUVCfifo_pkg.ALL;
ENTITY rawUVCfifo_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF rawUVCfifo_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:rawUVCfifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
|
----------------------------------------------------------------------------------
-- Company: N/A
-- Engineer: WTMW
-- Create Date: 22:27:15 09/26/2014
-- Design Name:
-- Module Name: SPI_hardware_interface_test.vhd
-- Project Name: project_nrf
-- Target Devices: Nexys 4
-- Tool versions: ISE WEBPACK 64-Bit
-- Description: Testing MOSI and MISO
-- for at edge case of 32byte burst read and write
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
ENTITY SPI_hw_interface_test IS
END SPI_hw_interface_test;
ARCHITECTURE behavior OF SPI_hw_interface_test IS
COMPONENT SPI_hw_interface
PORT(
clk : IN std_logic;
masterReset : IN std_logic;
en : IN std_logic;
data_byte_in : IN std_logic_vector(7 downto 0);
data_byte_out : OUT std_logic_vector(7 downto 0);
wen : IN std_logic;
ren : IN std_logic;
M_active : OUT std_logic;
M_finished : out std_logic;
regLocation : IN std_logic_vector(7 downto 0);
dataAmount : IN std_logic_vector(5 downto 0);
CS : OUT std_logic;
SCLK : OUT std_logic;
MOSI : OUT std_logic;
MISO : IN std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal masterReset : std_logic := '0';
signal en : std_logic := '0';
signal data_byte_in : std_logic_vector(7 downto 0) := (others => '0');
signal wen : std_logic := '0';
signal ren : std_logic := '0';
signal regLocation : std_logic_vector(7 downto 0) := (others => '0');
signal dataAmount : std_logic_vector(5 downto 0) := (others => '0');
signal MISO : std_logic := '0';
--Outputs
signal data_byte_out : std_logic_vector(7 downto 0) := (others => '0');
signal CS : std_logic;
signal SCLK : std_logic;
signal MOSI : std_logic;
signal M_finished : std_logic;
signal M_active : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
--Procedure should mimic NRF, will need to clock out
procedure SPI_MISO (
byte_in : in std_logic_vector(7 downto 0) ;
signal MISO : out std_logic
) is
begin
for i in 7 downto 0 loop
MISO <= byte_in(i);
wait until falling_edge(SCLK);
end loop;
end SPI_MISO;
BEGIN
uut: SPI_hw_interface PORT MAP (
clk => clk,
masterReset => masterReset,
en => en,
data_byte_in => data_byte_in,
data_byte_out => data_byte_out,
wen => wen,
ren => ren,
M_active => M_active,
M_finished => M_finished,
regLocation => regLocation,
dataAmount => dataAmount,
CS => CS,
SCLK => SCLK,
MOSI => MOSI,
MISO => MISO
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait until rising_edge(clk);
masterReset <= '1';
wait for clk_period*5;
wait until rising_edge(clk);
masterReset <= '0';
-- PART ONE Retest Sending, 3 Bytes
wait until rising_edge(clk);
en <= '1';
data_byte_in <= "11001001";
wait until rising_edge(clk);
data_byte_in <= "00111001";
wait until rising_edge(clk);
data_byte_in <= "10011011";
wait until rising_edge(clk);
data_byte_in <= (others => '0'); -- Check data is in
en <= '0';
regLocation <= "10001011";
dataAmount <= "000011"; -- 3 bytes to send
wen <= '1'; -- Pulse WEN
wait until rising_edge(clk);
wen <= '0';
wait for clk_period*1000;
wait until M_finished = '1';
wait for clk_period*10;
-- PART TWO Retest Sending, 32 Bytes
wait for clk_period*5;
masterReset <= '0';
wait until rising_edge(clk);
en <= '1';
data_byte_in <= "10000001"; -- 0
wait until rising_edge(clk);
data_byte_in <= "10000011"; -- 1
wait until rising_edge(clk);
data_byte_in <= "10000101"; -- 2
wait until rising_edge(clk);
data_byte_in <= "10000111"; -- 3
wait until rising_edge(clk);
data_byte_in <= "10001001"; -- 4
wait until rising_edge(clk);
data_byte_in <= "10001011"; -- 5
wait until rising_edge(clk);
data_byte_in <= "10001101"; -- 6
wait until rising_edge(clk);
data_byte_in <= "10001111"; -- 7
wait until rising_edge(clk);
data_byte_in <= "10010001"; -- 8
wait until rising_edge(clk);
data_byte_in <= "10010011"; -- 9
wait until rising_edge(clk);
data_byte_in <= "10010101"; -- 10
wait until rising_edge(clk);
data_byte_in <= "10010111"; -- 11
wait until rising_edge(clk);
data_byte_in <= "10011001"; -- 12
wait until rising_edge(clk);
data_byte_in <= "10011011"; -- 13
wait until rising_edge(clk);
data_byte_in <= "10011101"; -- 14
wait until rising_edge(clk);
data_byte_in <= "10011111"; -- 15
wait until rising_edge(clk);
data_byte_in <= "10100001"; -- 16
wait until rising_edge(clk);
data_byte_in <= "10100011"; -- 17
wait until rising_edge(clk);
data_byte_in <= "10100101"; -- 18
wait until rising_edge(clk);
data_byte_in <= "10100111"; -- 19
wait until rising_edge(clk);
data_byte_in <= "10101001"; -- 20
wait until rising_edge(clk);
data_byte_in <= "10101011"; -- 21
wait until rising_edge(clk);
data_byte_in <= "10101101"; -- 22
wait until rising_edge(clk);
data_byte_in <= "10101111"; -- 23
wait until rising_edge(clk);
data_byte_in <= "10110001"; -- 24
wait until rising_edge(clk);
data_byte_in <= "10110011"; -- 25
wait until rising_edge(clk);
data_byte_in <= "10110101"; -- 26
wait until rising_edge(clk);
data_byte_in <= "10110111"; -- 27
wait until rising_edge(clk);
data_byte_in <= "10111001"; -- 28
wait until rising_edge(clk);
data_byte_in <= "10111011"; -- 29
wait until rising_edge(clk);
data_byte_in <= "10111101"; -- 30
wait until rising_edge(clk);
data_byte_in <= "10111111"; -- 31
wait until rising_edge(clk);
data_byte_in <= (others => '0'); -- Check data is in
en <= '0'; -- Data is loaded in properly
regLocation <= "10101011";
dataAmount <= "100000"; -- 32 bytes to send
wen <= '1'; -- Pulse WEN
wait until rising_edge(clk);
wen <= '0';
-- PART 3 Test Reading, 4 Bytes
wait for clk_period*1000;
wait until M_finished = '1';
wait for clk_period*10;
wait until rising_edge(clk);
regLocation <= "11101011";
dataAmount <= "000100"; -- 4 bytes to read
ren <= '1';
wait until rising_edge(clk);
ren <= '0';
SPI_MISO("11111110", MISO); -- Dummy Shift
SPI_MISO("10110011", MISO); -- Byte 1
SPI_MISO("10011000", MISO); -- Byte 2
SPI_MISO("10101101", MISO); -- Byte 3
SPI_MISO("11101111", MISO); -- Byte 3
-- CLK out the data
wait until M_finished = '1';
wait for clk_period*10;
wait until rising_edge(clk); -- Clocking out is delayed 1 clk cycle, be careful
en <= '1';
wait for clk_period*6;
wait until rising_edge(clk);
en <= '0';
-- Tested OK , 4 bytes now 32 byte test
-- PART 4 Test Reading, 32 Bytes
wait for clk_period*10;
wait until rising_edge(clk);
regLocation <= "10110111";
dataAmount <= "100000"; -- 4 bytes to read
ren <= '1';
wait until rising_edge(clk);
ren <= '0';
SPI_MISO("11111111", MISO); -- Dummy Shift
SPI_MISO("10000001", MISO); -- Byte 0
SPI_MISO("10000011", MISO); -- Byte 1
SPI_MISO("10000101", MISO); -- Byte 2
SPI_MISO("10000111", MISO); -- Byte 3
SPI_MISO("10001001", MISO); -- Byte 4
SPI_MISO("10001011", MISO); -- Byte 5
SPI_MISO("10001101", MISO); -- Byte 6
SPI_MISO("10001111", MISO); -- Byte 7
SPI_MISO("10010001", MISO); -- Byte 8
SPI_MISO("10010011", MISO); -- Byte 9
SPI_MISO("10010101", MISO); -- Byte 10
SPI_MISO("10010111", MISO); -- Byte 11
SPI_MISO("10011001", MISO); -- Byte 12
SPI_MISO("10011011", MISO); -- Byte 13
SPI_MISO("10011101", MISO); -- Byte 14
SPI_MISO("10011111", MISO); -- Byte 15
SPI_MISO("10100001", MISO); -- Byte 16
SPI_MISO("10100011", MISO); -- Byte 17
SPI_MISO("10100101", MISO); -- Byte 18
SPI_MISO("10100111", MISO); -- Byte 19
SPI_MISO("10101001", MISO); -- Byte 20
SPI_MISO("10101011", MISO); -- Byte 21
SPI_MISO("10101101", MISO); -- Byte 22
SPI_MISO("10101111", MISO); -- Byte 23
SPI_MISO("10110001", MISO); -- Byte 24
SPI_MISO("10110011", MISO); -- Byte 25
SPI_MISO("10110101", MISO); -- Byte 26
SPI_MISO("10110111", MISO); -- Byte 27
SPI_MISO("10111001", MISO); -- Byte 28
SPI_MISO("10111011", MISO); -- Byte 29
SPI_MISO("10111101", MISO); -- Byte 30
SPI_MISO("10111111", MISO); -- Byte 31
-- CLK out the data
wait until M_finished = '1';
wait for clk_period*10;
wait until rising_edge(clk); -- Clocking out is delayed 1 clk cycle, be careful
en <= '1';
wait for clk_period*32; -- Last Clocked byte is also remains for 1 clk cycle
wait until rising_edge(clk);
en <= '0';
-- TEST OK
wait;
end process;
END;
|
-- NEED RESULT: ARCH00016: Associated composite generics with globally static subtype passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00016
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.1.1 (2)
-- 1.1.1.1 (6)
--
-- DESIGN UNIT ORDERING:
--
-- GENERIC_STANDARD_TYPES(ARCH00016)
-- ENT00016_Test_Bench(ARCH00016_Test_Bench)
--
-- REVISION HISTORY:
--
-- 26-JUN-1987 - initial revision
-- 28-NOV-1989 - (ESL) changed the associated values in the generic map
-- to be same as those used in correct test
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00016 of GENERIC_STANDARD_TYPES is
begin
L1 :
block
generic (
i_bit_vector_1, i_bit_vector_2 : bit_vector
:= c_st_bit_vector_1 ;
i_string_1, i_string_2 : string
:= c_st_string_1 ;
i_t_rec1_1, i_t_rec1_2 : t_rec1
:= c_st_rec1_1 ;
i_st_rec1_1, i_st_rec1_2 : st_rec1
:= c_st_rec1_1 ;
i_t_rec2_1, i_t_rec2_2 : t_rec2
:= c_st_rec2_1 ;
i_st_rec2_1, i_st_rec2_2 : st_rec2
:= c_st_rec2_1 ;
i_t_rec3_1, i_t_rec3_2 : t_rec3
:= c_st_rec3_1 ;
i_st_rec3_1, i_st_rec3_2 : st_rec3
:= c_st_rec3_1 ;
i_t_arr1_1, i_t_arr1_2 : t_arr1
:= c_st_arr1_1 ;
i_st_arr1_1, i_st_arr1_2 : st_arr1
:= c_st_arr1_1 ;
i_t_arr2_1, i_t_arr2_2 : t_arr2
:= c_st_arr2_1 ;
i_st_arr2_1, i_st_arr2_2 : st_arr2
:= c_st_arr2_1 ;
i_t_arr3_1, i_t_arr3_2 : t_arr3
:= c_st_arr3_1 ;
i_st_arr3_1, i_st_arr3_2 : st_arr3
:= c_st_arr3_1
) ;
generic map (
c_st_bit_vector_2, c_st_bit_vector_2,
c_st_string_2, c_st_string_2,
c_st_rec1_2, c_st_rec1_2,
c_st_rec1_2, c_st_rec1_2,
c_st_rec2_2, c_st_rec2_2,
c_st_rec2_2, c_st_rec2_2,
c_st_rec3_2, c_st_rec3_2,
c_st_rec3_2, c_st_rec3_2,
c_st_arr1_2, c_st_arr1_2,
c_st_arr1_2, c_st_arr1_2,
c_st_arr2_2, c_st_arr2_2,
c_st_arr2_2, c_st_arr2_2,
c_st_arr3_2, c_st_arr3_2,
c_st_arr3_2, c_st_arr3_2
) ;
begin
process
variable correct : boolean := true ;
begin
correct := correct and i_bit_vector_1 = c_st_bit_vector_2
and i_bit_vector_2 = c_st_bit_vector_2 ;
correct := correct and i_string_1 = c_st_string_2
and i_string_2 = c_st_string_2 ;
correct := correct and i_t_rec1_1 = c_st_rec1_2
and i_t_rec1_2 = c_st_rec1_2 ;
correct := correct and i_st_rec1_1 = c_st_rec1_2
and i_st_rec1_2 = c_st_rec1_2 ;
correct := correct and i_t_rec2_1 = c_st_rec2_2
and i_t_rec2_2 = c_st_rec2_2 ;
correct := correct and i_st_rec2_1 = c_st_rec2_2
and i_st_rec2_2 = c_st_rec2_2 ;
correct := correct and i_t_rec3_1 = c_st_rec3_2
and i_t_rec3_2 = c_st_rec3_2 ;
correct := correct and i_st_rec3_1 = c_st_rec3_2
and i_st_rec3_2 = c_st_rec3_2 ;
correct := correct and i_t_arr1_1 = c_st_arr1_2
and i_t_arr1_2 = c_st_arr1_2 ;
correct := correct and i_st_arr1_1 = c_st_arr1_2
and i_st_arr1_2 = c_st_arr1_2 ;
correct := correct and i_t_arr2_1 = c_st_arr2_2
and i_t_arr2_2 = c_st_arr2_2 ;
correct := correct and i_st_arr2_1 = c_st_arr2_2
and i_st_arr2_2 = c_st_arr2_2 ;
correct := correct and i_t_arr3_1 = c_st_arr3_2
and i_t_arr3_2 = c_st_arr3_2 ;
correct := correct and i_st_arr3_1 = c_st_arr3_2
and i_st_arr3_2 = c_st_arr3_2 ;
test_report ( "ARCH00016" ,
"Associated composite generics with globally static subtype" ,
correct) ;
wait ;
end process ;
end block L1 ;
end ARCH00016 ;
--
entity ENT00016_Test_Bench is
end ENT00016_Test_Bench ;
architecture ARCH00016_Test_Bench of ENT00016_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00016 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00016_Test_Bench ;
--
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_eba_e
--
-- Generated
-- by: wig
-- on: Mon Apr 10 13:27:22 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_eba_e-rtl-conf-c.vhd,v 1.1 2006/04/10 15:42:08 wig Exp $
-- $Date: 2006/04/10 15:42:08 $
-- $Log: inst_eba_e-rtl-conf-c.vhd,v $
-- Revision 1.1 2006/04/10 15:42:08 wig
-- Updated testcase (__TOP__)
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_eba_e_rtl_conf / inst_eba_e
--
configuration inst_eba_e_rtl_conf of inst_eba_e is
for rtl
-- Generated Configuration
end for;
end inst_eba_e_rtl_conf;
--
-- End of Generated Configuration inst_eba_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sign_ext_unit is
Port( entrada : in STD_LOGIC_VECTOR (12 downto 0);
salida : out STD_LOGIC_VECTOR (31 downto 0)
);
end sign_ext_unit;
architecture ArqSignExt of sign_ext_unit is
begin
process(entrada)
begin
if (entrada(12) = '1') then
salida <= "1111111111111111111" & entrada;
else
salida <= "0000000000000000000" & entrada;
end if;
end process;
end ArqSignExt;
|
------------------------------------------------------------------------------
---- ----
---- ZPU Small ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is the small size version. ----
---- It doesn't support external memories, needs a dual ported memory. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: ZPUSmallCore(Behave) (Entity and architecture) ----
---- File name: zpu_small.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- zpu.zpupkg ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.all;
library zpu;
use zpu.zpupkg.all;
entity ZPUSmallCore is
generic(
WORD_SIZE : integer:=32; -- Data width 16/32
ADDR_W : integer:=16; -- Total address space width (incl. I/O)
MEM_W : integer:=15; -- Memory (prog+data+stack) width
D_CARE_VAL : std_logic:='X'); -- Value used to fill the unsused bits
port(
clk_i : in std_logic; -- System Clock
reset_i : in std_logic; -- Synchronous Reset
interrupt_i : in std_logic; -- Interrupt
break_o : out std_logic; -- Breakpoint opcode executed
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- BRAM (text, data, bss and stack)
a_we_o : out std_logic; -- BRAM A port Write Enable
a_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM A Address
a_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM A port
a_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM A port
b_we_o : out std_logic; -- BRAM B port Write Enable
b_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM B Address
b_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM B port
b_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM B port
-- Memory mapped I/O
mem_busy_i : in std_logic;
data_i : in unsigned(WORD_SIZE-1 downto 0);
data_o : out unsigned(WORD_SIZE-1 downto 0);
addr_o : out unsigned(ADDR_W-1 downto 0);
write_en_o : out std_logic;
read_en_o : out std_logic);
end entity ZPUSmallCore;
architecture Behave of ZPUSmallCore is
constant MAX_ADDR_BIT : integer:=ADDR_W-2;
constant BYTE_BITS : integer:=WORD_SIZE/16; -- # of bits in a word that addresses bytes
-- Stack Pointer initial value: BRAM size-8
constant SP_START_1 : unsigned(ADDR_W-1 downto 0):=to_unsigned((2**MEM_W)-8,ADDR_W);
constant SP_START : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=
SP_START_1(MAX_ADDR_BIT downto BYTE_BITS);
constant IO_BIT : integer:=ADDR_W-1; -- Address bit to determine this is an I/O
-- Program counter
signal pc_r : unsigned(MAX_ADDR_BIT downto 0):=(others => '0');
-- Stack pointer
signal sp_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=SP_START;
signal idim_r : std_logic:='0';
-- BRAM (text, data, bss and stack)
-- a_r is a register for the top of the stack [SP]
-- Note: as this is a stack CPU this is a very important register.
signal a_we_r : std_logic:='0';
signal a_addr_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=(others => '0');
signal a_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
-- b_r is a register for the next value in the stack [SP+1]
-- We also use the B port to fetch instructions.
signal b_we_r : std_logic:='0';
signal b_addr_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=(others => '0');
signal b_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
-- State machine.
type state_t is (st_fetch, st_write_io_done, st_execute, st_add, st_or,
st_and, st_store, st_read_io, st_write_io, st_fetch_next,
st_add_sp, st_decode, st_resync);
signal state : state_t:=st_resync;
-- Decoded Opcode
type decode_t is (dec_nop, dec_im, dec_load_sp, dec_store_sp, dec_add_sp,
dec_emulate, dec_break, dec_push_sp, dec_pop_pc, dec_add,
dec_or, dec_and, dec_load, dec_not, dec_flip, dec_store,
dec_pop_sp, dec_interrupt);
signal d_opcode_r : decode_t;
signal d_opcode : decode_t;
signal opcode : unsigned(OPCODE_W-1 downto 0); -- Decoded
signal opcode_r : unsigned(OPCODE_W-1 downto 0); -- Registered
-- IRQ flag
signal in_irq_r : std_logic:='0';
-- I/O space address
signal addr_r : unsigned(ADDR_W-1 downto 0):=(others => '0');
begin
-- Dual ported memory interface
a_we_o <= a_we_r;
a_addr_o <= a_addr_r(MEM_W-1 downto BYTE_BITS);
a_o <= a_r;
b_we_o <= b_we_r;
b_addr_o <= b_addr_r(MEM_W-1 downto BYTE_BITS);
b_o <= b_r;
-------------------------
-- Instruction Decoder --
-------------------------
-- Note: We use Port B memory to fetch the opcodes.
decode_control:
process(b_i, pc_r)
variable topcode : unsigned(OPCODE_W-1 downto 0);
begin
-- Select the addressed byte inside the fetched word
case (to_integer(pc_r(BYTE_BITS-1 downto 0))) is
when 0 =>
topcode := to_01( b_i(31 downto 24));
when 1 =>
topcode := to_01( b_i(23 downto 16));
when 2 =>
topcode := to_01( b_i(15 downto 8));
when others => -- 3
topcode := to_01( b_i(7 downto 0));
end case;
opcode <= topcode;
if (topcode(7 downto 7)=OPCODE_IM) then
d_opcode <= dec_im;
elsif (topcode(7 downto 5)=OPCODE_STORESP) then
d_opcode <= dec_store_sp;
elsif (topcode(7 downto 5)=OPCODE_LOADSP) then
d_opcode <= dec_load_sp;
elsif (topcode(7 downto 5)=OPCODE_EMULATE) then
d_opcode <= dec_emulate;
elsif (topcode(7 downto 4)=OPCODE_ADDSP) then
d_opcode <= dec_add_sp;
else -- OPCODE_SHORT
case topcode(3 downto 0) is
when OPCODE_BREAK =>
d_opcode <= dec_break;
when OPCODE_PUSHSP =>
d_opcode <= dec_push_sp;
when OPCODE_POPPC =>
d_opcode <= dec_pop_pc;
when OPCODE_ADD =>
d_opcode <= dec_add;
when OPCODE_OR =>
d_opcode <= dec_or;
when OPCODE_AND =>
d_opcode <= dec_and;
when OPCODE_LOAD =>
d_opcode <= dec_load;
when OPCODE_NOT =>
d_opcode <= dec_not;
when OPCODE_FLIP =>
d_opcode <= dec_flip;
when OPCODE_STORE =>
d_opcode <= dec_store;
when OPCODE_POPSP =>
d_opcode <= dec_pop_sp;
when others => -- OPCODE_NOP and others
d_opcode <= dec_nop;
end case;
end if;
end process decode_control;
data_o <= b_i;
opcode_control:
process (clk_i)
variable sp_offset : unsigned(4 downto 0);
begin
if rising_edge(clk_i) then
break_o <= '0';
write_en_o <= '0';
read_en_o <= '0';
dbg_o.b_inst <= '0';
if reset_i='1' then
state <= st_resync;
sp_r <= SP_START;
pc_r <= (others => '0');
idim_r <= '0';
a_addr_r <= (others => '0');
b_addr_r <= (others => '0');
a_we_r <= '0';
b_we_r <= '0';
a_r <= (others => '0');
b_r <= (others => '0');
in_irq_r <= '0';
addr_r <= (others => '0');
else -- reset_i/='1'
a_we_r <= '0';
b_we_r <= '0';
-- This saves LUTs, by explicitly declaring that the
-- a_o can be left at whatever value if a_we_r is
-- not set.
a_r <= (others => D_CARE_VAL);
b_r <= (others => D_CARE_VAL);
sp_offset:=(others => D_CARE_VAL);
a_addr_r <= (others => D_CARE_VAL);
b_addr_r <= (others => D_CARE_VAL);
addr_r <= a_i(ADDR_W-1 downto 0);
d_opcode_r <= d_opcode;
opcode_r <= opcode;
if interrupt_i='0' then
in_irq_r <= '0'; -- no longer in an interrupt
end if;
case state is
when st_execute =>
state <= st_fetch;
-- At this point:
-- b_i contains opcode word
-- a_i contains top of stack
pc_r <= pc_r+1;
-- Debug info (Trace)
dbg_o.b_inst <= '1';
dbg_o.pc <= (others => '0');
dbg_o.pc(MAX_ADDR_BIT downto 0) <= pc_r;
dbg_o.opcode <= opcode_r;
dbg_o.sp <= (others => '0');
dbg_o.sp(MAX_ADDR_BIT downto BYTE_BITS) <= sp_r;
dbg_o.stk_a <= a_i;
dbg_o.stk_b <= b_i;
-- During the next cycle we'll be reading the next opcode
sp_offset(4):=not opcode_r(4);
sp_offset(3 downto 0):=opcode_r(3 downto 0);
idim_r <= '0';
--------------------
-- Execution Unit --
--------------------
case d_opcode_r is
when dec_interrupt =>
-- Not a real instruction, but an interrupt
-- Push(PC); PC=32
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_we_r <= '1';
a_r <= (others => D_CARE_VAL);
a_r(MAX_ADDR_BIT downto 0) <= pc_r;
-- Jump to ISR
pc_r <= to_unsigned(32,MAX_ADDR_BIT+1); -- interrupt address
--report "ZPU jumped to interrupt!" severity note;
when dec_im =>
idim_r <= '1';
a_we_r <= '1';
if idim_r='0' then
-- First IM
-- Push the 7 bits (extending the sign)
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_r <= unsigned(resize(signed(opcode_r(6 downto 0)),WORD_SIZE));
else
-- Next IMs, shift the word and put the new value in the lower
-- bits
a_addr_r <= sp_r;
a_r(WORD_SIZE-1 downto 7) <= a_i(WORD_SIZE-8 downto 0);
a_r(6 downto 0) <= opcode_r(6 downto 0);
end if;
when dec_store_sp =>
-- [SP+Offset]=Pop()
b_we_r <= '1';
b_addr_r <= sp_r+sp_offset;
b_r <= a_i;
sp_r <= sp_r+1;
state <= st_resync;
when dec_load_sp =>
-- Push([SP+Offset])
sp_r <= sp_r-1;
a_addr_r <= sp_r+sp_offset;
when dec_emulate =>
-- Push(PC+1), PC=Opcode[4:0]*32
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => D_CARE_VAL);
a_r(MAX_ADDR_BIT downto 0) <= pc_r+1;
-- Jump to NUM*32
-- The emulate address is:
-- 98 7654 3210
-- 0000 00aa aaa0 0000
pc_r <= (others => '0');
pc_r(9 downto 5) <= opcode_r(4 downto 0);
when dec_add_sp =>
-- Push(Pop()+[SP+Offset])
a_addr_r <= sp_r;
b_addr_r <= sp_r+sp_offset;
state <= st_add_sp;
when dec_break =>
--report "Break instruction encountered" severity failure;
break_o <= '1';
when dec_push_sp =>
-- Push(SP)
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => D_CARE_VAL);
a_r(MAX_ADDR_BIT downto BYTE_BITS) <= sp_r;
when dec_pop_pc =>
-- Pop(PC)
pc_r <= a_i(MAX_ADDR_BIT downto 0);
sp_r <= sp_r+1;
state <= st_resync;
when dec_add =>
-- Push(Pop()+Pop())
sp_r <= sp_r+1;
state <= st_add;
when dec_or =>
-- Push(Pop() or Pop())
sp_r <= sp_r+1;
state <= st_or;
when dec_and =>
-- Push(Pop() and Pop())
sp_r <= sp_r+1;
state <= st_and;
when dec_load =>
-- Push([Pop()])
if a_i(IO_BIT)='1' then
addr_r <= a_i(ADDR_W-1 downto 0);
read_en_o <= '1';
state <= st_read_io;
else
a_addr_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS);
end if;
when dec_not =>
-- Push(not(Pop()))
a_addr_r <= sp_r(MAX_ADDR_BIT downto BYTE_BITS);
a_we_r <= '1';
a_r <= not a_i;
when dec_flip =>
-- Push(flip(Pop()))
a_addr_r <= sp_r(MAX_ADDR_BIT downto BYTE_BITS);
a_we_r <= '1';
for i in 0 to WORD_SIZE-1 loop
a_r(i) <= a_i(WORD_SIZE-1-i);
end loop;
when dec_store =>
-- a=Pop(), b=Pop(), [a]=b
b_addr_r <= sp_r+1;
sp_r <= sp_r+1;
if a_i(IO_BIT)='1' then
state <= st_write_io;
else
state <= st_store;
end if;
when dec_pop_sp =>
-- SP=Pop()
sp_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS);
state <= st_resync;
when dec_nop =>
-- Default, keep addressing to of the stack (A)
a_addr_r <= sp_r;
when others =>
null;
end case;
when st_read_io =>
a_addr_r <= sp_r;
-- Wait until memory I/O isn't busy
if mem_busy_i='0' then
state <= st_fetch;
a_we_r <= '1';
a_r <= data_i;
end if;
when st_write_io =>
-- [A]=B
sp_r <= sp_r+1;
write_en_o <= '1';
addr_r <= a_i(ADDR_W-1 downto 0);
state <= st_write_io_done;
when st_write_io_done =>
-- Wait until memory I/O isn't busy
if mem_busy_i='0' then
state <= st_resync;
end if;
when st_fetch =>
-- We need to resync. During the *next* cycle
-- we'll fetch the opcode @ pc and thus it will
-- be available for st_execute the cycle after
-- next
b_addr_r <= pc_r(MAX_ADDR_BIT downto BYTE_BITS);
state <= st_fetch_next;
when st_fetch_next =>
-- At this point a_i contains the value that is either
-- from the top of stack or should be copied to the top of the stack
a_we_r <= '1';
a_r <= a_i;
a_addr_r <= sp_r;
b_addr_r <= sp_r+1;
state <= st_decode;
when st_decode =>
if interrupt_i='1' and in_irq_r='0' and idim_r='0' then
-- We got an interrupt, execute interrupt instead of next instruction
in_irq_r <= '1';
d_opcode_r <= dec_interrupt;
end if;
-- during the st_execute cycle we'll be fetching SP+1
a_addr_r <= sp_r;
b_addr_r <= sp_r+1;
state <= st_execute;
when st_store =>
sp_r <= sp_r+1;
a_we_r <= '1';
a_addr_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS);
a_r <= b_i;
state <= st_resync;
when st_add_sp =>
state <= st_add;
when st_add =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i+b_i;
state <= st_fetch;
when st_or =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i or b_i;
state <= st_fetch;
when st_and =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i and b_i;
state <= st_fetch;
when st_resync =>
a_addr_r <= sp_r;
state <= st_fetch;
when others =>
null;
end case;
end if; -- else reset_i/='1'
end if; -- rising_edge(clk_i)
end process opcode_control;
addr_o <= addr_r;
end architecture Behave; -- Entity: ZPUSmallCore
|
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
-- E N A B L E C O N T R O L L E R
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity enable_controller is
port (
-- mcu interface
fpga_active_i : in std_logic;
mcu_active_o : out std_logic;
-- soc interface
mcu_select_i : in std_logic;
fifo_enable_o : out std_logic;
clk_i : in std_logic;
rst_i : in std_logic
);
end enable_controller;
architecture fsm of enable_controller is
type state_type is (mcu_active, fpga_active, switch_to_mcu);
signal current_state, next_state : state_type;
begin
-------------------------------------------------
-- Combinational next state and output logic
-------------------------------------------------
STATEMACHINE : process (current_state, fpga_active_i, mcu_select_i) is
begin
case current_state is
when mcu_active =>
fifo_enable_o <= '0';
mcu_active_o <= '1';
if rising_edge(fpga_active_i) then
next_state <= fpga_active;
else
next_state <= mcu_active;
end if;
when fpga_active =>
fifo_enable_o <= '1';
mcu_active_o <= '0';
if mcu_select_i = '1' then
next_state <= switch_to_mcu;
else
next_state <= fpga_active;
end if;
when switch_to_mcu =>
fifo_enable_o <= '1';
mcu_active_o <= '1';
if fpga_active_i = '1' then
next_state <= switch_to_mcu;
else
next_state <= mcu_active;
end if;
end case;
end process STATEMACHINE;
-------------------------------------------------------------------
-- State register with sync reset. Resets to mcu_active state
-------------------------------------------------------------------
STATE_REGISTER : process (clk_i, rst_i) is
begin
if (rising_edge(clk_i)) then
if (rst_i = '1') then
current_state <= mcu_active;
else
current_state <= next_state;
end if;
end if;
end process STATE_REGISTER;
end fsm;
|
-- $Id: tbd_serport_uart_rxtx.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tbd_serport_uart_rxtx - syn
-- Description: Wrapper for serport_uart_rxtx to avoid records. It
-- has a port interface which will not be modified by xst
-- synthesis (no records, no generic port).
--
-- Dependencies: serport_uart_rxtx
--
-- To test: serport_uart_rxtx
--
-- Target Devices: generic
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2007-10-27 92 9.2.02 J39 xc3s1000-4 69 122 0 - t 9.13
-- 2007-10-27 92 9.1 J30 xc3s1000-4 69 122 0 - t 9.13
-- 2007-10-27 92 8.2.03 I34 xc3s1000-4 73 152 0 81 s 9.30
-- 2007-10-27 92 8.1.03 I27 xc3s1000-4 73 125 0 - s 9.30
--
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2007-10-21 91 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
entity tbd_serport_uart_rxtx is -- serial port uart [tb design]
-- generic: CDWIDTH=13
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CLKDIV : in slv13; -- clock divider setting
RXSD : in slbit; -- receive serial data (uart view)
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXERR : out slbit; -- receiver data error (frame error)
RXACT : out slbit; -- receiver active
TXSD : out slbit; -- transmit serial data (uart view)
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit -- transmit busy
);
end tbd_serport_uart_rxtx;
architecture syn of tbd_serport_uart_rxtx is
begin
UART : serport_uart_rxtx
generic map (
CDWIDTH => 13)
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
RXSD => RXSD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => TXSD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
end syn;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated Please do not change!
-- Here are the parameters:
-- network size x:2
-- network size y:2
-- data width:32-- traffic pattern:------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use work.TB_Package.all;
use work.mlite_pack.all;
USE ieee.numeric_std.ALL;
--use IEEE.math_real."ceil";
--use IEEE.math_real."log2";
entity tb_network_2x2 is
end tb_network_2x2;
architecture behavior of tb_network_2x2 is
constant fcXS : std_logic_vector(0 to 3) := "1011";
constant fcXN : std_logic_vector(0 to 3) := "1010";
constant RAMDataSize : positive := 32;
constant RAMAddrSize : positive := 12;
constant path : string(1 to 12) := "Testbenches/"; --uncomment this if you are SIMULATING in MODELSIM, or if you're synthesizing.
-- constant path : string(positive range <>) := "/home/tsotne/ownCloud/git/Bonfire_sim/Bonfire/RTL/Chip_Designs/IMMORTAL_Chip_2017/Testbenches/"; --used only for Vivado similation. Tsotnes PC.
-- Declaring network component
component network_2x2_with_PE is
generic (DATA_WIDTH: integer := 32; DATA_WIDTH_LV: integer := 11);
port (reset: in std_logic;
clk: in std_logic;
-- IJTAG network for fault injection and checker status monitoring
TCK : in std_logic;
RST : in std_logic;
SEL : in std_logic;
SI : in std_logic;
SE : in std_logic;
UE : in std_logic;
CE : in std_logic;
SO : out std_logic;
toF : out std_logic;
toC : out std_logic;
-- GPIO for Node 0
GPIO_out: out std_logic_vector(15 downto 0);
GPIO_in: in std_logic_vector(21 downto 0);
-- UART for all Plasmas
uart_write_0 : out std_logic;
uart_read_0 : in std_logic;
uart_write_1 : out std_logic;
uart_read_1 : in std_logic;
uart_write_2 : out std_logic;
uart_read_2 : in std_logic;
uart_write_3 : out std_logic;
uart_read_3 : in std_logic;
-- Monitor connections
temperature_control : out std_logic_vector(2 downto 0);
-- temperature_data : in std_logic_vector(12 downto 0);
iddt_control : out std_logic_vector(2 downto 0);
-- iddt_data : in std_logic_vector(12 downto 0);
slack_control : out std_logic_vector(2 downto 0);
slack_data : in std_logic_vector(31 downto 0);
voltage_control : out std_logic_vector(2 downto 0);
voltage_data : in std_logic_vector(31 downto 0)
);
end component;
constant clk_period : time := 10 ns;
constant tck_period : time := 35 ns;
constant HALF_SEPARATOR : time := 2*tck_period;
constant FULL_SEPARATOR : time := 8*tck_period;
signal reset, not_reset, clk: std_logic :='0';
signal TCK, RST, SEL, SI, SE, UE, CE, SO, toF, toC : std_logic := '0';
-- GPIO
signal PE_0_GPIO_out : std_logic_vector(15 downto 0);
signal PE_0_GPIO_in : std_logic_vector(21 downto 0) := (others => '1');
signal uart_write_0, uart_write_1, uart_write_2, uart_write_3: std_logic;
signal uart_read_0, uart_read_1, uart_read_2, uart_read_3: std_logic;
signal temperature_control : std_logic_vector(2 downto 0);
signal temperature_data : std_logic_vector(12 downto 0);
signal iddt_control : std_logic_vector(2 downto 0);
signal iddt_data : std_logic_vector(12 downto 0);
signal slack_control : std_logic_vector(2 downto 0);
signal slack_data : std_logic_vector(31 downto 0);
signal voltage_control : std_logic_vector(2 downto 0);
signal voltage_data : std_logic_vector(31 downto 0);
signal current_test : string(1 to 16);
signal RAM_readout: std_logic_vector(RAMDataSize-1 downto 0);
signal r0_sta_value : std_logic_vector (0 to 24);
signal slack_value : std_logic_vector (0 to 31);
signal temp_value : std_logic_vector (0 to 31);
signal volt_value : std_logic_vector (0 to 31);
shared variable pre_shift, post_shift: std_logic_vector(0 to 127);
shared variable pre_shift_len, post_shift_len : natural;
begin
-- instantiating the top module for the network
NoC_top: network_2x2_with_PE generic map (DATA_WIDTH => 32, DATA_WIDTH_LV => 11)
port map (reset, clk,
TCK, RST, SEL, SI, SE, UE, CE, SO, toF, toC,
PE_0_GPIO_out, PE_0_GPIO_in,
uart_write_0, uart_read_0,
uart_write_1, uart_read_1,
uart_write_2, uart_read_2,
uart_write_3, uart_read_3,
temperature_control,
iddt_control,
slack_control, slack_data,
voltage_control, voltage_data
-- temperature_control, temperature_data,
-- iddt_control, iddt_data,
-- slack_control, slack_data,
-- voltage_control, voltage_data
);
-- Added for IJTAG
not_reset <= not reset;
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
ijtag_shift_proc: process
variable read_out_data: std_logic_vector(RAMDataSize-1 downto 0);
variable I, J: integer := 0;
variable stuck_at: std_logic_vector (1 downto 0) := (others => '0');
variable address_fifo: std_logic_vector (5 downto 0) := (others => '0');
variable address_arbiter_out: std_logic_vector (4 downto 0) := (others => '0');
variable address_arbiter_in: std_logic_vector (4 downto 0) := (others => '0');
variable address_arbiter_logic: std_logic_vector (8 downto 0) := (others => '0');
variable address_lbdr: std_logic_vector (6 downto 0) := (others => '0');
-- Generate a number of TCK ticks
procedure tck_tick (number_of_tick : in positive) is
begin
for i in 1 to number_of_tick loop
TCK <= '0';
wait for TCK_period/2;
TCK <= '1';
wait for TCK_period/2;
end loop;
end procedure tck_tick;
procedure tck_halftick_high is
begin
TCK <= '1';
wait for TCK_period/2;
end procedure tck_halftick_high;
procedure tck_halftick_low is
begin
TCK <= '0';
wait for TCK_period/2;
end procedure tck_halftick_low;
-- Shifts in specified data (Capture -> Shift -> Update)
procedure shift_data (data : in std_logic_vector) is
begin
-- Capture phase
CE <= '1';
tck_tick(1);
CE <= '0';
-- Shift phase
SE <= '1';
if pre_shift_len > 0 then
for i in 0 to pre_shift_len-1 loop
SI <= pre_shift(i);
tck_tick(1);
end loop;
end if ;
for i in data'range loop
SI <= data(i);
tck_tick(1);
end loop;
if post_shift_len > 0 then
for i in 0 to post_shift_len-1 loop
SI <= post_shift(i);
tck_tick(1);
end loop;
end if ;
SE <= '0';
-- Update phase
tck_halftick_low;
UE <= '1';
tck_halftick_high;
tck_halftick_low;
UE <= '0';
tck_halftick_high;
end procedure shift_data;
-- Shifts in specified data (Capture -> Shift -> Update)
procedure shift_data_with_readout (data : in std_logic_vector; capture_data : out std_logic_vector) is
begin
--Capture phase
CE <= '1';
tck_tick(1);
CE <= '0';
--Shift phase
SE <= '1';
if pre_shift_len > 0 then
for i in 0 to pre_shift_len-1 loop
SI <= pre_shift(i);
tck_tick(1);
end loop;
end if ;
for i in data'range loop
SI <= data(i);
capture_data(i) := SO;
tck_tick(1);
end loop;
if post_shift_len > 0 then
for i in 0 to post_shift_len-1 loop
SI <= post_shift(i);
tck_tick(1);
end loop;
end if ;
SE <= '0';
-- Update phase
--tck_tick(1);
tck_halftick_low;
UE <= '1';
tck_halftick_high;
tck_halftick_low;
UE <= '0';
tck_halftick_high;
end procedure shift_data_with_readout;
-- Returns all zeroes std_logic_vector of specified size
function all_zeroes (number_of_zeroes : in positive) return std_logic_vector is
variable zero_array : std_logic_vector(0 to number_of_zeroes-1);
begin
for i in zero_array'range loop
zero_array(i) := '0';
end loop;
return zero_array;
end function all_zeroes;
-- Returns all ones std_logic_vector of specified size
function all_ones (number_of_ones : in positive) return std_logic_vector is
variable ones_array : std_logic_vector(0 to number_of_ones-1);
begin
for i in ones_array'range loop
ones_array(i) := '1';
end loop;
return ones_array;
end function all_ones;
function reverse_vector (a: in std_logic_vector) return std_logic_vector is
variable result: std_logic_vector(a'RANGE);
alias aa: std_logic_vector(a'REVERSE_RANGE) is a;
begin
for i in aa'RANGE loop
result(i) := aa(i);
end loop;
return result;
end;
procedure set_ram_address (address : in std_logic_vector(RAMAddrSize-1 downto 0); autoinc : in boolean; write_en : in boolean) is
-- This function should be called in simulation when sib_mem is already opened, but sib_addr and sib_data are still closed
-- After shifting in the provided bit vector, address sib is closed and data sib is opened
constant open_mem_close_addr_sibs : std_logic_vector := "10";
constant open_sib_data : std_logic := '1';
variable autoincrement_bit : std_logic;
variable writeen_bit : std_logic;
variable bitstream_vector : std_logic_vector(0 to RAMAddrSize+4);
begin
if autoinc then
autoincrement_bit := '1';
else
autoincrement_bit := '0';
end if;
if write_en then
writeen_bit := '1';
else
writeen_bit := '0';
end if;
shift_data("11"&"0"); -- open sib_mem and sib_addr and close sib_data
bitstream_vector(0 to 1) := open_mem_close_addr_sibs;
bitstream_vector(2 to RAMAddrSize+1) := reverse_vector(address);
bitstream_vector(RAMAddrSize+2) := autoincrement_bit;
bitstream_vector(RAMAddrSize+3) := writeen_bit;
bitstream_vector(RAMAddrSize+4) := open_sib_data;
shift_data(bitstream_vector);
end procedure set_ram_address;
procedure get_set_data (write_data: in std_logic_vector (RAMDataSize-1 downto 0); read_data: out std_logic_vector (RAMDataSize-1 downto 0); leave_data_sib_open: in boolean) is
-- This function should be called in simulation when sib_mem and sib_data is opened, but sib_addr is closed.
constant open_mem_close_addr_sibs : std_logic_vector := "10";
variable leavedatasibopen_bit : std_logic;
variable read_data_vector : std_logic_vector (RAMDataSize-1 downto 0) := (others => '0');
variable bitstream_vector : std_logic_vector (0 to RAMDataSize+2);
variable readout_vector : std_logic_vector (0 to RAMDataSize+2);
begin
if leave_data_sib_open then
leavedatasibopen_bit := '1';
else
leavedatasibopen_bit := '0';
end if;
tck_tick(3); --otherwise previous data can be captured
bitstream_vector(0 to 1) := open_mem_close_addr_sibs;
bitstream_vector(2) := leavedatasibopen_bit;
bitstream_vector(3 to RAMDataSize+2) := reverse_vector(write_data);
shift_data_with_readout(bitstream_vector, readout_vector);
read_data := reverse_vector(readout_vector(3 to RAMDataSize+2));
end procedure get_set_data;
procedure test_ram_access is
begin
-- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA closed
current_test <= "ram0_addr_003 ";
set_ram_address(X"003", true, true); -- Set WORD address to 0x003, autoincrement on, RAM write on
-- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA open
current_test <= "ram0_write_to_3 ";
get_set_data(X"0AA0F0F0", read_out_data, true); -- Shift in some data to write to address 0x003, increment address and leave SIB_DATA open
-- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA open
current_test <= "ram0_write_to_4 ";
get_set_data(X"0BB0FF00", read_out_data, true); -- Shift in some data to write to address 0x004, increment address and leave SIB_DATA open
-- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA open
current_test <= "ram0_write_to_5C";
get_set_data(X"0CC0F00F", read_out_data, false); -- Shift in some data to write to address 0x005, increment address and close SIB_DATA
-- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA closed
current_test <= "ram0_addr_033 ";
set_ram_address(X"033", true, true); -- Set WORD address to 0x033, autoincrement on, RAM write on
-- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA open
current_test <= "ram0_write_to_33";
get_set_data(X"0000F0F0", read_out_data, true); -- Shift in some data to write to address 0x033, increment address and leave SIB_DATA open
-- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA open
current_test <= "ram0_write_to34C";
get_set_data(X"0000FF00", read_out_data, false); -- Shift in some data to write to address 0x034, increment address and close SIB_DATA
-- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA closed
RAM_readout <= (others => '0');
current_test <= "ram0_addr_003 ";
set_ram_address(X"003", true, false); -- Set WORD address to 0x003, autoincrement off, RAM write off
-- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA open
current_test <= "ram0_read_003 ";
get_set_data(X"00000000", read_out_data, true); -- Shift in some data (no write) and leave SIB_DATA open, possible to read out data from address 0x003
-- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA open
current_test <= "ram0_read_004 ";
get_set_data(X"00000000", read_out_data, false); -- Shift in some data (no write) and close SIB_DATA, possible to read out data from address 0x004
-- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA closed
RAM_readout <= read_out_data; -- put data from word address 0x004
current_test <= "close_sib_mem ";
shift_data("000"); -- close all but sib_ram: sib_noc & sib_sens & 3xsib_mem + opened sib_mem
tck_tick(4);
end procedure test_ram_access;
variable r0_sta_value_var : std_logic_vector (0 to 24);
variable slack_value_var : std_logic_vector (0 to 31);
variable temp_value_var : std_logic_vector (0 to 31);
variable volt_value_var : std_logic_vector (0 to 31);
begin
-- the order of bits in each sib is: SXCF where S is opening bit!
-- to open sib 3 we need to shift the following: "0001"&"0000"&"0000"&"0000"&"0000"
-- * note that the shifting order is oposite!
-- Organization of IJTAG network (top level):
-- .----------. .-----------. .----------.
-- SI ----| sib_ram |---| sib_sens |---| sib_noc |-- SO
-- '----------' '-----------' '----------'
-- | |_________________________________________________.
-- | |
-- | .-----------. .-----------. .-----------. .-----------. |
-- '-| sib_ram_0 |-| sib_ram_1 |-| sib_ram_2 |-| sib_ram_3 |-'
-- '-----------' '-----------' '-----------' '-----------'
-- .-------.
-- SI -----|sib_mem|-- SO
-- '-------'
-- | |_________________________________________________.
-- | |
-- | .----------. .------------. |
-- '--| sib_data |--------------------->| sib_addr |----'
-- '----------' '------------'
-- | |_____________ | |______________
-- | _____________ | | ______ _______ |
-- '--->| data |-' '->|we,inc|-|address|-'
-- '-------------' '------' '-------'
-- Auto increment bit is MSb in Address shift register
-- .-----------.
-- SI ----| sib_sens |---------------------------------------------- SO
-- '-----------'
-- | |_____________________________________________.
-- | |
-- | .----------. .----------. .----------. .----------. |
-- '-| sib_temp |-| sib_iddt |-| sib_slck |-| sib_volt |-'
-- '----------' '----------' '----------' '----------'
-- .-----------.
-- SI ----| sib_noc |---------------------------------------------- SO
-- '-----------'
-- | |_________________________________.
-- | |
-- | .-------. .-------. .-------. .-------. |
-- '-| sib_0 |-| sib_1 |-| sib_2 |-| sib_3 |-'
-- '-------' '-------' '-------' '-------'
-- | |_________________________________________.
-- | |
-- | .----------. .------------. |
-- '--| sib3 inj |------------->|sib3 status |----'
-- '----------' '------------'
-- | |_____________ | |_____________
-- | _____________ | | _____________ |
-- '--->|injection reg|-' '--->|async adapter|-'
-- '-------------' '-------------'
-- Reset iJTAG chain and Instruments
RST <= '1';
wait for tck_period;
RST <= '0';
SEL <= '1';
tck_tick(4);
reset <= '1';
-- RAM access instrument test
--reset <= '0';
--current_test <= "open_sib_ram ";
--shift_data(fcXN&fcXN&fcXS); -- open sib_ram
---- Test mem0
--current_test <= "open_sib_ram0 ";
--pre_shift(0 to 14) := fcXN&fcXN&fcXS&"0"&"0"&"0";
--pre_shift_len := 15;
--post_shift_len := 0;
--shift_data("1"); -- open sib_ram and sib_ram0: sib_noc & sib_sens & sib_ram & 3xsib_mem
--tck_tick(4);
--test_ram_access;
---- Test mem1
--current_test <= "open_sib_ram1 ";
--pre_shift(0 to 13) := fcXN&fcXN&fcXS&"0"&"0";
--pre_shift_len := 14;
--post_shift(0 to 0) := "0";
--post_shift_len := 1;
--shift_data("1"); -- open sib_ram and sib_ram_1: sib_noc & sib_sens & sib_ram & 4xsib_mem
--tck_tick(4);
--test_ram_access;
---- Test mem2
--current_test <= "open_sib_ram2 ";
--pre_shift(0 to 12) := fcXN&fcXN&fcXS&"0";
--pre_shift_len := 13;
--post_shift(0 to 1) := "00";
--post_shift_len := 2;
--shift_data("1"); -- open sib_ram and sib_ram_2: sib_noc & sib_sens & sib_ram & 4xsib_mem
--tck_tick(4);
--test_ram_access;
---- Test mem2
--current_test <= "open_sib_ram3 ";
--pre_shift(0 to 11) := fcXN&fcXN&fcXS;
--pre_shift_len := 12;
--post_shift(0 to 2) := "000";
--post_shift_len := 3;
--shift_data("1"); -- open sib_ram and sib_ram_3: sib_noc & sib_sens & sib_ram & 4xsib_mem
--tck_tick(4);
--test_ram_access;
--current_test <= "close_sib_ram ";
--pre_shift_len := 0;
--post_shift_len := 0;
--shift_data(fcXN&fcXN&fcXN&"0"&"0"&"0"&"0"); -- close all sibs
---- Release chip reset
--reset <= '1';
wait for 10us;
-- Sensors
--temperature_data(12 downto 1) <= "000000000000";
--temperature_data(0) <= '0';
--current_test <= "open_sib_sens ";
--pre_shift_len := 0;
--post_shift_len := 0;
--shift_data(fcXN&fcXS&fcXN); -- open sib_sens
-- Temperature monitor test
--current_test <= "open_sib_temp ";
--pre_shift(0 to 23) := fcXN&fcXS&fcXN&fcXN&fcXN&fcXS; -- (top)noc, (top)sens, volt, slack, iddt, sib_temp
--pre_shift_len := 24;
--post_shift(0 to 3) := fcXN; --(top)mem
--post_shift_len := 4;
--shift_data(""); --open sib_temp
--current_test <= "shift_temp_setup";
--shift_data("001000000000"&"010000000000"&"0"&"1"&"1"&"01111"); -- shift in threshold H without update
--tck_tick(4);
--current_test <= "temp 1 ";
--temperature_data(12 downto 1) <= "000000000011";
--tck_tick(1);
--temperature_data(0) <= '1';
--tck_tick(1);
--temperature_data(0) <= '0';
--tck_tick(4);
--current_test <= "temp 2 ";
--temperature_data(12 downto 1) <= "000000000100";
--tck_tick(1);
--temperature_data(0) <= '1';
--tck_tick(1);
--temperature_data(0) <= '0';
--tck_tick(4);
--current_test <= "temp 3 ";
--temperature_data(12 downto 1) <= "000000001100";
--tck_tick(1);
--temperature_data(0) <= '1';
--tck_tick(1);
--temperature_data(0) <= '0';
--tck_tick(4);
--current_test <= "shift_temp_setup";
--shift_data("001000000000"&"010000000000"&"0"&"0"&"1"&"01011"); -- shift in threshold H without update
--tck_tick(10);
--current_test <= "close_sib_temp ";
--pre_shift(0 to 23) := fcXN&fcXS&fcXN&fcXN&fcXN&fcXN; -- (top)noc, (top)sens, volt, slack, iddt, temp
--pre_shift_len := 24;
--post_shift(0 to 3) := fcXN; --(top)mem
--post_shift_len := 4;
----shift_data(all_zeroes(32));
--shift_data_with_readout(all_zeroes(32), temp_value_var);
--temp_value <= reverse_vector(temp_value_var);
---- IDDt monitor test
-- current_test <= "open_sib_iddt ";
-- pre_shift(0 to 19) := fcXN&fcXS&fcXN&fcXN&fcXS; -- (top)noc, (top)sens, volt, slack, iddt
-- pre_shift_len := 20;
-- post_shift(0 to 7) := fcXN&fcXN; -- temp, (top)mem
-- post_shift_len := 8;
-- shift_data(""); --open sib_temp
-- current_test <= "close_sib_iddt ";
-- pre_shift(0 to 19) := fcXN&fcXS&fcXN&fcXN&fcXN; -- (top)noc, (top)sens, volt, slack, iddt
-- pre_shift_len := 20;
-- post_shift(0 to 7) := fcXN&fcXN; -- temp, (top)mem
-- post_shift_len := 8;
-- shift_data(all_zeroes(32));
-- Slack monitor test
--current_test <= "open_sib_slack ";
--pre_shift(0 to 15) := fcXN&fcXS&fcXN&fcXS; -- (top)noc, (top)sens, volt, slack
--pre_shift_len := 16;
--post_shift(0 to 11) := fcXN&fcXN&fcXN; -- iddt, temp, (top)mem
--post_shift_len := 12;
--shift_data(""); --open sib_temp
--current_test <= "Slack ";
--shift_data("11100"&"00000"&"0"&"1"&"1"&"0000000000000001111"); -- shift in threshold H without update
--tck_tick(4);
--slack_data <= "00101010101010101010101010101010";
--tck_tick(10);
--slack_data <= "10101010101010101010101010100101";
--tck_tick(4);
--current_test <= "close_sib_slack ";
--pre_shift(0 to 15) := fcXN&fcXS&fcXN&fcXN; -- (top)noc, (top)sens, volt, slack
--pre_shift_len := 16;
--post_shift(0 to 11) := fcXN&fcXN&fcXN; -- iddt, temp, (top)mem
--post_shift_len := 12;
--shift_data_with_readout(all_zeroes(32), slack_value_var);
--slack_value <= reverse_vector(slack_value_var);
--shift_data(all_zeroes(32));
-- Voltage monitor test
--voltage_data <= "00000000000000000000000000000000";
--current_test <= "open_sib_volt ";
--pre_shift(0 to 11) := fcXN&fcXS&fcXS; -- (top)noc, (top)sens, volt
--pre_shift_len := 12;
--post_shift(0 to 15) := fcXN&fcXN&fcXN&fcXN; -- slack, iddt, temp, (top)mem
--post_shift_len := 16;
--shift_data(""); --open sib_temp
--current_test <= "Voltage ";
--shift_data("00001"&"11100"&"1"&"1"&"1"&"0000000000000001111"); -- shift in threshold H without update
--voltage_data <= "00000000000000000000000000000000";
--tck_tick(1);
--voltage_data <= "00000000000000000000000000000001";
--tck_tick(1);
--voltage_data <= "00000000000000000000000000000011";
--tck_tick(1);
--voltage_data <= "00000000000000000000000000000111";
--tck_tick(1);
--voltage_data <= "00000000000000000000000000001111";
--tck_tick(1);
--voltage_data <= "00000000000000000000000000011111";
--tck_tick(1);
--voltage_data <= "00000000000000000000000000111111";
--tck_tick(1);
--voltage_data <= "00000000000000000000000001111111";
--tck_tick(1);
--voltage_data <= "00000000000000000000000011111111";
--tck_tick(1);
--voltage_data <= "00000000000000000000000111111111";
--tck_tick(1);
--voltage_data <= "00000000000000000000001111111111";
--tck_tick(1);
--voltage_data <= "00000000000000000000011111111111";
--tck_tick(1);
--voltage_data <= "00000000000000000000111111111111";
--tck_tick(1);
--voltage_data <= "00000000000000000001111111111111";
--tck_tick(1);
--voltage_data <= "00000000000000000011111111111111";
--tck_tick(1);
--voltage_data <= "00000000000000000111111111111111";
--tck_tick(1);
--voltage_data <= "00000000000000001111111111111111";
--tck_tick(1);
--voltage_data <= "00000000000000011111111111111111";
--tck_tick(1);
--voltage_data <= "00000000000000111111111111111111";
--tck_tick(1);
--voltage_data <= "00000000000001111111111111111111";
--tck_tick(1);
--voltage_data <= "00000000000011111111111111111111";
--tck_tick(1);
--voltage_data <= "00000000000111111111111111111111";
--tck_tick(1);
--voltage_data <= "00000000001111111111111111111111";
--tck_tick(1);
--voltage_data <= "00000000011111111111111111111111";
--tck_tick(1);
--voltage_data <= "00000000111111111111111111111111";
--tck_tick(1);
--voltage_data <= "00000001111111111111111111111111";
--tck_tick(1);
--voltage_data <= "00000011111111111111111111111111";
--tck_tick(1);
--voltage_data <= "00000111111111111111111111111111";
--tck_tick(1);
--voltage_data <= "00001111111111111111111111111111";
--tck_tick(1);
--voltage_data <= "00011111111111111111111111111111";
--tck_tick(1);
--voltage_data <= "00111111111111111111111111111111";
--tck_tick(1);
--voltage_data <= "01111111111111111111111111111111";
--tck_tick(1);
--voltage_data <= "11111111111111111111111111111111";
--tck_tick(10);
--shift_data("11100"&"00001"&"0"&"1"&"1"&"0000000000000001111"); -- shift in threshold H without update
--tck_tick(10);
--voltage_data <= "00000000000000000000000011111111";
--tck_tick(10);
--current_test <= "close_sib_volt ";
--pre_shift(0 to 11) := fcXN&fcXS&fcXN; -- (top)noc, (top)sens, volt
--pre_shift_len := 12;
--post_shift(0 to 15) := fcXN&fcXN&fcXN&fcXN; -- slack, iddt, temp, (top)mem
--post_shift_len := 16;
----shift_data(all_zeroes(32));
--shift_data_with_readout(all_zeroes(32), volt_value_var);
--volt_value <= reverse_vector(volt_value_var);
--current_test <= "close_sib_sens ";
--pre_shift_len := 0;
--post_shift_len := 0;
--shift_data(fcXN&fcXN&fcXN&fcXN&fcXN&fcXN&fcXN); -- close all sibs
-- Router SIBs
current_test <= "open_sib_noc ";
pre_shift_len := 0;
post_shift_len := 0;
shift_data(fcXS&fcXN&fcXN); -- open sib_noc
--Router 0
current_test <= "open_sib_r0 ";
pre_shift(0 to 19) := fcXS&fcXN&fcXN&fcXN&fcXS; -- (top)noc, r3, r2, r1, r0
pre_shift_len := 20;
post_shift(0 to 7) := fcXN&fcXN; -- (top)sens, (top)mem
post_shift_len := 8;
shift_data(""); --open sib_r0
--Router 0 injection
current_test <= "open_sib_r0_inj ";
pre_shift(0 to 27) := fcXS&fcXN&fcXN&fcXN&fcXS&fcXN&fcXS; -- (top)noc, r3, r2, r1, r0, r0_sta, r0_inj
pre_shift_len := 28;
post_shift(0 to 7) := fcXN&fcXN; -- (top)sens, (top)mem
post_shift_len := 8;
shift_data(""); --open sib_r0_inj
current_test <= "r0_inj_arb_out ";
--shift_data(all_zeroes(130));
shift_data("000000000"& "0000001"&"0000001"&"0000001"&"0000001"&"0000001"& "0000000"&"0000000"&"0000000"&"0000000"&"0000000"& "000000000"&"000000000"&"000000000"& "00000000"&"00000000"&"00000000");
current_test <= "close_sib_r0_inj";
pre_shift(0 to 27) := fcXS&fcXN&fcXN&fcXN&fcXS&fcXN&fcXN; -- (top)noc, r3, r2, r1, r0, r0_sta, r0_inj
pre_shift_len := 28;
post_shift(0 to 7) := fcXN&fcXN; -- (top)sens, (top)mem
post_shift_len := 8;
shift_data(all_zeroes(130));
--Router 0 status
current_test <= "open_sib_r0_sta ";
pre_shift(0 to 23) := fcXS&fcXN&fcXN&fcXN&fcXS&fcXS; -- (top)noc, r3, r2, r1, r0, r0_sta
pre_shift_len := 24;
post_shift(0 to 11) := fcXN&fcXN&fcXN; -- r0_inj, (top)sens, (top)mem
post_shift_len := 12;
shift_data(""); --open sib_r0_sta
current_test <= "r0_sta_readout ";
shift_data_with_readout(all_zeroes(25), r0_sta_value_var);
r0_sta_value <= reverse_vector(r0_sta_value_var);
--shift_data(all_zeroes(25));
current_test <= "close_sib_r0_sta";
pre_shift(0 to 23) := fcXS&fcXN&fcXN&fcXN&fcXS&fcXN; -- (top)noc, r3, r2, r1, r0, r0_sta
pre_shift_len := 24;
post_shift(0 to 11) := fcXN&fcXN&fcXN; -- r0_inj, (top)sens, (top)mem
post_shift_len := 12;
shift_data("11111"&all_zeroes(20));
current_test <= "close_sib_r0 ";
pre_shift(0 to 19) := fcXS&fcXN&fcXN&fcXN&fcXN; -- (top)noc, r3, r2, r1, r0
pre_shift_len := 20;
post_shift(0 to 7) := fcXN&fcXN; -- (top)sens, (top)mem
post_shift_len := 8;
shift_data(fcXN&fcXN); -- inj and status sibs of r0
----Router 1
--current_test <= "open_sib_r1 ";
--pre_shift(0 to 15) := fcXS&fcXN&fcXN&fcXS; -- (top)noc, r3, r2, r1
--pre_shift_len := 16;
--post_shift(0 to 11) := fcXN&fcXN&fcXN; -- r0, (top)sens, (top)mem
--post_shift_len := 12;
--shift_data(""); --open sib_r1
----Router 1 injection
--current_test <= "open_sib_r1_inj ";
--pre_shift(0 to 23) := fcXS&fcXN&fcXN&fcXS&fcXN&fcXS; -- (top)noc, r3, r2, r1, r1_sta, r1_inj
--pre_shift_len := 24;
--post_shift(0 to 11) := fcXN&fcXN&fcXN; -- r0, (top)sens, (top)mem
--post_shift_len := 12;
--shift_data(""); --open sib_r1_inj
--current_test <= "r1_inj_arb_out ";
--shift_data(all_zeroes(130));
----shift_data("000000000"& "0000001"&"0000001"&"0000001"&"0000001"&"0000001"& "0000000"&"0000000"&"0000000"&"0000000"&"0000000"& "000000000"&"000000000"&"000000000"& "00000000"&"00000000"&"00000000");
--current_test <= "close_sib_r1_inj";
--pre_shift(0 to 23) := fcXS&fcXN&fcXN&fcXS&fcXN&fcXN; -- (top)noc, r3, r2, r1, r1_sta, r1_inj
--pre_shift_len := 24;
--post_shift(0 to 11) := fcXN&fcXN&fcXN; -- r0, (top)sens, (top)mem
--post_shift_len := 12;
--shift_data(all_zeroes(130));
--current_test <= "close_sib_r1 ";
--pre_shift(0 to 15) := fcXS&fcXN&fcXN&fcXN; -- (top)noc, r3, r2, r1
--pre_shift_len := 16;
--post_shift(0 to 11) := fcXN&fcXN&fcXN; -- r0, (top)sens, (top)mem
--post_shift_len := 12;
--shift_data(fcXN&fcXN); -- inj and status sibs of r1
----Router 2
--current_test <= "open_sib_r2 ";
--pre_shift(0 to 11) := fcXS&fcXN&fcXS; -- (top)noc, r3, r2
--pre_shift_len := 12;
--post_shift(0 to 15) := fcXN&fcXN&fcXN&fcXN; -- r1, r0, (top)sens, (top)mem
--post_shift_len := 16;
--shift_data(""); --open sib_r2
----Router 2 injection
--current_test <= "open_sib_r2_inj ";
--pre_shift(0 to 19) := fcXS&fcXN&fcXS&fcXN&fcXS; -- (top)noc, r3, r2, r2_sta, r2_inj
--pre_shift_len := 20;
--post_shift(0 to 15) := fcXN&fcXN&fcXN&fcXN; -- r1, r0, (top)sens, (top)mem
--post_shift_len := 16;
--shift_data(""); --open sib_r2_inj
--current_test <= "r2_inj_arb_out ";
--shift_data(all_zeroes(130));
----shift_data("000000000"& "0000001"&"0000001"&"0000001"&"0000001"&"0000001"& "0000000"&"0000000"&"0000000"&"0000000"&"0000000"& "000000000"&"000000000"&"000000000"& "00000000"&"00000000"&"00000000");
--current_test <= "close_sib_r2_inj";
--pre_shift(0 to 19) := fcXS&fcXN&fcXS&fcXN&fcXN; -- (top)noc, r3, r2, r2_sta, r2_inj
--pre_shift_len := 20;
--post_shift(0 to 15) := fcXN&fcXN&fcXN&fcXN; -- r1, r0, (top)sens, (top)mem
--post_shift_len := 16;
--shift_data(all_zeroes(130));
--current_test <= "close_sib_r2 ";
--pre_shift(0 to 11) := fcXS&fcXN&fcXN; -- (top)noc, r3, r2
--pre_shift_len := 12;
--post_shift(0 to 15) := fcXN&fcXN&fcXN&fcXN; -- r1, r0, (top)sens, (top)mem
--post_shift_len := 16;
--shift_data(fcXN&fcXN); -- inj and status sibs of r2
----Router 3
--current_test <= "open_sib_r3 ";
--pre_shift(0 to 7) := fcXS&fcXS; -- (top)noc, r3
--pre_shift_len := 8;
--post_shift(0 to 19) := fcXN&fcXN&fcXN&fcXN&fcXN; -- r2, r1, r0, (top)sens, (top)mem
--post_shift_len := 20;
--shift_data(""); --open sib_r3
----Router 2 injection
--current_test <= "open_sib_r3_inj ";
--pre_shift(0 to 15) := fcXS&fcXS&fcXN&fcXS; -- (top)noc, r3, r3_sta, r3_inj
--pre_shift_len := 16;
--post_shift(0 to 19) := fcXN&fcXN&fcXN&fcXN&fcXN; -- r2, r1, r0, (top)sens, (top)mem
--post_shift_len := 20;
--shift_data(""); --open sib_r3_inj
--current_test <= "r3_inj_arb_out ";
--shift_data(all_zeroes(130));
----shift_data("000000000"& "0000001"&"0000001"&"0000001"&"0000001"&"0000001"& "0000000"&"0000000"&"0000000"&"0000000"&"0000000"& "000000000"&"000000000"&"000000000"& "00000000"&"00000000"&"00000000");
--current_test <= "close_sib_r3_inj";
--pre_shift(0 to 15) := fcXS&fcXS&fcXN&fcXN; -- (top)noc, r3, r3_sta, r3_inj
--pre_shift_len := 16;
--post_shift(0 to 19) := fcXN&fcXN&fcXN&fcXN&fcXN; -- r2, r1, r0, (top)sens, (top)mem
--post_shift_len := 20;
--shift_data(all_zeroes(130));
--current_test <= "close_sib_r3 ";
--pre_shift(0 to 7) := fcXS&fcXN; -- (top)noc, r3
--pre_shift_len := 8;
--post_shift(0 to 19) := fcXN&fcXN&fcXN&fcXN&fcXN; -- r2, r1, r0, (top)sens, (top)mem
--post_shift_len := 20;
--shift_data(fcXN&fcXN); -- inj and status sibs of r3
current_test <= "close_sib_noc ";
pre_shift_len := 0;
post_shift_len := 0;
shift_data(fcXN&fcXN&fcXN&fcXN&fcXN&fcXN&fcXN); -- close all sibs
wait;
end process;
end behavior;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated Please do not change!
-- Here are the parameters:
-- network size x:2
-- network size y:2
-- data width:32-- traffic pattern:------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use work.TB_Package.all;
use work.mlite_pack.all;
USE ieee.numeric_std.ALL;
--use IEEE.math_real."ceil";
--use IEEE.math_real."log2";
entity tb_network_2x2 is
end tb_network_2x2;
architecture behavior of tb_network_2x2 is
constant fcXS : std_logic_vector(0 to 3) := "1011";
constant fcXN : std_logic_vector(0 to 3) := "1010";
constant RAMDataSize : positive := 32;
constant RAMAddrSize : positive := 12;
constant path : string(1 to 12) := "Testbenches/"; --uncomment this if you are SIMULATING in MODELSIM, or if you're synthesizing.
-- constant path : string(positive range <>) := "/home/tsotne/ownCloud/git/Bonfire_sim/Bonfire/RTL/Chip_Designs/IMMORTAL_Chip_2017/Testbenches/"; --used only for Vivado similation. Tsotnes PC.
-- Declaring network component
component network_2x2_with_PE is
generic (DATA_WIDTH: integer := 32; DATA_WIDTH_LV: integer := 11);
port (reset: in std_logic;
clk: in std_logic;
-- IJTAG network for fault injection and checker status monitoring
TCK : in std_logic;
RST : in std_logic;
SEL : in std_logic;
SI : in std_logic;
SE : in std_logic;
UE : in std_logic;
CE : in std_logic;
SO : out std_logic;
toF : out std_logic;
toC : out std_logic;
-- GPIO for Node 0
GPIO_out: out std_logic_vector(15 downto 0);
GPIO_in: in std_logic_vector(21 downto 0);
-- UART for all Plasmas
uart_write_0 : out std_logic;
uart_read_0 : in std_logic;
uart_write_1 : out std_logic;
uart_read_1 : in std_logic;
uart_write_2 : out std_logic;
uart_read_2 : in std_logic;
uart_write_3 : out std_logic;
uart_read_3 : in std_logic;
-- Monitor connections
temperature_control : out std_logic_vector(2 downto 0);
-- temperature_data : in std_logic_vector(12 downto 0);
iddt_control : out std_logic_vector(2 downto 0);
-- iddt_data : in std_logic_vector(12 downto 0);
slack_control : out std_logic_vector(2 downto 0);
slack_data : in std_logic_vector(31 downto 0);
voltage_control : out std_logic_vector(2 downto 0);
voltage_data : in std_logic_vector(31 downto 0)
);
end component;
constant clk_period : time := 10 ns;
constant tck_period : time := 35 ns;
constant HALF_SEPARATOR : time := 2*tck_period;
constant FULL_SEPARATOR : time := 8*tck_period;
signal reset, not_reset, clk: std_logic :='0';
signal TCK, RST, SEL, SI, SE, UE, CE, SO, toF, toC : std_logic := '0';
-- GPIO
signal PE_0_GPIO_out : std_logic_vector(15 downto 0);
signal PE_0_GPIO_in : std_logic_vector(21 downto 0) := (others => '1');
signal uart_write_0, uart_write_1, uart_write_2, uart_write_3: std_logic;
signal uart_read_0, uart_read_1, uart_read_2, uart_read_3: std_logic;
signal temperature_control : std_logic_vector(2 downto 0);
signal temperature_data : std_logic_vector(12 downto 0);
signal iddt_control : std_logic_vector(2 downto 0);
signal iddt_data : std_logic_vector(12 downto 0);
signal slack_control : std_logic_vector(2 downto 0);
signal slack_data : std_logic_vector(31 downto 0);
signal voltage_control : std_logic_vector(2 downto 0);
signal voltage_data : std_logic_vector(31 downto 0);
signal current_test : string(1 to 16);
signal RAM_readout: std_logic_vector(RAMDataSize-1 downto 0);
signal r0_sta_value : std_logic_vector (0 to 24);
signal slack_value : std_logic_vector (0 to 31);
signal temp_value : std_logic_vector (0 to 31);
signal volt_value : std_logic_vector (0 to 31);
shared variable pre_shift, post_shift: std_logic_vector(0 to 127);
shared variable pre_shift_len, post_shift_len : natural;
begin
-- instantiating the top module for the network
NoC_top: network_2x2_with_PE generic map (DATA_WIDTH => 32, DATA_WIDTH_LV => 11)
port map (reset, clk,
TCK, RST, SEL, SI, SE, UE, CE, SO, toF, toC,
PE_0_GPIO_out, PE_0_GPIO_in,
uart_write_0, uart_read_0,
uart_write_1, uart_read_1,
uart_write_2, uart_read_2,
uart_write_3, uart_read_3,
temperature_control,
iddt_control,
slack_control, slack_data,
voltage_control, voltage_data
-- temperature_control, temperature_data,
-- iddt_control, iddt_data,
-- slack_control, slack_data,
-- voltage_control, voltage_data
);
-- Added for IJTAG
not_reset <= not reset;
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
ijtag_shift_proc: process
variable read_out_data: std_logic_vector(RAMDataSize-1 downto 0);
variable I, J: integer := 0;
variable stuck_at: std_logic_vector (1 downto 0) := (others => '0');
variable address_fifo: std_logic_vector (5 downto 0) := (others => '0');
variable address_arbiter_out: std_logic_vector (4 downto 0) := (others => '0');
variable address_arbiter_in: std_logic_vector (4 downto 0) := (others => '0');
variable address_arbiter_logic: std_logic_vector (8 downto 0) := (others => '0');
variable address_lbdr: std_logic_vector (6 downto 0) := (others => '0');
-- Generate a number of TCK ticks
procedure tck_tick (number_of_tick : in positive) is
begin
for i in 1 to number_of_tick loop
TCK <= '0';
wait for TCK_period/2;
TCK <= '1';
wait for TCK_period/2;
end loop;
end procedure tck_tick;
procedure tck_halftick_high is
begin
TCK <= '1';
wait for TCK_period/2;
end procedure tck_halftick_high;
procedure tck_halftick_low is
begin
TCK <= '0';
wait for TCK_period/2;
end procedure tck_halftick_low;
-- Shifts in specified data (Capture -> Shift -> Update)
procedure shift_data (data : in std_logic_vector) is
begin
-- Capture phase
CE <= '1';
tck_tick(1);
CE <= '0';
-- Shift phase
SE <= '1';
if pre_shift_len > 0 then
for i in 0 to pre_shift_len-1 loop
SI <= pre_shift(i);
tck_tick(1);
end loop;
end if ;
for i in data'range loop
SI <= data(i);
tck_tick(1);
end loop;
if post_shift_len > 0 then
for i in 0 to post_shift_len-1 loop
SI <= post_shift(i);
tck_tick(1);
end loop;
end if ;
SE <= '0';
-- Update phase
tck_halftick_low;
UE <= '1';
tck_halftick_high;
tck_halftick_low;
UE <= '0';
tck_halftick_high;
end procedure shift_data;
-- Shifts in specified data (Capture -> Shift -> Update)
procedure shift_data_with_readout (data : in std_logic_vector; capture_data : out std_logic_vector) is
begin
--Capture phase
CE <= '1';
tck_tick(1);
CE <= '0';
--Shift phase
SE <= '1';
if pre_shift_len > 0 then
for i in 0 to pre_shift_len-1 loop
SI <= pre_shift(i);
tck_tick(1);
end loop;
end if ;
for i in data'range loop
SI <= data(i);
capture_data(i) := SO;
tck_tick(1);
end loop;
if post_shift_len > 0 then
for i in 0 to post_shift_len-1 loop
SI <= post_shift(i);
tck_tick(1);
end loop;
end if ;
SE <= '0';
-- Update phase
--tck_tick(1);
tck_halftick_low;
UE <= '1';
tck_halftick_high;
tck_halftick_low;
UE <= '0';
tck_halftick_high;
end procedure shift_data_with_readout;
-- Returns all zeroes std_logic_vector of specified size
function all_zeroes (number_of_zeroes : in positive) return std_logic_vector is
variable zero_array : std_logic_vector(0 to number_of_zeroes-1);
begin
for i in zero_array'range loop
zero_array(i) := '0';
end loop;
return zero_array;
end function all_zeroes;
-- Returns all ones std_logic_vector of specified size
function all_ones (number_of_ones : in positive) return std_logic_vector is
variable ones_array : std_logic_vector(0 to number_of_ones-1);
begin
for i in ones_array'range loop
ones_array(i) := '1';
end loop;
return ones_array;
end function all_ones;
function reverse_vector (a: in std_logic_vector) return std_logic_vector is
variable result: std_logic_vector(a'RANGE);
alias aa: std_logic_vector(a'REVERSE_RANGE) is a;
begin
for i in aa'RANGE loop
result(i) := aa(i);
end loop;
return result;
end;
procedure set_ram_address (address : in std_logic_vector(RAMAddrSize-1 downto 0); autoinc : in boolean; write_en : in boolean) is
-- This function should be called in simulation when sib_mem is already opened, but sib_addr and sib_data are still closed
-- After shifting in the provided bit vector, address sib is closed and data sib is opened
constant open_mem_close_addr_sibs : std_logic_vector := "10";
constant open_sib_data : std_logic := '1';
variable autoincrement_bit : std_logic;
variable writeen_bit : std_logic;
variable bitstream_vector : std_logic_vector(0 to RAMAddrSize+4);
begin
if autoinc then
autoincrement_bit := '1';
else
autoincrement_bit := '0';
end if;
if write_en then
writeen_bit := '1';
else
writeen_bit := '0';
end if;
shift_data("11"&"0"); -- open sib_mem and sib_addr and close sib_data
bitstream_vector(0 to 1) := open_mem_close_addr_sibs;
bitstream_vector(2 to RAMAddrSize+1) := reverse_vector(address);
bitstream_vector(RAMAddrSize+2) := autoincrement_bit;
bitstream_vector(RAMAddrSize+3) := writeen_bit;
bitstream_vector(RAMAddrSize+4) := open_sib_data;
shift_data(bitstream_vector);
end procedure set_ram_address;
procedure get_set_data (write_data: in std_logic_vector (RAMDataSize-1 downto 0); read_data: out std_logic_vector (RAMDataSize-1 downto 0); leave_data_sib_open: in boolean) is
-- This function should be called in simulation when sib_mem and sib_data is opened, but sib_addr is closed.
constant open_mem_close_addr_sibs : std_logic_vector := "10";
variable leavedatasibopen_bit : std_logic;
variable read_data_vector : std_logic_vector (RAMDataSize-1 downto 0) := (others => '0');
variable bitstream_vector : std_logic_vector (0 to RAMDataSize+2);
variable readout_vector : std_logic_vector (0 to RAMDataSize+2);
begin
if leave_data_sib_open then
leavedatasibopen_bit := '1';
else
leavedatasibopen_bit := '0';
end if;
tck_tick(3); --otherwise previous data can be captured
bitstream_vector(0 to 1) := open_mem_close_addr_sibs;
bitstream_vector(2) := leavedatasibopen_bit;
bitstream_vector(3 to RAMDataSize+2) := reverse_vector(write_data);
shift_data_with_readout(bitstream_vector, readout_vector);
read_data := reverse_vector(readout_vector(3 to RAMDataSize+2));
end procedure get_set_data;
procedure test_ram_access is
begin
-- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA closed
current_test <= "ram0_addr_003 ";
set_ram_address(X"003", true, true); -- Set WORD address to 0x003, autoincrement on, RAM write on
-- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA open
current_test <= "ram0_write_to_3 ";
get_set_data(X"0AA0F0F0", read_out_data, true); -- Shift in some data to write to address 0x003, increment address and leave SIB_DATA open
-- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA open
current_test <= "ram0_write_to_4 ";
get_set_data(X"0BB0FF00", read_out_data, true); -- Shift in some data to write to address 0x004, increment address and leave SIB_DATA open
-- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA open
current_test <= "ram0_write_to_5C";
get_set_data(X"0CC0F00F", read_out_data, false); -- Shift in some data to write to address 0x005, increment address and close SIB_DATA
-- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA closed
current_test <= "ram0_addr_033 ";
set_ram_address(X"033", true, true); -- Set WORD address to 0x033, autoincrement on, RAM write on
-- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA open
current_test <= "ram0_write_to_33";
get_set_data(X"0000F0F0", read_out_data, true); -- Shift in some data to write to address 0x033, increment address and leave SIB_DATA open
-- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA open
current_test <= "ram0_write_to34C";
get_set_data(X"0000FF00", read_out_data, false); -- Shift in some data to write to address 0x034, increment address and close SIB_DATA
-- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA closed
RAM_readout <= (others => '0');
current_test <= "ram0_addr_003 ";
set_ram_address(X"003", true, false); -- Set WORD address to 0x003, autoincrement off, RAM write off
-- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA open
current_test <= "ram0_read_003 ";
get_set_data(X"00000000", read_out_data, true); -- Shift in some data (no write) and leave SIB_DATA open, possible to read out data from address 0x003
-- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA open
current_test <= "ram0_read_004 ";
get_set_data(X"00000000", read_out_data, false); -- Shift in some data (no write) and close SIB_DATA, possible to read out data from address 0x004
-- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA closed
RAM_readout <= read_out_data; -- put data from word address 0x004
current_test <= "close_sib_mem ";
shift_data("000"); -- close all but sib_ram: sib_noc & sib_sens & 3xsib_mem + opened sib_mem
tck_tick(4);
end procedure test_ram_access;
variable r0_sta_value_var : std_logic_vector (0 to 24);
variable slack_value_var : std_logic_vector (0 to 31);
variable temp_value_var : std_logic_vector (0 to 31);
variable volt_value_var : std_logic_vector (0 to 31);
begin
-- the order of bits in each sib is: SXCF where S is opening bit!
-- to open sib 3 we need to shift the following: "0001"&"0000"&"0000"&"0000"&"0000"
-- * note that the shifting order is oposite!
-- Organization of IJTAG network (top level):
-- .----------. .-----------. .----------.
-- SI ----| sib_ram |---| sib_sens |---| sib_noc |-- SO
-- '----------' '-----------' '----------'
-- | |_________________________________________________.
-- | |
-- | .-----------. .-----------. .-----------. .-----------. |
-- '-| sib_ram_0 |-| sib_ram_1 |-| sib_ram_2 |-| sib_ram_3 |-'
-- '-----------' '-----------' '-----------' '-----------'
-- .-------.
-- SI -----|sib_mem|-- SO
-- '-------'
-- | |_________________________________________________.
-- | |
-- | .----------. .------------. |
-- '--| sib_data |--------------------->| sib_addr |----'
-- '----------' '------------'
-- | |_____________ | |______________
-- | _____________ | | ______ _______ |
-- '--->| data |-' '->|we,inc|-|address|-'
-- '-------------' '------' '-------'
-- Auto increment bit is MSb in Address shift register
-- .-----------.
-- SI ----| sib_sens |---------------------------------------------- SO
-- '-----------'
-- | |_____________________________________________.
-- | |
-- | .----------. .----------. .----------. .----------. |
-- '-| sib_temp |-| sib_iddt |-| sib_slck |-| sib_volt |-'
-- '----------' '----------' '----------' '----------'
-- .-----------.
-- SI ----| sib_noc |---------------------------------------------- SO
-- '-----------'
-- | |_________________________________.
-- | |
-- | .-------. .-------. .-------. .-------. |
-- '-| sib_0 |-| sib_1 |-| sib_2 |-| sib_3 |-'
-- '-------' '-------' '-------' '-------'
-- | |_________________________________________.
-- | |
-- | .----------. .------------. |
-- '--| sib3 inj |------------->|sib3 status |----'
-- '----------' '------------'
-- | |_____________ | |_____________
-- | _____________ | | _____________ |
-- '--->|injection reg|-' '--->|async adapter|-'
-- '-------------' '-------------'
-- Reset iJTAG chain and Instruments
RST <= '1';
wait for tck_period;
RST <= '0';
SEL <= '1';
tck_tick(4);
reset <= '1';
-- RAM access instrument test
--reset <= '0';
--current_test <= "open_sib_ram ";
--shift_data(fcXN&fcXN&fcXS); -- open sib_ram
---- Test mem0
--current_test <= "open_sib_ram0 ";
--pre_shift(0 to 14) := fcXN&fcXN&fcXS&"0"&"0"&"0";
--pre_shift_len := 15;
--post_shift_len := 0;
--shift_data("1"); -- open sib_ram and sib_ram0: sib_noc & sib_sens & sib_ram & 3xsib_mem
--tck_tick(4);
--test_ram_access;
---- Test mem1
--current_test <= "open_sib_ram1 ";
--pre_shift(0 to 13) := fcXN&fcXN&fcXS&"0"&"0";
--pre_shift_len := 14;
--post_shift(0 to 0) := "0";
--post_shift_len := 1;
--shift_data("1"); -- open sib_ram and sib_ram_1: sib_noc & sib_sens & sib_ram & 4xsib_mem
--tck_tick(4);
--test_ram_access;
---- Test mem2
--current_test <= "open_sib_ram2 ";
--pre_shift(0 to 12) := fcXN&fcXN&fcXS&"0";
--pre_shift_len := 13;
--post_shift(0 to 1) := "00";
--post_shift_len := 2;
--shift_data("1"); -- open sib_ram and sib_ram_2: sib_noc & sib_sens & sib_ram & 4xsib_mem
--tck_tick(4);
--test_ram_access;
---- Test mem2
--current_test <= "open_sib_ram3 ";
--pre_shift(0 to 11) := fcXN&fcXN&fcXS;
--pre_shift_len := 12;
--post_shift(0 to 2) := "000";
--post_shift_len := 3;
--shift_data("1"); -- open sib_ram and sib_ram_3: sib_noc & sib_sens & sib_ram & 4xsib_mem
--tck_tick(4);
--test_ram_access;
--current_test <= "close_sib_ram ";
--pre_shift_len := 0;
--post_shift_len := 0;
--shift_data(fcXN&fcXN&fcXN&"0"&"0"&"0"&"0"); -- close all sibs
---- Release chip reset
--reset <= '1';
wait for 10us;
-- Sensors
--temperature_data(12 downto 1) <= "000000000000";
--temperature_data(0) <= '0';
--current_test <= "open_sib_sens ";
--pre_shift_len := 0;
--post_shift_len := 0;
--shift_data(fcXN&fcXS&fcXN); -- open sib_sens
-- Temperature monitor test
--current_test <= "open_sib_temp ";
--pre_shift(0 to 23) := fcXN&fcXS&fcXN&fcXN&fcXN&fcXS; -- (top)noc, (top)sens, volt, slack, iddt, sib_temp
--pre_shift_len := 24;
--post_shift(0 to 3) := fcXN; --(top)mem
--post_shift_len := 4;
--shift_data(""); --open sib_temp
--current_test <= "shift_temp_setup";
--shift_data("001000000000"&"010000000000"&"0"&"1"&"1"&"01111"); -- shift in threshold H without update
--tck_tick(4);
--current_test <= "temp 1 ";
--temperature_data(12 downto 1) <= "000000000011";
--tck_tick(1);
--temperature_data(0) <= '1';
--tck_tick(1);
--temperature_data(0) <= '0';
--tck_tick(4);
--current_test <= "temp 2 ";
--temperature_data(12 downto 1) <= "000000000100";
--tck_tick(1);
--temperature_data(0) <= '1';
--tck_tick(1);
--temperature_data(0) <= '0';
--tck_tick(4);
--current_test <= "temp 3 ";
--temperature_data(12 downto 1) <= "000000001100";
--tck_tick(1);
--temperature_data(0) <= '1';
--tck_tick(1);
--temperature_data(0) <= '0';
--tck_tick(4);
--current_test <= "shift_temp_setup";
--shift_data("001000000000"&"010000000000"&"0"&"0"&"1"&"01011"); -- shift in threshold H without update
--tck_tick(10);
--current_test <= "close_sib_temp ";
--pre_shift(0 to 23) := fcXN&fcXS&fcXN&fcXN&fcXN&fcXN; -- (top)noc, (top)sens, volt, slack, iddt, temp
--pre_shift_len := 24;
--post_shift(0 to 3) := fcXN; --(top)mem
--post_shift_len := 4;
----shift_data(all_zeroes(32));
--shift_data_with_readout(all_zeroes(32), temp_value_var);
--temp_value <= reverse_vector(temp_value_var);
---- IDDt monitor test
-- current_test <= "open_sib_iddt ";
-- pre_shift(0 to 19) := fcXN&fcXS&fcXN&fcXN&fcXS; -- (top)noc, (top)sens, volt, slack, iddt
-- pre_shift_len := 20;
-- post_shift(0 to 7) := fcXN&fcXN; -- temp, (top)mem
-- post_shift_len := 8;
-- shift_data(""); --open sib_temp
-- current_test <= "close_sib_iddt ";
-- pre_shift(0 to 19) := fcXN&fcXS&fcXN&fcXN&fcXN; -- (top)noc, (top)sens, volt, slack, iddt
-- pre_shift_len := 20;
-- post_shift(0 to 7) := fcXN&fcXN; -- temp, (top)mem
-- post_shift_len := 8;
-- shift_data(all_zeroes(32));
-- Slack monitor test
--current_test <= "open_sib_slack ";
--pre_shift(0 to 15) := fcXN&fcXS&fcXN&fcXS; -- (top)noc, (top)sens, volt, slack
--pre_shift_len := 16;
--post_shift(0 to 11) := fcXN&fcXN&fcXN; -- iddt, temp, (top)mem
--post_shift_len := 12;
--shift_data(""); --open sib_temp
--current_test <= "Slack ";
--shift_data("11100"&"00000"&"0"&"1"&"1"&"0000000000000001111"); -- shift in threshold H without update
--tck_tick(4);
--slack_data <= "00101010101010101010101010101010";
--tck_tick(10);
--slack_data <= "10101010101010101010101010100101";
--tck_tick(4);
--current_test <= "close_sib_slack ";
--pre_shift(0 to 15) := fcXN&fcXS&fcXN&fcXN; -- (top)noc, (top)sens, volt, slack
--pre_shift_len := 16;
--post_shift(0 to 11) := fcXN&fcXN&fcXN; -- iddt, temp, (top)mem
--post_shift_len := 12;
--shift_data_with_readout(all_zeroes(32), slack_value_var);
--slack_value <= reverse_vector(slack_value_var);
--shift_data(all_zeroes(32));
-- Voltage monitor test
--voltage_data <= "00000000000000000000000000000000";
--current_test <= "open_sib_volt ";
--pre_shift(0 to 11) := fcXN&fcXS&fcXS; -- (top)noc, (top)sens, volt
--pre_shift_len := 12;
--post_shift(0 to 15) := fcXN&fcXN&fcXN&fcXN; -- slack, iddt, temp, (top)mem
--post_shift_len := 16;
--shift_data(""); --open sib_temp
--current_test <= "Voltage ";
--shift_data("00001"&"11100"&"1"&"1"&"1"&"0000000000000001111"); -- shift in threshold H without update
--voltage_data <= "00000000000000000000000000000000";
--tck_tick(1);
--voltage_data <= "00000000000000000000000000000001";
--tck_tick(1);
--voltage_data <= "00000000000000000000000000000011";
--tck_tick(1);
--voltage_data <= "00000000000000000000000000000111";
--tck_tick(1);
--voltage_data <= "00000000000000000000000000001111";
--tck_tick(1);
--voltage_data <= "00000000000000000000000000011111";
--tck_tick(1);
--voltage_data <= "00000000000000000000000000111111";
--tck_tick(1);
--voltage_data <= "00000000000000000000000001111111";
--tck_tick(1);
--voltage_data <= "00000000000000000000000011111111";
--tck_tick(1);
--voltage_data <= "00000000000000000000000111111111";
--tck_tick(1);
--voltage_data <= "00000000000000000000001111111111";
--tck_tick(1);
--voltage_data <= "00000000000000000000011111111111";
--tck_tick(1);
--voltage_data <= "00000000000000000000111111111111";
--tck_tick(1);
--voltage_data <= "00000000000000000001111111111111";
--tck_tick(1);
--voltage_data <= "00000000000000000011111111111111";
--tck_tick(1);
--voltage_data <= "00000000000000000111111111111111";
--tck_tick(1);
--voltage_data <= "00000000000000001111111111111111";
--tck_tick(1);
--voltage_data <= "00000000000000011111111111111111";
--tck_tick(1);
--voltage_data <= "00000000000000111111111111111111";
--tck_tick(1);
--voltage_data <= "00000000000001111111111111111111";
--tck_tick(1);
--voltage_data <= "00000000000011111111111111111111";
--tck_tick(1);
--voltage_data <= "00000000000111111111111111111111";
--tck_tick(1);
--voltage_data <= "00000000001111111111111111111111";
--tck_tick(1);
--voltage_data <= "00000000011111111111111111111111";
--tck_tick(1);
--voltage_data <= "00000000111111111111111111111111";
--tck_tick(1);
--voltage_data <= "00000001111111111111111111111111";
--tck_tick(1);
--voltage_data <= "00000011111111111111111111111111";
--tck_tick(1);
--voltage_data <= "00000111111111111111111111111111";
--tck_tick(1);
--voltage_data <= "00001111111111111111111111111111";
--tck_tick(1);
--voltage_data <= "00011111111111111111111111111111";
--tck_tick(1);
--voltage_data <= "00111111111111111111111111111111";
--tck_tick(1);
--voltage_data <= "01111111111111111111111111111111";
--tck_tick(1);
--voltage_data <= "11111111111111111111111111111111";
--tck_tick(10);
--shift_data("11100"&"00001"&"0"&"1"&"1"&"0000000000000001111"); -- shift in threshold H without update
--tck_tick(10);
--voltage_data <= "00000000000000000000000011111111";
--tck_tick(10);
--current_test <= "close_sib_volt ";
--pre_shift(0 to 11) := fcXN&fcXS&fcXN; -- (top)noc, (top)sens, volt
--pre_shift_len := 12;
--post_shift(0 to 15) := fcXN&fcXN&fcXN&fcXN; -- slack, iddt, temp, (top)mem
--post_shift_len := 16;
----shift_data(all_zeroes(32));
--shift_data_with_readout(all_zeroes(32), volt_value_var);
--volt_value <= reverse_vector(volt_value_var);
--current_test <= "close_sib_sens ";
--pre_shift_len := 0;
--post_shift_len := 0;
--shift_data(fcXN&fcXN&fcXN&fcXN&fcXN&fcXN&fcXN); -- close all sibs
-- Router SIBs
current_test <= "open_sib_noc ";
pre_shift_len := 0;
post_shift_len := 0;
shift_data(fcXS&fcXN&fcXN); -- open sib_noc
--Router 0
current_test <= "open_sib_r0 ";
pre_shift(0 to 19) := fcXS&fcXN&fcXN&fcXN&fcXS; -- (top)noc, r3, r2, r1, r0
pre_shift_len := 20;
post_shift(0 to 7) := fcXN&fcXN; -- (top)sens, (top)mem
post_shift_len := 8;
shift_data(""); --open sib_r0
--Router 0 injection
current_test <= "open_sib_r0_inj ";
pre_shift(0 to 27) := fcXS&fcXN&fcXN&fcXN&fcXS&fcXN&fcXS; -- (top)noc, r3, r2, r1, r0, r0_sta, r0_inj
pre_shift_len := 28;
post_shift(0 to 7) := fcXN&fcXN; -- (top)sens, (top)mem
post_shift_len := 8;
shift_data(""); --open sib_r0_inj
current_test <= "r0_inj_arb_out ";
--shift_data(all_zeroes(130));
shift_data("000000000"& "0000001"&"0000001"&"0000001"&"0000001"&"0000001"& "0000000"&"0000000"&"0000000"&"0000000"&"0000000"& "000000000"&"000000000"&"000000000"& "00000000"&"00000000"&"00000000");
current_test <= "close_sib_r0_inj";
pre_shift(0 to 27) := fcXS&fcXN&fcXN&fcXN&fcXS&fcXN&fcXN; -- (top)noc, r3, r2, r1, r0, r0_sta, r0_inj
pre_shift_len := 28;
post_shift(0 to 7) := fcXN&fcXN; -- (top)sens, (top)mem
post_shift_len := 8;
shift_data(all_zeroes(130));
--Router 0 status
current_test <= "open_sib_r0_sta ";
pre_shift(0 to 23) := fcXS&fcXN&fcXN&fcXN&fcXS&fcXS; -- (top)noc, r3, r2, r1, r0, r0_sta
pre_shift_len := 24;
post_shift(0 to 11) := fcXN&fcXN&fcXN; -- r0_inj, (top)sens, (top)mem
post_shift_len := 12;
shift_data(""); --open sib_r0_sta
current_test <= "r0_sta_readout ";
shift_data_with_readout(all_zeroes(25), r0_sta_value_var);
r0_sta_value <= reverse_vector(r0_sta_value_var);
--shift_data(all_zeroes(25));
current_test <= "close_sib_r0_sta";
pre_shift(0 to 23) := fcXS&fcXN&fcXN&fcXN&fcXS&fcXN; -- (top)noc, r3, r2, r1, r0, r0_sta
pre_shift_len := 24;
post_shift(0 to 11) := fcXN&fcXN&fcXN; -- r0_inj, (top)sens, (top)mem
post_shift_len := 12;
shift_data("11111"&all_zeroes(20));
current_test <= "close_sib_r0 ";
pre_shift(0 to 19) := fcXS&fcXN&fcXN&fcXN&fcXN; -- (top)noc, r3, r2, r1, r0
pre_shift_len := 20;
post_shift(0 to 7) := fcXN&fcXN; -- (top)sens, (top)mem
post_shift_len := 8;
shift_data(fcXN&fcXN); -- inj and status sibs of r0
----Router 1
--current_test <= "open_sib_r1 ";
--pre_shift(0 to 15) := fcXS&fcXN&fcXN&fcXS; -- (top)noc, r3, r2, r1
--pre_shift_len := 16;
--post_shift(0 to 11) := fcXN&fcXN&fcXN; -- r0, (top)sens, (top)mem
--post_shift_len := 12;
--shift_data(""); --open sib_r1
----Router 1 injection
--current_test <= "open_sib_r1_inj ";
--pre_shift(0 to 23) := fcXS&fcXN&fcXN&fcXS&fcXN&fcXS; -- (top)noc, r3, r2, r1, r1_sta, r1_inj
--pre_shift_len := 24;
--post_shift(0 to 11) := fcXN&fcXN&fcXN; -- r0, (top)sens, (top)mem
--post_shift_len := 12;
--shift_data(""); --open sib_r1_inj
--current_test <= "r1_inj_arb_out ";
--shift_data(all_zeroes(130));
----shift_data("000000000"& "0000001"&"0000001"&"0000001"&"0000001"&"0000001"& "0000000"&"0000000"&"0000000"&"0000000"&"0000000"& "000000000"&"000000000"&"000000000"& "00000000"&"00000000"&"00000000");
--current_test <= "close_sib_r1_inj";
--pre_shift(0 to 23) := fcXS&fcXN&fcXN&fcXS&fcXN&fcXN; -- (top)noc, r3, r2, r1, r1_sta, r1_inj
--pre_shift_len := 24;
--post_shift(0 to 11) := fcXN&fcXN&fcXN; -- r0, (top)sens, (top)mem
--post_shift_len := 12;
--shift_data(all_zeroes(130));
--current_test <= "close_sib_r1 ";
--pre_shift(0 to 15) := fcXS&fcXN&fcXN&fcXN; -- (top)noc, r3, r2, r1
--pre_shift_len := 16;
--post_shift(0 to 11) := fcXN&fcXN&fcXN; -- r0, (top)sens, (top)mem
--post_shift_len := 12;
--shift_data(fcXN&fcXN); -- inj and status sibs of r1
----Router 2
--current_test <= "open_sib_r2 ";
--pre_shift(0 to 11) := fcXS&fcXN&fcXS; -- (top)noc, r3, r2
--pre_shift_len := 12;
--post_shift(0 to 15) := fcXN&fcXN&fcXN&fcXN; -- r1, r0, (top)sens, (top)mem
--post_shift_len := 16;
--shift_data(""); --open sib_r2
----Router 2 injection
--current_test <= "open_sib_r2_inj ";
--pre_shift(0 to 19) := fcXS&fcXN&fcXS&fcXN&fcXS; -- (top)noc, r3, r2, r2_sta, r2_inj
--pre_shift_len := 20;
--post_shift(0 to 15) := fcXN&fcXN&fcXN&fcXN; -- r1, r0, (top)sens, (top)mem
--post_shift_len := 16;
--shift_data(""); --open sib_r2_inj
--current_test <= "r2_inj_arb_out ";
--shift_data(all_zeroes(130));
----shift_data("000000000"& "0000001"&"0000001"&"0000001"&"0000001"&"0000001"& "0000000"&"0000000"&"0000000"&"0000000"&"0000000"& "000000000"&"000000000"&"000000000"& "00000000"&"00000000"&"00000000");
--current_test <= "close_sib_r2_inj";
--pre_shift(0 to 19) := fcXS&fcXN&fcXS&fcXN&fcXN; -- (top)noc, r3, r2, r2_sta, r2_inj
--pre_shift_len := 20;
--post_shift(0 to 15) := fcXN&fcXN&fcXN&fcXN; -- r1, r0, (top)sens, (top)mem
--post_shift_len := 16;
--shift_data(all_zeroes(130));
--current_test <= "close_sib_r2 ";
--pre_shift(0 to 11) := fcXS&fcXN&fcXN; -- (top)noc, r3, r2
--pre_shift_len := 12;
--post_shift(0 to 15) := fcXN&fcXN&fcXN&fcXN; -- r1, r0, (top)sens, (top)mem
--post_shift_len := 16;
--shift_data(fcXN&fcXN); -- inj and status sibs of r2
----Router 3
--current_test <= "open_sib_r3 ";
--pre_shift(0 to 7) := fcXS&fcXS; -- (top)noc, r3
--pre_shift_len := 8;
--post_shift(0 to 19) := fcXN&fcXN&fcXN&fcXN&fcXN; -- r2, r1, r0, (top)sens, (top)mem
--post_shift_len := 20;
--shift_data(""); --open sib_r3
----Router 2 injection
--current_test <= "open_sib_r3_inj ";
--pre_shift(0 to 15) := fcXS&fcXS&fcXN&fcXS; -- (top)noc, r3, r3_sta, r3_inj
--pre_shift_len := 16;
--post_shift(0 to 19) := fcXN&fcXN&fcXN&fcXN&fcXN; -- r2, r1, r0, (top)sens, (top)mem
--post_shift_len := 20;
--shift_data(""); --open sib_r3_inj
--current_test <= "r3_inj_arb_out ";
--shift_data(all_zeroes(130));
----shift_data("000000000"& "0000001"&"0000001"&"0000001"&"0000001"&"0000001"& "0000000"&"0000000"&"0000000"&"0000000"&"0000000"& "000000000"&"000000000"&"000000000"& "00000000"&"00000000"&"00000000");
--current_test <= "close_sib_r3_inj";
--pre_shift(0 to 15) := fcXS&fcXS&fcXN&fcXN; -- (top)noc, r3, r3_sta, r3_inj
--pre_shift_len := 16;
--post_shift(0 to 19) := fcXN&fcXN&fcXN&fcXN&fcXN; -- r2, r1, r0, (top)sens, (top)mem
--post_shift_len := 20;
--shift_data(all_zeroes(130));
--current_test <= "close_sib_r3 ";
--pre_shift(0 to 7) := fcXS&fcXN; -- (top)noc, r3
--pre_shift_len := 8;
--post_shift(0 to 19) := fcXN&fcXN&fcXN&fcXN&fcXN; -- r2, r1, r0, (top)sens, (top)mem
--post_shift_len := 20;
--shift_data(fcXN&fcXN); -- inj and status sibs of r3
current_test <= "close_sib_noc ";
pre_shift_len := 0;
post_shift_len := 0;
shift_data(fcXN&fcXN&fcXN&fcXN&fcXN&fcXN&fcXN); -- close all sibs
wait;
end process;
end behavior;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated Please do not change!
-- Here are the parameters:
-- network size x:2
-- network size y:2
-- data width:32-- traffic pattern:------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use work.TB_Package.all;
use work.mlite_pack.all;
USE ieee.numeric_std.ALL;
--use IEEE.math_real."ceil";
--use IEEE.math_real."log2";
entity tb_network_2x2 is
end tb_network_2x2;
architecture behavior of tb_network_2x2 is
constant fcXS : std_logic_vector(0 to 3) := "1011";
constant fcXN : std_logic_vector(0 to 3) := "1010";
constant RAMDataSize : positive := 32;
constant RAMAddrSize : positive := 12;
constant path : string(1 to 12) := "Testbenches/"; --uncomment this if you are SIMULATING in MODELSIM, or if you're synthesizing.
-- constant path : string(positive range <>) := "/home/tsotne/ownCloud/git/Bonfire_sim/Bonfire/RTL/Chip_Designs/IMMORTAL_Chip_2017/Testbenches/"; --used only for Vivado similation. Tsotnes PC.
-- Declaring network component
component network_2x2_with_PE is
generic (DATA_WIDTH: integer := 32; DATA_WIDTH_LV: integer := 11);
port (reset: in std_logic;
clk: in std_logic;
-- IJTAG network for fault injection and checker status monitoring
TCK : in std_logic;
RST : in std_logic;
SEL : in std_logic;
SI : in std_logic;
SE : in std_logic;
UE : in std_logic;
CE : in std_logic;
SO : out std_logic;
toF : out std_logic;
toC : out std_logic;
-- GPIO for Node 0
GPIO_out: out std_logic_vector(15 downto 0);
GPIO_in: in std_logic_vector(21 downto 0);
-- UART for all Plasmas
uart_write_0 : out std_logic;
uart_read_0 : in std_logic;
uart_write_1 : out std_logic;
uart_read_1 : in std_logic;
uart_write_2 : out std_logic;
uart_read_2 : in std_logic;
uart_write_3 : out std_logic;
uart_read_3 : in std_logic;
-- Monitor connections
temperature_control : out std_logic_vector(2 downto 0);
-- temperature_data : in std_logic_vector(12 downto 0);
iddt_control : out std_logic_vector(2 downto 0);
-- iddt_data : in std_logic_vector(12 downto 0);
slack_control : out std_logic_vector(2 downto 0);
slack_data : in std_logic_vector(31 downto 0);
voltage_control : out std_logic_vector(2 downto 0);
voltage_data : in std_logic_vector(31 downto 0)
);
end component;
constant clk_period : time := 10 ns;
constant tck_period : time := 35 ns;
constant HALF_SEPARATOR : time := 2*tck_period;
constant FULL_SEPARATOR : time := 8*tck_period;
signal reset, not_reset, clk: std_logic :='0';
signal TCK, RST, SEL, SI, SE, UE, CE, SO, toF, toC : std_logic := '0';
-- GPIO
signal PE_0_GPIO_out : std_logic_vector(15 downto 0);
signal PE_0_GPIO_in : std_logic_vector(21 downto 0) := (others => '1');
signal uart_write_0, uart_write_1, uart_write_2, uart_write_3: std_logic;
signal uart_read_0, uart_read_1, uart_read_2, uart_read_3: std_logic;
signal temperature_control : std_logic_vector(2 downto 0);
signal temperature_data : std_logic_vector(12 downto 0);
signal iddt_control : std_logic_vector(2 downto 0);
signal iddt_data : std_logic_vector(12 downto 0);
signal slack_control : std_logic_vector(2 downto 0);
signal slack_data : std_logic_vector(31 downto 0);
signal voltage_control : std_logic_vector(2 downto 0);
signal voltage_data : std_logic_vector(31 downto 0);
signal current_test : string(1 to 16);
signal RAM_readout: std_logic_vector(RAMDataSize-1 downto 0);
signal r0_sta_value : std_logic_vector (0 to 24);
signal slack_value : std_logic_vector (0 to 31);
signal temp_value : std_logic_vector (0 to 31);
signal volt_value : std_logic_vector (0 to 31);
shared variable pre_shift, post_shift: std_logic_vector(0 to 127);
shared variable pre_shift_len, post_shift_len : natural;
begin
-- instantiating the top module for the network
NoC_top: network_2x2_with_PE generic map (DATA_WIDTH => 32, DATA_WIDTH_LV => 11)
port map (reset, clk,
TCK, RST, SEL, SI, SE, UE, CE, SO, toF, toC,
PE_0_GPIO_out, PE_0_GPIO_in,
uart_write_0, uart_read_0,
uart_write_1, uart_read_1,
uart_write_2, uart_read_2,
uart_write_3, uart_read_3,
temperature_control,
iddt_control,
slack_control, slack_data,
voltage_control, voltage_data
-- temperature_control, temperature_data,
-- iddt_control, iddt_data,
-- slack_control, slack_data,
-- voltage_control, voltage_data
);
-- Added for IJTAG
not_reset <= not reset;
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
ijtag_shift_proc: process
variable read_out_data: std_logic_vector(RAMDataSize-1 downto 0);
variable I, J: integer := 0;
variable stuck_at: std_logic_vector (1 downto 0) := (others => '0');
variable address_fifo: std_logic_vector (5 downto 0) := (others => '0');
variable address_arbiter_out: std_logic_vector (4 downto 0) := (others => '0');
variable address_arbiter_in: std_logic_vector (4 downto 0) := (others => '0');
variable address_arbiter_logic: std_logic_vector (8 downto 0) := (others => '0');
variable address_lbdr: std_logic_vector (6 downto 0) := (others => '0');
-- Generate a number of TCK ticks
procedure tck_tick (number_of_tick : in positive) is
begin
for i in 1 to number_of_tick loop
TCK <= '0';
wait for TCK_period/2;
TCK <= '1';
wait for TCK_period/2;
end loop;
end procedure tck_tick;
procedure tck_halftick_high is
begin
TCK <= '1';
wait for TCK_period/2;
end procedure tck_halftick_high;
procedure tck_halftick_low is
begin
TCK <= '0';
wait for TCK_period/2;
end procedure tck_halftick_low;
-- Shifts in specified data (Capture -> Shift -> Update)
procedure shift_data (data : in std_logic_vector) is
begin
-- Capture phase
CE <= '1';
tck_tick(1);
CE <= '0';
-- Shift phase
SE <= '1';
if pre_shift_len > 0 then
for i in 0 to pre_shift_len-1 loop
SI <= pre_shift(i);
tck_tick(1);
end loop;
end if ;
for i in data'range loop
SI <= data(i);
tck_tick(1);
end loop;
if post_shift_len > 0 then
for i in 0 to post_shift_len-1 loop
SI <= post_shift(i);
tck_tick(1);
end loop;
end if ;
SE <= '0';
-- Update phase
tck_halftick_low;
UE <= '1';
tck_halftick_high;
tck_halftick_low;
UE <= '0';
tck_halftick_high;
end procedure shift_data;
-- Shifts in specified data (Capture -> Shift -> Update)
procedure shift_data_with_readout (data : in std_logic_vector; capture_data : out std_logic_vector) is
begin
--Capture phase
CE <= '1';
tck_tick(1);
CE <= '0';
--Shift phase
SE <= '1';
if pre_shift_len > 0 then
for i in 0 to pre_shift_len-1 loop
SI <= pre_shift(i);
tck_tick(1);
end loop;
end if ;
for i in data'range loop
SI <= data(i);
capture_data(i) := SO;
tck_tick(1);
end loop;
if post_shift_len > 0 then
for i in 0 to post_shift_len-1 loop
SI <= post_shift(i);
tck_tick(1);
end loop;
end if ;
SE <= '0';
-- Update phase
--tck_tick(1);
tck_halftick_low;
UE <= '1';
tck_halftick_high;
tck_halftick_low;
UE <= '0';
tck_halftick_high;
end procedure shift_data_with_readout;
-- Returns all zeroes std_logic_vector of specified size
function all_zeroes (number_of_zeroes : in positive) return std_logic_vector is
variable zero_array : std_logic_vector(0 to number_of_zeroes-1);
begin
for i in zero_array'range loop
zero_array(i) := '0';
end loop;
return zero_array;
end function all_zeroes;
-- Returns all ones std_logic_vector of specified size
function all_ones (number_of_ones : in positive) return std_logic_vector is
variable ones_array : std_logic_vector(0 to number_of_ones-1);
begin
for i in ones_array'range loop
ones_array(i) := '1';
end loop;
return ones_array;
end function all_ones;
function reverse_vector (a: in std_logic_vector) return std_logic_vector is
variable result: std_logic_vector(a'RANGE);
alias aa: std_logic_vector(a'REVERSE_RANGE) is a;
begin
for i in aa'RANGE loop
result(i) := aa(i);
end loop;
return result;
end;
procedure set_ram_address (address : in std_logic_vector(RAMAddrSize-1 downto 0); autoinc : in boolean; write_en : in boolean) is
-- This function should be called in simulation when sib_mem is already opened, but sib_addr and sib_data are still closed
-- After shifting in the provided bit vector, address sib is closed and data sib is opened
constant open_mem_close_addr_sibs : std_logic_vector := "10";
constant open_sib_data : std_logic := '1';
variable autoincrement_bit : std_logic;
variable writeen_bit : std_logic;
variable bitstream_vector : std_logic_vector(0 to RAMAddrSize+4);
begin
if autoinc then
autoincrement_bit := '1';
else
autoincrement_bit := '0';
end if;
if write_en then
writeen_bit := '1';
else
writeen_bit := '0';
end if;
shift_data("11"&"0"); -- open sib_mem and sib_addr and close sib_data
bitstream_vector(0 to 1) := open_mem_close_addr_sibs;
bitstream_vector(2 to RAMAddrSize+1) := reverse_vector(address);
bitstream_vector(RAMAddrSize+2) := autoincrement_bit;
bitstream_vector(RAMAddrSize+3) := writeen_bit;
bitstream_vector(RAMAddrSize+4) := open_sib_data;
shift_data(bitstream_vector);
end procedure set_ram_address;
procedure get_set_data (write_data: in std_logic_vector (RAMDataSize-1 downto 0); read_data: out std_logic_vector (RAMDataSize-1 downto 0); leave_data_sib_open: in boolean) is
-- This function should be called in simulation when sib_mem and sib_data is opened, but sib_addr is closed.
constant open_mem_close_addr_sibs : std_logic_vector := "10";
variable leavedatasibopen_bit : std_logic;
variable read_data_vector : std_logic_vector (RAMDataSize-1 downto 0) := (others => '0');
variable bitstream_vector : std_logic_vector (0 to RAMDataSize+2);
variable readout_vector : std_logic_vector (0 to RAMDataSize+2);
begin
if leave_data_sib_open then
leavedatasibopen_bit := '1';
else
leavedatasibopen_bit := '0';
end if;
tck_tick(3); --otherwise previous data can be captured
bitstream_vector(0 to 1) := open_mem_close_addr_sibs;
bitstream_vector(2) := leavedatasibopen_bit;
bitstream_vector(3 to RAMDataSize+2) := reverse_vector(write_data);
shift_data_with_readout(bitstream_vector, readout_vector);
read_data := reverse_vector(readout_vector(3 to RAMDataSize+2));
end procedure get_set_data;
procedure test_ram_access is
begin
-- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA closed
current_test <= "ram0_addr_003 ";
set_ram_address(X"003", true, true); -- Set WORD address to 0x003, autoincrement on, RAM write on
-- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA open
current_test <= "ram0_write_to_3 ";
get_set_data(X"0AA0F0F0", read_out_data, true); -- Shift in some data to write to address 0x003, increment address and leave SIB_DATA open
-- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA open
current_test <= "ram0_write_to_4 ";
get_set_data(X"0BB0FF00", read_out_data, true); -- Shift in some data to write to address 0x004, increment address and leave SIB_DATA open
-- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA open
current_test <= "ram0_write_to_5C";
get_set_data(X"0CC0F00F", read_out_data, false); -- Shift in some data to write to address 0x005, increment address and close SIB_DATA
-- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA closed
current_test <= "ram0_addr_033 ";
set_ram_address(X"033", true, true); -- Set WORD address to 0x033, autoincrement on, RAM write on
-- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA open
current_test <= "ram0_write_to_33";
get_set_data(X"0000F0F0", read_out_data, true); -- Shift in some data to write to address 0x033, increment address and leave SIB_DATA open
-- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA open
current_test <= "ram0_write_to34C";
get_set_data(X"0000FF00", read_out_data, false); -- Shift in some data to write to address 0x034, increment address and close SIB_DATA
-- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA closed
RAM_readout <= (others => '0');
current_test <= "ram0_addr_003 ";
set_ram_address(X"003", true, false); -- Set WORD address to 0x003, autoincrement off, RAM write off
-- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA open
current_test <= "ram0_read_003 ";
get_set_data(X"00000000", read_out_data, true); -- Shift in some data (no write) and leave SIB_DATA open, possible to read out data from address 0x003
-- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA open
current_test <= "ram0_read_004 ";
get_set_data(X"00000000", read_out_data, false); -- Shift in some data (no write) and close SIB_DATA, possible to read out data from address 0x004
-- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA closed
RAM_readout <= read_out_data; -- put data from word address 0x004
current_test <= "close_sib_mem ";
shift_data("000"); -- close all but sib_ram: sib_noc & sib_sens & 3xsib_mem + opened sib_mem
tck_tick(4);
end procedure test_ram_access;
variable r0_sta_value_var : std_logic_vector (0 to 24);
variable slack_value_var : std_logic_vector (0 to 31);
variable temp_value_var : std_logic_vector (0 to 31);
variable volt_value_var : std_logic_vector (0 to 31);
begin
-- the order of bits in each sib is: SXCF where S is opening bit!
-- to open sib 3 we need to shift the following: "0001"&"0000"&"0000"&"0000"&"0000"
-- * note that the shifting order is oposite!
-- Organization of IJTAG network (top level):
-- .----------. .-----------. .----------.
-- SI ----| sib_ram |---| sib_sens |---| sib_noc |-- SO
-- '----------' '-----------' '----------'
-- | |_________________________________________________.
-- | |
-- | .-----------. .-----------. .-----------. .-----------. |
-- '-| sib_ram_0 |-| sib_ram_1 |-| sib_ram_2 |-| sib_ram_3 |-'
-- '-----------' '-----------' '-----------' '-----------'
-- .-------.
-- SI -----|sib_mem|-- SO
-- '-------'
-- | |_________________________________________________.
-- | |
-- | .----------. .------------. |
-- '--| sib_data |--------------------->| sib_addr |----'
-- '----------' '------------'
-- | |_____________ | |______________
-- | _____________ | | ______ _______ |
-- '--->| data |-' '->|we,inc|-|address|-'
-- '-------------' '------' '-------'
-- Auto increment bit is MSb in Address shift register
-- .-----------.
-- SI ----| sib_sens |---------------------------------------------- SO
-- '-----------'
-- | |_____________________________________________.
-- | |
-- | .----------. .----------. .----------. .----------. |
-- '-| sib_temp |-| sib_iddt |-| sib_slck |-| sib_volt |-'
-- '----------' '----------' '----------' '----------'
-- .-----------.
-- SI ----| sib_noc |---------------------------------------------- SO
-- '-----------'
-- | |_________________________________.
-- | |
-- | .-------. .-------. .-------. .-------. |
-- '-| sib_0 |-| sib_1 |-| sib_2 |-| sib_3 |-'
-- '-------' '-------' '-------' '-------'
-- | |_________________________________________.
-- | |
-- | .----------. .------------. |
-- '--| sib3 inj |------------->|sib3 status |----'
-- '----------' '------------'
-- | |_____________ | |_____________
-- | _____________ | | _____________ |
-- '--->|injection reg|-' '--->|async adapter|-'
-- '-------------' '-------------'
-- Reset iJTAG chain and Instruments
RST <= '1';
wait for tck_period;
RST <= '0';
SEL <= '1';
tck_tick(4);
reset <= '1';
-- RAM access instrument test
--reset <= '0';
--current_test <= "open_sib_ram ";
--shift_data(fcXN&fcXN&fcXS); -- open sib_ram
---- Test mem0
--current_test <= "open_sib_ram0 ";
--pre_shift(0 to 14) := fcXN&fcXN&fcXS&"0"&"0"&"0";
--pre_shift_len := 15;
--post_shift_len := 0;
--shift_data("1"); -- open sib_ram and sib_ram0: sib_noc & sib_sens & sib_ram & 3xsib_mem
--tck_tick(4);
--test_ram_access;
---- Test mem1
--current_test <= "open_sib_ram1 ";
--pre_shift(0 to 13) := fcXN&fcXN&fcXS&"0"&"0";
--pre_shift_len := 14;
--post_shift(0 to 0) := "0";
--post_shift_len := 1;
--shift_data("1"); -- open sib_ram and sib_ram_1: sib_noc & sib_sens & sib_ram & 4xsib_mem
--tck_tick(4);
--test_ram_access;
---- Test mem2
--current_test <= "open_sib_ram2 ";
--pre_shift(0 to 12) := fcXN&fcXN&fcXS&"0";
--pre_shift_len := 13;
--post_shift(0 to 1) := "00";
--post_shift_len := 2;
--shift_data("1"); -- open sib_ram and sib_ram_2: sib_noc & sib_sens & sib_ram & 4xsib_mem
--tck_tick(4);
--test_ram_access;
---- Test mem2
--current_test <= "open_sib_ram3 ";
--pre_shift(0 to 11) := fcXN&fcXN&fcXS;
--pre_shift_len := 12;
--post_shift(0 to 2) := "000";
--post_shift_len := 3;
--shift_data("1"); -- open sib_ram and sib_ram_3: sib_noc & sib_sens & sib_ram & 4xsib_mem
--tck_tick(4);
--test_ram_access;
--current_test <= "close_sib_ram ";
--pre_shift_len := 0;
--post_shift_len := 0;
--shift_data(fcXN&fcXN&fcXN&"0"&"0"&"0"&"0"); -- close all sibs
---- Release chip reset
--reset <= '1';
wait for 10us;
-- Sensors
--temperature_data(12 downto 1) <= "000000000000";
--temperature_data(0) <= '0';
--current_test <= "open_sib_sens ";
--pre_shift_len := 0;
--post_shift_len := 0;
--shift_data(fcXN&fcXS&fcXN); -- open sib_sens
-- Temperature monitor test
--current_test <= "open_sib_temp ";
--pre_shift(0 to 23) := fcXN&fcXS&fcXN&fcXN&fcXN&fcXS; -- (top)noc, (top)sens, volt, slack, iddt, sib_temp
--pre_shift_len := 24;
--post_shift(0 to 3) := fcXN; --(top)mem
--post_shift_len := 4;
--shift_data(""); --open sib_temp
--current_test <= "shift_temp_setup";
--shift_data("001000000000"&"010000000000"&"0"&"1"&"1"&"01111"); -- shift in threshold H without update
--tck_tick(4);
--current_test <= "temp 1 ";
--temperature_data(12 downto 1) <= "000000000011";
--tck_tick(1);
--temperature_data(0) <= '1';
--tck_tick(1);
--temperature_data(0) <= '0';
--tck_tick(4);
--current_test <= "temp 2 ";
--temperature_data(12 downto 1) <= "000000000100";
--tck_tick(1);
--temperature_data(0) <= '1';
--tck_tick(1);
--temperature_data(0) <= '0';
--tck_tick(4);
--current_test <= "temp 3 ";
--temperature_data(12 downto 1) <= "000000001100";
--tck_tick(1);
--temperature_data(0) <= '1';
--tck_tick(1);
--temperature_data(0) <= '0';
--tck_tick(4);
--current_test <= "shift_temp_setup";
--shift_data("001000000000"&"010000000000"&"0"&"0"&"1"&"01011"); -- shift in threshold H without update
--tck_tick(10);
--current_test <= "close_sib_temp ";
--pre_shift(0 to 23) := fcXN&fcXS&fcXN&fcXN&fcXN&fcXN; -- (top)noc, (top)sens, volt, slack, iddt, temp
--pre_shift_len := 24;
--post_shift(0 to 3) := fcXN; --(top)mem
--post_shift_len := 4;
----shift_data(all_zeroes(32));
--shift_data_with_readout(all_zeroes(32), temp_value_var);
--temp_value <= reverse_vector(temp_value_var);
---- IDDt monitor test
-- current_test <= "open_sib_iddt ";
-- pre_shift(0 to 19) := fcXN&fcXS&fcXN&fcXN&fcXS; -- (top)noc, (top)sens, volt, slack, iddt
-- pre_shift_len := 20;
-- post_shift(0 to 7) := fcXN&fcXN; -- temp, (top)mem
-- post_shift_len := 8;
-- shift_data(""); --open sib_temp
-- current_test <= "close_sib_iddt ";
-- pre_shift(0 to 19) := fcXN&fcXS&fcXN&fcXN&fcXN; -- (top)noc, (top)sens, volt, slack, iddt
-- pre_shift_len := 20;
-- post_shift(0 to 7) := fcXN&fcXN; -- temp, (top)mem
-- post_shift_len := 8;
-- shift_data(all_zeroes(32));
-- Slack monitor test
--current_test <= "open_sib_slack ";
--pre_shift(0 to 15) := fcXN&fcXS&fcXN&fcXS; -- (top)noc, (top)sens, volt, slack
--pre_shift_len := 16;
--post_shift(0 to 11) := fcXN&fcXN&fcXN; -- iddt, temp, (top)mem
--post_shift_len := 12;
--shift_data(""); --open sib_temp
--current_test <= "Slack ";
--shift_data("11100"&"00000"&"0"&"1"&"1"&"0000000000000001111"); -- shift in threshold H without update
--tck_tick(4);
--slack_data <= "00101010101010101010101010101010";
--tck_tick(10);
--slack_data <= "10101010101010101010101010100101";
--tck_tick(4);
--current_test <= "close_sib_slack ";
--pre_shift(0 to 15) := fcXN&fcXS&fcXN&fcXN; -- (top)noc, (top)sens, volt, slack
--pre_shift_len := 16;
--post_shift(0 to 11) := fcXN&fcXN&fcXN; -- iddt, temp, (top)mem
--post_shift_len := 12;
--shift_data_with_readout(all_zeroes(32), slack_value_var);
--slack_value <= reverse_vector(slack_value_var);
--shift_data(all_zeroes(32));
-- Voltage monitor test
--voltage_data <= "00000000000000000000000000000000";
--current_test <= "open_sib_volt ";
--pre_shift(0 to 11) := fcXN&fcXS&fcXS; -- (top)noc, (top)sens, volt
--pre_shift_len := 12;
--post_shift(0 to 15) := fcXN&fcXN&fcXN&fcXN; -- slack, iddt, temp, (top)mem
--post_shift_len := 16;
--shift_data(""); --open sib_temp
--current_test <= "Voltage ";
--shift_data("00001"&"11100"&"1"&"1"&"1"&"0000000000000001111"); -- shift in threshold H without update
--voltage_data <= "00000000000000000000000000000000";
--tck_tick(1);
--voltage_data <= "00000000000000000000000000000001";
--tck_tick(1);
--voltage_data <= "00000000000000000000000000000011";
--tck_tick(1);
--voltage_data <= "00000000000000000000000000000111";
--tck_tick(1);
--voltage_data <= "00000000000000000000000000001111";
--tck_tick(1);
--voltage_data <= "00000000000000000000000000011111";
--tck_tick(1);
--voltage_data <= "00000000000000000000000000111111";
--tck_tick(1);
--voltage_data <= "00000000000000000000000001111111";
--tck_tick(1);
--voltage_data <= "00000000000000000000000011111111";
--tck_tick(1);
--voltage_data <= "00000000000000000000000111111111";
--tck_tick(1);
--voltage_data <= "00000000000000000000001111111111";
--tck_tick(1);
--voltage_data <= "00000000000000000000011111111111";
--tck_tick(1);
--voltage_data <= "00000000000000000000111111111111";
--tck_tick(1);
--voltage_data <= "00000000000000000001111111111111";
--tck_tick(1);
--voltage_data <= "00000000000000000011111111111111";
--tck_tick(1);
--voltage_data <= "00000000000000000111111111111111";
--tck_tick(1);
--voltage_data <= "00000000000000001111111111111111";
--tck_tick(1);
--voltage_data <= "00000000000000011111111111111111";
--tck_tick(1);
--voltage_data <= "00000000000000111111111111111111";
--tck_tick(1);
--voltage_data <= "00000000000001111111111111111111";
--tck_tick(1);
--voltage_data <= "00000000000011111111111111111111";
--tck_tick(1);
--voltage_data <= "00000000000111111111111111111111";
--tck_tick(1);
--voltage_data <= "00000000001111111111111111111111";
--tck_tick(1);
--voltage_data <= "00000000011111111111111111111111";
--tck_tick(1);
--voltage_data <= "00000000111111111111111111111111";
--tck_tick(1);
--voltage_data <= "00000001111111111111111111111111";
--tck_tick(1);
--voltage_data <= "00000011111111111111111111111111";
--tck_tick(1);
--voltage_data <= "00000111111111111111111111111111";
--tck_tick(1);
--voltage_data <= "00001111111111111111111111111111";
--tck_tick(1);
--voltage_data <= "00011111111111111111111111111111";
--tck_tick(1);
--voltage_data <= "00111111111111111111111111111111";
--tck_tick(1);
--voltage_data <= "01111111111111111111111111111111";
--tck_tick(1);
--voltage_data <= "11111111111111111111111111111111";
--tck_tick(10);
--shift_data("11100"&"00001"&"0"&"1"&"1"&"0000000000000001111"); -- shift in threshold H without update
--tck_tick(10);
--voltage_data <= "00000000000000000000000011111111";
--tck_tick(10);
--current_test <= "close_sib_volt ";
--pre_shift(0 to 11) := fcXN&fcXS&fcXN; -- (top)noc, (top)sens, volt
--pre_shift_len := 12;
--post_shift(0 to 15) := fcXN&fcXN&fcXN&fcXN; -- slack, iddt, temp, (top)mem
--post_shift_len := 16;
----shift_data(all_zeroes(32));
--shift_data_with_readout(all_zeroes(32), volt_value_var);
--volt_value <= reverse_vector(volt_value_var);
--current_test <= "close_sib_sens ";
--pre_shift_len := 0;
--post_shift_len := 0;
--shift_data(fcXN&fcXN&fcXN&fcXN&fcXN&fcXN&fcXN); -- close all sibs
-- Router SIBs
current_test <= "open_sib_noc ";
pre_shift_len := 0;
post_shift_len := 0;
shift_data(fcXS&fcXN&fcXN); -- open sib_noc
--Router 0
current_test <= "open_sib_r0 ";
pre_shift(0 to 19) := fcXS&fcXN&fcXN&fcXN&fcXS; -- (top)noc, r3, r2, r1, r0
pre_shift_len := 20;
post_shift(0 to 7) := fcXN&fcXN; -- (top)sens, (top)mem
post_shift_len := 8;
shift_data(""); --open sib_r0
--Router 0 injection
current_test <= "open_sib_r0_inj ";
pre_shift(0 to 27) := fcXS&fcXN&fcXN&fcXN&fcXS&fcXN&fcXS; -- (top)noc, r3, r2, r1, r0, r0_sta, r0_inj
pre_shift_len := 28;
post_shift(0 to 7) := fcXN&fcXN; -- (top)sens, (top)mem
post_shift_len := 8;
shift_data(""); --open sib_r0_inj
current_test <= "r0_inj_arb_out ";
--shift_data(all_zeroes(130));
shift_data("000000000"& "0000001"&"0000001"&"0000001"&"0000001"&"0000001"& "0000000"&"0000000"&"0000000"&"0000000"&"0000000"& "000000000"&"000000000"&"000000000"& "00000000"&"00000000"&"00000000");
current_test <= "close_sib_r0_inj";
pre_shift(0 to 27) := fcXS&fcXN&fcXN&fcXN&fcXS&fcXN&fcXN; -- (top)noc, r3, r2, r1, r0, r0_sta, r0_inj
pre_shift_len := 28;
post_shift(0 to 7) := fcXN&fcXN; -- (top)sens, (top)mem
post_shift_len := 8;
shift_data(all_zeroes(130));
--Router 0 status
current_test <= "open_sib_r0_sta ";
pre_shift(0 to 23) := fcXS&fcXN&fcXN&fcXN&fcXS&fcXS; -- (top)noc, r3, r2, r1, r0, r0_sta
pre_shift_len := 24;
post_shift(0 to 11) := fcXN&fcXN&fcXN; -- r0_inj, (top)sens, (top)mem
post_shift_len := 12;
shift_data(""); --open sib_r0_sta
current_test <= "r0_sta_readout ";
shift_data_with_readout(all_zeroes(25), r0_sta_value_var);
r0_sta_value <= reverse_vector(r0_sta_value_var);
--shift_data(all_zeroes(25));
current_test <= "close_sib_r0_sta";
pre_shift(0 to 23) := fcXS&fcXN&fcXN&fcXN&fcXS&fcXN; -- (top)noc, r3, r2, r1, r0, r0_sta
pre_shift_len := 24;
post_shift(0 to 11) := fcXN&fcXN&fcXN; -- r0_inj, (top)sens, (top)mem
post_shift_len := 12;
shift_data("11111"&all_zeroes(20));
current_test <= "close_sib_r0 ";
pre_shift(0 to 19) := fcXS&fcXN&fcXN&fcXN&fcXN; -- (top)noc, r3, r2, r1, r0
pre_shift_len := 20;
post_shift(0 to 7) := fcXN&fcXN; -- (top)sens, (top)mem
post_shift_len := 8;
shift_data(fcXN&fcXN); -- inj and status sibs of r0
----Router 1
--current_test <= "open_sib_r1 ";
--pre_shift(0 to 15) := fcXS&fcXN&fcXN&fcXS; -- (top)noc, r3, r2, r1
--pre_shift_len := 16;
--post_shift(0 to 11) := fcXN&fcXN&fcXN; -- r0, (top)sens, (top)mem
--post_shift_len := 12;
--shift_data(""); --open sib_r1
----Router 1 injection
--current_test <= "open_sib_r1_inj ";
--pre_shift(0 to 23) := fcXS&fcXN&fcXN&fcXS&fcXN&fcXS; -- (top)noc, r3, r2, r1, r1_sta, r1_inj
--pre_shift_len := 24;
--post_shift(0 to 11) := fcXN&fcXN&fcXN; -- r0, (top)sens, (top)mem
--post_shift_len := 12;
--shift_data(""); --open sib_r1_inj
--current_test <= "r1_inj_arb_out ";
--shift_data(all_zeroes(130));
----shift_data("000000000"& "0000001"&"0000001"&"0000001"&"0000001"&"0000001"& "0000000"&"0000000"&"0000000"&"0000000"&"0000000"& "000000000"&"000000000"&"000000000"& "00000000"&"00000000"&"00000000");
--current_test <= "close_sib_r1_inj";
--pre_shift(0 to 23) := fcXS&fcXN&fcXN&fcXS&fcXN&fcXN; -- (top)noc, r3, r2, r1, r1_sta, r1_inj
--pre_shift_len := 24;
--post_shift(0 to 11) := fcXN&fcXN&fcXN; -- r0, (top)sens, (top)mem
--post_shift_len := 12;
--shift_data(all_zeroes(130));
--current_test <= "close_sib_r1 ";
--pre_shift(0 to 15) := fcXS&fcXN&fcXN&fcXN; -- (top)noc, r3, r2, r1
--pre_shift_len := 16;
--post_shift(0 to 11) := fcXN&fcXN&fcXN; -- r0, (top)sens, (top)mem
--post_shift_len := 12;
--shift_data(fcXN&fcXN); -- inj and status sibs of r1
----Router 2
--current_test <= "open_sib_r2 ";
--pre_shift(0 to 11) := fcXS&fcXN&fcXS; -- (top)noc, r3, r2
--pre_shift_len := 12;
--post_shift(0 to 15) := fcXN&fcXN&fcXN&fcXN; -- r1, r0, (top)sens, (top)mem
--post_shift_len := 16;
--shift_data(""); --open sib_r2
----Router 2 injection
--current_test <= "open_sib_r2_inj ";
--pre_shift(0 to 19) := fcXS&fcXN&fcXS&fcXN&fcXS; -- (top)noc, r3, r2, r2_sta, r2_inj
--pre_shift_len := 20;
--post_shift(0 to 15) := fcXN&fcXN&fcXN&fcXN; -- r1, r0, (top)sens, (top)mem
--post_shift_len := 16;
--shift_data(""); --open sib_r2_inj
--current_test <= "r2_inj_arb_out ";
--shift_data(all_zeroes(130));
----shift_data("000000000"& "0000001"&"0000001"&"0000001"&"0000001"&"0000001"& "0000000"&"0000000"&"0000000"&"0000000"&"0000000"& "000000000"&"000000000"&"000000000"& "00000000"&"00000000"&"00000000");
--current_test <= "close_sib_r2_inj";
--pre_shift(0 to 19) := fcXS&fcXN&fcXS&fcXN&fcXN; -- (top)noc, r3, r2, r2_sta, r2_inj
--pre_shift_len := 20;
--post_shift(0 to 15) := fcXN&fcXN&fcXN&fcXN; -- r1, r0, (top)sens, (top)mem
--post_shift_len := 16;
--shift_data(all_zeroes(130));
--current_test <= "close_sib_r2 ";
--pre_shift(0 to 11) := fcXS&fcXN&fcXN; -- (top)noc, r3, r2
--pre_shift_len := 12;
--post_shift(0 to 15) := fcXN&fcXN&fcXN&fcXN; -- r1, r0, (top)sens, (top)mem
--post_shift_len := 16;
--shift_data(fcXN&fcXN); -- inj and status sibs of r2
----Router 3
--current_test <= "open_sib_r3 ";
--pre_shift(0 to 7) := fcXS&fcXS; -- (top)noc, r3
--pre_shift_len := 8;
--post_shift(0 to 19) := fcXN&fcXN&fcXN&fcXN&fcXN; -- r2, r1, r0, (top)sens, (top)mem
--post_shift_len := 20;
--shift_data(""); --open sib_r3
----Router 2 injection
--current_test <= "open_sib_r3_inj ";
--pre_shift(0 to 15) := fcXS&fcXS&fcXN&fcXS; -- (top)noc, r3, r3_sta, r3_inj
--pre_shift_len := 16;
--post_shift(0 to 19) := fcXN&fcXN&fcXN&fcXN&fcXN; -- r2, r1, r0, (top)sens, (top)mem
--post_shift_len := 20;
--shift_data(""); --open sib_r3_inj
--current_test <= "r3_inj_arb_out ";
--shift_data(all_zeroes(130));
----shift_data("000000000"& "0000001"&"0000001"&"0000001"&"0000001"&"0000001"& "0000000"&"0000000"&"0000000"&"0000000"&"0000000"& "000000000"&"000000000"&"000000000"& "00000000"&"00000000"&"00000000");
--current_test <= "close_sib_r3_inj";
--pre_shift(0 to 15) := fcXS&fcXS&fcXN&fcXN; -- (top)noc, r3, r3_sta, r3_inj
--pre_shift_len := 16;
--post_shift(0 to 19) := fcXN&fcXN&fcXN&fcXN&fcXN; -- r2, r1, r0, (top)sens, (top)mem
--post_shift_len := 20;
--shift_data(all_zeroes(130));
--current_test <= "close_sib_r3 ";
--pre_shift(0 to 7) := fcXS&fcXN; -- (top)noc, r3
--pre_shift_len := 8;
--post_shift(0 to 19) := fcXN&fcXN&fcXN&fcXN&fcXN; -- r2, r1, r0, (top)sens, (top)mem
--post_shift_len := 20;
--shift_data(fcXN&fcXN); -- inj and status sibs of r3
current_test <= "close_sib_noc ";
pre_shift_len := 0;
post_shift_len := 0;
shift_data(fcXN&fcXN&fcXN&fcXN&fcXN&fcXN&fcXN); -- close all sibs
wait;
end process;
end behavior;
|
-- $Id: sys_tst_snhumanio_n2.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_snhumanio_n2 - syn
-- Description: snhumanio tester design for nexys2
--
-- Dependencies: vlib/genlib/clkdivce
-- bplib/bpgen/sn_humanio
-- tst_snhumanio
-- vlib/nxcramlib/nx_cram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-09-17 410 13.1 O40d xc3s1200e-4 149 207 - 144 t 10.2
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 remove clksys output hack
-- 2011-11-26 433 1.0.3 use nx_cram_dummy now
-- 2011-11-23 432 1.0.3 update O_FLA_CE_N usage
-- 2011-10-25 419 1.0.2 get entity name right...
-- 2011-09-17 410 1.0 Initial version
------------------------------------------------------------------------------
-- Usage of Nexys 2 Switches, Buttons, LEDs:
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_snhumanio_n2 is -- top level
-- implements nexys2_aif
port (
I_CLK50 : in slbit; -- 50 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit -- flash ce.. (act.low)
);
end sys_tst_snhumanio_n2;
architecture syn of sys_tst_snhumanio_n2 is
signal CLK : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RESET : slbit := '0';
signal CE_MSEC : slbit := '0';
begin
RESET <= '0'; -- so far not used
CLK <= I_CLK50;
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => 50,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => open,
CE_MSEC => CE_MSEC
);
HIO : sn_humanio
generic map (
BWIDTH => 4,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
HIOTEST : entity work.tst_snhumanio
generic map (
BWIDTH => 4)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
O_TXD <= I_RXD;
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
end syn;
|
entity test is
subtype t is foo(bar)(open);
end;
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.15:30:58)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY fir1_wsga_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18, input19, input20, input21, input22: IN unsigned(0 TO 3);
output1: OUT unsigned(0 TO 4));
END fir1_wsga_entity;
ARCHITECTURE fir1_wsga_description OF fir1_wsga_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register9: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register10: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register11: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 and input1;
register2 := input2 and input2;
register3 := input3 and input3;
register4 := input4 and input4;
WHEN "00000010" =>
register5 := input5 and input5;
register6 := input6 and input6;
register7 := input7 and input7;
register1 := register1 * register4;
register4 := input8 and input8;
register2 := register3 * register2;
WHEN "00000011" =>
register3 := register6 * register4;
register4 := input9 and input9;
register6 := input10 and input10;
register5 := register7 * register5;
register7 := input11 and input11;
WHEN "00000100" =>
register6 := register6 * register7;
register7 := input12 and input12;
WHEN "00000101" =>
register4 := register4 * register7;
register3 := register6 + register3;
WHEN "00000110" =>
register2 := register3 + register2;
register3 := input13 and input13;
register6 := input14 and input14;
register7 := input15 and input15;
register8 := input16 and input16;
WHEN "00000111" =>
register3 := register8 * register3;
register8 := input17 and input17;
register9 := input18 and input18;
register10 := input19 and input19;
register11 := input20 and input20;
register1 := register1 + register2;
WHEN "00001000" =>
register2 := input21 and input21;
register6 := register10 * register6;
register9 := register11 * register9;
register7 := register8 * register7;
WHEN "00001001" =>
register5 := register5 + register9;
register8 := input22 and input22;
register6 := register7 + register6;
WHEN "00001010" =>
register1 := register6 + register1;
WHEN "00001011" =>
register1 := register1 + register4;
register2 := register2 * register8;
WHEN "00001100" =>
register1 := register5 + register1;
WHEN "00001101" =>
register1 := register1 + register2;
WHEN "00001110" =>
register1 := register3 + register1;
WHEN "00001111" =>
output1 <= register1 and register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END fir1_wsga_description; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library lib;
use lib.controller.all;
use lib.general.all;
use lib.io.all;
entity spaceinvaders is
generic
(
rx : integer := 160; -- H resolution
ry : integer := 120; -- W resolution
cpu_num : integer := ALIENS_PER_LINE; -- aliens per line (set in io.vhd)
cpu_lines : integer := ALIEN_LINES; -- number of lines (set in io.vhd)
py : integer := 110; --
alien_w : integer := 11; -- enemy width
alien_h : integer := 8; -- enemy height
player_w : integer := 13; -- player width
player_h : integer := 6 -- player height
);
port
(
------------------------ Clock Input ------------------------
CLOCK_24 : in STD_LOGIC_VECTOR (1 downto 0); -- 24 MHz
CLOCK_50 : in STD_LOGIC; -- 50 MHz
CLOCK_27 : in STD_LOGIC; -- 27 MHz
------------------------ Push Button ------------------------
KEY : in STD_LOGIC_VECTOR (3 downto 0); -- Pushbutton[3:0]
------------------------ 7-SEG Display ------------------------
HEX0 : out STD_LOGIC_VECTOR (6 downto 0);
HEX1 : out STD_LOGIC_VECTOR (6 downto 0);
HEX2 : out STD_LOGIC_VECTOR (6 downto 0);
HEX3 : out STD_LOGIC_VECTOR (6 downto 0);
---------------------------- LED ----------------------------
LEDG : out STD_LOGIC_VECTOR (7 downto 0); -- LED Green[7:0]
------------------------ PS2 --------------------------------
PS2_DAT : inout STD_LOGIC; -- PS2 Data
PS2_CLK : inout STD_LOGIC; -- PS2 Clock
------------------------ VGA --------------------------------
VGA_R, VGA_G, VGA_B : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
VGA_HS, VGA_VS : OUT STD_LOGIC
);
end entity;
architecture Behavior of spaceinvaders is
--------------------------- CLK/RESET ------------------------------
signal clock_s,reset_s,reset: std_logic;
SIGNAL state : GAME_STATE;
------------------------ PLAYER ----------------------------
signal move_s,shot_s,shot_e_s: std_logic;
signal controls: std_logic_vector(2 downto 0);
signal position_x_s: integer range 0 to rx;
signal position_y_s: integer range 0 to ry;
signal shot_y_s: integer range 0 to ry;
signal shot_x_s: integer range 0 to rx;
signal shot_r_s: std_logic;
------------------------ CPU --------------------------------
signal cpu_arr_x: pos_arr_xt;
signal cpu_arr_y: pos_arr_yt;
signal cpu_arr_e: std_logic_vector(cpu_num*cpu_lines-1 downto 0);
signal cpu_arr_c: std_logic_vector(cpu_num*cpu_lines-1 downto 0);
signal cpu_arr_m: std_logic_vector(cpu_num*cpu_lines-1 downto 0);
signal cpu_arr_d: std_logic_vector(cpu_num*cpu_lines-1 downto 0);
signal cpu_game_over: std_logic_vector(cpu_num*cpu_lines-1 downto 0);
signal turn: std_logic;
signal shot_enemy_y_s: integer range 0 to ry;
signal shot_enemy_x_s: integer range 0 to rx;
signal shot_enemy_e_s: std_logic;
signal shot_enemy_r_s: std_logic;
signal enemy_shooting: std_logic;
signal clk_enemy_shoot: std_logic;
signal player_death, player_reset : std_logic;
signal player_death_by_alien : std_logic;
signal player_exploding,pc_dead_delay : std_logic;
type PC_STATE_TYPE is (ALIVE, EXPLODING, DEAD);
signal pc_state : PC_STATE_TYPE;
signal game_over,game_over_by_lives : std_logic;
signal game_win : std_logic;
------------------------ HEX --------------------------------
signal hex_s: std_logic_vector(27 downto 0);
signal rnd_s,cmb_s: integer;
signal choosen_enemy : integer;
type hex_arr_t is array(cpu_num-1 downto 0) of std_logic_vector(6 downto 0);
signal hex0_arr,hex1_arr,hex2_arr,hex3_arr: hex_arr_t;
signal lives : natural range 0 to 4 := 4;
begin
----------------------------------------------------------------
-- Game reset
----------------------------------------------------------------
reset <= not(KEY(0)); -- Push Button 0
----------------------------------------------------------------
----------------------------------------------------------------
-- Keyboard control
----------------------------------------------------------------
control: kbd_input
port map
( CLOCK_24(0), not(reset_s), KEY(1), PS2_DAT, PS2_CLK, SHOT_S, MOVE_S, CONTROLS );
----------------------------------------------------------------
----------------------------------------------------------------
-- VGA
----------------------------------------------------------------
vga: vga_module
generic map (
rx,
ry,
cpu_num*cpu_lines
)
port map
(
CLOCK_27, NOT(reset),
state,
POSITION_X_S,
POSITION_Y_S,
player_exploding,
SHOT_X_S,
SHOT_Y_S,
shot_enemy_x_s,
shot_enemy_y_s,
cpu_arr_e,
cpu_arr_d,
cpu_arr_x,
cpu_arr_y,
VGA_R, VGA_G, VGA_B, VGA_HS, VGA_VS
);
----------------------------------------------------------------
----------------------------------------------------------------
-- Player
----------------------------------------------------------------
-- Player controller
player: pc
generic map
(
clock_div => 1000000,
res_x=>rx,
res_y=>ry,
aux_x=>player_w,
aux_y=>player_h,
pos_y=>py
)
port map
( reset_s OR player_reset, move_s and not(player_exploding), controls(0), CLOCK_50, clock_s, position_x_s, position_y_s);
-- Player shot
pc_shooter: shot
generic map
(
clock_div => 500000,
res_x=>rx,
res_y=>ry,
aux_x=>player_w,
aux_y=>player_h
)
port map
(CLOCK_50, reset_s or shot_r_s, shot_s and not(player_exploding), position_x_s, position_y_s,shot_e_s,shot_x_s,shot_y_s);
-- Player dead sprite
pc_delay: clock_counter
generic map ( 18000000 )
port map ( CLOCK_27, pc_dead_delay );
process (pc_dead_delay)
begin
if reset_s = '1' or player_reset = '1' then
player_exploding <= '0';
player_reset <= '0';
pc_state <= ALIVE;
elsif player_death = '1' then
player_exploding <= '1';
pc_state <= EXPLODING;
elsif rising_edge(pc_dead_delay) then
case pc_state is
when ALIVE =>
when EXPLODING =>
pc_state <= DEAD;
when DEAD =>
player_reset <= '1';
player_exploding <= '0';
end case;
end if;
end process;
----------------------------------------------------------------
----------------------------------------------------------------
-- Aliens generator
----------------------------------------------------------------
-- Verify if any enemy reached one of the sides
turn <= '0' when cpu_arr_m = (cpu_arr_m'range => '0') else '1';
-- Generate enemies
generate_cpu:
for i in 0 to (cpu_num*cpu_lines-1) generate
cpu_x: cpu
generic map
(
res_x => rx,
res_y => ry,
pos_x => 15+(18*(i mod cpu_num)),
pos_y => 15+10*(i/cpu_num),
aux_x => alien_w,
aux_y => alien_h,
clock_div => 18000000 -- 18000000
)
port map
(reset_s,cpu_arr_c(i),CLOCK_50,turn,cpu_arr_m(i),cpu_arr_e(i),cpu_arr_x(i),cpu_arr_y(i),cpu_arr_d(i),cpu_game_over(i));
collision_x: collisor
generic map
( res_x=>rx,
res_y=>ry,
w=>alien_w,
h=>alien_h,
clock_div=>100
)
port map
(CLOCK_27, cpu_arr_e(i) and shot_e_s, shot_x_s,cpu_arr_x(i),shot_y_s,cpu_arr_y(i),cpu_arr_c(i));
end generate;
----------------------------------------------------------------
----------------------------------------------------------------
-- ALIEN SHOOTER
----------------------------------------------------------------
enemy_shot_clock: clock_counter
generic map ( 27000000 )
port map ( CLOCK_27, clk_enemy_shoot );
-- Randomly select an alive enemy to shoot
PROCESS (clk_enemy_shoot)
BEGIN
if rising_edge(clk_enemy_shoot) then
choosen_enemy <= rnd_s;
enemy_shooting <= cpu_arr_e(choosen_enemy);
end if;
end process;
cpu_x_shooter: shot
generic map
(
clock_div => 1000000, -- 2500000
res_x=>rx,
res_y=>ry,
aux_x=>alien_w,
aux_y=>0,
flag_up=>'0'
)
port map
(CLOCK_50, reset_s OR shot_enemy_r_s, enemy_shooting, cpu_arr_x(choosen_enemy), cpu_arr_y(choosen_enemy),shot_enemy_e_s,shot_enemy_x_s,shot_enemy_y_s);
-- ALIEN SHOOT COLLISION WITH PLAYER
collision_x: collisor
generic map
( res_x=>rx,
res_y=>ry,
w=>player_w,
h=>player_h,
clock_div=>100
)
port map
(CLOCK_27, shot_enemy_e_s, shot_enemy_x_s, position_x_s, shot_enemy_y_s, position_y_s, shot_enemy_r_s);
shot_r_s <= '0' when cpu_arr_c = (cpu_arr_c'range => '0') else '1';
----------------------------------------------------------------
----------------------------------------------------------------
-- GAME STATE MACHINE
----------------------------------------------------------------
spaceinvaders_fsm:
PROCESS (reset,CLOCK_27)
BEGIN
IF reset = '1' THEN
reset_s <= '1';
state <= START;
ELSIF rising_edge(CLOCK_27) THEN
CASE state IS
WHEN START =>
reset_s <= '0';
IF controls(1) = '1' THEN
reset_s <= '1';
state <= PLAYING;
END IF;
WHEN PLAYING =>
reset_s <= '0';
IF game_over = '1' THEN
state <= GAME_OVER_STATE;
ELSIF game_win = '1' THEN
state <= WIN;
END IF;
WHEN GAME_OVER_STATE | WIN =>
IF controls(1) = '1' THEN
reset_s <= '1';
state <= PLAYING;
END IF;
END CASE;
END IF;
END PROCESS;
----------------------------------------------------------------
----------------------------------------------------------------
-- Live system
----------------------------------------------------------------
-- Death verification
player_death_by_alien <= '0' when cpu_game_over = (cpu_game_over'range => '0') else '1';
player_death <= shot_enemy_r_s;
-- lives: asynchronous reverse counter
process (player_death, reset_s)
begin
if reset_s = '1' then
lives <= 4;
elsif rising_edge(player_death) then
lives <= lives - 1;
end if;
end process;
-- Game win verification
game_win <= '1' when cpu_arr_e = (cpu_arr_e'range => '0') else '0';
-- Game over verification
game_over_by_lives <= '1' when lives = 0 else '0'; -- game over when lives = 0
game_over <= (player_death_by_alien OR game_over_by_lives) and not (player_exploding); -- game over when aliens reach player
-- Lives counter (shown in LEDS)
with lives select
LEDG(0) <= '0' when 0 | 1,
'1' when others;
with lives select
LEDG(1) <= '0' when 0 | 1 | 2,
'1' when others;
with lives select
LEDG(2) <= '1' when 4,
'0' when others;
----------------------------------------------------------------
----------------------------------------------------------------
-- Random number generator
----------------------------------------------------------------
rnd: random_gen
generic map ( cpu_num*cpu_lines )
port map ( clk_enemy_shoot, clock_50, rnd_s);
----------------------------------------------------------------
-- Score system
----------------------------------------------------------------
show_score: score
port map(shot_r_s, reset_s, hex_s); -- shot_r_s as clock
HEX0 <= hex_s(6 downto 0);
HEX1 <= hex_s(13 downto 7);
HEX2 <= hex_s(20 downto 14);
HEX3 <= hex_s(27 downto 21);
----------------------------------------------------------------
end architecture; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:17:25 02/11/2015
-- Design Name:
-- Module Name: aaatop - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
----------------------------------------------------------------------------------
-- LED example, by Jerome Cornet
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity Aaatop is
Port (
CLK,reset : in STD_LOGIC;
txd : inout std_logic;
rxd : in std_logic;
ARD_RESET : out STD_LOGIC;
DUO_SW1 : in STD_LOGIC;
-- DUO_LED : out std_logic;
sram_addr : out std_logic_vector(20 downto 0);
sram_data : inout std_logic_vector(7 downto 0);
sram_ce : out std_logic;
sram_we : out std_logic;
sram_oe : out std_logic;
W1A : inout STD_LOGIC_VECTOR (7 downto 0);
W1B : inout STD_LOGIC_VECTOR (7 downto 0);
W2C : inout STD_LOGIC_VECTOR (15 downto 0);
W2D : inout STD_LOGIC_VECTOR (15 downto 0);
Arduino : inout STD_LOGIC_VECTOR (21 downto 0)
-- Arduino : inout STD_LOGIC_VECTOR (53 downto 0)
);
end Aaatop;
architecture Behavioral of Aaatop is
signal CLOCK_40MHZ : std_logic;
signal CTS : std_logic := '1';
signal PIN3 : std_logic;
signal LED1 : std_logic;
signal LED2N : std_logic;
signal LED3N : std_logic;
signal PIN4 : std_logic;
signal RTS : std_logic;
signal SD_MISO : std_logic;
signal SD_MOSI : std_logic;
signal SD_SCK : std_logic;
signal SD_nCS : std_logic;
signal buttons : std_logic_vector(5 downto 0);
signal audio_left : STD_LOGIC;
signal audio_right : STD_LOGIC;
signal ud : STD_LOGIC;
signal rl : STD_LOGIC;
signal enab : STD_LOGIC;
signal vsync : STD_LOGIC;
signal hsync : STD_LOGIC;
signal ck : STD_LOGIC;
signal r : std_logic_vector(5 downto 0);
signal g : std_logic_vector(5 downto 0);
signal b : std_logic_vector(5 downto 0);
signal vramaddr : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal vramdata : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal spi_clk : std_logic := '1';
signal spi_csn : std_logic := '1';
signal spi_mosi : std_logic := '1';
signal spi_miso : std_logic := '1';
signal buttons2 : STD_LOGIC_VECTOR (3 downto 0);
signal leds : STD_LOGIC_VECTOR (3 downto 0);
component clk32to40
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end component;
begin
ARD_RESET <= not(DUO_SW1);
CTS <= '1';
-- PIN3 <= not Arduino(40); -- por
-- PIN3 <= reset; -- por
PIN3 <= '1'; -- por
-- Arduino(38) <= Arduino(40);
-- Arduino(42) <= Arduino(44);
-- Arduino(46) <= Arduino(48);
-- Arduino(50) <= Arduino(52);
-- Arduino(38) <= LED1;
-- Arduino(42) <= LED2N;
-- Arduino(46) <= LED3N;
-- Arduino(50) <= '0';
-- sram_addr <= (others => '0');
-- sram_ce <= '0';
-- sram_we <= '0';
-- sram_oe <= '0';
drigmorn1_top0 : entity work.drigmorn1_top
PORT map(
sram_addr => sram_addr,
sram_data => sram_data,
sram_ce => sram_ce,
sram_we => sram_we,
sram_oe => sram_oe,
vramaddr => vramaddr,
vramdata => vramdata,
spi_cs => spi_csn,
spi_clk => spi_clk,
spi_mosi => spi_mosi,
spi_miso => spi_miso,
buttons => buttons2,
leds => leds,
CLOCK_40MHZ => CLOCK_40MHZ,
CTS => CTS,
PIN3 => PIN3,
RXD => RXD,
LED1 => LED1,
LED2N => LED2N,
LED3N => LED3N,
PIN4 => PIN4,
RTS => RTS,
TXD => TXD
);
dcm0: clk32to40
port map
(-- Clock in ports
CLK_IN1 => clk,
-- Clock out ports
CLK_OUT1 => CLOCK_40MHZ);
winglcd0 : entity work.winglcdsndbut Port map(
W1A => w2c,
W1B => w2d,
buttons => buttons,
audio_left => audio_left,
audio_right => audio_right,
ud => ud,
rl => rl,
enab => enab,
vsync => vsync,
hsync => hsync,
ck => ck,
r => r,
g => g,
b => b
);
w1a(0) <= vsync;
w1a(5) <= hsync;
w1a(7) <= r(0);
lcdctl0 : entity work.lcdctl Port map(
clk => CLOCK_40MHZ,
-- clk => clk,
reset=>reset,
vramaddr => vramaddr,
vramdata => vramdata,
ud => ud,
rl => rl,
enab => enab,
vsync => vsync,
hsync => hsync,
ck => ck,
r => r,
g => g,
b => b
);
--microSDwing
--0 not used in SPI
--1 MISO
--2 SCK
--3 MOSI
--4 CSN
spi_miso <= w1a(1);
w1a(2) <= spi_clk;
w1a(3) <= spi_mosi;
w1a(4) <= spi_csn;
butled1: entity work.wingbutled
Port map (
io => w1b,
buttons => buttons2,
leds => leds
);
-- leds <= buttons2;
end Behavioral;
|
-----------------------------------------------------------
-- Default Libs
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
-- My libs
-- USE work.my_functions.all
-----------------------------------------------------------
ENTITY FlashReader IS
PORT (
KEY : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
LEDG : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
CLOCK_50 : IN STD_LOGIC;
UART_TXD : OUT STD_LOGIC
);
END FlashReader;
--------------------------------------------------------
ARCHITECTURE structure OF FlashReader IS
COMPONENT FlashController
PORT (
clk : IN STD_LOGIC;
addr : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
rdy : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT BaudGenerator IS
PORT ( clk : IN STD_LOGIC;
clk_out : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT UartTransmitter IS
PORT (
clk : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
send : IN STD_LOGIC;
rdy : OUT STD_LOGIC;
TXD : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT DataGenerator IS
PORT (
clk : IN STD_LOGIC;
nxt : IN STD_LOGIC;
data : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rdy : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL uart_send : STD_LOGIC;
SIGNAL uart_clk : STD_LOGIC;
SIGNAL uart_data : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL uart_rdy : STD_LOGIC := '1';
SIGNAL s_addr : STD_LOGIC_VECTOR(18 DOWNTO 0);
BEGIN
controller : FlashController PORT MAP ( clk => CLOCK_50, addr=>s_addr, data=>LEDG(7 DOWNTO 0), rdy=>LEDG(9));
baudgen : BaudGenerator PORT MAP ( clk => CLOCK_50, clk_out => uart_clk);
transmitter : UartTransmitter PORT MAP (clk => uart_clk, data => uart_data, send => uart_send, rdy=>uart_rdy, TXD => UART_TXD);
datagen : DataGenerator PORT MAP ( clk=> CLOCK_50, nxt => uart_rdy, data => uart_data, rdy => uart_send);
s_addr(9 DOWNTO 0) <= SW;
s_addr(18 DOWNTO 10) <= "000000000";
END structure;
-------------------------------------------------------- |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:22:34 12/02/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/jummmmmmmm/tbfetchhhh.vhd
-- Project Name: jummmmmmmm
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: fetch
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tbfetchhhh IS
END tbfetchhhh;
ARCHITECTURE behavior OF tbfetchhhh IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT fetch
PORT(
Clk : IN std_logic;
Reset : IN std_logic;
CUentrada : IN std_logic_vector(1 downto 0);
Entradain : IN std_logic_vector(31 downto 0);
Instruccionout : OUT std_logic_vector(31 downto 0);
PCout : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Reset : std_logic := '0';
signal CUentrada : std_logic_vector(1 downto 0) := (others => '0');
signal Entradain : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal Instruccionout : std_logic_vector(31 downto 0);
signal PCout : std_logic_vector(31 downto 0);
-- Clock period definitions
constant Clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: fetch PORT MAP (
Clk => Clk,
Reset => Reset,
CUentrada => CUentrada,
Entradain => Entradain,
Instruccionout => Instruccionout,
PCout => PCout
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
Reset <= '0';
CUentrada <= "10";
Entradain <= "00000000000000000000000000000101";
wait for 100 ns;
Reset <= '1';
CUentrada <= "10";
Entradain <= "00000000000000000000000000000101";
wait for 100 ns;
Reset <= '0';
CUentrada <= "10";
Entradain <= "00000000000000000000000000000101";
wait for 100 ns;
Reset <= '0';
CUentrada <= "10";
Entradain <= "00000000000000000000000000000101";
wait for 100 ns;
Reset <= '0';
CUentrada <= "10";
Entradain <= "00000000000000000000000000000000";
wait for 100 ns;
Reset <= '0';
CUentrada <= "10";
Entradain <= "00000000000000000000000000000001";
wait for 100 ns;
wait;
end process;
END;
|
constant SensorFSMLength : integer := 1180;
constant SensorFSMCfg : std_logic_vector(SensorFSMLength-1 downto 0) := "1111100000000000000011111000000000000000111110000000000000001111100000000000000011111000000000000000000000000000001010000000100100000000000000000011000101001000100000001000000010001000010010010000000010000000100100011000101100000001000000001000100010001001000000010000000010010001110001110000000110000000100010001100100100000001100000001001001000000111001000100000000010001001000010010000001000000000100100100100011100000010100000000010101000000010001000001010000001001100000011001000110000101000000100100100010100100010000011000001100000001001010010010000001100000100000110000101001001000000110000011000000100010100100100010011100000000101100001000001010100001110000000010001100111000101000001000000000001011000001000010101000100000000000100011010000001010000010010000000010110011000000100010101000100100000000100011001101001000101000011111000000000000000000000000000000000111110000000000000000000000000000000001111100000000000000000000000000000000011111000000000000000000000000000000000000000001111100000000000000000000000000000000000000000111110000000000000000000000000000000000000000011111000000000000000000000000000000000000000001111100000000000000000000000000000000000000000";
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTCOMB36.VHD ***
--*** ***
--*** Function: Combinatorial left shift, 36 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END hcc_lsftcomb36;
ARCHITECTURE rtl OF hcc_lsftcomb36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 36 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 36 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTCOMB36.VHD ***
--*** ***
--*** Function: Combinatorial left shift, 36 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END hcc_lsftcomb36;
ARCHITECTURE rtl OF hcc_lsftcomb36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 36 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 36 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTCOMB36.VHD ***
--*** ***
--*** Function: Combinatorial left shift, 36 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END hcc_lsftcomb36;
ARCHITECTURE rtl OF hcc_lsftcomb36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 36 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 36 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTCOMB36.VHD ***
--*** ***
--*** Function: Combinatorial left shift, 36 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END hcc_lsftcomb36;
ARCHITECTURE rtl OF hcc_lsftcomb36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 36 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 36 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTCOMB36.VHD ***
--*** ***
--*** Function: Combinatorial left shift, 36 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END hcc_lsftcomb36;
ARCHITECTURE rtl OF hcc_lsftcomb36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 36 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 36 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTCOMB36.VHD ***
--*** ***
--*** Function: Combinatorial left shift, 36 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END hcc_lsftcomb36;
ARCHITECTURE rtl OF hcc_lsftcomb36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 36 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 36 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTCOMB36.VHD ***
--*** ***
--*** Function: Combinatorial left shift, 36 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END hcc_lsftcomb36;
ARCHITECTURE rtl OF hcc_lsftcomb36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 36 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 36 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTCOMB36.VHD ***
--*** ***
--*** Function: Combinatorial left shift, 36 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END hcc_lsftcomb36;
ARCHITECTURE rtl OF hcc_lsftcomb36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 36 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 36 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTCOMB36.VHD ***
--*** ***
--*** Function: Combinatorial left shift, 36 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END hcc_lsftcomb36;
ARCHITECTURE rtl OF hcc_lsftcomb36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 36 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 36 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTCOMB36.VHD ***
--*** ***
--*** Function: Combinatorial left shift, 36 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END hcc_lsftcomb36;
ARCHITECTURE rtl OF hcc_lsftcomb36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 36 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 36 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
entity io_dummy is
port (
clock : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp );
end entity;
architecture dummy of io_dummy is
begin
io_resp.data <= X"00";
process(clock)
begin
if rising_edge(clock) then
io_resp.ack <= io_req.read or io_req.write;
end if;
end process;
end dummy;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
entity io_dummy is
port (
clock : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp );
end entity;
architecture dummy of io_dummy is
begin
io_resp.data <= X"00";
process(clock)
begin
if rising_edge(clock) then
io_resp.ack <= io_req.read or io_req.write;
end if;
end process;
end dummy;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
entity io_dummy is
port (
clock : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp );
end entity;
architecture dummy of io_dummy is
begin
io_resp.data <= X"00";
process(clock)
begin
if rising_edge(clock) then
io_resp.ack <= io_req.read or io_req.write;
end if;
end process;
end dummy;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
entity io_dummy is
port (
clock : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp );
end entity;
architecture dummy of io_dummy is
begin
io_resp.data <= X"00";
process(clock)
begin
if rising_edge(clock) then
io_resp.ack <= io_req.read or io_req.write;
end if;
end process;
end dummy;
|
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