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-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY OpenSSD2_Dispatcher_uCode_0_0 IS
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END OpenSSD2_Dispatcher_uCode_0_0;
ARCHITECTURE OpenSSD2_Dispatcher_uCode_0_0_arch OF OpenSSD2_Dispatcher_uCode_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF OpenSSD2_Dispatcher_uCode_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF OpenSSD2_Dispatcher_uCode_0_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF OpenSSD2_Dispatcher_uCode_0_0_arch : ARCHITECTURE IS "OpenSSD2_Dispatcher_uCode_0_0,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF OpenSSD2_Dispatcher_uCode_0_0_arch: ARCHITECTURE IS "OpenSSD2_Dispatcher_uCode_0_0,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=OpenSSD2_Dispatcher_uCode_0_0.mif,C_INIT_FILE=NONE,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=1,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=64,C_READ_WIDTH_A=64,C_WRITE_DEPTH_A=256,C_READ_DEPTH_A=256,C_ADDRA_WIDTH=8,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=64,C_READ_WIDTH_B=64,C_WRITE_DEPTH_B=256,C_READ_DEPTH_B=256,C_ADDRB_WIDTH=8,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 6.700549 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF rsta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "OpenSSD2_Dispatcher_uCode_0_0.mif",
C_INIT_FILE => "NONE",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 1,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 64,
C_READ_WIDTH_A => 64,
C_WRITE_DEPTH_A => 256,
C_READ_DEPTH_A => 256,
C_ADDRA_WIDTH => 8,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 64,
C_READ_WIDTH_B => 64,
C_WRITE_DEPTH_B => 256,
C_READ_DEPTH_B => 256,
C_ADDRB_WIDTH => 8,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 6.700549 mW"
)
PORT MAP (
clka => clka,
rsta => rsta,
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END OpenSSD2_Dispatcher_uCode_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY OpenSSD2_Dispatcher_uCode_0_0 IS
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END OpenSSD2_Dispatcher_uCode_0_0;
ARCHITECTURE OpenSSD2_Dispatcher_uCode_0_0_arch OF OpenSSD2_Dispatcher_uCode_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF OpenSSD2_Dispatcher_uCode_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF OpenSSD2_Dispatcher_uCode_0_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF OpenSSD2_Dispatcher_uCode_0_0_arch : ARCHITECTURE IS "OpenSSD2_Dispatcher_uCode_0_0,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF OpenSSD2_Dispatcher_uCode_0_0_arch: ARCHITECTURE IS "OpenSSD2_Dispatcher_uCode_0_0,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=OpenSSD2_Dispatcher_uCode_0_0.mif,C_INIT_FILE=NONE,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=1,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=64,C_READ_WIDTH_A=64,C_WRITE_DEPTH_A=256,C_READ_DEPTH_A=256,C_ADDRA_WIDTH=8,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=64,C_READ_WIDTH_B=64,C_WRITE_DEPTH_B=256,C_READ_DEPTH_B=256,C_ADDRB_WIDTH=8,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 6.700549 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF rsta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "OpenSSD2_Dispatcher_uCode_0_0.mif",
C_INIT_FILE => "NONE",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 1,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 64,
C_READ_WIDTH_A => 64,
C_WRITE_DEPTH_A => 256,
C_READ_DEPTH_A => 256,
C_ADDRA_WIDTH => 8,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 64,
C_READ_WIDTH_B => 64,
C_WRITE_DEPTH_B => 256,
C_READ_DEPTH_B => 256,
C_ADDRB_WIDTH => 8,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 6.700549 mW"
)
PORT MAP (
clka => clka,
rsta => rsta,
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END OpenSSD2_Dispatcher_uCode_0_0_arch;
|
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11232)
`protect data_block
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efc3s7HMdgFJ0QG5zRExYAHLYyhiD1SKslKH3xIMgr9Mk6tIFHGeN0UXXRbbKo0BlDnzdkw6/6Bu
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RAZw
`protect end_protected
|
-- FRECUENCIMETRO
-- Librerias necesarias
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
-- Definimos la entidad
ENTITY Frecuencimetro IS
PORT(
reloj : IN STD_LOGIC; -- Reloj interno de la placa
senialGenerador : IN STD_LOGIC; -- Senial introducida por el generador
decenasDisplay : OUT STD_LOGIC_VECTOR (6 DOWNTO 0); -- Valor de las decenas a mostrar en el display
unidadesDisplay: OUT STD_LOGIC_VECTOR (6 DOWNTO 0) -- Valor de las unidades a mostrar en el display
);
END Frecuencimetro;
-- Definimos la arquitectura
ARCHITECTURE arquitecturaFrecuencimetro OF Frecuencimetro IS
SIGNAL salida : INTEGER RANGE 0 TO 90; -- En esta senial guardaremos el valor del numero de pulsos de la senial para mostrar dicho resultado
SIGNAL unidades : INTEGER RANGE 0 TO 9; -- Valor de las unidades
SIGNAL decenas : INTEGER RANGE 0 TO 9; -- Valor de las decenas
SIGNAL pulsosReloj : INTEGER RANGE 0 TO 26000; -- Contamos los pulsos de nuestra senial de reloj
SIGNAL pulsosSenial : INTEGER RANGE 0 TO 99; -- Contamos los pulsos de la senial introducida
SIGNAL flag : std_logic:='0'; -- Marca utilizada para reiniciar los pulso de la senial
-- Instanciamos el codificador de 7 segmentos para la representacion mediante display
COMPONENT codificador7Segmentos
PORT(
entrada : IN INTEGER RANGE 0 TO 9;
salida : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
);
END COMPONENT;
BEGIN
-- Proceso que cuenta el numero de pulsos que da el reloj. Cuando llegue a 25175 (ya que la frecuencia es de
-- 25'175 MHz = 25175000 pulsos por segundo) es que ha pasado un segundo. Por tanto mostramos los pulsos que ha dado
-- nuestra senial hasta entonces (en KHz)
cuantificadorReloj : PROCESS (reloj)
BEGIN
IF (reloj'EVENT AND reloj= '1') THEN
pulsosReloj <= pulsosReloj + 1;
flag <= '0';
IF (pulsosReloj >= 25175) THEN
flag <= '1';
salida <= pulsosSenial;
pulsosReloj <= 0;
END IF;
END IF;
END PROCESS cuantificadorReloj;
-- Proceso que cuenta el numero de pulsos que da la senial del generador en un segundo. Obtenemos asi su frecuencia
cuantificadorGenerador : PROCESS (flag, senialGenerador)
BEGIN
IF flag = '1' THEN
pulsosSenial <= 0;
else
IF (senialGenerador'EVENT AND senialGenerador = '1') THEN
pulsosSenial <= pulsosSenial + 1;
END IF;
END IF;
END PROCESS cuantificadorGenerador;
-- Proceso para obtener el valor de la frecuencia de la senial a partir del numero de pulsos obtenidos de esta
-- Como sabemos que se movera el valor entre los 1-90 KHz, en el primer display mostraremos las unidades en KHz y en el segundo las decenas en KHz
valoresDisplays : PROCESS (salida)
BEGIN
decenas <= (salida/10); -- Obtenemos las decenas
unidades <= salida - decenas*10; -- Obtenemos las unidades
END PROCESS valoresDisplays;
-- Codificamos para mostrar por el display de 7 segmentos las unidades
mostrarUnidadesDisplay : codificador7Segmentos PORT MAP(
entrada => unidades,
salida => unidadesDisplay
);
-- Codificamos para mostrar por el display de 7 segmenos las decenas
mostrarDecenasDisplay : codificador7Segmentos PORT MAP(
entrada => decenas,
salida => decenasDisplay
);
END arquitecturaFrecuencimetro; |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.thermal_systems.all;
entity tb_diode is
end tb_diode;
architecture TB_diode of tb_diode is
-- Component declarations
-- Signal declarations
terminal in_src : electrical;
terminal r1_d1 : electrical;
terminal temp_in : thermal;
begin
-- Signal assignments
-- Component instances
vio : entity work.v_sine(ideal)
generic map(
freq => 100.0,
amplitude => 5.0
)
port map(
pos => in_src,
neg => ELECTRICAL_REF
);
tmp : entity work.TempConstant(ideal)
generic map(
level => 100.0
)
port map(
th1 => temp_in,
th2 => thermal_REF
);
R1 : entity work.resistor(ideal)
generic map(
res => 100.0
)
port map(
p1 => in_src,
p2 => r1_d1
);
D1 : entity work.diode(one)
port map(
p => r1_d1,
m => electrical_ref,
j => temp_in
);
end TB_diode;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.thermal_systems.all;
entity tb_diode is
end tb_diode;
architecture TB_diode of tb_diode is
-- Component declarations
-- Signal declarations
terminal in_src : electrical;
terminal r1_d1 : electrical;
terminal temp_in : thermal;
begin
-- Signal assignments
-- Component instances
vio : entity work.v_sine(ideal)
generic map(
freq => 100.0,
amplitude => 5.0
)
port map(
pos => in_src,
neg => ELECTRICAL_REF
);
tmp : entity work.TempConstant(ideal)
generic map(
level => 100.0
)
port map(
th1 => temp_in,
th2 => thermal_REF
);
R1 : entity work.resistor(ideal)
generic map(
res => 100.0
)
port map(
p1 => in_src,
p2 => r1_d1
);
D1 : entity work.diode(one)
port map(
p => r1_d1,
m => electrical_ref,
j => temp_in
);
end TB_diode;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.thermal_systems.all;
entity tb_diode is
end tb_diode;
architecture TB_diode of tb_diode is
-- Component declarations
-- Signal declarations
terminal in_src : electrical;
terminal r1_d1 : electrical;
terminal temp_in : thermal;
begin
-- Signal assignments
-- Component instances
vio : entity work.v_sine(ideal)
generic map(
freq => 100.0,
amplitude => 5.0
)
port map(
pos => in_src,
neg => ELECTRICAL_REF
);
tmp : entity work.TempConstant(ideal)
generic map(
level => 100.0
)
port map(
th1 => temp_in,
th2 => thermal_REF
);
R1 : entity work.resistor(ideal)
generic map(
res => 100.0
)
port map(
p1 => in_src,
p2 => r1_d1
);
D1 : entity work.diode(one)
port map(
p => r1_d1,
m => electrical_ref,
j => temp_in
);
end TB_diode;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1411.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b01x00p01n01i01411ent IS
END c08s05b01x00p01n01i01411ent;
ARCHITECTURE c08s05b01x00p01n01i01411arch OF c08s05b01x00p01n01i01411ent IS
BEGIN
TESTING: PROCESS
type A1 is array (1 to 15) of integer;
variable XC : A1;
BEGIN
XC (4 to 1) := 4321;
assert FALSE
report "***PASSED TEST: c08s05b01x00p01n01i01411"
severity NOTE;
wait;
END PROCESS TESTING;
END c08s05b01x00p01n01i01411arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1411.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b01x00p01n01i01411ent IS
END c08s05b01x00p01n01i01411ent;
ARCHITECTURE c08s05b01x00p01n01i01411arch OF c08s05b01x00p01n01i01411ent IS
BEGIN
TESTING: PROCESS
type A1 is array (1 to 15) of integer;
variable XC : A1;
BEGIN
XC (4 to 1) := 4321;
assert FALSE
report "***PASSED TEST: c08s05b01x00p01n01i01411"
severity NOTE;
wait;
END PROCESS TESTING;
END c08s05b01x00p01n01i01411arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1411.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b01x00p01n01i01411ent IS
END c08s05b01x00p01n01i01411ent;
ARCHITECTURE c08s05b01x00p01n01i01411arch OF c08s05b01x00p01n01i01411ent IS
BEGIN
TESTING: PROCESS
type A1 is array (1 to 15) of integer;
variable XC : A1;
BEGIN
XC (4 to 1) := 4321;
assert FALSE
report "***PASSED TEST: c08s05b01x00p01n01i01411"
severity NOTE;
wait;
END PROCESS TESTING;
END c08s05b01x00p01n01i01411arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity led_timer is
generic
(
on_time_exp : positive := 10
);
port
(
clk : in std_logic;
rst : in std_logic;
input : in std_logic;
led : out std_logic
);
end entity;
architecture rtl of led_timer is
signal cnt : std_logic_vector((on_time_exp-1) downto 0);
begin
process
begin
wait until rising_edge(clk);
if rst = '1' then
cnt <= (others => '0');
led <= '0';
else
-- advance the counter
cnt <= std_logic_vector(unsigned(cnt) + 1);
-- reset the LED if the MSB goes high
if cnt(cnt'high) = '1' then
led <= '0';
end if;
-- set the LED and reset the counter
if input = '1' then
cnt <= (others => '0');
led <= '1';
end if;
end if;
end process;
end rtl;
|
-- +UEFSHDR----------------------------------------------------------------------
-- 2014 UEFS Universidade Estadual de Feira de Santana
-- TEC499-Sistemas Digitais
-- ------------------------------------------------------------------------------
-- TEAM: 01
-- ------------------------------------------------------------------------------
-- PROJECT: Warm up
-- ------------------------------------------------------------------------------
-- FILE NAME : interface_tb
-- KEYWORDS test, interface, control
-- -----------------------------------------------------------------------------
-- PURPOSE: Testa o módulo internet control
-- -UEFSHDR----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity interface_tb is
end interface_tb;
architecture Behavioral of interface_tb is
----------------------------------------------
-- Constants
----------------------------------------------
constant MAIN_CLK_PER : time := 20 ns; -- 50 MHz
constant MAIN_CLK : integer := 50;
constant BAUD_RATE : integer := 9600; -- Bits per Second
constant RST_LVL : std_logic := '1'; -- Active Level of Reset
----------------------------------------------
-- Signal Declaration
----------------------------------------------
-- Clock and reset Signals
signal clk_50m : std_logic := '0';
signal rst : std_logic;
signal rx_ready_in : std_logic;
signal rx_data_in : std_logic_vector(7 downto 0);
-- componente descrito como manda o documento de arquitetura,
-- segundo fontes, caso o mapeamento das portas seja esse, funciona
-- independentemente da linguagem.
component interfaceControl is
port (
clk: in std_logic;
reset: in std_logic;
rx_data_ready: in std_logic;
rx_data: in std_logic_vector(7 downto 0);
data_a: out std_logic_vector(7 downto 0);
data_b: out std_logic_vector(7 downto 0);
operation: out std_logic_vector(7 downto 0)
);
end component;
begin
----------------------------------------------
-- Components Instantiation
----------------------------------------------
uut: component interfaceControl port map(
-- Controle
clk => clk_50m, -- seta clock para o gerado por este rtl
reset => rst, -- seta o reset para o gerado por este rtl
-- interface de entrada
rx_data_ready => rx_ready_in, -- seta o pino que anuncia a transmissão
rx_data => rx_data_in, -- seta o pino que tem os dados da transmissão
-- Saídas
data_a => open,
data_b => open,
operation => open
);
----------------------------------------------
-- Main Signals Generation
----------------------------------------------
-- gera clocl que é enviado para o modulo de interface_control
main_clock_generation : process
begin
wait for MAIN_CLK_PER / 2;
clk_50m <= not clk_50m;
end process;
envia_dados : process
variable temp : integer := 1;
begin
--verifica qual o valor de temp, pois temp define qual dado será enviado
if temp = 1 then
rx_data_in <= "00000001";
temp:= temp +1;
elsif temp = 2 then
rx_data_in <= "01000010";
temp:= temp+1;
else
rx_data_in <= "11111111";
end if;
-- atraso
wait for 100ns;
-- rx_ready_in fica com valor '1' durante tempo de um pulso de clock
rx_ready_in <= '1';
wait for MAIN_CLK_PER / 2;
rx_ready_in <= '0';
-- reinicia a variavel temp e envia um reset caso 3 dados já forem enviados
if temp = 3 then
temp := 1;
wait for 200ns;
rst <= '0';
wait for MAIN_CLK_PER /2;
rst <= '1';
end if;
end process envia_dados;
end Behavioral; |
-- $Id: tst_serlooplib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: tst_serlooplib
-- Description: Definitions for tst_serloop records and helpers
--
-- Dependencies: -
-- Tool versions: ise 13.1-14.7; viv 2014.7-2015.4; ghdl 0.29-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-10 438 1.0.2 add rxui(cnt|dat) fields in hio_stat_type
-- 2011-12-09 437 1.0.1 rename serport stat->moni port
-- 2011-10-14 416 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.serportlib.all;
package tst_serlooplib is
constant c_mode_idle : slv2 := "00"; -- mode: idle (no tx activity)
constant c_mode_rxblast : slv2 := "01"; -- mode: rxblast (check rx activity)
constant c_mode_txblast : slv2 := "10"; -- mode: txblast (saturate tx)
constant c_mode_loop : slv2 := "11"; -- mode: loop (rx->tx loop-back)
type hio_cntl_type is record -- humanio controls
mode : slv2; -- mode (idle,(tx|tx)blast,loop)
enaxon : slbit; -- enable xon/xoff handling
enaesc : slbit; -- enable xon/xoff escaping
enathrottle : slbit; -- enable 1 msec tx throttling
enaftdi : slbit; -- enable ftdi flush handling
end record hio_cntl_type;
constant hio_cntl_init : hio_cntl_type := (
c_mode_idle, -- mode
'0','0','0','0' -- enaxon,enaesc,enathrottle,enaftdi
);
type hio_stat_type is record -- humanio status
rxfecnt : slv16; -- rx frame error counter
rxoecnt : slv16; -- rx overrun error counter
rxsecnt : slv16; -- rx sequence error counter
rxcnt : slv32; -- rx char counter
txcnt : slv32; -- tx char counter
rxuicnt : slv8; -- rx unsolicited input counter
rxuidat : slv8; -- rx unsolicited input data
rxokcnt : slv16; -- rxok 1->0 transition counter
txokcnt : slv16; -- txok 1->0 transition counter
end record hio_stat_type;
constant hio_stat_init : hio_stat_type := (
(others=>'0'), -- rxfecnt
(others=>'0'), -- rxoecnt
(others=>'0'), -- rxsecnt
(others=>'0'), -- rxcnt
(others=>'0'), -- txcnt
(others=>'0'), -- rxuicnt
(others=>'0'), -- rxuidat
(others=>'0'), -- rxokcnt
(others=>'0') -- txokcnt
);
-- -------------------------------------
component tst_serloop is -- tester for serport components
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE_MSEC : in slbit; -- msec pulse
HIO_CNTL : in hio_cntl_type; -- humanio controls
HIO_STAT : out hio_stat_type; -- humanio status
SER_MONI : in serport_moni_type; -- serport monitor
RXDATA : in slv8; -- receiver data out
RXVAL : in slbit; -- receiver data valid
RXHOLD : out slbit; -- receiver data hold
TXDATA : out slv8; -- transmit data in
TXENA : out slbit; -- transmit data enable
TXBUSY : in slbit -- transmit busy
);
end component;
component tst_serloop_hiomap is -- default human I/O mapper
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
HIO_CNTL : out hio_cntl_type; -- tester controls from hio
HIO_STAT : in hio_stat_type; -- tester status to display by hio
SER_MONI : in serport_moni_type; -- serport monitor to display by hio
SWI : in slv8; -- switch settings
BTN : in slv4; -- button settings
LED : out slv8; -- led data
DSP_DAT : out slv16; -- display data
DSP_DP : out slv4 -- display decimal points
);
end component;
end package tst_serlooplib;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY halfAdder IS
PORT (
in1 : IN std_logic;
in2 : IN std_logic;
res : OUT std_logic;
carry : OUT std_logic
);
END halfAdder;
ARCHITECTURE behavior OF halfAdder IS
BEGIN
res <= in1 XOR in2;
carry <= in1 AND in2;
END behavior;
|
------------------------------------------------------------------------------
-- Create/rivision Date: 7/13/2008, 7/15/2009, 6/28/2010
-- Design Name: Instruction Cache Emulator Unit
-- Module Name: inst_cache
-- Authors: Rahul P. Tekawade, Gandhi Puvvada
-- File: inst_cache_r2.vhd
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
-- use ieee.std_logic_unsigned.all;
--synopsys translate_off
use work.instr_stream_pkg.all; -- instruction stream defining package
--synopsys translate_on
------------------------------------------------------------------------------
entity inst_cache is
generic (
DATA_WIDTH : integer := 128; --DATA_WIDTH_CONSTANT; -- defined as 128 in the instr_stream_pkg;
ADDR_WIDTH : integer := 6 --ADDR_WIDTH_CONSTANT -- defined as 6 in the instr_stream_pkg;
);
port (
Clk : in std_logic;
Resetb : in std_logic;
read_cache : in std_logic;
abort_prev_read : in std_logic; -- will be used under jump or successful branch
addr : in std_logic_vector (31 downto 0);
cd0 : out std_logic_vector (31 downto 0);
cd1 : out std_logic_vector (31 downto 0);
cd2 : out std_logic_vector (31 downto 0);
cd3 : out std_logic_vector (31 downto 0);
-- synopsys translate_off
registered_addr : out std_logic_vector(31 downto 0);
-- synopsys translate_on
read_hit : out std_logic;
fio_icache_addr_a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
fio_icache_data_in_a : in std_logic_vector(DATA_WIDTH-1 downto 0);
fio_icache_wea : in std_logic;
fio_icache_data_out_a : out std_logic_vector(DATA_WIDTH-1 downto 0);
fio_icache_ena : in std_logic
);
end inst_cache;
------------------------------------------------------------------------------
architecture behv of inst_cache is
--constant DATA_WIDTH : integer := 128;
--constant ADDR_WIDTH : integer := 6;
signal count : std_logic_vector( 3 downto 0); -- count for latency
-- signal indx : std_logic_vector ( 3 downto 0); -- index to the register array contaning latencies
signal latency : std_logic_vector ( 3 downto 0); -- latency read from the latency register array
signal data_out : std_logic_vector(127 downto 0);
signal pending_req : std_logic; -- basically a new read_cache request is recorded as a pending request
signal read_hit_int : std_logic; -- internal signal for the output port read_hit
-- Type definition for latencies
-- Type definition for a 4-bit individual register for the register array.
subtype reg is std_logic_vector (3 downto 0);
-- Type definition of 16-latencies register array
type reg_array is array (0 to 15) of reg;
constant latency_array : reg_array := -- minimum latency = 0 after registering the request
-- ( X"7", --0 -- which guarantees the 1 clock delay due to BRAM
-- X"1", --1
-- X"2", --2
-- X"3", --3 -- however, the BRAM works like a pipeline
-- X"6", --4 -- if the latency is continuously 0 and if
-- X"6", --5 -- read_cache request is true continuously.
-- X"6", --6
-- X"7", --7
-- X"3", --8
-- x"1", --9
-- x"2", --10
-- X"6", --11
-- X"4", --12
-- X"5", --13
-- X"8", --14
-- X"7" --15
-- );
( X"3", --0 -- which guarantees the 1 clock delay due to BRAM
X"5", --1
X"0", --2
X"0", --3 -- however, the BRAM works like a pipeline
X"0", --4 -- if the latency is continuously 0 and if
X"0", --5 -- read_cache request is true continuously.
X"0", --6
X"5", --7
X"4", --8
x"9", --9
x"2", --10
X"7", --11
X"0", --12
X"0", --13
X"A", --14
X"7" --15
);
------
-- component declarations [ instruction memory]
component inst_cache_dpram is
generic (
DATA_WIDTH : integer := 128; -- defined as 128 in the instr_stream_pkg;
ADDR_WIDTH : integer := 6 -- defined as 6 in the instr_stream_pkg;
);
port (
Clka : in std_logic;
addr_a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
data_in_a : in std_logic_vector(DATA_WIDTH-1 downto 0);
wea : in std_logic;
data_out_a : out std_logic_vector(DATA_WIDTH-1 downto 0);
ena : in std_logic;
Clkb : in std_logic;
addr_b : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-- data_in_b : in std_logic_vector(DATA_WIDTH-1 downto 0);
-- web : in std_logic;
data_out_b : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end component inst_cache_dpram;
begin -- begin of architecture
-- component port map
memory: inst_cache_dpram
generic map(DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH)
port map(Clka => Clk, addr_a => fio_icache_addr_a, data_in_a => fio_icache_data_in_a,
wea => fio_icache_wea, data_out_a => fio_icache_data_out_a, ena => fio_icache_ena,
Clkb=>Clk, addr_b=>addr(9 downto 4), data_out_b=>data_out);
-- note that we shall not be sending the registered address as we
-- do not want to create an additional pipeline stage!
read_hit <= read_hit_int ; -- read_hit port is assigned with internal read_hit_int
-------------------------------------------------------------------------------
pending_req_two_state_state_machine: process ( Clk, Resetb )
begin
if (Resetb = '0') then
pending_req <= '0';
elsif Clk'event and Clk = '1' then
case pending_req is
when '0' =>
if read_cache = '1' then
pending_req <= '1';
end if;
when others => -- i.e. when '1' =>
-- if ( ( (read_hit_int = '1') or (abort_prev_read = '1') ) and (read_cache = '0') ) then
if (read_cache = '0' ) then
pending_req <= '0';
end if;
end case;
end if;
end process pending_req_two_state_state_machine;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
register_addr_and_latecy: process ( Clk, Resetb )
begin
if (Resetb = '0') then
-- synopsys translate_off
registered_addr <= x"08080808"; -- actually does not need any initalization
-- synopsys translate_on
latency <= X"0"; -- actually does not need any initalization
count <= X"0";
-- indx <= X"0"; --
elsif ( Clk'event and Clk='1') then
if ( ( read_cache = '1') and
( (pending_req = '0') or (read_hit_int = '1') or (abort_prev_read = '1') )
) then -- i.e. a new request has been initiated;
-- we need to record the address of memory location to be read,
-- the latency pointed to by the index,
-- initiate count to zero, and
-- increment the index
-- synopsys translate_off
registered_addr <= addr(31 downto 0); -- need to change according to the width
-- synopsys translate_on
latency <= latency_array (CONV_INTEGER(unsigned(addr(9 downto 6))));
count <= X"0";
-- indx <= unsigned(indx) + 1; -- index will naturally roll over
elsif (pending_req = '1') then
count <= unsigned(count) + 1;
else
count <= X"0";
end if;
end if;
end process register_addr_and_latecy;
-------------------------------------------------------------------------------
read_hit_comb_process:
process (pending_req, latency, count, data_out)
begin
if ((pending_req = '1') and (latency = count)) then
read_hit_int <= '1';
cd0 <= data_out( 31 downto 0);
cd1 <= data_out( 63 downto 32);
cd2 <= data_out( 95 downto 64);
cd3 <= data_out( 127 downto 96);
else
read_hit_int <= '0';
cd0 <= (others => 'X'); -- don't care
cd1 <= (others => 'X'); -- don't care
cd2 <= (others => 'X'); -- don't care
cd3 <= (others => 'X'); -- don't care
end if;
end process read_hit_comb_process;
-------------------------------------------------------------------------------
end behv;
|
----------------------------------------------------------------------------------------------------
-- demuxer
----------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
----------------------------------------------------------------------------------------------------
-- PACKAGE
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
package demuxer_pkg is
--demuxer componenet declaration
component demuxer is
generic( INIT_SEL : std_logic_vector(1 downto 0) := b"01");
port( clk : in std_logic;
clk_2x : in std_logic;
rst : in std_logic;
sigs : in std_logic_vector;
sig1 : out std_logic_vector;
sig2 : out std_logic_vector);
end component;
end package;
----------------------------------------------------------------------------------------------------
-- ENTITY
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--This entity takes 2 input signals and interlaces them into 1 output signal. During development
--it was determined that the clock inputs must be phase aligned for best results
entity demuxer is
generic( INIT_SEL : std_logic_vector(1 downto 0) := b"01");
port( clk : in std_logic;
clk_2x : in std_logic;
rst : in std_logic;
sigs : in std_logic_vector;
sig1 : out std_logic_vector;
sig2 : out std_logic_vector);
end demuxer;
----------------------------------------------------------------------------------------------------
-- ARCHITECTURE
----------------------------------------------------------------------------------------------------
architecture behave of demuxer is
signal sigs_reg : std_logic_vector(sig1'range) := (others => '0');
signal selector : std_logic_vector(INIT_SEL'range) := INIT_SEL;
signal sel1 : std_logic_vector(sig1'range) := (others => '0');
signal sel2 : std_logic_vector(sig2'range) := (others => '0');
signal selx : std_logic_vector(sig1'range) := (others => '0');
signal sig1_reg : std_logic_vector(sig1'range) := (others => '0');
signal sig2_reg : std_logic_vector(sig2'range) := (others => '0');
begin
--Register the input
reg_in : process(clk_2x)
begin
if(rising_edge(clk_2x)) then
if(rst = '1') then
sigs_reg <= (others => '0');
else
sigs_reg <= sigs;
end if;
end if;
end process;
--Selection
update_selection : process(clk_2x)
begin
if(rising_edge(clk_2x)) then
if(rst = '1') then
selector <= INIT_SEL;
else
selector <= std_logic_vector(rotate_right(unsigned(selector), 1));
end if;
end if;
end process;
--Register the selection
reg_sel : process(clk_2x)
begin
if(rising_edge(clk_2x)) then
if(rst = '1') then
sel1 <= (others => '0');
sel2 <= (others => '0');
else
case selector is
when b"01" => sel1 <= sigs;
when b"10" => sel2 <= sigs;
when others => selx <= sigs;
end case;
end if;
end if;
end process;
--Register the output
reg_out : process(clk)
begin
if(rising_edge(clk)) then
if(rst = '1') then
sig1_reg <= (others => '0');
sig2_reg <= (others => '0');
else
sig1_reg <= sel1;
sig2_reg <= sel2;
end if;
end if;
end process;
sig1 <= sig1_reg;
sig2 <= sig2_reg;
end behave;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.my_lib.all;
entity timer is
port (
clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
output : out std_logic_vector(26 downto 0)
);
end timer;
architecture arch of timer is
component pulser is
generic(
delay:integer := 500000
);
port(
clk: in std_logic;
enable: in std_logic;
output: out std_logic
);
end component;
component modn is
generic(
n:integer := 4
);
port (
clk : in std_logic;
inc : in std_logic;
enable: in std_logic;
reset: in std_logic;
overflow: out std_logic;
output : out std_logic_vector(f_log2(n)-1 downto 0)
);
end component;
signal timer_clk: std_logic;
signal seconds_hundrendth_overflow : std_logic;
signal seconds_tenths_overflow : std_logic;
signal seconds_ones_overflow : std_logic;
signal seconds_units_overflow : std_logic;
signal seconds_tens_overflow : std_logic;
signal mins_units_overflow : std_logic;
signal mins_tens_overflow : std_logic;
begin
p1: pulser generic map(delay=>50000) port map(clk,enable,timer_clk);
seconds_hundredth: modn generic map(n=>10) port map(clk,timer_clk,enable,reset,seconds_hundrendth_overflow,output(3 downto 0));
seconds_tenths: modn generic map(n=>10) port map(clk,seconds_hundrendth_overflow,enable,reset,seconds_tenths_overflow,output(7 downto 4));
seconds_ones: modn generic map(n=>10) port map(clk,seconds_tenths_overflow,enable,reset,seconds_ones_overflow,output(11 downto 8));
seconds_units: modn generic map(n=>10) port map(clk,seconds_ones_overflow,enable,reset,seconds_units_overflow,output(15 downto 12));
seconds_tens: modn generic map(n=>6) port map(clk,seconds_units_overflow,enable,reset,seconds_tens_overflow,output(18 downto 16)); --padd '0'
mins_units: modn generic map(n=>10) port map(clk,seconds_tens_overflow,enable,reset,mins_units_overflow,output(23 downto 20));
mins_tens: modn generic map(n=>6) port map(clk,mins_units_overflow,enable,reset,open,output(26 downto 24)); --padd '0'
end arch;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_p_src_cols_V_channel_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_p_src_cols_V_channel_shiftReg;
architecture rtl of FIFO_image_filter_p_src_cols_V_channel_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_p_src_cols_V_channel is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_p_src_cols_V_channel is
component FIFO_image_filter_p_src_cols_V_channel_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_p_src_cols_V_channel_shiftReg : FIFO_image_filter_p_src_cols_V_channel_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_p_src_cols_V_channel_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_p_src_cols_V_channel_shiftReg;
architecture rtl of FIFO_image_filter_p_src_cols_V_channel_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_p_src_cols_V_channel is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_p_src_cols_V_channel is
component FIFO_image_filter_p_src_cols_V_channel_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_p_src_cols_V_channel_shiftReg : FIFO_image_filter_p_src_cols_V_channel_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
-- NEED RESULT: ARCH00009.P1_1: Resume after time on timeout clause expired passed
-- NEED RESULT: ARCH00009.P1_2: Resume after time on timeout clause expired passed
-- NEED RESULT: ARCH00009.P1_3: Resume after time on timeout clause expired passed
-- NEED RESULT: ARCH00009.P1_4: Resume after time on timeout clause expired passed
-- NEED RESULT: ARCH00009.P2_1: Resume after time on timeout clause expired passed
-- NEED RESULT: ARCH00009.P2_2: Resume after time on timeout clause expired passed
-- NEED RESULT: ARCH00009.P2_3: Resume after time on timeout clause expired passed
-- NEED RESULT: ARCH00009.P2_4: Resume after time on timeout clause expired passed
-- NEED RESULT: ARCH00009.P3_1: Resume after time on timeout clause expired passed
-- NEED RESULT: ARCH00009.P3_2: Resume after time on timeout clause expired passed
-- NEED RESULT: ARCH00009.P3_3: Resume after time on timeout clause expired passed
-- NEED RESULT: ARCH00009.P3_4: Resume after time on timeout clause expired passed
-- NEED RESULT: ARCH00009.PROC1_1: Resume after time on timeout clause expired passed
-- NEED RESULT: ARCH00009.PROC1_2: Resume after time on timeout clause expired passed
-- NEED RESULT: ARCH00009.PROC1_3: Resume after time on timeout clause expired passed
-- NEED RESULT: ARCH00009.PROC1_4: Resume after time on timeout clause expired passed
-- NEED RESULT: ARCH00009.PROC2_1: Resume after time on timeout clause expired passed
-- NEED RESULT: ARCH00009.PROC2_2: Resume after time on timeout clause expired passed
-- NEED RESULT: ARCH00009.PROC2_3: Resume after time on timeout clause expired passed
-- NEED RESULT: ARCH00009.PROC2_4: Resume after time on timeout clause expired passed
-- NEED RESULT: ARCH00009.PROC3_1: Resume after time on timeout clause expired passed
-- NEED RESULT: ARCH00009.PROC3_2: Resume after time on timeout clause expired passed
-- NEED RESULT: ARCH00009.PROC3_3: Resume after time on timeout clause expired passed
-- NEED RESULT: ARCH00009.PROC3_4: Resume after time on timeout clause expired passed
-- NEED RESULT: ARCH00009.PROC4_1: Resume after time on timeout clause expired passed
-- NEED RESULT: ARCH00009.PROC4_2: Resume after time on timeout clause expired passed
-- NEED RESULT: ARCH00009.PROC4_3: Resume after time on timeout clause expired passed
-- NEED RESULT: ARCH00009.PROC4_4: Resume after time on timeout clause expired passed
-- NEED RESULT: ARCH00009: Wait in P1_1 did resume passed
-- NEED RESULT: ARCH00009: Wait in P1_2 did resume passed
-- NEED RESULT: ARCH00009: Wait in P1_3 did resume passed
-- NEED RESULT: ARCH00009: Wait in P1_4 did resume passed
-- NEED RESULT: ARCH00009: Wait in P2_1 did resume passed
-- NEED RESULT: ARCH00009: Wait in P2_2 did resume passed
-- NEED RESULT: ARCH00009: Wait in P2_3 did resume passed
-- NEED RESULT: ARCH00009: Wait in P2_4 did resume passed
-- NEED RESULT: ARCH00009: Wait in P3_1 did resume passed
-- NEED RESULT: ARCH00009: Wait in P3_2 did resume passed
-- NEED RESULT: ARCH00009: Wait in P3_3 did resume passed
-- NEED RESULT: ARCH00009: Wait in P3_4 did resume passed
-- NEED RESULT: ARCH00009: Wait in PROC1_1 did resume passed
-- NEED RESULT: ARCH00009: Wait in PROC1_2 did resume passed
-- NEED RESULT: ARCH00009: Wait in PROC1_3 did resume passed
-- NEED RESULT: ARCH00009: Wait in PROC1_4 did resume passed
-- NEED RESULT: ARCH00009: Wait in PROC2_1 did resume passed
-- NEED RESULT: ARCH00009: Wait in PROC2_2 did resume passed
-- NEED RESULT: ARCH00009: Wait in PROC2_3 did resume passed
-- NEED RESULT: ARCH00009: Wait in PROC2_4 did resume passed
-- NEED RESULT: ARCH00009: Wait in PROC3_1 did resume passed
-- NEED RESULT: ARCH00009: Wait in PROC3_2 did resume passed
-- NEED RESULT: ARCH00009: Wait in PROC3_3 did resume passed
-- NEED RESULT: ARCH00009: Wait in PROC3_4 did resume passed
-- NEED RESULT: ARCH00009: Wait in PROC4_1 did resume passed
-- NEED RESULT: ARCH00009: Wait in PROC4_2 did resume passed
-- NEED RESULT: ARCH00009: Wait in PROC4_3 did resume passed
-- NEED RESULT: ARCH00009: Wait in PROC4_4 did resume passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00009
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.1 (7)
-- 8.1 (10)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00009(ARCH00009)
-- ENT00009_Test_Bench(ARCH00009_Test_Bench)
--
-- REVISION HISTORY:
--
-- 26-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
entity ENT00009 is
generic ( G1 : Time := 10 ns ) ;
port ( P1 : in Time := 10 ns ) ;
end ENT00009 ;
architecture ARCH00009 of ENT00009 is
signal Num_Cycles : Integer := 0 ;
signal Dummy, Dummy_Cond : Boolean := false ;
signal P1_1_Did_Resume, P1_2_Did_Resume,
P1_3_Did_Resume, P1_4_Did_Resume : Boolean := false ;
signal P2_1_Did_Resume, P2_2_Did_Resume,
P2_3_Did_Resume, P2_4_Did_Resume : Boolean := false ;
signal P3_1_Did_Resume, P3_2_Did_Resume,
P3_3_Did_Resume, P3_4_Did_Resume : Boolean := false ;
signal PROC1_1_Did_Resume, PROC1_2_Did_Resume,
PROC1_3_Did_Resume, PROC1_4_Did_Resume : Boolean := false ;
signal PROC2_1_Did_Resume, PROC2_2_Did_Resume,
PROC2_3_Did_Resume, PROC2_4_Did_Resume : Boolean := false ;
signal PROC3_1_Did_Resume, PROC3_2_Did_Resume,
PROC3_3_Did_Resume, PROC3_4_Did_Resume : Boolean := false ;
signal PROC4_1_Did_Resume, PROC4_2_Did_Resume,
PROC4_3_Did_Resume, PROC4_4_Did_Resume : Boolean := false ;
constant Time_To_Wait : Time := 10 ns ;
procedure PROC1_1 ( Signal Resume_Chk : inout Boolean ) is
variable Save_Time : Time ;
begin
Save_Time := Std.Standard.Now ;
wait on Dummy until Dummy_Cond for Time_To_Wait ; -- Locally Static
test_report ( "ARCH00009.PROC1_1" ,
"Resume after time on timeout clause expired",
Time_To_Wait = (Std.Standard.Now - Save_Time)) ;
Resume_Chk <= transport True ;
end PROC1_1 ;
procedure PROC1_2 ( Signal Resume_Chk : inout Boolean ) is
variable Save_Time : Time ;
begin
Save_Time := Std.Standard.Now ;
wait on Dummy for Time_To_Wait ; -- Locally Static
test_report ( "ARCH00009.PROC1_2" ,
"Resume after time on timeout clause expired",
Time_To_Wait = (Std.Standard.Now - Save_Time)) ;
Resume_Chk <= transport True ;
end PROC1_2 ;
procedure PROC1_3 ( Signal Resume_Chk : inout Boolean ) is
variable Save_Time : Time ;
begin
Save_Time := Std.Standard.Now ;
wait until Dummy_Cond for Time_To_Wait ; -- Locally Static
test_report ( "ARCH00009.PROC1_3" ,
"Resume after time on timeout clause expired",
Time_To_Wait = (Std.Standard.Now - Save_Time)) ;
Resume_Chk <= transport True ;
end PROC1_3 ;
procedure PROC1_4 ( Signal Resume_Chk : inout Boolean ) is
variable Save_Time : Time ;
begin
Save_Time := Std.Standard.Now ;
wait for Time_To_Wait ; -- Locally Static
test_report ( "ARCH00009.PROC1_4" ,
"Resume after time on timeout clause expired",
Time_To_Wait = (Std.Standard.Now - Save_Time)) ;
Resume_Chk <= transport True ;
end PROC1_4 ;
procedure PROC2_1 ( Signal Resume_Chk : inout Boolean ) is
variable Save_Time : Time ;
begin
Save_Time := Std.Standard.Now ;
wait on Dummy until Dummy_Cond for G1 ; -- Globally Static
test_report ( "ARCH00009.PROC2_1" ,
"Resume after time on timeout clause expired",
G1 = (Std.Standard.Now - Save_Time)) ;
Resume_Chk <= transport True ;
end PROC2_1 ;
procedure PROC2_2 ( Signal Resume_Chk : inout Boolean ) is
variable Save_Time : Time ;
begin
Save_Time := Std.Standard.Now ;
wait on Dummy for G1 ; -- Globally Static
test_report ( "ARCH00009.PROC2_2" ,
"Resume after time on timeout clause expired",
G1 = (Std.Standard.Now - Save_Time)) ;
Resume_Chk <= transport True ;
end PROC2_2 ;
procedure PROC2_3 ( Signal Resume_Chk : inout Boolean ) is
variable Save_Time : Time ;
begin
Save_Time := Std.Standard.Now ;
wait until Dummy_Cond for G1 ; -- Globally Static
test_report ( "ARCH00009.PROC2_3" ,
"Resume after time on timeout clause expired",
G1 = (Std.Standard.Now - Save_Time)) ;
Resume_Chk <= transport True ;
end PROC2_3 ;
procedure PROC2_4 ( Signal Resume_Chk : inout Boolean ) is
variable Save_Time : Time ;
begin
Save_Time := Std.Standard.Now ;
wait for G1 ; -- Globally Static
test_report ( "ARCH00009.PROC2_4" ,
"Resume after time on timeout clause expired",
G1 = (Std.Standard.Now - Save_Time)) ;
Resume_Chk <= transport True ;
end PROC2_4 ;
procedure PROC3_1 ( Signal Resume_Chk : inout Boolean ) is
variable Save_Time : Time ;
begin
Save_Time := Std.Standard.Now ;
wait on Dummy until Dummy_Cond for P1 ; -- Dynamic
test_report ( "ARCH00009.PROC3_1" ,
"Resume after time on timeout clause expired",
P1 = (Std.Standard.Now - Save_Time)) ;
Resume_Chk <= transport True ;
end PROC3_1 ;
procedure PROC3_2 ( Signal Resume_Chk : inout Boolean ) is
variable Save_Time : Time ;
begin
Save_Time := Std.Standard.Now ;
wait on Dummy for P1 ; -- Dynamic
test_report ( "ARCH00009.PROC3_2" ,
"Resume after time on timeout clause expired",
P1 = (Std.Standard.Now - Save_Time)) ;
Resume_Chk <= transport True ;
end PROC3_2 ;
procedure PROC3_3 ( Signal Resume_Chk : inout Boolean ) is
variable Save_Time : Time ;
begin
Save_Time := Std.Standard.Now ;
wait until Dummy_Cond for P1 ; -- Dynamic
test_report ( "ARCH00009.PROC3_3" ,
"Resume after time on timeout clause expired",
P1 = (Std.Standard.Now - Save_Time)) ;
Resume_Chk <= transport True ;
end PROC3_3 ;
procedure PROC3_4 ( Signal Resume_Chk : inout Boolean ) is
variable Save_Time : Time ;
begin
Save_Time := Std.Standard.Now ;
wait for P1 ; -- Dynamic
test_report ( "ARCH00009.PROC3_4" ,
"Resume after time on timeout clause expired",
P1 = (Std.Standard.Now - Save_Time)) ;
Resume_Chk <= transport True ;
end PROC3_4 ;
procedure PROC4_1 (Time_To_Wait : Time; Signal Resume_Chk : inout Boolean) is
variable Save_Time : Time ;
begin
Save_Time := Std.Standard.Now ;
wait on Dummy until Dummy_Cond for Time_To_Wait ;
test_report ( "ARCH00009.PROC4_1" ,
"Resume after time on timeout clause expired",
Time_To_Wait = (Std.Standard.Now - Save_Time)) ;
Resume_Chk <= transport True ;
end PROC4_1 ;
procedure PROC4_2 (Time_To_Wait : Time; Signal Resume_Chk : inout Boolean) is
variable Save_Time : Time ;
begin
Save_Time := Std.Standard.Now ;
wait on Dummy for Time_To_Wait ;
test_report ( "ARCH00009.PROC4_2" ,
"Resume after time on timeout clause expired",
Time_To_Wait = (Std.Standard.Now - Save_Time)) ;
Resume_Chk <= transport True ;
end PROC4_2 ;
procedure PROC4_3 (Time_To_Wait : Time; Signal Resume_Chk : inout Boolean) is
variable Save_Time : Time ;
begin
Save_Time := Std.Standard.Now ;
wait until Dummy_Cond for Time_To_Wait ;
test_report ( "ARCH00009.PROC4_3" ,
"Resume after time on timeout clause expired",
Time_To_Wait = (Std.Standard.Now - Save_Time)) ;
Resume_Chk <= transport True ;
end PROC4_3 ;
procedure PROC4_4 (Time_To_Wait : Time; Signal Resume_Chk : inout Boolean) is
variable Save_Time : Time ;
begin
Save_Time := Std.Standard.Now ;
wait for Time_To_Wait ;
test_report ( "ARCH00009.PROC4_4" ,
"Resume after time on timeout clause expired",
Time_To_Wait = (Std.Standard.Now - Save_Time)) ;
Resume_Chk <= transport True ;
end PROC4_4 ;
begin
Test_Control :
process ( Num_Cycles )
begin
if Num_Cycles < 11 then
Num_Cycles <= transport Num_Cycles + 1 after 1 ns ;
elsif Num_Cycles = 11 then
-- Verify that in fact, each of the wait statements did resume
test_report ( "ARCH00009" ,
"Wait in P1_1 did resume" ,
P1_1_Did_Resume ) ;
test_report ( "ARCH00009" ,
"Wait in P1_2 did resume" ,
P1_2_Did_Resume ) ;
test_report ( "ARCH00009" ,
"Wait in P1_3 did resume" ,
P1_3_Did_Resume ) ;
test_report ( "ARCH00009" ,
"Wait in P1_4 did resume" ,
P1_4_Did_Resume ) ;
test_report ( "ARCH00009" ,
"Wait in P2_1 did resume" ,
P2_1_Did_Resume ) ;
test_report ( "ARCH00009" ,
"Wait in P2_2 did resume" ,
P2_2_Did_Resume ) ;
test_report ( "ARCH00009" ,
"Wait in P2_3 did resume" ,
P2_3_Did_Resume ) ;
test_report ( "ARCH00009" ,
"Wait in P2_4 did resume" ,
P2_4_Did_Resume ) ;
test_report ( "ARCH00009" ,
"Wait in P3_1 did resume" ,
P3_1_Did_Resume ) ;
test_report ( "ARCH00009" ,
"Wait in P3_2 did resume" ,
P3_2_Did_Resume ) ;
test_report ( "ARCH00009" ,
"Wait in P3_3 did resume" ,
P3_3_Did_Resume ) ;
test_report ( "ARCH00009" ,
"Wait in P3_4 did resume" ,
P3_4_Did_Resume ) ;
test_report ( "ARCH00009" ,
"Wait in PROC1_1 did resume" ,
PROC1_1_Did_Resume ) ;
test_report ( "ARCH00009" ,
"Wait in PROC1_2 did resume" ,
PROC1_2_Did_Resume ) ;
test_report ( "ARCH00009" ,
"Wait in PROC1_3 did resume" ,
PROC1_3_Did_Resume ) ;
test_report ( "ARCH00009" ,
"Wait in PROC1_4 did resume" ,
PROC1_4_Did_Resume ) ;
test_report ( "ARCH00009" ,
"Wait in PROC2_1 did resume" ,
PROC2_1_Did_Resume ) ;
test_report ( "ARCH00009" ,
"Wait in PROC2_2 did resume" ,
PROC2_2_Did_Resume ) ;
test_report ( "ARCH00009" ,
"Wait in PROC2_3 did resume" ,
PROC2_3_Did_Resume ) ;
test_report ( "ARCH00009" ,
"Wait in PROC2_4 did resume" ,
PROC2_4_Did_Resume ) ;
test_report ( "ARCH00009" ,
"Wait in PROC3_1 did resume" ,
PROC3_1_Did_Resume ) ;
test_report ( "ARCH00009" ,
"Wait in PROC3_2 did resume" ,
PROC3_2_Did_Resume ) ;
test_report ( "ARCH00009" ,
"Wait in PROC3_3 did resume" ,
PROC3_3_Did_Resume ) ;
test_report ( "ARCH00009" ,
"Wait in PROC3_4 did resume" ,
PROC3_4_Did_Resume ) ;
test_report ( "ARCH00009" ,
"Wait in PROC4_1 did resume" ,
PROC4_1_Did_Resume ) ;
test_report ( "ARCH00009" ,
"Wait in PROC4_2 did resume" ,
PROC4_2_Did_Resume ) ;
test_report ( "ARCH00009" ,
"Wait in PROC4_3 did resume" ,
PROC4_3_Did_Resume ) ;
test_report ( "ARCH00009" ,
"Wait in PROC4_4 did resume" ,
PROC4_4_Did_Resume ) ;
end if ;
end process Test_Control ;
P1_1 :
process
variable Save_Time : Time ;
begin
Save_Time := Std.Standard.Now ;
wait on Dummy until Dummy_Cond for Time_To_Wait ; -- Locally Static
test_report ( "ARCH00009.P1_1" ,
"Resume after time on timeout clause expired",
Time_To_Wait = (Std.Standard.Now - Save_Time)) ;
P1_1_Did_Resume <= transport True ;
wait;
end process P1_1 ;
P1_2 :
process
variable Save_Time : Time ;
begin
Save_Time := Std.Standard.Now ;
wait on Dummy for Time_To_Wait ; -- Locally Static
test_report ( "ARCH00009.P1_2" ,
"Resume after time on timeout clause expired",
Time_To_Wait = (Std.Standard.Now - Save_Time)) ;
P1_2_Did_Resume <= transport True ;
wait;
end process P1_2 ;
P1_3 :
process
variable Save_Time : Time ;
begin
Save_Time := Std.Standard.Now ;
wait until Dummy_Cond for Time_To_Wait ; -- Locally Static
test_report ( "ARCH00009.P1_3" ,
"Resume after time on timeout clause expired",
Time_To_Wait = (Std.Standard.Now - Save_Time)) ;
P1_3_Did_Resume <= transport True ;
wait;
end process P1_3 ;
P1_4 :
process
variable Save_Time : Time ;
begin
Save_Time := Std.Standard.Now ;
wait for Time_To_Wait ; -- Locally Static
test_report ( "ARCH00009.P1_4" ,
"Resume after time on timeout clause expired",
Time_To_Wait = (Std.Standard.Now - Save_Time)) ;
P1_4_Did_Resume <= transport True ;
wait;
end process P1_4 ;
P2_1 :
process
variable Save_Time : Time ;
begin
Save_Time := Std.Standard.Now ;
wait on Dummy until Dummy_Cond for G1 ; -- Globally Static
test_report ( "ARCH00009.P2_1" ,
"Resume after time on timeout clause expired",
G1 = (Std.Standard.Now - Save_Time)) ;
P2_1_Did_Resume <= transport True ;
wait;
end process P2_1 ;
P2_2 :
process
variable Save_Time : Time ;
begin
Save_Time := Std.Standard.Now ;
wait on Dummy for G1 ; -- Globally Static
test_report ( "ARCH00009.P2_2" ,
"Resume after time on timeout clause expired",
G1 = (Std.Standard.Now - Save_Time)) ;
P2_2_Did_Resume <= transport True ;
wait;
end process P2_2 ;
P2_3 :
process
variable Save_Time : Time ;
begin
Save_Time := Std.Standard.Now ;
wait until Dummy_Cond for G1 ; -- Globally Static
test_report ( "ARCH00009.P2_3" ,
"Resume after time on timeout clause expired",
G1 = (Std.Standard.Now - Save_Time)) ;
P2_3_Did_Resume <= transport True ;
wait;
end process P2_3 ;
P2_4 :
process
variable Save_Time : Time ;
begin
Save_Time := Std.Standard.Now ;
wait for G1 ; -- Globally Static
test_report ( "ARCH00009.P2_4" ,
"Resume after time on timeout clause expired",
G1 = (Std.Standard.Now - Save_Time)) ;
P2_4_Did_Resume <= transport True ;
wait;
end process P2_4 ;
P3_1 :
process
variable Save_Time : Time ;
begin
Save_Time := Std.Standard.Now ;
wait on Dummy until Dummy_Cond for P1 ; -- Dynamic
test_report ( "ARCH00009.P3_1" ,
"Resume after time on timeout clause expired",
P1 = (Std.Standard.Now - Save_Time)) ;
P3_1_Did_Resume <= transport True ;
wait;
end process P3_1 ;
P3_2 :
process
variable Save_Time : Time ;
begin
Save_Time := Std.Standard.Now ;
wait on Dummy for P1 ; -- Dynamic
test_report ( "ARCH00009.P3_2" ,
"Resume after time on timeout clause expired",
P1 = (Std.Standard.Now - Save_Time)) ;
P3_2_Did_Resume <= transport True ;
wait;
end process P3_2 ;
P3_3 :
process
variable Save_Time : Time ;
begin
Save_Time := Std.Standard.Now ;
wait until Dummy_Cond for P1 ; -- Dynamic
test_report ( "ARCH00009.P3_3" ,
"Resume after time on timeout clause expired",
P1 = (Std.Standard.Now - Save_Time)) ;
P3_3_Did_Resume <= transport True ;
wait;
end process P3_3 ;
P3_4 :
process
variable Save_Time : Time ;
begin
Save_Time := Std.Standard.Now ;
wait for P1 ; -- Dynamic
test_report ( "ARCH00009.P3_4" ,
"Resume after time on timeout clause expired",
P1 = (Std.Standard.Now - Save_Time)) ;
P3_4_Did_Resume <= transport True ;
wait;
end process P3_4 ;
Q1_1 :
process
begin
PROC1_1 (PROC1_1_Did_Resume);
wait;
end process Q1_1 ;
Q1_2 :
process
begin
PROC1_2 (PROC1_2_Did_Resume);
wait;
end process Q1_2 ;
Q1_3 :
process
begin
PROC1_3 (PROC1_3_Did_Resume);
wait;
end process Q1_3 ;
Q1_4 :
process
begin
PROC1_4 (PROC1_4_Did_Resume);
wait;
end process Q1_4 ;
Q2_1 :
process
begin
PROC2_1 (PROC2_1_Did_Resume);
wait;
end process Q2_1 ;
Q2_2 :
process
begin
PROC2_2 (PROC2_2_Did_Resume);
wait;
end process Q2_2 ;
Q2_3 :
process
begin
PROC2_3 (PROC2_3_Did_Resume);
wait;
end process Q2_3 ;
Q2_4 :
process
begin
PROC2_4 (PROC2_4_Did_Resume);
wait;
end process Q2_4 ;
Q3_1 :
process
begin
PROC3_1 (PROC3_1_Did_Resume);
wait;
end process Q3_1 ;
Q3_2 :
process
begin
PROC3_2 (PROC3_2_Did_Resume);
wait;
end process Q3_2 ;
Q3_3 :
process
begin
PROC3_3 (PROC3_3_Did_Resume);
wait;
end process Q3_3 ;
Q3_4 :
process
begin
PROC3_4 (PROC3_4_Did_Resume);
wait;
end process Q3_4 ;
Q4_1 :
process
begin
PROC4_1 (Time_To_Wait, PROC4_1_Did_Resume) ;
wait;
end process Q4_1 ;
Q4_2 :
process
begin
PROC4_2 (G1, PROC4_2_Did_Resume) ;
wait;
end process Q4_2 ;
Q4_3 :
process
begin
PROC4_3 (P1, PROC4_3_Did_Resume) ;
wait;
end process Q4_3 ;
Q4_4 :
process
begin
PROC4_4 (P1, PROC4_4_Did_Resume) ;
wait;
end process Q4_4 ;
end ARCH00009 ;
entity ENT00009_Test_Bench is
end ENT00009_Test_Bench ;
architecture ARCH00009_Test_Bench of ENT00009_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00009 ( ARCH00009 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00009_Test_Bench ;
|
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.iface.all;
use work.amba.all;
use work.mdctrom256.all;
package mdctlib is
constant TRIGBITS: integer := 14;
--constant rom_lenght: integer:=14;
constant cPI3_8 :std_logic_vector (31 downto 0) := "00000000000000000001100001111110";
constant cPI2_8 :std_logic_vector (31 downto 0) := "00000000000000000010110101000001";
constant cPI1_8 :std_logic_vector (31 downto 0) := "00000000000000000011101100100001";
constant zero32 : std_logic_vector (31 downto 0):= "00000000000000000000000000000000";
type btf8_data is array(0 to 7) of std_logic_vector (31 downto 0);
type btf16_data is array(0 to 1) of btf8_data;
type btf32_data is array(0 to 1) of btf16_data;
type block4_data is array(0 to 3) of std_logic_vector (31 downto 0);
type block8_data is array(0 to 7) of std_logic_vector (31 downto 0);
type block16_data is array(0 to 15) of std_logic_vector (31 downto 0);
type block32_data is array(0 to 31) of std_logic_vector (31 downto 0);
--type rom_table is array (0 to rom_lenght-1) of std_logic_vector (31 downto 0);
type in_multadd is record
op1_m1: std_logic_vector (31 downto 0);
op2_m1: std_logic_vector (31 downto 0);
op1_m2: std_logic_vector (31 downto 0);
op2_m2: std_logic_vector (31 downto 0);
add_fun: std_logic;
end record;
type out_multadd is record
r_m1: std_logic_vector (31 downto 0);
r_m2: std_logic_vector (31 downto 0);
r_mult: std_logic_vector (31 downto 0);
end record;
type in_addbank is record
op1_a1 : std_logic_vector(31 downto 0);
op2_a1 : std_logic_vector(31 downto 0);
op1_a2 : std_logic_vector(31 downto 0);
op2_a2 : std_logic_vector(31 downto 0);
op1_a3 : std_logic_vector(31 downto 0);
op2_a3 : std_logic_vector(31 downto 0);
op1_s1 : std_logic_vector(31 downto 0);
op2_s1 : std_logic_vector(31 downto 0);
op1_s2 : std_logic_vector(31 downto 0);
op2_s2 : std_logic_vector(31 downto 0);
op1_s3 : std_logic_vector(31 downto 0);
op2_s3 : std_logic_vector(31 downto 0);
end record;
type out_addbank is record
r_a1: std_logic_vector(31 downto 0);
r_a2: std_logic_vector(31 downto 0);
r_a3: std_logic_vector(31 downto 0);
r_s1: std_logic_vector(31 downto 0);
r_s2: std_logic_vector(31 downto 0);
r_s3: std_logic_vector(31 downto 0);
end record;
type ctrlregs is record
-- registers and signals used to communicate mdctctrl with amba wrapper
ntoprocess : std_logic_vector(5 downto 0); -- number of resting elements to be processed
memwr : std_logic; -- '1' for write, '0' for read
startadr: std_logic_vector(31 downto 0); -- start address of current block
incr : std_logic; -- Bytes increment for blocks ('0'=>4 '1'=>8)
pos : std_logic_vector(1 downto 0);
-- Pointer to read/store from buffer
-- (00,01,10,11)=>(0,4,8,12)
finish : std_logic; -- '1' if whole mdct is finished
end record;
type mdctregs is record
-- ***********************
-- memory mapped registers
-- Control register
-- bit 0 of 0x80000300
mdctenreq : std_logic; -- mdct function enabled
-- bit 1 of 0x80000300
irqen : std_logic; -- enable interrupt
-- bit 2 of 0x80000300
irq : std_logic; -- irq request
-- 10 bit at 0x80000304
size : std_logic; -- number of points of mdct '0'=>256 '1'=>2048
-- 32 bit at 0x80000308
rdstartaddr : std_logic_vector(31 downto 0); -- read dma transfer start address
-- 32 bit at 0x800030c
wrstartaddr : std_logic_vector(31 downto 0); -- write dma transfer start address
-- Status register
-- bit 0 of 0x80000310
ready : std_logic; -- '1' if function done, '0' if busy / read only
-- bit 1 of 0x80000310
memwr : std_logic; -- '1' if writting, '0' if reading data from memory /read only
-- 32 bit at 0x80000314
memoryadr : std_logic_vector(31 downto 0); -- actual dma address /read only
-- memory mapped registers end
-- ***************************
-- internal registers
mdcten : std_logic;
dmatransfreq : std_logic;
ntoprocess : std_logic_vector(5 downto 0); -- number of resting elements to be processed
inputdata : block32_data; -- original data from memory
result : block32_data; -- result after mdct to store in memory
-- amba status registers
busact : std_logic;
busown : std_logic;
busgrant : std_logic;
busown2cyc : std_logic;
end record;
component mdct
port (
rst : in std_logic;
clk : in clk_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
irq : out std_logic
);
end component;
component butterfly_8
port (
rst : in std_logic;
clk : in std_logic;
datain : in btf8_data;
dataout : out btf8_data;
enabled : in std_logic
);
end component;
component butterfly_16
port (
rst : in std_logic;
clk : in std_logic;
datain : in btf16_data;
dataout : out btf16_data;
enabled : in std_logic
);
end component;
component butterfly_32
port (
rst : in std_logic;
clk : in std_logic;
datain : in btf32_data;
dataout : out btf32_data;
enabled : in std_logic;
ready : out std_logic
);
end component;
function MULT_NORM(w :std_logic_vector (63 downto 0))
return std_logic_vector;
function HALVE(w :std_logic_vector (31 downto 0))
return std_logic_vector;
function BT32_to_BLOCK32(bt: btf32_data )
return block32_data;
function BLOCK32_to_BT32(b: block32_data )
return btf32_data;
function BLOCK8_to_BLOCK16(b1: block8_data; b2: block8_data)
return block16_data;
function BLOCK16_to_BLOCK8(b: block16_data; x: integer range 0 to 1)
return block8_data;
function BLOCK32_to_BLOCK4(b: block32_data)
return block4_data;
function BLOCK4_to_BLOCK32(b: block4_data)
return block32_data;
function ROM_to_BLOCK4(t: rom_table; start:integer)
return block4_data;end;
package body mdctlib is
function MULT_NORM(w :std_logic_vector (63 downto 0))
return std_logic_vector is
variable result: std_logic_vector (31 downto 0);
variable rshift: bit_vector (63 downto 0);
begin
rshift := TO_BITVECTOR (w); -- convert to bitvector in order to prepare shift
rshift := rshift sra TRIGBITS; -- shift arithmetic right
result := TO_STDLOGICVECTOR(rshift(31 downto 0));-- convert to std_logic_vector again
return result;
end MULT_NORM;
function HALVE(w :std_logic_vector (31 downto 0))
return std_logic_vector is
variable result: std_logic_vector (31 downto 0);
variable rshift: bit_vector (31 downto 0);
begin
rshift := TO_BITVECTOR (w); -- convert to bitvector in order to prepare shift
rshift := rshift sra 1; -- shift arithmetic right
result := TO_STDLOGICVECTOR(rshift);-- convert to std_logic_vector again
return result;
end HALVE;
function BT32_to_BLOCK32(bt: btf32_data )
return block32_data is
variable result: block32_data;
begin
for i in 0 to 1 loop
for j in 0 to 1 loop
for k in 0 to 7 loop
result (8*i + 8*(j+i) + k) := bt (i)(j)(k);
end loop;
end loop;
end loop;
return result;
end BT32_to_BLOCK32;
function BLOCK32_to_BT32(b: block32_data )
return btf32_data is
variable result: btf32_data;
begin
for i in 0 to 1 loop
for j in 0 to 1 loop
for k in 0 to 7 loop
result (i)(j)(k) := b (8*i + 8*(j+i) + k) ;
end loop;
end loop;
end loop;
return result;
end BLOCK32_to_BT32;
function BLOCK8_to_BLOCK16(b1: block8_data; b2: block8_data)
return block16_data is
variable result: block16_data;
begin
for i in 0 to 7 loop
result(i) := b1(i);
end loop;
for i in 8 to 15 loop
result(i) := b2(i-8);
end loop;
return result;
end BLOCK8_to_BLOCK16;
function BLOCK16_to_BLOCK8(b: block16_data; x: integer range 0 to 1)
return block8_data is
variable result: block8_data;
begin
for i in 0 to 7 loop
result(i) := b(i + x*8);
end loop;
return result;
end BLOCK16_to_BLOCK8;
function BLOCK32_to_BLOCK4(b: block32_data)
return block4_data is
variable result: block4_data;
begin
for i in 0 to 3 loop
result(i) := b(i);
end loop;
return result;
end BLOCK32_to_BLOCK4;
function BLOCK4_to_BLOCK32(b: block4_data)
return block32_data is
variable result: block32_data;
begin
for i in 0 to 3 loop
result(i) := b(i);
end loop;
return result;
end BLOCK4_to_BLOCK32;
function ROM_to_BLOCK4(t: rom_table; start:integer)
return block4_data is
variable result: block4_data;
begin
for i in 0 to 3 loop
result(i) := t(i+start);
end loop;
return result;
end ROM_to_BLOCK4;
end; -- end mdct lib
|
----------------------------------------------------------------------------------
-- Company: Laboratoire Leprince-Ringuet
-- Engineer:
--
-- Create Date: 12:09:35 10/14/2011
-- Design Name:
-- Module Name: crc32_8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- CRC Calculation
-- This VHDL code was generated using CRCGEN.PL version 1.7
-- Last Modified: 01/02/2002
-- Options Used:
-- Module Name = crc32
-- CRC Width = 32
-- Data Width = 8
-- CRC Init = F
-- Polynomial = [0 -> 32]
-- 1 1 1 0 1 1 0 1 1 0 1 1 1 0 0 0 1 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 1
--
-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
-- WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
-- Copyright (c) 2001,2002 Xilinx, Inc. All rights reserved.
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity crc32_8 is Port(
CRC_REG : out STD_LOGIC_VECTOR(31 downto 0);
CRC : out STD_LOGIC_VECTOR(7 downto 0);
D : in STD_LOGIC_VECTOR(7 downto 0);
CALC : in STD_LOGIC;
INIT : in STD_LOGIC;--synchronous reset
D_VALID : in STD_LOGIC;
CLK : in STD_LOGIC;
RESET : in STD_LOGIC);--asynchronous reset
end crc32_8;
architecture Behavioral of crc32_8 is
signal next_crc : STD_LOGIC_VECTOR(31 downto 0);
signal crcreg : STD_LOGIC_VECTOR(31 downto 0);
begin
CRC_REG <= crcreg;
--CRC XOR equations
next_crc(0) <= crcreg(30) xor D(1) xor crcreg(24) xor D(7);
next_crc(1) <= D(6) xor D(7) xor D(0) xor crcreg(30) xor crcreg(31) xor D(1) xor crcreg(24) xor crcreg(25);
next_crc(2) <= crcreg(26) xor D(5) xor D(6) xor D(7) xor crcreg(30) xor D(0) xor D(1) xor crcreg(31) xor crcreg(24) xor crcreg(25);
next_crc(3) <= D(4) xor crcreg(26) xor D(5) xor crcreg(27) xor D(6) xor D(0) xor crcreg(31) xor crcreg(25);
next_crc(4) <= D(4) xor crcreg(26) xor D(5) xor crcreg(27) xor crcreg(28) xor D(7) xor crcreg(30) xor D(1) xor crcreg(24) xor D(3);
next_crc(5) <= D(4) xor crcreg(27) xor D(6) xor crcreg(28) xor D(7) xor crcreg(29) xor crcreg(30) xor D(0) xor D(1) xor crcreg(31) xor D(2) xor crcreg(24) xor D(3) xor crcreg(25);
next_crc(6) <= crcreg(26) xor D(5) xor D(6) xor crcreg(28) xor crcreg(29) xor D(0) xor crcreg(30) xor crcreg(31) xor D(1) xor D(2) xor D(3) xor crcreg(25);
next_crc(7) <= D(4) xor crcreg(26) xor D(5) xor crcreg(27) xor D(7) xor crcreg(29) xor D(0) xor crcreg(31) xor D(2) xor crcreg(24);
next_crc(8) <= D(4) xor crcreg(27) xor D(6) xor crcreg(28) xor D(7) xor crcreg(24) xor crcreg(0) xor D(3) xor crcreg(25);
next_crc(9) <= crcreg(26) xor D(5) xor D(6) xor crcreg(28) xor crcreg(29) xor D(2) xor D(3) xor crcreg(25) xor crcreg(1);
next_crc(10) <= D(4) xor crcreg(26) xor crcreg(2) xor D(5) xor crcreg(27) xor D(7) xor crcreg(29) xor D(2) xor crcreg(24);
next_crc(11) <= D(4) xor crcreg(27) xor D(6) xor crcreg(3) xor crcreg(28) xor D(7) xor crcreg(24) xor D(3) xor crcreg(25);
next_crc(12) <= crcreg(26) xor D(5) xor D(6) xor crcreg(28) xor D(7) xor crcreg(4) xor crcreg(29) xor crcreg(30) xor D(1) xor D(2) xor crcreg(24) xor D(3) xor crcreg(25);
next_crc(13) <= D(4) xor crcreg(26) xor D(5) xor crcreg(27) xor D(6) xor crcreg(29) xor D(0) xor crcreg(30) xor crcreg(5) xor crcreg(31) xor D(1) xor D(2) xor crcreg(25);
next_crc(14) <= D(4) xor crcreg(26) xor D(5) xor crcreg(27) xor crcreg(28) xor crcreg(30) xor D(0) xor D(1) xor crcreg(31) xor crcreg(6) xor D(3);
next_crc(15) <= D(4) xor crcreg(27) xor crcreg(28) xor crcreg(29) xor D(0) xor crcreg(31) xor D(2) xor crcreg(7) xor D(3);
next_crc(16) <= crcreg(28) xor D(7) xor crcreg(29) xor D(2) xor crcreg(24) xor D(3) xor crcreg(8);
next_crc(17) <= crcreg(9) xor D(6) xor crcreg(29) xor crcreg(30) xor D(1) xor D(2) xor crcreg(25);
next_crc(18) <= crcreg(26) xor D(5) xor crcreg(10) xor crcreg(30) xor D(0) xor D(1) xor crcreg(31);
next_crc(19) <= D(4) xor crcreg(27) xor crcreg(11) xor D(0) xor crcreg(31);
next_crc(20) <= crcreg(28) xor crcreg(12) xor D(3);
next_crc(21) <= crcreg(29) xor crcreg(13) xor D(2);
next_crc(22) <= D(7) xor crcreg(14) xor crcreg(24);
next_crc(23) <= D(6) xor D(7) xor crcreg(30) xor D(1) xor crcreg(15) xor crcreg(24) xor crcreg(25);
next_crc(24) <= crcreg(26) xor D(5) xor D(6) xor D(0) xor crcreg(31) xor crcreg(16) xor crcreg(25);
next_crc(25) <= D(4) xor crcreg(17) xor crcreg(26) xor D(5) xor crcreg(27);
next_crc(26) <= D(4) xor crcreg(18) xor crcreg(27) xor crcreg(28) xor D(7) xor crcreg(30) xor D(1) xor crcreg(24) xor D(3);
next_crc(27) <= D(6) xor crcreg(19) xor crcreg(28) xor crcreg(29) xor D(0) xor crcreg(31) xor D(2) xor D(3) xor crcreg(25);
next_crc(28) <= crcreg(26) xor D(5) xor crcreg(20) xor crcreg(29) xor crcreg(30) xor D(1) xor D(2);
next_crc(29) <= D(4) xor crcreg(27) xor crcreg(21) xor crcreg(30) xor D(0) xor D(1) xor crcreg(31);
next_crc(30) <= crcreg(28) xor D(0) xor crcreg(22) xor crcreg(31) xor D(3);
next_crc(31) <= crcreg(29) xor crcreg(23) xor D(2);
-- Infer CRC-32 registers
-- The crcreg register stores the CRC-32 value.
-- CRC is the most significant 8 bits of the CRC-32 value.
--
-- Truth Table:
-- -----+---------+----------+----------------------------------------------
-- CALC | D_VALID | crcreg | CRC
-- -----+---------+----------+----------------------------------------------
-- 0 | 0 | crcreg | CRC
-- 0 | 1 | shift | bit-swapped, complimented msbyte of crcreg
-- 1 | 0 | crcreg | CRC
-- 1 | 1 | next_crc | bit-swapped, complimented msbyte of next_crc
process(CLK, RESET)
begin
if RESET = '0' then
crcreg <= x"FFFFFFFF";
CRC <= x"FF";
elsif CLK'event and CLK = '1' then
if INIT = '1' then
crcreg <= x"FFFFFFFF";
CRC <= x"FF";
elsif CALC = '1' and D_VALID = '1' then
crcreg <= next_crc;
CRC <= not(next_crc(24) & next_crc(25) & next_crc(26) & next_crc(27) &
next_crc(28) & next_crc(29) & next_crc(30) & next_crc(31));
elsif CALC = '0' and D_VALID = '1' then
crcreg <= crcreg(23 downto 0) & x"FF";
CRC <= not(crcreg(16) & crcreg(17) & crcreg(18) & crcreg(19) &
crcreg(20) & crcreg(21) & crcreg(22) & crcreg(23));
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
-- flash_2mx16_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library xps_mch_emc_v3_01_a;
use xps_mch_emc_v3_01_a.all;
entity flash_2mx16_wrapper is
port (
MCH_SPLB_Clk : in std_logic;
RdClk : in std_logic;
MCH_SPLB_Rst : in std_logic;
MCH0_Access_Control : in std_logic;
MCH0_Access_Data : in std_logic_vector(0 to 31);
MCH0_Access_Write : in std_logic;
MCH0_Access_Full : out std_logic;
MCH0_ReadData_Control : out std_logic;
MCH0_ReadData_Data : out std_logic_vector(0 to 31);
MCH0_ReadData_Read : in std_logic;
MCH0_ReadData_Exists : out std_logic;
MCH1_Access_Control : in std_logic;
MCH1_Access_Data : in std_logic_vector(0 to 31);
MCH1_Access_Write : in std_logic;
MCH1_Access_Full : out std_logic;
MCH1_ReadData_Control : out std_logic;
MCH1_ReadData_Data : out std_logic_vector(0 to 31);
MCH1_ReadData_Read : in std_logic;
MCH1_ReadData_Exists : out std_logic;
MCH2_Access_Control : in std_logic;
MCH2_Access_Data : in std_logic_vector(0 to 31);
MCH2_Access_Write : in std_logic;
MCH2_Access_Full : out std_logic;
MCH2_ReadData_Control : out std_logic;
MCH2_ReadData_Data : out std_logic_vector(0 to 31);
MCH2_ReadData_Read : in std_logic;
MCH2_ReadData_Exists : out std_logic;
MCH3_Access_Control : in std_logic;
MCH3_Access_Data : in std_logic_vector(0 to 31);
MCH3_Access_Write : in std_logic;
MCH3_Access_Full : out std_logic;
MCH3_ReadData_Control : out std_logic;
MCH3_ReadData_Data : out std_logic_vector(0 to 31);
MCH3_ReadData_Read : in std_logic;
MCH3_ReadData_Exists : out std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 3);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 31);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 31);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 1);
Sl_MWrErr : out std_logic_vector(0 to 1);
Sl_MRdErr : out std_logic_vector(0 to 1);
Sl_MIRQ : out std_logic_vector(0 to 1);
Mem_DQ_I : in std_logic_vector(0 to 15);
Mem_DQ_O : out std_logic_vector(0 to 15);
Mem_DQ_T : out std_logic_vector(0 to 15);
Mem_A : out std_logic_vector(0 to 31);
Mem_RPN : out std_logic;
Mem_CEN : out std_logic_vector(0 to 0);
Mem_OEN : out std_logic_vector(0 to 0);
Mem_WEN : out std_logic;
Mem_QWEN : out std_logic_vector(0 to 1);
Mem_BEN : out std_logic_vector(0 to 1);
Mem_CE : out std_logic_vector(0 to 0);
Mem_ADV_LDN : out std_logic;
Mem_LBON : out std_logic;
Mem_CKEN : out std_logic;
Mem_RNW : out std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of flash_2mx16_wrapper : entity is "xps_mch_emc_v3_01_a";
end flash_2mx16_wrapper;
architecture STRUCTURE of flash_2mx16_wrapper is
component xps_mch_emc is
generic (
C_FAMILY : STRING;
C_NUM_BANKS_MEM : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_PRIORITY_MODE : INTEGER;
C_INCLUDE_PLB_IPIF : INTEGER;
C_INCLUDE_WRBUF : INTEGER;
C_SPLB_MID_WIDTH : INTEGER;
C_SPLB_NUM_MASTERS : INTEGER;
C_SPLB_P2P : INTEGER;
C_SPLB_DWIDTH : INTEGER;
C_MCH_SPLB_AWIDTH : INTEGER;
C_SPLB_SMALLEST_MASTER : INTEGER;
C_MCH_NATIVE_DWIDTH : INTEGER;
C_MCH_SPLB_CLK_PERIOD_PS : INTEGER;
C_MEM0_BASEADDR : std_logic_vector;
C_MEM0_HIGHADDR : std_logic_vector;
C_MEM1_BASEADDR : std_logic_vector;
C_MEM1_HIGHADDR : std_logic_vector;
C_MEM2_BASEADDR : std_logic_vector;
C_MEM2_HIGHADDR : std_logic_vector;
C_MEM3_BASEADDR : std_logic_vector;
C_MEM3_HIGHADDR : std_logic_vector;
C_PAGEMODE_FLASH_0 : INTEGER;
C_PAGEMODE_FLASH_1 : INTEGER;
C_PAGEMODE_FLASH_2 : INTEGER;
C_PAGEMODE_FLASH_3 : INTEGER;
C_INCLUDE_NEGEDGE_IOREGS : INTEGER;
C_MEM0_WIDTH : INTEGER;
C_MEM1_WIDTH : INTEGER;
C_MEM2_WIDTH : INTEGER;
C_MEM3_WIDTH : INTEGER;
C_MAX_MEM_WIDTH : INTEGER;
C_INCLUDE_DATAWIDTH_MATCHING_0 : INTEGER;
C_INCLUDE_DATAWIDTH_MATCHING_1 : INTEGER;
C_INCLUDE_DATAWIDTH_MATCHING_2 : INTEGER;
C_INCLUDE_DATAWIDTH_MATCHING_3 : INTEGER;
C_SYNCH_MEM_0 : INTEGER;
C_SYNCH_PIPEDELAY_0 : INTEGER;
C_TCEDV_PS_MEM_0 : INTEGER;
C_TAVDV_PS_MEM_0 : INTEGER;
C_TPACC_PS_FLASH_0 : INTEGER;
C_THZCE_PS_MEM_0 : INTEGER;
C_THZOE_PS_MEM_0 : INTEGER;
C_TWC_PS_MEM_0 : INTEGER;
C_TWP_PS_MEM_0 : INTEGER;
C_TLZWE_PS_MEM_0 : INTEGER;
C_SYNCH_MEM_1 : INTEGER;
C_SYNCH_PIPEDELAY_1 : INTEGER;
C_TCEDV_PS_MEM_1 : INTEGER;
C_TAVDV_PS_MEM_1 : INTEGER;
C_TPACC_PS_FLASH_1 : INTEGER;
C_THZCE_PS_MEM_1 : INTEGER;
C_THZOE_PS_MEM_1 : INTEGER;
C_TWC_PS_MEM_1 : INTEGER;
C_TWP_PS_MEM_1 : INTEGER;
C_TLZWE_PS_MEM_1 : INTEGER;
C_SYNCH_MEM_2 : INTEGER;
C_SYNCH_PIPEDELAY_2 : INTEGER;
C_TCEDV_PS_MEM_2 : INTEGER;
C_TAVDV_PS_MEM_2 : INTEGER;
C_TPACC_PS_FLASH_2 : INTEGER;
C_THZCE_PS_MEM_2 : INTEGER;
C_THZOE_PS_MEM_2 : INTEGER;
C_TWC_PS_MEM_2 : INTEGER;
C_TWP_PS_MEM_2 : INTEGER;
C_TLZWE_PS_MEM_2 : INTEGER;
C_SYNCH_MEM_3 : INTEGER;
C_SYNCH_PIPEDELAY_3 : INTEGER;
C_TCEDV_PS_MEM_3 : INTEGER;
C_TAVDV_PS_MEM_3 : INTEGER;
C_TPACC_PS_FLASH_3 : INTEGER;
C_THZCE_PS_MEM_3 : INTEGER;
C_THZOE_PS_MEM_3 : INTEGER;
C_TWC_PS_MEM_3 : INTEGER;
C_TWP_PS_MEM_3 : INTEGER;
C_TLZWE_PS_MEM_3 : INTEGER;
C_MCH0_PROTOCOL : INTEGER;
C_MCH0_ACCESSBUF_DEPTH : INTEGER;
C_MCH0_RDDATABUF_DEPTH : INTEGER;
C_MCH1_PROTOCOL : INTEGER;
C_MCH1_ACCESSBUF_DEPTH : INTEGER;
C_MCH1_RDDATABUF_DEPTH : INTEGER;
C_MCH2_PROTOCOL : INTEGER;
C_MCH2_ACCESSBUF_DEPTH : INTEGER;
C_MCH2_RDDATABUF_DEPTH : INTEGER;
C_MCH3_PROTOCOL : INTEGER;
C_MCH3_ACCESSBUF_DEPTH : INTEGER;
C_MCH3_RDDATABUF_DEPTH : INTEGER;
C_XCL0_LINESIZE : INTEGER;
C_XCL0_WRITEXFER : INTEGER;
C_XCL1_LINESIZE : INTEGER;
C_XCL1_WRITEXFER : INTEGER;
C_XCL2_LINESIZE : INTEGER;
C_XCL2_WRITEXFER : INTEGER;
C_XCL3_LINESIZE : INTEGER;
C_XCL3_WRITEXFER : INTEGER
);
port (
MCH_SPLB_Clk : in std_logic;
RdClk : in std_logic;
MCH_SPLB_Rst : in std_logic;
MCH0_Access_Control : in std_logic;
MCH0_Access_Data : in std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH0_Access_Write : in std_logic;
MCH0_Access_Full : out std_logic;
MCH0_ReadData_Control : out std_logic;
MCH0_ReadData_Data : out std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH0_ReadData_Read : in std_logic;
MCH0_ReadData_Exists : out std_logic;
MCH1_Access_Control : in std_logic;
MCH1_Access_Data : in std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH1_Access_Write : in std_logic;
MCH1_Access_Full : out std_logic;
MCH1_ReadData_Control : out std_logic;
MCH1_ReadData_Data : out std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH1_ReadData_Read : in std_logic;
MCH1_ReadData_Exists : out std_logic;
MCH2_Access_Control : in std_logic;
MCH2_Access_Data : in std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH2_Access_Write : in std_logic;
MCH2_Access_Full : out std_logic;
MCH2_ReadData_Control : out std_logic;
MCH2_ReadData_Data : out std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH2_ReadData_Read : in std_logic;
MCH2_ReadData_Exists : out std_logic;
MCH3_Access_Control : in std_logic;
MCH3_Access_Data : in std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH3_Access_Write : in std_logic;
MCH3_Access_Full : out std_logic;
MCH3_ReadData_Control : out std_logic;
MCH3_ReadData_Data : out std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH3_ReadData_Read : in std_logic;
MCH3_ReadData_Exists : out std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1));
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1));
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Mem_DQ_I : in std_logic_vector(0 to (C_MAX_MEM_WIDTH-1));
Mem_DQ_O : out std_logic_vector(0 to (C_MAX_MEM_WIDTH-1));
Mem_DQ_T : out std_logic_vector(0 to (C_MAX_MEM_WIDTH-1));
Mem_A : out std_logic_vector(0 to (C_MCH_SPLB_AWIDTH-1));
Mem_RPN : out std_logic;
Mem_CEN : out std_logic_vector(0 to (C_NUM_BANKS_MEM-1));
Mem_OEN : out std_logic_vector(0 to (C_NUM_BANKS_MEM-1));
Mem_WEN : out std_logic;
Mem_QWEN : out std_logic_vector(0 to ((C_MAX_MEM_WIDTH/8)-1));
Mem_BEN : out std_logic_vector(0 to ((C_MAX_MEM_WIDTH/8)-1));
Mem_CE : out std_logic_vector(0 to (C_NUM_BANKS_MEM-1));
Mem_ADV_LDN : out std_logic;
Mem_LBON : out std_logic;
Mem_CKEN : out std_logic;
Mem_RNW : out std_logic
);
end component;
begin
FLASH_2Mx16 : xps_mch_emc
generic map (
C_FAMILY => "spartan3a",
C_NUM_BANKS_MEM => 1,
C_NUM_CHANNELS => 1,
C_PRIORITY_MODE => 0,
C_INCLUDE_PLB_IPIF => 1,
C_INCLUDE_WRBUF => 1,
C_SPLB_MID_WIDTH => 1,
C_SPLB_NUM_MASTERS => 2,
C_SPLB_P2P => 0,
C_SPLB_DWIDTH => 32,
C_MCH_SPLB_AWIDTH => 32,
C_SPLB_SMALLEST_MASTER => 32,
C_MCH_NATIVE_DWIDTH => 32,
C_MCH_SPLB_CLK_PERIOD_PS => 15000,
C_MEM0_BASEADDR => X"84c00000",
C_MEM0_HIGHADDR => X"84ffffff",
C_MEM1_BASEADDR => X"ffffffff",
C_MEM1_HIGHADDR => X"00000000",
C_MEM2_BASEADDR => X"ffffffff",
C_MEM2_HIGHADDR => X"00000000",
C_MEM3_BASEADDR => X"ffffffff",
C_MEM3_HIGHADDR => X"00000000",
C_PAGEMODE_FLASH_0 => 0,
C_PAGEMODE_FLASH_1 => 0,
C_PAGEMODE_FLASH_2 => 0,
C_PAGEMODE_FLASH_3 => 0,
C_INCLUDE_NEGEDGE_IOREGS => 0,
C_MEM0_WIDTH => 16,
C_MEM1_WIDTH => 32,
C_MEM2_WIDTH => 32,
C_MEM3_WIDTH => 32,
C_MAX_MEM_WIDTH => 16,
C_INCLUDE_DATAWIDTH_MATCHING_0 => 1,
C_INCLUDE_DATAWIDTH_MATCHING_1 => 0,
C_INCLUDE_DATAWIDTH_MATCHING_2 => 0,
C_INCLUDE_DATAWIDTH_MATCHING_3 => 0,
C_SYNCH_MEM_0 => 0,
C_SYNCH_PIPEDELAY_0 => 2,
C_TCEDV_PS_MEM_0 => 90000,
C_TAVDV_PS_MEM_0 => 90000,
C_TPACC_PS_FLASH_0 => 25000,
C_THZCE_PS_MEM_0 => 20000,
C_THZOE_PS_MEM_0 => 20000,
C_TWC_PS_MEM_0 => 90000,
C_TWP_PS_MEM_0 => 90000,
C_TLZWE_PS_MEM_0 => 35000,
C_SYNCH_MEM_1 => 0,
C_SYNCH_PIPEDELAY_1 => 2,
C_TCEDV_PS_MEM_1 => 15000,
C_TAVDV_PS_MEM_1 => 15000,
C_TPACC_PS_FLASH_1 => 25000,
C_THZCE_PS_MEM_1 => 7000,
C_THZOE_PS_MEM_1 => 7000,
C_TWC_PS_MEM_1 => 15000,
C_TWP_PS_MEM_1 => 12000,
C_TLZWE_PS_MEM_1 => 0,
C_SYNCH_MEM_2 => 0,
C_SYNCH_PIPEDELAY_2 => 2,
C_TCEDV_PS_MEM_2 => 15000,
C_TAVDV_PS_MEM_2 => 15000,
C_TPACC_PS_FLASH_2 => 25000,
C_THZCE_PS_MEM_2 => 7000,
C_THZOE_PS_MEM_2 => 7000,
C_TWC_PS_MEM_2 => 15000,
C_TWP_PS_MEM_2 => 12000,
C_TLZWE_PS_MEM_2 => 0,
C_SYNCH_MEM_3 => 0,
C_SYNCH_PIPEDELAY_3 => 2,
C_TCEDV_PS_MEM_3 => 15000,
C_TAVDV_PS_MEM_3 => 15000,
C_TPACC_PS_FLASH_3 => 25000,
C_THZCE_PS_MEM_3 => 7000,
C_THZOE_PS_MEM_3 => 7000,
C_TWC_PS_MEM_3 => 15000,
C_TWP_PS_MEM_3 => 12000,
C_TLZWE_PS_MEM_3 => 0,
C_MCH0_PROTOCOL => 0,
C_MCH0_ACCESSBUF_DEPTH => 16,
C_MCH0_RDDATABUF_DEPTH => 16,
C_MCH1_PROTOCOL => 0,
C_MCH1_ACCESSBUF_DEPTH => 16,
C_MCH1_RDDATABUF_DEPTH => 16,
C_MCH2_PROTOCOL => 0,
C_MCH2_ACCESSBUF_DEPTH => 16,
C_MCH2_RDDATABUF_DEPTH => 16,
C_MCH3_PROTOCOL => 0,
C_MCH3_ACCESSBUF_DEPTH => 16,
C_MCH3_RDDATABUF_DEPTH => 16,
C_XCL0_LINESIZE => 4,
C_XCL0_WRITEXFER => 1,
C_XCL1_LINESIZE => 4,
C_XCL1_WRITEXFER => 1,
C_XCL2_LINESIZE => 4,
C_XCL2_WRITEXFER => 1,
C_XCL3_LINESIZE => 4,
C_XCL3_WRITEXFER => 1
)
port map (
MCH_SPLB_Clk => MCH_SPLB_Clk,
RdClk => RdClk,
MCH_SPLB_Rst => MCH_SPLB_Rst,
MCH0_Access_Control => MCH0_Access_Control,
MCH0_Access_Data => MCH0_Access_Data,
MCH0_Access_Write => MCH0_Access_Write,
MCH0_Access_Full => MCH0_Access_Full,
MCH0_ReadData_Control => MCH0_ReadData_Control,
MCH0_ReadData_Data => MCH0_ReadData_Data,
MCH0_ReadData_Read => MCH0_ReadData_Read,
MCH0_ReadData_Exists => MCH0_ReadData_Exists,
MCH1_Access_Control => MCH1_Access_Control,
MCH1_Access_Data => MCH1_Access_Data,
MCH1_Access_Write => MCH1_Access_Write,
MCH1_Access_Full => MCH1_Access_Full,
MCH1_ReadData_Control => MCH1_ReadData_Control,
MCH1_ReadData_Data => MCH1_ReadData_Data,
MCH1_ReadData_Read => MCH1_ReadData_Read,
MCH1_ReadData_Exists => MCH1_ReadData_Exists,
MCH2_Access_Control => MCH2_Access_Control,
MCH2_Access_Data => MCH2_Access_Data,
MCH2_Access_Write => MCH2_Access_Write,
MCH2_Access_Full => MCH2_Access_Full,
MCH2_ReadData_Control => MCH2_ReadData_Control,
MCH2_ReadData_Data => MCH2_ReadData_Data,
MCH2_ReadData_Read => MCH2_ReadData_Read,
MCH2_ReadData_Exists => MCH2_ReadData_Exists,
MCH3_Access_Control => MCH3_Access_Control,
MCH3_Access_Data => MCH3_Access_Data,
MCH3_Access_Write => MCH3_Access_Write,
MCH3_Access_Full => MCH3_Access_Full,
MCH3_ReadData_Control => MCH3_ReadData_Control,
MCH3_ReadData_Data => MCH3_ReadData_Data,
MCH3_ReadData_Read => MCH3_ReadData_Read,
MCH3_ReadData_Exists => MCH3_ReadData_Exists,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Mem_DQ_I => Mem_DQ_I,
Mem_DQ_O => Mem_DQ_O,
Mem_DQ_T => Mem_DQ_T,
Mem_A => Mem_A,
Mem_RPN => Mem_RPN,
Mem_CEN => Mem_CEN,
Mem_OEN => Mem_OEN,
Mem_WEN => Mem_WEN,
Mem_QWEN => Mem_QWEN,
Mem_BEN => Mem_BEN,
Mem_CE => Mem_CE,
Mem_ADV_LDN => Mem_ADV_LDN,
Mem_LBON => Mem_LBON,
Mem_CKEN => Mem_CKEN,
Mem_RNW => Mem_RNW
);
end architecture STRUCTURE;
|
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fir_compiler:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fir_compiler_v7_1;
USE fir_compiler_v7_1.fir_compiler_v7_1;
ENTITY half_band_FIR IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END half_band_FIR;
ARCHITECTURE half_band_FIR_arch OF half_band_FIR IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF half_band_FIR_arch: ARCHITECTURE IS "yes";
COMPONENT fir_compiler_v7_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_COMPONENT_NAME : STRING;
C_COEF_FILE : STRING;
C_COEF_FILE_LINES : INTEGER;
C_FILTER_TYPE : INTEGER;
C_INTERP_RATE : INTEGER;
C_DECIM_RATE : INTEGER;
C_ZERO_PACKING_FACTOR : INTEGER;
C_SYMMETRY : INTEGER;
C_NUM_FILTS : INTEGER;
C_NUM_TAPS : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_CHANNEL_PATTERN : STRING;
C_ROUND_MODE : INTEGER;
C_COEF_RELOAD : INTEGER;
C_NUM_RELOAD_SLOTS : INTEGER;
C_COL_MODE : INTEGER;
C_COL_PIPE_LEN : INTEGER;
C_COL_CONFIG : STRING;
C_OPTIMIZATION : INTEGER;
C_DATA_PATH_WIDTHS : STRING;
C_DATA_IP_PATH_WIDTHS : STRING;
C_DATA_PX_PATH_WIDTHS : STRING;
C_DATA_WIDTH : INTEGER;
C_COEF_PATH_WIDTHS : STRING;
C_COEF_WIDTH : INTEGER;
C_DATA_PATH_SRC : STRING;
C_COEF_PATH_SRC : STRING;
C_DATA_PATH_SIGN : STRING;
C_COEF_PATH_SIGN : STRING;
C_ACCUM_PATH_WIDTHS : STRING;
C_OUTPUT_WIDTH : INTEGER;
C_OUTPUT_PATH_WIDTHS : STRING;
C_ACCUM_OP_PATH_WIDTHS : STRING;
C_EXT_MULT_CNFG : STRING;
C_DATA_PATH_PSAMP_SRC : STRING;
C_OP_PATH_PSAMP_SRC : STRING;
C_NUM_MADDS : INTEGER;
C_OPT_MADDS : STRING;
C_OVERSAMPLING_RATE : INTEGER;
C_INPUT_RATE : INTEGER;
C_OUTPUT_RATE : INTEGER;
C_DATA_MEMTYPE : INTEGER;
C_COEF_MEMTYPE : INTEGER;
C_IPBUFF_MEMTYPE : INTEGER;
C_OPBUFF_MEMTYPE : INTEGER;
C_DATAPATH_MEMTYPE : INTEGER;
C_MEM_ARRANGEMENT : INTEGER;
C_DATA_MEM_PACKING : INTEGER;
C_COEF_MEM_PACKING : INTEGER;
C_FILTS_PACKED : INTEGER;
C_LATENCY : INTEGER;
C_HAS_ARESETn : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_DATA_HAS_TLAST : INTEGER;
C_S_DATA_HAS_FIFO : INTEGER;
C_S_DATA_HAS_TUSER : INTEGER;
C_S_DATA_TDATA_WIDTH : INTEGER;
C_S_DATA_TUSER_WIDTH : INTEGER;
C_M_DATA_HAS_TREADY : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_CONFIG_CHANNEL : INTEGER;
C_CONFIG_SYNC_MODE : INTEGER;
C_CONFIG_PACKET_SIZE : INTEGER;
C_CONFIG_TDATA_WIDTH : INTEGER;
C_RELOAD_TDATA_WIDTH : INTEGER
);
PORT (
aresetn : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tlast : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_reload_tvalid : IN STD_LOGIC;
s_axis_reload_tready : OUT STD_LOGIC;
s_axis_reload_tlast : IN STD_LOGIC;
s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
event_s_data_tlast_missing : OUT STD_LOGIC;
event_s_data_tlast_unexpected : OUT STD_LOGIC;
event_s_data_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC;
event_s_reload_tlast_missing : OUT STD_LOGIC;
event_s_reload_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT fir_compiler_v7_1;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
BEGIN
U0 : fir_compiler_v7_1
GENERIC MAP (
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_COMPONENT_NAME => "half_band_FIR",
C_COEF_FILE => "half_band_FIR.mif",
C_COEF_FILE_LINES => 5,
C_FILTER_TYPE => 7,
C_INTERP_RATE => 1,
C_DECIM_RATE => 2,
C_ZERO_PACKING_FACTOR => 1,
C_SYMMETRY => 1,
C_NUM_FILTS => 1,
C_NUM_TAPS => 15,
C_NUM_CHANNELS => 1,
C_CHANNEL_PATTERN => "fixed",
C_ROUND_MODE => 1,
C_COEF_RELOAD => 0,
C_NUM_RELOAD_SLOTS => 1,
C_COL_MODE => 1,
C_COL_PIPE_LEN => 4,
C_COL_CONFIG => "1",
C_OPTIMIZATION => 0,
C_DATA_PATH_WIDTHS => "22",
C_DATA_IP_PATH_WIDTHS => "22",
C_DATA_PX_PATH_WIDTHS => "22",
C_DATA_WIDTH => 22,
C_COEF_PATH_WIDTHS => "15",
C_COEF_WIDTH => 15,
C_DATA_PATH_SRC => "0",
C_COEF_PATH_SRC => "0",
C_DATA_PATH_SIGN => "0",
C_COEF_PATH_SIGN => "0",
C_ACCUM_PATH_WIDTHS => "38",
C_OUTPUT_WIDTH => 22,
C_OUTPUT_PATH_WIDTHS => "22",
C_ACCUM_OP_PATH_WIDTHS => "38",
C_EXT_MULT_CNFG => "none",
C_DATA_PATH_PSAMP_SRC => "0",
C_OP_PATH_PSAMP_SRC => "0",
C_NUM_MADDS => 1,
C_OPT_MADDS => "none",
C_OVERSAMPLING_RATE => 5,
C_INPUT_RATE => 16,
C_OUTPUT_RATE => 32,
C_DATA_MEMTYPE => 0,
C_COEF_MEMTYPE => 2,
C_IPBUFF_MEMTYPE => 2,
C_OPBUFF_MEMTYPE => 0,
C_DATAPATH_MEMTYPE => 2,
C_MEM_ARRANGEMENT => 1,
C_DATA_MEM_PACKING => 0,
C_COEF_MEM_PACKING => 0,
C_FILTS_PACKED => 0,
C_LATENCY => 42,
C_HAS_ARESETn => 0,
C_HAS_ACLKEN => 0,
C_DATA_HAS_TLAST => 0,
C_S_DATA_HAS_FIFO => 1,
C_S_DATA_HAS_TUSER => 0,
C_S_DATA_TDATA_WIDTH => 24,
C_S_DATA_TUSER_WIDTH => 1,
C_M_DATA_HAS_TREADY => 0,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TDATA_WIDTH => 24,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_CONFIG_CHANNEL => 0,
C_CONFIG_SYNC_MODE => 0,
C_CONFIG_PACKET_SIZE => 0,
C_CONFIG_TDATA_WIDTH => 1,
C_RELOAD_TDATA_WIDTH => 1
)
PORT MAP (
aresetn => '1',
aclk => aclk,
aclken => '1',
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_data_tdata => s_axis_data_tdata,
s_axis_config_tvalid => '0',
s_axis_config_tlast => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_reload_tvalid => '0',
s_axis_reload_tlast => '0',
s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '1',
m_axis_data_tdata => m_axis_data_tdata
);
END half_band_FIR_arch;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "capture_ctrl" and "storage"
-- Project : fpga_logic_analyzer
-------------------------------------------------------------------------------
-- File : capture_ctrl+storage_tb.vhd
-- Created : 2016-03-11
-- Last update: 2016-03-11
-- Standard : VHDL'08
-------------------------------------------------------------------------------
-- Description: Functional testbench for the integeration of the capture
-- control block and the storage FIFO.
-------------------------------------------------------------------------------
-- Copyright (c) 2016 Ashton Johnson, Paul Henny, Ian Swepston, David Hurt
-----------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-03-11 1.0 ashton Created
-------------------------------------------------------------------------------
USE std.textio.ALL;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
---------------------------------------------
ENTITY capture_ctrl_storage_tb IS
END ENTITY capture_ctrl_storage_tb;
-------------------------------------------------------------------------------
ARCHITECTURE acj_func_test OF capture_ctrl_storage_tb IS
-- component generics
CONSTANT DATA_WIDTH : POSITIVE RANGE 1 TO 32 := 8;
-- component ports
SIGNAL rst : STD_LOGIC := '1';
SIGNAL din : STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL armed : STD_LOGIC;
SIGNAL triggered : STD_LOGIC;
SIGNAL rst_cmd : STD_LOGIC := '0';
SIGNAL arm_cmd : STD_LOGIC := '0';
SIGNAL sample_enable : STD_LOGIC := '0';
SIGNAL sample_cnt_rst : STD_LOGIC;
SIGNAL read_cnt_4x : STD_LOGIC_VECTOR(16-1 DOWNTO 0) := (OTHERS => '1');-- := STD_LOGIC_VECTOR(to_unsigned(1000, 16));
SIGNAL par_trig_msk : STD_LOGIC_VECTOR(32-1 DOWNTO 0) := X"FE_6B_28_40";
SIGNAL par_trig_val : STD_LOGIC_VECTOR(32-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL capture_rdy : STD_LOGIC;
--
SIGNAL in_fifo_tdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL in_fifo_tvalid : STD_LOGIC;
SIGNAL in_fifo_tlast : STD_LOGIC;
SIGNAL in_fifo_tready : STD_LOGIC;
SIGNAL in_fifo_tfull : STD_LOGIC;
SIGNAL in_fifo_tempty : STD_LOGIC;
SIGNAL in_fifo_tflush : STD_LOGIC;
--
SIGNAL out_fifo_tdata : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL out_fifo_tvalid : STD_LOGIC;
SIGNAL out_fifo_tlast : STD_LOGIC;
SIGNAL out_fifo_tready : STD_LOGIC;
-- clock
SIGNAL Clk : STD_LOGIC := '1';
BEGIN -- ARCHITECTURE acj_func_test
-- component instantiation
DUT : ENTITY work.capture_ctrl
GENERIC MAP (
DATA_WIDTH => DATA_WIDTH)
PORT MAP (
clk => clk,
rst => rst,
din => din,
armed => armed,
triggered => triggered,
rst_cmd => rst_cmd,
arm_cmd => arm_cmd,
--sample_enable => sample_enable,
sample_cnt_rst => sample_cnt_rst,
delay_cnt_4x => read_cnt_4x,
read_cnt_4x => read_cnt_4x,
par_trig_msk => par_trig_msk,
par_trig_val => par_trig_val,
capture_rdy => capture_rdy,
--
fifo_tdata => in_fifo_tdata,
fifo_tvalid => in_fifo_tvalid,
fifo_tlast => in_fifo_tlast,
fifo_tready => in_fifo_tready,
fifo_tfull => in_fifo_tfull,
fifo_tempty => in_fifo_tempty,
fifo_aresetn => in_fifo_tflush);
sample_storage_block : ENTITY work.storage
GENERIC MAP (
FIFO_SIZE => 2**18)
PORT MAP (
clk => clk,
reset => rst,
--
in_fifo_tdata => in_fifo_tdata,
in_fifo_tvalid => in_fifo_tvalid,
in_fifo_tlast => in_fifo_tlast,
in_fifo_tready => in_fifo_tready,
in_fifo_tfull => in_fifo_tfull,
in_fifo_tempty => in_fifo_tempty,
in_fifo_tflush => in_fifo_tflush,
--
out_fifo_tdata => out_fifo_tdata,
out_fifo_tvalid => out_fifo_tvalid,
out_fifo_tlast => out_fifo_tlast,
out_fifo_tready => out_fifo_tready);
rst <= '0' AFTER 5 US;
-- clock generation
Clk <= NOT Clk AFTER 2 NS;
-- waveform generation
WaveGen_Proc : PROCESS
BEGIN
-- insert signal assignments here
WAIT UNTIL rst = '0';
WAIT UNTIL capture_rdy='1';
WAIT UNTIL rising_edge(clk);
arm_cmd <= '1';
WAIT UNTIL rising_edge(clk);
arm_cmd <= '0';
WAIT;
END PROCESS WaveGen_Proc;
din_gen : PROCESS (clk) IS
BEGIN -- PROCESS din_gen
IF rising_edge(clk) THEN -- rising clock edge
IF rst = '1' THEN -- synchronous reset (active high)
din <= (OTHERS => '0');
ELSE
din <= STD_LOGIC_VECTOR(UNSIGNED(din)+1);
END IF;
END IF;
END PROCESS din_gen;
PROCESS (armed) IS
BEGIN -- PROCESS
IF rising_edge(armed) THEN
REPORT "system has armed" SEVERITY NOTE;
END IF;
END PROCESS;
PROCESS (triggered) IS
BEGIN -- PROCESS
IF rising_edge(triggered) THEN
REPORT "system has triggered" SEVERITY NOTE;
ASSERT din = X"40" REPORT "system triggered on incorrect value" SEVERITY ERROR;
END IF;
END PROCESS;
PROCESS IS
BEGIN -- PROCESS
WAIT UNTIL falling_edge(rst);
WAIT FOR 1 US;
out_fifo_tready <= '1';
WAIT;
END PROCESS;
END ARCHITECTURE acj_func_test;
-------------------------------------------------------------------------------
------------------------------------------------
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spictrl_net
-- File: spictrl_net.vhd
-- Author: Jan Andersson - Aeroflex Gaisler
-- Description: Netlist wrapper for SPICTRL core
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.gencomp.all;
entity spictrl_net is
generic (
tech : integer range 0 to NTECH := 0;
fdepth : integer range 1 to 7 := 1;
slvselen : integer range 0 to 1 := 0;
slvselsz : integer range 1 to 32 := 1;
oepol : integer range 0 to 1 := 0;
odmode : integer range 0 to 1 := 0;
automode : integer range 0 to 1 := 0;
acntbits : integer range 1 to 32 := 32;
aslvsel : integer range 0 to 1 := 0;
twen : integer range 0 to 1 := 1;
maxwlen : integer range 0 to 15 := 0;
automask0 : integer := 0;
automask1 : integer := 0;
automask2 : integer := 0;
automask3 : integer := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
apbi_psel : in std_ulogic;
apbi_penable : in std_ulogic;
apbi_paddr : in std_logic_vector(31 downto 0);
apbi_pwrite : in std_ulogic;
apbi_pwdata : in std_logic_vector(31 downto 0);
apbi_testen : in std_ulogic;
apbi_testrst : in std_ulogic;
apbi_scanen : in std_ulogic;
apbi_testoen : in std_ulogic;
apbo_prdata : out std_logic_vector(31 downto 0);
apbo_pirq : out std_ulogic;
-- SPI signals
spii_miso : in std_ulogic;
spii_mosi : in std_ulogic;
spii_sck : in std_ulogic;
spii_spisel : in std_ulogic;
spii_astart : in std_ulogic;
spii_cstart : in std_ulogic;
spio_miso : out std_ulogic;
spio_misooen : out std_ulogic;
spio_mosi : out std_ulogic;
spio_mosioen : out std_ulogic;
spio_sck : out std_ulogic;
spio_sckoen : out std_ulogic;
spio_enable : out std_ulogic;
spio_astart : out std_ulogic;
spio_aready : out std_ulogic;
slvsel : out std_logic_vector((slvselsz-1) downto 0)
);
end entity spictrl_net;
architecture rtl of spictrl_net is
component spictrl_unisim
generic (
slvselen : integer range 0 to 1 := 0;
slvselsz : integer range 1 to 32 := 1);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
apbi_psel : in std_ulogic;
apbi_penable : in std_ulogic;
apbi_paddr : in std_logic_vector(31 downto 0);
apbi_pwrite : in std_ulogic;
apbi_pwdata : in std_logic_vector(31 downto 0);
apbi_testen : in std_ulogic;
apbi_testrst : in std_ulogic;
apbi_scanen : in std_ulogic;
apbi_testoen : in std_ulogic;
apbo_prdata : out std_logic_vector(31 downto 0);
apbo_pirq : out std_ulogic;
-- SPI signals
spii_miso : in std_ulogic;
spii_mosi : in std_ulogic;
spii_sck : in std_ulogic;
spii_spisel : in std_ulogic;
spii_astart : in std_ulogic;
spii_cstart : in std_ulogic;
spio_miso : out std_ulogic;
spio_misooen : out std_ulogic;
spio_mosi : out std_ulogic;
spio_mosioen : out std_ulogic;
spio_sck : out std_ulogic;
spio_sckoen : out std_ulogic;
spio_enable : out std_ulogic;
spio_astart : out std_ulogic;
spio_aready : out std_ulogic;
slvsel : out std_logic_vector((slvselsz-1) downto 0));
end component;
begin
xil : if false generate --(is_unisim(tech) = 1) generate
xilctrl : spictrl_unisim
generic map (
slvselen => slvselen,
slvselsz => slvselsz)
port map (
rstn => rstn,
clk => clk,
-- APB signals
apbi_psel => apbi_psel,
apbi_penable => apbi_penable,
apbi_paddr => apbi_paddr,
apbi_pwrite => apbi_pwrite,
apbi_pwdata => apbi_pwdata,
apbi_testen => apbi_testen,
apbi_testrst => apbi_testrst,
apbi_scanen => apbi_scanen,
apbi_testoen => apbi_testoen,
apbo_prdata => apbo_prdata,
apbo_pirq => apbo_pirq,
-- SPI signals
spii_miso => spii_miso,
spii_mosi => spii_mosi,
spii_sck => spii_sck,
spii_spisel => spii_spisel,
spii_astart => spii_astart,
spii_cstart => spii_cstart,
spio_miso => spio_miso,
spio_misooen => spio_misooen,
spio_mosi => spio_mosi,
spio_mosioen => spio_mosioen,
spio_sck => spio_sck,
spio_sckoen => spio_sckoen,
spio_enable => spio_enable,
spio_astart => spio_astart,
spio_aready => spio_aready,
slvsel => slvsel);
end generate;
-- pragma translate_off
nonet : if true generate --not ((is_unisim(tech) = 1)) generate
err : process
begin
assert false report "ERROR : No SPICTRL netlist available for this process!"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end architecture;
|
--!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
library misclib;
use misclib.types_misc.all;
entity axi4_irqctrl is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#
);
port
(
clk : in std_logic;
nrst : in std_logic;
i_irqs : in std_logic_vector(CFG_IRQ_TOTAL-1 downto 1);
o_cfg : out axi4_slave_config_type;
i_axi : in axi4_slave_in_type;
o_axi : out axi4_slave_out_type;
o_irq_meip : out std_logic
);
end;
architecture axi4_irqctrl_rtl of axi4_irqctrl is
constant xconfig : axi4_slave_config_type := (
descrtype => PNP_CFG_TYPE_SLAVE,
descrsize => PNP_CFG_SLAVE_DESCR_BYTES,
irq_idx => conv_std_logic_vector(0, 8),
xaddr => conv_std_logic_vector(xaddr, CFG_SYSBUS_CFG_ADDR_BITS),
xmask => conv_std_logic_vector(xmask, CFG_SYSBUS_CFG_ADDR_BITS),
vid => VENDOR_GNSSSENSOR,
did => GNSSSENSOR_IRQCTRL
);
constant IRQ_ZERO : std_logic_vector(CFG_IRQ_TOTAL-1 downto 1) := (others => '0');
type registers is record
--! interrupt signal delay signal to detect interrupt positive edge
irqs_z : std_logic_vector(CFG_IRQ_TOTAL-1 downto 1);
irqs_zz : std_logic_vector(CFG_IRQ_TOTAL-1 downto 1);
--! mask irq disabled: 1=disabled; 0=enabled
irqs_mask : std_logic_vector(CFG_IRQ_TOTAL-1 downto 1);
--! irq pending bit mask
irqs_pending : std_logic_vector(CFG_IRQ_TOTAL-1 downto 1);
--! interrupt handler address initialized by FW:
isr_table : std_logic_vector(63 downto 0);
--! hold-on generation of interrupt.
irq_lock : std_logic;
--! delayed interrupt
irq_wait_unlock : std_logic_vector(CFG_IRQ_TOTAL-1 downto 1);
irq_cause_idx : std_logic_vector(31 downto 0);
--! Function trap_entry copies the values of CSRs into these two regs:
dbg_cause : std_logic_vector(63 downto 0);
dbg_epc : std_logic_vector(63 downto 0);
raddr : global_addr_array_type;
end record;
constant R_RESET : registers := (
(others => '0'), (others => '0'), -- irqs_z, irqs_zz
(others => '1'), (others => '0'), -- irqs_mask, irqs_pending
(others => '0'), '0', -- isr_table, isr_lock
(others => '0'), (others => '0'), -- irq_wait_unlock, irq_cause_idx
(others => '0'), (others => '0'), -- dbg_cause, dbg_epc
((others => '0'), (others => '0'))
);
signal r, rin: registers;
signal wb_dev_rdata : std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0);
signal wb_bus_raddr : global_addr_array_type;
signal w_bus_re : std_logic;
signal wb_bus_waddr : global_addr_array_type;
signal w_bus_we : std_logic;
signal wb_bus_wstrb : std_logic_vector(CFG_SYSBUS_DATA_BYTES-1 downto 0);
signal wb_bus_wdata : std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0);
begin
axi0 : axi4_slave generic map (
async_reset => async_reset
) port map (
i_clk => clk,
i_nrst => nrst,
i_xcfg => xconfig,
i_xslvi => i_axi,
o_xslvo => o_axi,
i_ready => '1',
i_rdata => wb_dev_rdata,
o_re => w_bus_re,
o_r32 => open,
o_radr => wb_bus_raddr,
o_wadr => wb_bus_waddr,
o_we => w_bus_we,
o_wstrb => wb_bus_wstrb,
o_wdata => wb_bus_wdata
);
comblogic : process(nrst, i_irqs, r, w_bus_re, wb_bus_raddr, wb_bus_waddr,
w_bus_we, wb_bus_wstrb, wb_bus_wdata)
variable v : registers;
variable raddr : integer;
variable waddr : integer;
variable vrdata : std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0);
variable tmp : std_logic_vector(31 downto 0);
variable wstrb : std_logic_vector(CFG_ALIGN_BYTES-1 downto 0);
variable w_generate_ipi : std_logic;
begin
v := r;
v.raddr := wb_bus_raddr;
w_generate_ipi := '0';
vrdata := (others => '0');
for n in 0 to CFG_WORDS_ON_BUS-1 loop
raddr := conv_integer(r.raddr(n)(11 downto 2));
tmp := (others => '0');
case raddr is
when 0 => tmp(CFG_IRQ_TOTAL-1 downto 1) := r.irqs_mask; --! [RW]: 1=irq disable; 0=enable
when 1 => tmp(CFG_IRQ_TOTAL-1 downto 1) := r.irqs_pending; --! [RO]: Rised interrupts.
when 2 => tmp := (others => '0'); --! [WO]: Clear interrupts mask.
when 3 => tmp := (others => '0'); --! [WO]: Rise interrupts mask.
when 4 => tmp := r.isr_table(31 downto 0); --! [RW]: LSB of the function address
when 5 => tmp := r.isr_table(63 downto 32); --! [RW]: MSB of the function address
when 6 => tmp := r.dbg_cause(31 downto 0); --! [RW]: Cause of the interrupt
when 7 => tmp := r.dbg_cause(63 downto 32); --! [RW]:
when 8 => tmp := r.dbg_epc(31 downto 0); --! [RW]: Instruction pointer
when 9 => tmp := r.dbg_epc(63 downto 32); --! [RW]:
when 10 => tmp(0) := r.irq_lock;
when 11 => tmp := r.irq_cause_idx;
when others =>
end case;
vrdata(8*CFG_ALIGN_BYTES*(n+1)-1 downto 8*CFG_ALIGN_BYTES*n) := tmp;
end loop;
if w_bus_we = '1' then
for n in 0 to CFG_WORDS_ON_BUS-1 loop
if conv_integer(wb_bus_wstrb(CFG_ALIGN_BYTES*(n+1)-1 downto CFG_ALIGN_BYTES*n)) /= 0 then
waddr := conv_integer(wb_bus_waddr(n)(11 downto 2));
tmp := wb_bus_wdata(32*(n+1)-1 downto 32*n);
case waddr is
when 0 => v.irqs_mask := tmp(CFG_IRQ_TOTAL-1 downto 1);
when 1 => --! Read only
when 2 =>
v.irqs_pending := r.irqs_pending and (not tmp(CFG_IRQ_TOTAL-1 downto 1));
when 3 =>
w_generate_ipi := '1';
v.irqs_pending := (not r.irqs_mask) and tmp(CFG_IRQ_TOTAL-1 downto 1);
when 4 => v.isr_table(31 downto 0) := tmp;
when 5 => v.isr_table(63 downto 32) := tmp;
when 6 => v.dbg_cause(31 downto 0) := tmp;
when 7 => v.dbg_cause(63 downto 32) := tmp;
when 8 => v.dbg_epc(31 downto 0) := tmp;
when 9 => v.dbg_epc(63 downto 32) := tmp;
when 10 => v.irq_lock := tmp(0);
when 11 => v.irq_cause_idx := tmp;
when others =>
end case;
end if;
end loop;
end if;
v.irqs_z := i_irqs;
v.irqs_zz := r.irqs_z;
for n in 1 to CFG_IRQ_TOTAL-1 loop
if (r.irqs_z(n) = '1' and r.irqs_zz(n) = '0') or r.irq_wait_unlock(n) = '1' then
if r.irq_lock = '0' then
v.irq_wait_unlock(n) := '0';
v.irqs_pending(n) := not r.irqs_mask(n);
w_generate_ipi := w_generate_ipi or (not r.irqs_mask(n));
else
v.irq_wait_unlock(n) := '1';
end if;
end if;
end loop;
if r.irqs_pending = IRQ_ZERO or r.irq_lock = '1' then
o_irq_meip <= '0';
else
o_irq_meip <= '1';
end if;
if not async_reset and nrst = '0' then
v := R_RESET;
end if;
rin <= v;
wb_dev_rdata <= vrdata;
end process;
o_cfg <= xconfig;
-- registers:
regs : process(clk, nrst)
begin
if async_reset and nrst = '0' then
r <= R_RESET;
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dac_serial is
port(
SPI_SCK: out std_logic; -- spi clock
DAC_CS: out std_logic; -- chip select
SPI_MOSI_1: out std_logic; -- Master output, slave (DAC) input
SPI_MOSI_2: out std_logic; -- Master output, slave (DAC) input
--SPI_MISO: in std_logic; -- Master input, slave (DAC) output
--- control ---
data_in_1: in std_logic_vector(11 downto 0);
data_in_2: in std_logic_vector(11 downto 0);
ready_flag: out std_logic; -- sending data flag
send_data: in std_logic; -- send sine data over SPI
clk: in std_logic -- master clock
);
end dac_serial;
architecture Behavioral of dac_serial is
signal current_bit: integer range 0 to 15 := 0;
signal ready_flag_sig: std_logic;
signal spi_clk_delay: std_logic;
signal dac_cs_delay: std_logic;
begin
process(clk)
begin
if(rising_edge(clk)) then
if(send_data = '1') and (ready_flag_sig = '1') then
ready_flag_sig <= '0';
dac_cs_delay <= '0';
elsif ready_flag_sig = '0' then
if(spi_clk_delay = '1') then
spi_clk_delay <= '0';
else
spi_clk_delay <= '1';
current_bit <= current_bit + 1;
case current_bit is
-- command
when 2 => SPI_MOSI_1 <= '0';
SPI_MOSI_2 <= '0';
when 3 => SPI_MOSI_1 <= '0';
SPI_MOSI_2 <= '0';
-- data
when 4 => SPI_MOSI_1 <= data_in_1(11);
SPI_MOSI_2 <= data_in_2(11);
when 5 => SPI_MOSI_1 <= data_in_1(10);
SPI_MOSI_2 <= data_in_2(10);
when 6 => SPI_MOSI_1 <= data_in_1(9);
SPI_MOSI_2 <= data_in_2(9);
when 7 => SPI_MOSI_1 <= data_in_1(8);
SPI_MOSI_2 <= data_in_2(8);
when 8 => SPI_MOSI_1 <= data_in_1(7);
SPI_MOSI_2 <= data_in_2(7);
when 9 => SPI_MOSI_1 <= data_in_1(6);
SPI_MOSI_2 <= data_in_2(6);
when 10 => SPI_MOSI_1 <= data_in_1(5);
SPI_MOSI_2 <= data_in_2(5);
when 11 => SPI_MOSI_1 <= data_in_1(4);
SPI_MOSI_2 <= data_in_2(4);
when 12 => SPI_MOSI_1 <= data_in_1(3);
SPI_MOSI_2 <= data_in_2(3);
when 13 => SPI_MOSI_1 <= data_in_1(2);
SPI_MOSI_2 <= data_in_2(2);
when 14 => SPI_MOSI_1 <= data_in_1(1);
SPI_MOSI_2 <= data_in_2(1);
when 15 => SPI_MOSI_1 <= data_in_1(0);
SPI_MOSI_2 <= data_in_2(0);
ready_flag_sig <= '1';
-- other
when others => SPI_MOSI_1 <= '0'; -- used for don't cares
SPI_MOSI_2 <= '0';
end case;
end if;
else
dac_cs_delay <= '1';
current_bit <= 0;
spi_clk_delay <= dac_cs_delay;
end if;
DAC_CS <= dac_cs_delay;
SPI_SCK <= spi_clk_delay;
ready_flag <= ready_flag_sig;
end if;
end process;
end Behavioral;
--library IEEE;
--use IEEE.std_logic_1164.all;
--use IEEE.numeric_std.all;
--
--entity dac_serial is
-- port (
-- dac_clk: out std_logic;
-- dac_sync: out std_logic;
-- dac_data: out std_logic;
-- data_in: in std_logic_vector(11 downto 0);
-- ready: out std_logic;
-- send: in std_logic;
-- clk: in std_logic
-- );
--end dac_serial;
--
--architecture behavioral of dac_serial is
--
-- current_bit: unsigned(3 downto 0);
-- divide_counter: unsigned(3 downto 0);
-- sending: std_logic;
-- data_en: std_logic;
-- send_en: std_logic;
--
--begin
-- clk_divide:process(clk)
-- begin
-- if(rising_edge(clk)) then
-- if(divide_counter = to_unsigned(5,4)) then
-- divide_counter <= divide_counter + '1';
-- send_en <= '1';
-- elsif(divide_counter = to_unsigned(10,4)) then
-- divide_counter <= (others => '0');
-- data_en <= '1';
-- send_en <= '1';
-- else
-- divide_counter <= divide_counter + '1';
-- data_en <= '0';
-- send_en <= '0';
-- end if;
-- end if;
-- end process;
--
-- serial_clk: process(clk)
-- begin
-- if(rising_edge(clk)) then
-- if(sending = '1') then
--
-- end process;
--
-- serial_data: process(clk)
-- begin
-- if(rising_edge(clk)) then
-- if(send = '1') and (sending = '0') then
-- sending <= '1';
-- sending <= '1';
-- ready <= '0';
-- current_bit <= "0000";
-- dac_data <= '0';
-- elsif(data_en = '1') then
-- if(sending = '1') then
-- current_bit <= current_bit + '1';
-- dac_sync <= '0';
-- case current_bit is
-- when "0000" =>
-- dac_data <= '0'; -- don't care
-- when "0001" =>
-- dac_data <= '0'; -- don't care
-- when "0010" =>
-- dac_data <= '0'; -- 0 for normal operation
-- when "0011" =>
-- dac_data <= '0'; -- 0 for normal operation
-- when "0100" =>
-- dac_data <= data_in(11);
-- when "0101" =>
-- dac_data <= data_in(10);
-- when "0110" =>
-- dac_data <= data_in(9);
-- when "0111" =>
-- dac_data <= data_in(8);
-- when "1000" =>
-- dac_data <= data_in(7);
-- when "1001" =>
-- dac_data <= data_in(6);
-- when "1010" =>
-- dac_data <= data_in(5);
-- when "1011" =>
-- dac_data <= data_in(4);
-- when "1100" =>
-- dac_data <= data_in(3);
-- when "1101" =>
-- dac_data <= data_in(2);
-- when "1110" =>
-- dac_data <= data_in(1);
-- when "1111" =>
-- dac_data <= data_in(0);
-- when others =>
-- dac_data <= '0';
-- end case;
-- else
-- dac_sync <= '1';
-- ready <= '0';
-- current_bit <= "0000";
-- dac_data <= '0';
-- end if;
-- end if;
-- end if;
-- end process;
--
--end behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fir_types.all;
use work.fir_coeff_lib.all;
use std.textio.all;
entity fir_matlab is
end entity fir_matlab;
architecture sim of fir_matlab is
signal clk : std_logic := '0';
signal stb : std_logic := '0';
signal d : signed(26 downto 0);
signal q : signed(26 downto 0);
signal rdy : std_logic;
begin
dut : entity work.fir
generic map(
fir_order => fir_order,
fir_coeff => to_fir_coeff_t(fir_coeff_content)
)
port map(
clk => clk,
stb => stb,
d => d,
q => q,
rdy => rdy
);
clk <= not clk after 20345 ps;
process
variable cnt : unsigned(8 downto 0) := (others => '0');
begin
wait until rising_edge(clk);
if cnt = 511 then
stb <= '1';
else
stb <= '0';
end if;
cnt := cnt + 1;
end process;
process
variable l : line;
variable ll : integer;
begin
wait until rising_edge(clk);
if stb = '1' then
readline(input, l);
read(l, ll);
d <= to_signed(ll, 27);
end if;
if rdy = '1' then
ll := to_integer(q);
write(l, ll);
writeline(output, l);
end if;
end process;
end architecture sim;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fir_types.all;
use work.fir_coeff_lib.all;
use std.textio.all;
entity fir_matlab is
end entity fir_matlab;
architecture sim of fir_matlab is
signal clk : std_logic := '0';
signal stb : std_logic := '0';
signal d : signed(26 downto 0);
signal q : signed(26 downto 0);
signal rdy : std_logic;
begin
dut : entity work.fir
generic map(
fir_order => fir_order,
fir_coeff => to_fir_coeff_t(fir_coeff_content)
)
port map(
clk => clk,
stb => stb,
d => d,
q => q,
rdy => rdy
);
clk <= not clk after 20345 ps;
process
variable cnt : unsigned(8 downto 0) := (others => '0');
begin
wait until rising_edge(clk);
if cnt = 511 then
stb <= '1';
else
stb <= '0';
end if;
cnt := cnt + 1;
end process;
process
variable l : line;
variable ll : integer;
begin
wait until rising_edge(clk);
if stb = '1' then
readline(input, l);
read(l, ll);
d <= to_signed(ll, 27);
end if;
if rdy = '1' then
ll := to_integer(q);
write(l, ll);
writeline(output, l);
end if;
end process;
end architecture sim;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
use IEEE.STD_LOGIC_ARITH.ALL;
ENTITY windManager_tb IS
END windManager_tb;
ARCHITECTURE behavior OF windManager_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT windowsManager
PORT(
RS1 : IN std_logic_vector(4 downto 0);
RS2 : IN std_logic_vector(4 downto 0);
RD : IN std_logic_vector(4 downto 0);
OP : IN std_logic_vector(1 downto 0);
OP3 : IN std_logic_vector(5 downto 0);
CWP : IN std_logic_vector(4 downto 0);
NCWP : OUT std_logic_vector(4 downto 0);
NRS1 : OUT std_logic_vector(5 downto 0);
NRS2 : OUT std_logic_vector(5 downto 0);
NRD : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;
--Inputs
signal RS1 : std_logic_vector(4 downto 0) := (others => '0');
signal RS2 : std_logic_vector(4 downto 0) := (others => '0');
signal RD : std_logic_vector(4 downto 0) := (others => '0');
signal OP : std_logic_vector(1 downto 0) := (others => '0');
signal OP3 : std_logic_vector(5 downto 0) := (others => '0');
signal CWP : std_logic_vector(4 downto 0) := (others => '0');
--Outputs
signal NCWP : std_logic_vector(4 downto 0);
signal NRS1 : std_logic_vector(5 downto 0);
signal NRS2 : std_logic_vector(5 downto 0);
signal NRD : std_logic_vector(5 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: windowsManager PORT MAP (
RS1 => RS1,
RS2 => RS2,
RD => RD,
OP => OP,
OP3 => OP3,
CWP => CWP,
NCWP => NCWP,
NRS1 => NRS1,
NRS2 => NRS2,
NRD => NRD
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
--"111100" OR OP3 = "111101"
CWP <= "00000";
--CWP <= "00001";
OP <= "00";
OP3 <= "000000";
RS1 <= "00000"; --0
RS2 <= "00001"; --1
RD <= "00111"; --7
wait for 10 ns;
CWP <= "00001";
OP <= "10";
OP3 <= "111101"; --restore
RS1 <= "11111"; --31
RS2 <= "10000"; --16
RD <= "10100"; -- 8
wait for 10 ns;
CWP <= "00000";
OP <= "10"; -- save
OP3 <= "111100";
RS1 <= "11111"; --31
RS2 <= "10110"; --22
RD <= "01110"; --aqui iba el 14
wait for 10 ns;
CWP <= "00000";
OP <= "10"; --restore
OP3 <= "111101";
RS1 <= "10011";--19
RS2 <= "00010"; --2
RD <= "11010"; --26
wait for 10 ns;
CWP <= "00001";
OP <= "10"; -- save
OP3 <= "111100";
RS1 <= "01111";
RS2 <= "11100";
RD <= "10110";
wait for 10 ns;
CWP <= "00000";
OP <= "00";
OP3 <= "000000";
RS1 <= "00000"; --0
RS2 <= "00001"; --1
RD <= "00111"; --7
wait for 10 ns;
RS1 <= "11111"; --31
RS2 <= "10000"; --16
RD <= "10100"; -- 8
wait for 10 ns;
CWP <= "00001";
RS1 <= "11111"; --31
RS2 <= "10110"; --22
RD <= "01110"; --aqui iba el 14
wait for 10 ns;
RS1 <= "10011";--19
RS2 <= "00010"; --2
RD <= "11010"; --26
wait for 10 ns;
CWP <= "00001";
RS1 <= "01111";
RS2 <= "11100";
RD <= "10110";
wait for 10 ns;
-- insert stimulus here
wait;
end process;
END;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_xilinx_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Memory generators for Xilinx rams
------------------------------------------------------------------------------
-- parametrisable sync ram generator using UNISIM RAMB16 block rams
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
--pragma translate_off
library unisim;
use unisim.RAMB16_S36_S36;
use unisim.RAMB16_S36;
use unisim.RAMB16_S18;
use unisim.RAMB16_S9;
use unisim.RAMB16_S4;
use unisim.RAMB16_S2;
use unisim.RAMB16_S1;
--pragma translate_on
entity unisim_syncram is
generic ( abits : integer := 9; dbits : integer := 32);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture behav of unisim_syncram is
component RAMB16_S36_S36
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
component RAMB16_S1
port (
DO : out std_logic_vector (0 downto 0);
ADDR : in std_logic_vector (13 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (0 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S2
port (
DO : out std_logic_vector (1 downto 0);
ADDR : in std_logic_vector (12 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (1 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S4
port (
DO : out std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (11 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (3 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S9
port (
DO : out std_logic_vector (7 downto 0);
DOP : out std_logic_vector (0 downto 0);
ADDR : in std_logic_vector (10 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (7 downto 0);
DIP : in std_logic_vector (0 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S18
port (
DO : out std_logic_vector (15 downto 0);
DOP : out std_logic_vector (1 downto 0);
ADDR : in std_logic_vector (9 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (15 downto 0);
DIP : in std_logic_vector (1 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S36
port (
DO : out std_logic_vector (31 downto 0);
DOP : out std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (8 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (31 downto 0);
DIP : in std_logic_vector (3 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component generic_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic);
end component;
signal gnd : std_ulogic;
signal do, di : std_logic_vector(dbits+72 downto 0);
signal xa, ya : std_logic_vector(19 downto 0);
begin
gnd <= '0'; dataout <= do(dbits-1 downto 0); di(dbits-1 downto 0) <= datain;
di(dbits+72 downto dbits) <= (others => '0'); xa(abits-1 downto 0) <= address;
xa(19 downto abits) <= (others => '0'); ya(abits-1 downto 0) <= address;
ya(19 downto abits) <= (others => '1');
a0 : if (abits <= 5) and (GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) = 0) generate
r0 : generic_syncram generic map (abits, dbits)
port map (clk, address, datain, do(dbits-1 downto 0), write);
do(dbits+72 downto dbits) <= (others => '0');
end generate;
a8 : if ((abits > 5 or GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) /= 0) and
(abits <= 8)) generate
x : for i in 0 to ((dbits-1)/72) generate
r0 : RAMB16_S36_S36
generic map (SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do(i*72+36+31 downto i*72+36), do(i*72+31 downto i*72),
do(i*72+36+32+3 downto i*72+36+32), do(i*72+32+3 downto i*72+32),
xa(8 downto 0), ya(8 downto 0), clk, clk,
di(i*72+36+31 downto i*72+36), di(i*72+31 downto i*72),
di(i*72+36+32+3 downto i*72+36+32), di(i*72+32+3 downto i*72+32),
enable, enable, gnd, gnd, write, write);
end generate;
do(dbits+72 downto 72*(((dbits-1)/72)+1)) <= (others => '0');
end generate;
a9 : if (abits = 9) generate
x : for i in 0 to ((dbits-1)/36) generate
r : RAMB16_S36 port map ( do(((i+1)*36)-5 downto i*36),
do(((i+1)*36)-1 downto i*36+32), xa(8 downto 0), clk,
di(((i+1)*36)-5 downto i*36), di(((i+1)*36)-1 downto i*36+32),
enable, gnd, write);
end generate;
do(dbits+72 downto 36*(((dbits-1)/36)+1)) <= (others => '0');
end generate;
a10 : if (abits = 10) generate
x : for i in 0 to ((dbits-1)/18) generate
r : RAMB16_S18 port map ( do(((i+1)*18)-3 downto i*18),
do(((i+1)*18)-1 downto i*18+16), xa(9 downto 0), clk,
di(((i+1)*18)-3 downto i*18), di(((i+1)*18)-1 downto i*18+16),
enable, gnd, write);
end generate;
do(dbits+72 downto 18*(((dbits-1)/18)+1)) <= (others => '0');
end generate;
a11 : if abits = 11 generate
x : for i in 0 to ((dbits-1)/9) generate
r : RAMB16_S9 port map ( do(((i+1)*9)-2 downto i*9),
do(((i+1)*9)-1 downto i*9+8), xa(10 downto 0), clk,
di(((i+1)*9)-2 downto i*9), di(((i+1)*9)-1 downto i*9+8),
enable, gnd, write);
end generate;
do(dbits+72 downto 9*(((dbits-1)/9)+1)) <= (others => '0');
end generate;
a12 : if abits = 12 generate
x : for i in 0 to ((dbits-1)/4) generate
r : RAMB16_S4 port map ( do(((i+1)*4)-1 downto i*4), xa(11 downto 0),
clk, di(((i+1)*4)-1 downto i*4), enable, gnd, write);
end generate;
do(dbits+72 downto 4*(((dbits-1)/4)+1)) <= (others => '0');
end generate;
a13 : if abits = 13 generate
x : for i in 0 to ((dbits-1)/2) generate
r : RAMB16_S2 port map ( do(((i+1)*2)-1 downto i*2), xa(12 downto 0),
clk, di(((i+1)*2)-1 downto i*2), enable, gnd, write);
end generate;
do(dbits+72 downto 2*(((dbits-1)/2)+1)) <= (others => '0');
end generate;
a14 : if abits = 14 generate
x : for i in 0 to (dbits-1) generate
r : RAMB16_S1 port map ( do((i+1)-1 downto i), xa(13 downto 0),
clk, di((i+1)-1 downto i), enable, gnd, write);
end generate;
do(dbits+72 downto dbits) <= (others => '0');
end generate;
a15 : if abits > 14 generate
x: generic_syncram generic map (abits, dbits)
port map (clk, address, datain, do(dbits-1 downto 0), write);
do(dbits+72 downto dbits) <= (others => '0');
end generate;
-- pragma translate_off
-- a_to_high : if abits > 14 generate
-- x : process
-- begin
-- assert false
-- report "Address depth larger than 14 not supported for unisim_syncram"
-- severity failure;
-- wait;
-- end process;
-- end generate;
-- pragma translate_on
end;
LIBRARY ieee;
use ieee.std_logic_1164.all;
--pragma translate_off
library unisim;
use unisim.RAMB16_S36_S36;
use unisim.RAMB16_S18_S18;
use unisim.RAMB16_S9_S9;
use unisim.RAMB16_S4_S4;
use unisim.RAMB16_S2_S2;
use unisim.RAMB16_S1_S1;
--pragma translate_on
entity unisim_syncram_dp is
generic (
abits : integer := 4; dbits : integer := 32
);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic);
end;
architecture behav of unisim_syncram_dp is
component RAMB16_S4_S4
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S1_S1
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (13 downto 0);
ADDRB : in std_logic_vector (13 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S2_S2
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (12 downto 0);
ADDRB : in std_logic_vector (12 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S9_S9
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S18_S18
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (15 downto 0);
DOB : out std_logic_vector (15 downto 0);
DOPA : out std_logic_vector (1 downto 0);
DOPB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (9 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (15 downto 0);
DIB : in std_logic_vector (15 downto 0);
DIPA : in std_logic_vector (1 downto 0);
DIPB : in std_logic_vector (1 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
component RAMB16_S36_S36
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
signal gnd, vcc : std_ulogic;
signal do1, do2, di1, di2 : std_logic_vector(dbits+36 downto 0);
signal addr1, addr2 : std_logic_vector(19 downto 0);
begin
gnd <= '0'; vcc <= '1';
dataout1 <= do1(dbits-1 downto 0); dataout2 <= do2(dbits-1 downto 0);
di1(dbits-1 downto 0) <= datain1; di1(dbits+36 downto dbits) <= (others => '0');
di2(dbits-1 downto 0) <= datain2; di2(dbits+36 downto dbits) <= (others => '0');
addr1(abits-1 downto 0) <= address1; addr1(19 downto abits) <= (others => '0');
addr2(abits-1 downto 0) <= address2; addr2(19 downto abits) <= (others => '0');
a9 : if abits <= 9 generate
x : for i in 0 to ((dbits-1)/36) generate
r0 : RAMB16_S36_S36
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*36)-5 downto i*36), do2(((i+1)*36)-5 downto i*36),
do1(((i+1)*36)-1 downto i*36+32), do2(((i+1)*36)-1 downto i*36+32),
addr1(8 downto 0), addr2(8 downto 0), clk1, clk2,
di1(((i+1)*36)-5 downto i*36), di2(((i+1)*36)-5 downto i*36),
di1(((i+1)*36)-1 downto i*36+32), di2(((i+1)*36)-1 downto i*36+32),
enable1, enable2, gnd, gnd, write1, write2);
-- vcc, vcc, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 36*(((dbits-1)/36)+1)) <= (others => '0');
do2(dbits+36 downto 36*(((dbits-1)/36)+1)) <= (others => '0');
end generate;
a10 : if abits = 10 generate
x : for i in 0 to ((dbits-1)/18) generate
r0 : RAMB16_S18_S18
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*18)-3 downto i*18), do2(((i+1)*18)-3 downto i*18),
do1(((i+1)*18)-1 downto i*18+16), do2(((i+1)*18)-1 downto i*18+16),
addr1(9 downto 0), addr2(9 downto 0), clk1, clk2,
di1(((i+1)*18)-3 downto i*18), di2(((i+1)*18)-3 downto i*18),
di1(((i+1)*18)-1 downto i*18+16), di2(((i+1)*18)-1 downto i*18+16),
-- vcc, vcc, gnd, gnd, write1, write2);
enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 18*(((dbits-1)/18)+1)) <= (others => '0');
do2(dbits+36 downto 18*(((dbits-1)/18)+1)) <= (others => '0');
end generate;
a11 : if abits = 11 generate
x : for i in 0 to ((dbits-1)/9) generate
r0 : RAMB16_S9_S9
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*9)-2 downto i*9), do2(((i+1)*9)-2 downto i*9),
do1(((i+1)*9)-1 downto i*9+8), do2(((i+1)*9)-1 downto i*9+8),
addr1(10 downto 0), addr2(10 downto 0), clk1, clk2,
di1(((i+1)*9)-2 downto i*9), di2(((i+1)*9)-2 downto i*9),
di1(((i+1)*9)-1 downto i*9+8), di2(((i+1)*9)-1 downto i*9+8),
-- vcc, vcc, gnd, gnd, write1, write2);
enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 9*(((dbits-1)/9)+1)) <= (others => '0');
do2(dbits+36 downto 9*(((dbits-1)/9)+1)) <= (others => '0');
end generate;
a12 : if abits = 12 generate
x : for i in 0 to ((dbits-1)/4) generate
r0 : RAMB16_S4_S4
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*4)-1 downto i*4), do2(((i+1)*4)-1 downto i*4),
addr1(11 downto 0), addr2(11 downto 0), clk1, clk2,
di1(((i+1)*4)-1 downto i*4), di2(((i+1)*4)-1 downto i*4),
-- vcc, vcc, gnd, gnd, write1, write2);
enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 4*(((dbits-1)/4)+1)) <= (others => '0');
do2(dbits+36 downto 4*(((dbits-1)/4)+1)) <= (others => '0');
end generate;
a13 : if abits = 13 generate
x : for i in 0 to ((dbits-1)/2) generate
r0 : RAMB16_S2_S2
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*2)-1 downto i*2), do2(((i+1)*2)-1 downto i*2),
addr1(12 downto 0), addr2(12 downto 0), clk1, clk2,
di1(((i+1)*2)-1 downto i*2), di2(((i+1)*2)-1 downto i*2),
-- vcc, vcc, gnd, gnd, write1, write2);
enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 2*(((dbits-1)/2)+1)) <= (others => '0');
do2(dbits+36 downto 2*(((dbits-1)/2)+1)) <= (others => '0');
end generate;
a14 : if abits = 14 generate
x : for i in 0 to ((dbits-1)/1) generate
r0 : RAMB16_S1_S1
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*1)-1 downto i*1), do2(((i+1)*1)-1 downto i*1),
addr1(13 downto 0), addr2(13 downto 0), clk1, clk2,
di1(((i+1)*1)-1 downto i*1), di2(((i+1)*1)-1 downto i*1),
-- vcc, vcc, gnd, gnd, write1, write2);
enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto dbits) <= (others => '0');
do2(dbits+36 downto dbits) <= (others => '0');
end generate;
-- pragma translate_off
a_to_high : if abits > 14 generate
x : process
begin
assert false
report "Address depth larger than 14 not supported for unisim_syncram_dp"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
entity unisim_syncram_2p is
generic (abits : integer := 6; dbits : integer := 8; sepclk : integer := 0;
wrfst : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end;
architecture behav of unisim_syncram_2p is
component unisim_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component generic_syncram_2p
generic (abits : integer := 8; dbits : integer := 32; sepclk : integer := 0);
port (
rclk : in std_ulogic;
wclk : in std_ulogic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_ulogic;
q: out std_logic_vector (dbits -1 downto 0)
);
end component;
signal write2, renable2 : std_ulogic;
signal datain2 : std_logic_vector((dbits-1) downto 0);
begin
-- nowf: if wrfst = 0 generate
write2 <= '0'; renable2 <= renable; datain2 <= (others => '0');
-- end generate;
-- wf : if wrfst = 1 generate
-- write2 <= '0' when (waddress /= raddress) else write;
-- renable2 <= renable or write2; datain2 <= datain;
-- end generate;
a0 : if abits <= 5 and GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) = 0 generate
x0 : generic_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, wclk, raddress, waddress, datain, write, dataout);
end generate;
a6 : if abits > 5 or GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) /= 0 generate
x0 : unisim_syncram_dp generic map (abits, dbits)
port map (wclk, waddress, datain, open, write, write,
rclk, raddress, datain2, dataout, renable2, write2);
end generate;
end;
-- parametrisable sync ram generator using unisim block rams
library ieee;
use ieee.std_logic_1164.all;
--pragma translate_off
library unisim;
use unisim.RAMB16_S36_S36;
--pragma translate_on
entity unisim_syncram64 is
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (63 downto 0);
dataout : out std_logic_vector (63 downto 0);
enable : in std_logic_vector (1 downto 0);
write : in std_logic_vector (1 downto 0)
);
end;
architecture behav of unisim_syncram64 is
component unisim_syncram
generic ( abits : integer := 9; dbits : integer := 32);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component RAMB16_S36_S36
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
signal gnd : std_logic_vector(3 downto 0);
signal xa, ya : std_logic_vector(19 downto 0);
begin
gnd <= "0000";
xa(abits-1 downto 0) <= address; xa(19 downto abits) <= (others => '0');
ya(abits-1 downto 0) <= address; ya(19 downto abits) <= (others => '1');
a8 : if abits <= 8 generate
r0 : RAMB16_S36_S36
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
dataout(63 downto 32), dataout(31 downto 0), open, open,
xa(8 downto 0), ya(8 downto 0), clk, clk,
datain(63 downto 32), datain(31 downto 0), gnd, gnd,
enable(1), enable(0), gnd(0), gnd(0), write(1), write(0));
end generate;
a9 : if abits > 8 generate
x1 : unisim_syncram generic map ( abits, 32)
port map (clk, address, datain(63 downto 32), dataout(63 downto 32),
enable(1), write(1));
x2 : unisim_syncram generic map ( abits, 32)
port map (clk, address, datain(31 downto 0), dataout(31 downto 0),
enable(0), write(0));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
entity unisim_syncram128 is
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (3 downto 0);
write : in std_logic_vector (3 downto 0)
);
end;
architecture behav of unisim_syncram128 is
component unisim_syncram64 is
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (63 downto 0);
dataout : out std_logic_vector (63 downto 0);
enable : in std_logic_vector (1 downto 0);
write : in std_logic_vector (1 downto 0)
);
end component;
begin
x0 : unisim_syncram64 generic map (abits)
port map (clk, address, datain(127 downto 64), dataout(127 downto 64),
enable(3 downto 2), write(3 downto 2));
x1 : unisim_syncram64 generic map (abits)
port map (clk, address, datain(63 downto 0), dataout(63 downto 0),
enable(1 downto 0), write(1 downto 0));
end;
library ieee;
use ieee.std_logic_1164.all;
--pragma translate_off
library unisim;
use unisim.RAMB16_S36_S36;
--pragma translate_on
entity unisim_syncram128bw is
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0)
);
end;
architecture behav of unisim_syncram128bw is
component unisim_syncram
generic ( abits : integer := 9; dbits : integer := 32);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component RAMB16_S9_S9
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
signal gnd : std_logic_vector(3 downto 0);
signal xa, ya : std_logic_vector(19 downto 0);
begin
gnd <= "0000";
xa(abits-1 downto 0) <= address; xa(19 downto abits) <= (others => '0');
ya(abits-1 downto 0) <= address; ya(19 downto abits) <= (others => '1');
a11 : if abits <= 10 generate
x0 : for i in 0 to 7 generate
r0 : RAMB16_S9_S9
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
dataout(i*8+7+64 downto i*8+64), dataout(i*8+7 downto i*8), open, open,
xa(10 downto 0), ya(10 downto 0), clk, clk,
datain(i*8+7+64 downto i*8+64), datain(i*8+7 downto i*8), gnd(0 downto 0), gnd(0 downto 0),
enable(i+8), enable(i), gnd(0), gnd(0), write(i+8), write(i));
end generate;
end generate;
a12 : if abits > 10 generate
x0 : for i in 0 to 15 generate
x2 : unisim_syncram generic map ( abits, 8)
port map (clk, address, datain(i*8+7 downto i*8),
dataout(i*8+7 downto i*8), enable(i), write(i));
end generate;
end generate;
end;
|
-- This code is used to configure the Marvell 88e1111 and handle the MDIO pins (PHY_RESET, PHY_MDC and PHY_MDIO).
-- It can write and read the internals registers of the marvell.
-- Right now, the configuration used is the configuration by default and this entity only outputs an hardware reset when power up.
-- You can add a configuration only by uncommenting the request signal (just set your address register and the data you want to write).
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity eth_mdio is
Port(
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
E_RST_L : out STD_LOGIC;
E_MDC : out STD_LOGIC;
E_MDIO : inout STD_LOGIC);
end eth_mdio;
architecture Behavioral of eth_mdio is
signal count : unsigned(27 downto 0) ;
signal request : unsigned(0 to 31);--write
signal request_r : unsigned(0 to 13);--read
signal stop_count_s : std_logic:='0';
type state_mdio is (idle, set_conf, reset_st,read_st,wait_st,config);
signal state : state_mdio;
signal count_conf : unsigned(3 downto 0):=x"0";
signal reset_done : std_logic:='0';
signal tempo : std_logic:='1';
begin
process(CLK,RESET)
begin
if RESET = '0' then
E_RST_L <= '0';--hold reset condition for 1 second
E_MDC <= '1';
E_MDIO <= 'Z';
stop_count_s <= '0';
count <= x"0000000";
elsif CLK'event and CLK = '1' then
if (count(11) = '1' or count(4) = '1') then
E_MDC <= '1';
else--maximum frequency of E_MDC is 8.3 MHz
E_MDC <= '0';--3.9 MHz
end if;
case state is
when idle =>
if count = x"F000000" and stop_count_s='0' then
state <= wait_st;
count <= x"0000000";
elsif count > x"0140000" and count < x"0280000" and stop_count_s='0' then
E_RST_L <= '0';
count <= count +1;
elsif count = x"F000000" and stop_count_s='1' then
state <= read_st;
count <= x"8000000";
else
E_RST_L <= '1';
count <= count +1;
end if;
when wait_st =>
if count = x"FFFFFFF" then
count <= x"8000000";
if reset_done='0' then
state <= set_conf;
elsif reset_done='1' and tempo='1' then
state <= wait_st;
tempo <= '0';
else
state <= config;
end if;
else
count <= count +1;
end if;
when set_conf =>
--request <= "0101" & "10010" & "10100" & "100000110011100000"; -- set delay for RX and TX in rgmii mode
if count=x"8000FFF" then
state <= reset_st;
count <= x"8000000";
else
count <= count +1;
end if;
when reset_st =>
--request <= "0101" & "10010" & "00000" & "101001000101000000"; -- reset PHY
if count=x"8000FFF" then
--stop_count_s <= '1';
count <= x"0000000";
state <= wait_st;
reset_done<='1' ;
else
count <= count +1;
end if;
when config =>
if count_conf=x"0" then
--request <= "0101" & "10010" & "10100" & "100000110011100001"; -- set reg 20 for rgmii
--request <= "0101" & "10010" & "00000" & "100101000101000000"; -- stop loopback = 100101000101000000 --reg 0
else
--request <= "0101" & "10010" & "11110" & "101000100100100000"; -- packet generator activated
end if;
if count=x"8000FFF" then
if count_conf=x"0" then
state <= config;
count <= x"8000000";
count_conf <= count_conf +1;
else
stop_count_s <= '1';
state <= idle;
end if;
else
count <= count +1;
end if;
when read_st =>
request_r <= "0110" & "10010" & "10100";
if count=x"8000FFF" then
state <= idle;
count <= x"8000000";
else
count <= count +1;
end if;
when others =>
state <= idle;
end case;
end if;
end process;
E_MDIO <= '1' when count(11 downto 5) < "0100000" and (state=set_conf or state=reset_st or state=read_st or state=config) --32 1's preamble
else request(to_integer(count(9 downto 5))) when (state=set_conf or state=reset_st or state=config) and count(11 downto 5) <= "0111111" --write data
else request_r(to_integer(count(9 downto 5))) when state=read_st and count(11 downto 5) <= "0101101" -- read data
else 'Z';
end Behavioral;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 24 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 480 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 99
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
entity elab2_bot is
port (
i : in integer;
o : out integer );
end entity;
architecture test of elab2_bot is
begin
process (i) is
begin
o <= i + 1;
end process;
end architecture;
-------------------------------------------------------------------------------
entity elab2 is
end entity;
architecture test of elab2 is
signal a, b, c : integer;
begin
bot1: entity work.elab2_bot
port map ( a, b );
bot2: entity work.elab2_bot
port map ( b, c );
process is
begin
a <= 0;
wait for 1 ns;
assert b = 1;
assert c = 2;
a <= 2;
wait for 1 ns;
assert b = 3;
assert c = 4;
wait;
end process;
end architecture;
|
entity elab2_bot is
port (
i : in integer;
o : out integer );
end entity;
architecture test of elab2_bot is
begin
process (i) is
begin
o <= i + 1;
end process;
end architecture;
-------------------------------------------------------------------------------
entity elab2 is
end entity;
architecture test of elab2 is
signal a, b, c : integer;
begin
bot1: entity work.elab2_bot
port map ( a, b );
bot2: entity work.elab2_bot
port map ( b, c );
process is
begin
a <= 0;
wait for 1 ns;
assert b = 1;
assert c = 2;
a <= 2;
wait for 1 ns;
assert b = 3;
assert c = 4;
wait;
end process;
end architecture;
|
entity elab2_bot is
port (
i : in integer;
o : out integer );
end entity;
architecture test of elab2_bot is
begin
process (i) is
begin
o <= i + 1;
end process;
end architecture;
-------------------------------------------------------------------------------
entity elab2 is
end entity;
architecture test of elab2 is
signal a, b, c : integer;
begin
bot1: entity work.elab2_bot
port map ( a, b );
bot2: entity work.elab2_bot
port map ( b, c );
process is
begin
a <= 0;
wait for 1 ns;
assert b = 1;
assert c = 2;
a <= 2;
wait for 1 ns;
assert b = 3;
assert c = 4;
wait;
end process;
end architecture;
|
entity elab2_bot is
port (
i : in integer;
o : out integer );
end entity;
architecture test of elab2_bot is
begin
process (i) is
begin
o <= i + 1;
end process;
end architecture;
-------------------------------------------------------------------------------
entity elab2 is
end entity;
architecture test of elab2 is
signal a, b, c : integer;
begin
bot1: entity work.elab2_bot
port map ( a, b );
bot2: entity work.elab2_bot
port map ( b, c );
process is
begin
a <= 0;
wait for 1 ns;
assert b = 1;
assert c = 2;
a <= 2;
wait for 1 ns;
assert b = 3;
assert c = 4;
wait;
end process;
end architecture;
|
entity elab2_bot is
port (
i : in integer;
o : out integer );
end entity;
architecture test of elab2_bot is
begin
process (i) is
begin
o <= i + 1;
end process;
end architecture;
-------------------------------------------------------------------------------
entity elab2 is
end entity;
architecture test of elab2 is
signal a, b, c : integer;
begin
bot1: entity work.elab2_bot
port map ( a, b );
bot2: entity work.elab2_bot
port map ( b, c );
process is
begin
a <= 0;
wait for 1 ns;
assert b = 1;
assert c = 2;
a <= 2;
wait for 1 ns;
assert b = 3;
assert c = 4;
wait;
end process;
end architecture;
|
-------------------------------------------------------------------------------
--! @file dpRamSplx-e.vhd
--
--! @brief Simplex Dual Port Ram Entity
--
--! @details This is the Simplex DPRAM entity.
--! The DPRAM has one write and one read port only.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--! use global library
use work.global.all;
entity dpRamSplx is
generic (
--! Word width port A [bit]
gWordWidthA : natural := 16;
--! Byteenable width port A [bit]
gByteenableWidthA : natural := 2;
--! Number of words (reference is port A)
gNumberOfWordsA : natural := 1024;
--! Word width port B [bit]
gWordWidthB : natural := 32;
--! Number of words (reference is port B)
gNumberOfWordsB : natural := 512;
--! Initialization file
gInitFile : string := "UNUSED"
);
port (
-- PORT A
--! Clock of port A
iClk_A : in std_logic;
--! Enable of port A
iEnable_A : in std_logic;
--! Write enable of port A
iWriteEnable_A : in std_logic;
--! Address of port A
iAddress_A : in std_logic_vector(logDualis(gNumberOfWordsA)-1 downto 0);
--! Byteenable of port A
iByteenable_A : in std_logic_vector(gByteenableWidthA-1 downto 0);
--! Writedata of port A
iWritedata_A : in std_logic_vector(gWordWidthA-1 downto 0);
-- PORT B
--! Clock of port B
iClk_B : in std_logic;
--! Enable of port B
iEnable_B : in std_logic;
--! Address of port B
iAddress_B : in std_logic_vector(logDualis(gNumberOfWordsB)-1 downto 0);
--! Readdata of port B
oReaddata_B : out std_logic_vector(gWordWidthB-1 downto 0)
);
end dpRamSplx;
|
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|
`protect begin_protected
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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E7tzU0WM+sEENRZp12nqAbYerQE+tb3If5KIrj3pPfxcKnFX94ZnV20NzFcLCAGxHzzPqlLvOQS1
b4sLfF66TBzqzONMNE36JH0c6ZEUC5SF0HaZBfoplxOSrJgIEm5Ly0SS5Ex9eCSS3idoBSsMgIYJ
r2LkdEPrl5TV63lCuo2DOLG7+vN9d12Da/OUThtV/RdJMOdNByKRtMMmwUID2mG4BHErI4O2D8Oq
l6OjQPn7i2t4t+mwIIrXSECIUn1TeIjLCedi46IZo5a4AjwV
`protect end_protected
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fetch_mem is
port(
clk, rst : in std_logic;
read_addr : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(15 downto 0));
end fetch_mem;
architecture mixed of fetch_mem is
type mem_type is array(255 downto 0) of std_logic_vector(15 downto 0);
signal mem_data : mem_type;
begin
process(clk, rst)
begin
if (rst = '1') then
--mem_data(0) <= X"0000";
--mem_data(1) <= X"A000"; --load R0 <= Mem(0) //R0 = 0x0A
--mem_data(2) <= X"A101"; --load R1 <= Mem(1) //R0 = 0x02
--mem_data(3) <= X"2001"; -- add R0 <= R0 + R1
--mem_data(4) <= X"A202"; --load R2
--mem_data(5) <= X"0000"; --nop
--mem_data(6) <= X"2001"; --add R0 <= R0 + R1 //R0 = 0x0C
--mem_data(7) <= X"0000";
--mem_data(8) <= X"B000"; --store Mem(0) <= R0
--mem_data(9) <= X"8021";
--mem_data(4) <= X"A101"; --load R1 <= Mem(1) //R1 = 0x02
--mem_data(5) <= X"0000"; --nop
--mem_data(6) <= X"B101"; --store Mem(1) <= R1
--mem_data(4) <= X"A202"; --load R2 <= Mem(2) //R2 = 0x31
--mem_data(5) <= X"2001"; --add R0 <= R0 + R1 //R0 = 0x0C
--mem_data(6) <= X"B001"; --store Mem(1) <= R0 //Mem(1) = 0x0C
--mem_data(6) <= X"2101"; --sub R0 <= R0 - R1 //R0 = 0x0B
--mem_data(7) <= X"B001"; --store Mem(1) <= R0 //Mem(1) = 0x0B
--mem_data(8) <= X"9011"; --store Mem(R1) <= R1 //Mem(49) = 0x31
--mem_data(9) <= X"A201"; --load R2 <= Mem(1) //R2 = 0x0B
--mem_data(10) <= X"8031"; --load R3 <= Mem(R1) //R3 = 0x31
--mem_data(11) <= X"5600"; --clear R0 //R0 = 0
--mem_data(12) <= X"5710"; --set R1 //R1 = 1
--mem_data(13) <= X"5F10"; --if (R1<R0) set R1=1
--mem_data(14) <= X"5F01"; --if (R0<R1) set R0=1 //R0 = 1
--mem_data(15) <= X"C000"; --jump
mem_data(0) <= X"0000";
mem_data(1) <= X"A000"; --load R0 <= Mem(0) //R0 = 0x0A
mem_data(2) <= X"A101"; --load R1 <= Mem(1) //R1 = 0x02
mem_data(3) <= X"8011"; --load R1 <= Mem(R1) //R1 = 0x31
mem_data(4) <= X"1001"; --add R0 <= R0 + X"01" //R0 = 0x0B
mem_data(5) <= X"2001"; --add R0 <= R0 + R1 //R0 = 0x3C
mem_data(6) <= X"2101"; --sub R0 <= R0 - R1 //R0 = 0x0B
mem_data(7) <= X"B001"; --store Mem(1) <= R0 //Mem(1) = 0x0B
mem_data(8) <= X"9011"; --store Mem(R1) <= R1 //Mem(49) = 0x31
mem_data(9) <= X"A201"; --load R2 <= Mem(1) //R2 = 0x0B
mem_data(10) <= X"8031"; --load R3 <= Mem(R1) //R3 = 0x31
mem_data(11) <= X"D00F"; --branch if R0 is zero
mem_data(12) <= X"5600"; --clear R0 //R0 = 0
mem_data(13) <= X"5710"; --set R1 //R1 = 1
mem_data(14) <= X"E110"; --branch if R1 is not zero
mem_data(15) <= X"5F10"; --if (R1<R0) set R1=1
mem_data(16) <= X"5F01"; --if (R0<R1) set R0=1 //R0 = 1
mem_data(17) <= X"5831"; --mv R3, R1 //R3 = 1
mem_data(18) <= X"C028"; --jump // PC = 40
mem_data(19) <= X"B300"; --store Mem(0) <= R3 //Mem(0) = 0x31
mem_data(20) <= X"1001"; --add R0 <= R0 + X"01" //R0 = 0x0B
mem_data(21) <= X"B001"; --store Mem(1) <= R0 //Mem(1) = 0x0B
mem_data(22) <= X"F000"; --Return from interrupt
mem_data(32) <= X"2101"; --sub R0 <= R0 - R1 //R0 = 0x0B
mem_data(33) <= X"9011"; --store Mem(R1) <= R1 //Mem(49) = 0x31
mem_data(34) <= X"F000"; --Return from interrupt
mem_data(40) <= X"5403"; --and R0, R3 //R0 = 1
end if;
if falling_edge(clk) then
data_out <= mem_data(conv_integer(read_addr));
end if;
end process;
end mixed;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
-- Linear feedback shift register
library ieee;
use ieee.std_logic_1164.all;
entity lfsr_inferred is
generic (
state_bits : natural := 2
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
en : in std_ulogic;
output : out std_ulogic
);
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
package component_pack is
-- constant definitions
CONSTANT IDLE: std_logic_vector (5 downto 0) := "000001";
CONSTANT Local: std_logic_vector (5 downto 0) := "000010";
CONSTANT North: std_logic_vector (5 downto 0) := "000100";
CONSTANT East: std_logic_vector (5 downto 0) := "001000";
CONSTANT West: std_logic_vector (5 downto 0) := "010000";
CONSTANT South: std_logic_vector (5 downto 0) := "100000";
constant fake_tail : std_logic_vector := "10000000000000000000000000000001";
component router_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Rxy_rst : integer := 10;
Cx_rst : integer := 10;
healthy_counter_threshold : integer := 8;
faulty_counter_threshold: integer := 2;
counter_depth: integer := 4;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
Faulty_N_in, Faulty_E_in, Faulty_W_in, Faulty_S_in: in std_logic;
Faulty_N_out, Faulty_E_out, Faulty_W_out, Faulty_S_out: out std_logic;
-- should be connected to NI (Outputs for classified fault information)
link_faults: out std_logic_vector(4 downto 0);
turn_faults: out std_logic_vector(19 downto 0);
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic
---- fault injector shift register with serial input signals
--TCK: in std_logic;
--SE: in std_logic; -- shift enable
--UE: in std_logic; -- update enable
--SI: in std_logic; -- serial Input
--SO: out std_logic; -- serial output
---- Outputs for non-classified fault information
--link_faults_async: out std_logic_vector(4 downto 0);
--turn_faults_async: out std_logic_vector(19 downto 0)
);
end component;
-- component declarations
component network_2x2 is
generic (DATA_WIDTH: integer := 32; DATA_WIDTH_LV: integer := 11);
port (reset: in std_logic;
clk: in std_logic;
--------------
--------------
RX_L_0: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_0, valid_out_L_0: out std_logic;
credit_in_L_0, valid_in_L_0: in std_logic;
TX_L_0: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_1: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_1, valid_out_L_1: out std_logic;
credit_in_L_1, valid_in_L_1: in std_logic;
TX_L_1: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_2: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_2, valid_out_L_2: out std_logic;
credit_in_L_2, valid_in_L_2: in std_logic;
TX_L_2: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_3: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_3, valid_out_L_3: out std_logic;
credit_in_L_3, valid_in_L_3: in std_logic;
TX_L_3: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
link_faults_0: out std_logic_vector(4 downto 0);
turn_faults_0: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_0: in std_logic_vector(7 downto 0);
Cx_reconf_PE_0: in std_logic_vector(3 downto 0);
Reconfig_command_0 : in std_logic;
--------------
link_faults_1: out std_logic_vector(4 downto 0);
turn_faults_1: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_1: in std_logic_vector(7 downto 0);
Cx_reconf_PE_1: in std_logic_vector(3 downto 0);
Reconfig_command_1 : in std_logic;
--------------
link_faults_2: out std_logic_vector(4 downto 0);
turn_faults_2: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_2: in std_logic_vector(7 downto 0);
Cx_reconf_PE_2: in std_logic_vector(3 downto 0);
Reconfig_command_2 : in std_logic;
--------------
link_faults_3: out std_logic_vector(4 downto 0);
turn_faults_3: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_3: in std_logic_vector(7 downto 0);
Cx_reconf_PE_3: in std_logic_vector(3 downto 0);
Reconfig_command_3 : in std_logic;
-- IJTAG network for fault injection and checker status monitoring
TCK : in std_logic;
RST : in std_logic;
SEL : in std_logic;
SI : in std_logic;
SE : in std_logic;
UE : in std_logic;
CE : in std_logic;
SO : out std_logic;
toF : out std_logic;
toC : out std_logic
);
end component;
component NoC_Node is
generic( current_address : integer := 0;
stim_file: string :="code.txt";
log_file : string := "output.txt";
memory_type : string :=
"TRI_PORT_X"
-- "DUAL_PORT_"
-- "ALTERA_LPM"
-- "XILINX_16X"
);
port( reset : in std_logic;
clk : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0);
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(19 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0); -- if you are not going to update Cx you should write all ones! (it will be and will the current Cx bits)
Reconfig_command : out std_logic;
GPIO_out: out std_logic_vector(15 downto 0);
GPIO_in: in std_logic_vector(21 downto 0)
);
end component; --entity NoC_Node
COMPONENT counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, intermittent, Faulty: out std_logic
);
end COMPONENT;
--COMPONENT checkers_counter_threshold_classifier is
-- generic (
-- counter_depth: integer := 8;
-- healthy_counter_threshold: integer := 4;
-- faulty_counter_threshold: integer := 4
-- );
-- port ( reset: in std_logic;
-- clk: in std_logic;
-- data_input: in std_logic;
-- Healthy, Intermittent, Faulty: out std_logic
-- );
--end COMPONENT;
component LBDR_packet_drop_routing_part_pseudo_checkers is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port (
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
faulty: in std_logic;
Cx: in std_logic_vector(3 downto 0);
Rxy: in std_logic_vector(7 downto 0);
packet_drop: in std_logic;
N1_out, E1_out, W1_out, S1_out: in std_logic;
Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: in std_logic;
grants: in std_logic;
packet_drop_order: in std_logic;
packet_drop_in: in std_logic;
-- Checker outputs
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot,
err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in,
err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in, err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order : out std_logic
);
end component;
component Cx_Reconf_pseudo_checkers is
port ( reconfig_cx: in std_logic; -- *
flit_type: in std_logic_vector(2 downto 0); -- *
empty: in std_logic; -- *
grants: in std_logic; -- *
Cx_in: in std_logic_vector(3 downto 0); -- *
Temp_Cx: in std_logic_vector(3 downto 0); -- *
reconfig_cx_in: in std_logic; -- *
Cx: in std_logic_vector(3 downto 0); -- *
Cx_reconf_PE: in std_logic_vector(3 downto 0); -- newly added
Reconfig_command : in std_logic; -- newly added
Faulty_C_N: in std_logic; -- *
Faulty_C_E: in std_logic; -- *
Faulty_C_W: in std_logic; -- *
Faulty_C_S: in std_logic; -- *
Temp_Cx_in: in std_logic_vector(3 downto 0); -- *
-- Checker Outputs
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal : out std_logic -- Added
);
end component;
component Rxy_Reconf_pseudo_checkers is
port ( ReConf_FF_out: in std_logic;
Rxy: in std_logic_vector(7 downto 0);
Rxy_tmp: in std_logic_vector(7 downto 0);
Reconfig_command : in std_logic;
flit_type: in std_logic_vector(2 downto 0);
grants: in std_logic;
empty: in std_logic;
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Rxy_in: in std_logic_vector(7 downto 0);
Rxy_tmp_in: in std_logic_vector(7 downto 0);
ReConf_FF_in: in std_logic;
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal : out std_logic
);
end component;
component FIFO_credit_based_control_part_checkers is
port ( valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
read_pointer_in: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
write_pointer_in: in std_logic_vector(3 downto 0);
credit_out: in std_logic;
empty_out: in std_logic;
full_out: in std_logic;
read_en_out: in std_logic;
write_en_out: in std_logic;
fake_credit: in std_logic;
fake_credit_counter: in std_logic_vector(1 downto 0);
fake_credit_counter_in: in std_logic_vector(1 downto 0);
state_out: in std_logic_vector(4 downto 0);
state_in: in std_logic_vector(4 downto 0);
fault_info: in std_logic;
fault_info_out: in std_logic;
fault_info_in: in std_logic;
health_info: in std_logic;
faulty_packet_out: in std_logic;
faulty_packet_in: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
fault_out: in std_logic;
write_fake_flit: in std_logic;
-- Functional checkers
err_empty_full, err_empty_read_en, err_full_write_en, err_state_in_onehot,
err_read_pointer_in_onehot, err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer, err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full,
err_read_pointer_increment, err_read_pointer_not_increment, err_write_en, err_not_write_en,
err_not_write_en1, err_not_write_en2, err_read_en_mismatch, err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in : out std_logic
);
end component;
COMPONENT FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
fault_info, health_info: out std_logic;
---- fault injector shift register with serial input signals
--TCK: in std_logic;
--SE: in std_logic; -- shift enable
--UE: in std_logic; -- update enable
--SI: in std_logic; -- serial Input
--SO: out std_logic; -- serial output
-- Checker outputs
-- Functional checkers
err_empty_full, err_empty_read_en, err_full_write_en, err_state_in_onehot,
err_read_pointer_in_onehot, err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_write_en, err_not_write_en, err_not_write_en1, err_not_write_en2,
err_read_en_mismatch, err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in : out std_logic
);
end COMPONENT;
COMPONENT parity_checker_for_LBDR is
generic(DATA_WIDTH : integer := 32);
port(
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
empty: in std_logic;
faulty: out std_logic
);
end COMPONENT;
COMPONENT LBDR_packet_drop is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
faulty: in std_logic;
packet_drop_order: out std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic;
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic;
---- fault injector shift register with serial input signals
--TCK: in std_logic;
--SE: in std_logic; -- shift enable
--UE: in std_logic; -- update enable
--SI: in std_logic; -- serial Input
--SO: out std_logic; -- serial output
-- Checker outputs
-- Routing part checkers
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot,
err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in,
err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in,
err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order,
-- Cx_Reconf checkers
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added
-- Rxy_Reconf checkers
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal : out std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
--component fault_injector
-- generic(
-- DATA_WIDTH : integer := 32;
-- ADDRESS_WIDTH : integer := 5
-- );
-- port(
-- data_in: in std_logic_vector (DATA_WIDTH-1 downto 0);
-- address: in std_logic_vector (ADDRESS_WIDTH-1 downto 0);
-- sta_0: in std_logic;
-- sta_1: in std_logic;
-- data_out: out std_logic_vector (DATA_WIDTH-1 downto 0)
-- );
--end component;
--component shift_register_serial_in
-- generic (
-- REG_WIDTH: integer := 32
-- );
-- port (
-- TCK, reset : in std_logic;
-- SE: in std_logic; -- shift enable
-- UE: in std_logic; -- update enable
-- SI: in std_logic; -- serial Input
-- SO: out std_logic; -- serial output
-- data_out_parallel: out std_logic_vector(REG_WIDTH-1 downto 0)
-- );
--end component;
component Arbiter_in
port ( reset: in std_logic;
clk: in std_logic;
Req_X_N, Req_X_E, Req_X_W, Req_X_S, Req_X_L: in std_logic; -- From LBDR modules
X_N, X_E, X_W, X_S, X_L: out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
-- fault injector shift register with serial input signals
--TCK: in std_logic;
--SE: in std_logic; -- shift enable
--UE: in std_logic; -- update enable
--SI: in std_logic; -- serial Input
--SO: out std_logic; -- serial output
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N, err_IDLE_grant_N,err_North_Req_N, err_North_grant_N, err_East_Req_E, err_East_grant_E,
err_West_Req_W, err_West_grant_W, err_South_Req_S,err_South_grant_S,err_Local_Req_L, err_Local_grant_L,
err_IDLE_Req_E, err_IDLE_grant_E, err_North_Req_E, err_North_grant_E, err_East_Req_W, err_East_grant_W,
err_West_Req_S, err_West_grant_S, err_South_Req_L, err_South_grant_L, err_Local_Req_N, err_Local_grant_N,
err_IDLE_Req_W, err_IDLE_grant_W, err_North_Req_W, err_North_grant_W, err_East_Req_S, err_East_grant_S,
err_West_Req_L, err_West_grant_L, err_South_Req_N, err_South_grant_N, err_Local_Req_E, err_Local_grant_E,
err_IDLE_Req_S, err_IDLE_grant_S, err_North_Req_S, err_North_grant_S, err_East_Req_L, err_East_grant_L,
err_West_Req_N, err_West_grant_N, err_South_Req_E, err_South_grant_E, err_Local_Req_W, err_Local_grant_W,
err_IDLE_Req_L, err_IDLE_grant_L, err_North_Req_L, err_North_grant_L, err_East_Req_N, err_East_grant_N,
err_West_Req_E, err_West_grant_E, err_South_Req_W, err_South_grant_W, err_Local_Req_S, err_Local_grant_S,
err_state_in_onehot, err_no_request_grants, err_request_no_grants,
err_no_Req_N_grant_N, err_no_Req_E_grant_E, err_no_Req_W_grant_W, err_no_Req_S_grant_S, err_no_Req_L_grant_L : out std_logic
);
end component;
component Arbiter_in_one_hot_checkers
port (
req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_logic;
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
X_N, X_E, X_W, X_S, X_L :in std_logic;
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N, err_IDLE_grant_N,err_North_Req_N, err_North_grant_N, err_East_Req_E, err_East_grant_E,
err_West_Req_W, err_West_grant_W, err_South_Req_S,err_South_grant_S,err_Local_Req_L, err_Local_grant_L,
err_IDLE_Req_E, err_IDLE_grant_E, err_North_Req_E, err_North_grant_E, err_East_Req_W, err_East_grant_W,
err_West_Req_S, err_West_grant_S, err_South_Req_L, err_South_grant_L, err_Local_Req_N, err_Local_grant_N,
err_IDLE_Req_W, err_IDLE_grant_W, err_North_Req_W, err_North_grant_W, err_East_Req_S, err_East_grant_S,
err_West_Req_L, err_West_grant_L, err_South_Req_N, err_South_grant_N, err_Local_Req_E, err_Local_grant_E,
err_IDLE_Req_S, err_IDLE_grant_S, err_North_Req_S, err_North_grant_S, err_East_Req_L, err_East_grant_L,
err_West_Req_N, err_West_grant_N, err_South_Req_E, err_South_grant_E, err_Local_Req_W, err_Local_grant_W,
err_IDLE_Req_L, err_IDLE_grant_L, err_North_Req_L, err_North_grant_L, err_East_Req_N, err_East_grant_N,
err_West_Req_E, err_West_grant_E, err_South_Req_W, err_South_grant_W, err_Local_Req_S, err_Local_grant_S,
err_state_in_onehot, err_no_request_grants, err_request_no_grants, err_no_Req_N_grant_N,
err_no_Req_E_grant_E, err_no_Req_W_grant_W, err_no_Req_S_grant_S, err_no_Req_L_grant_L : out std_logic
);
end component;
component Arbiter_out_one_hot_pseudo_checkers
port ( credit: in std_logic_vector(1 downto 0);
req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_logic; -- From LBDR modules
state: in std_logic_vector (5 downto 0); -- 6 states for Arbiter_out's FSM
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : in std_logic; -- Grants given to LBDR requests (encoded as one-hot)
state_in: in std_logic_vector (5 downto 0); -- 6 states for Arbiter's FSM
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_req_X_N, err_North_req_X_N, err_North_credit_not_zero_req_X_N_grant_N,
err_North_credit_zero_or_not_req_X_N_not_grant_N,
err_East_req_X_E, err_East_credit_not_zero_req_X_E_grant_E, err_East_credit_zero_or_not_req_X_E_not_grant_E,
err_West_req_X_W, err_West_credit_not_zero_req_X_W_grant_W, err_West_credit_zero_or_not_req_X_W_not_grant_W,
err_South_req_X_S, err_South_credit_not_zero_req_X_S_grant_S, err_South_credit_zero_or_not_req_X_S_not_grant_S,
err_Local_req_X_L, err_Local_credit_not_zero_req_X_L_grant_L, err_Local_credit_zero_or_not_req_X_L_not_grant_L,
err_IDLE_req_X_E, err_North_req_X_E, err_East_req_X_W, err_West_req_X_S, err_South_req_X_L, err_Local_req_X_N,
err_IDLE_req_X_W, err_North_req_X_W, err_East_req_X_S, err_West_req_X_L, err_South_req_X_N, err_Local_req_X_E,
err_IDLE_req_X_S, err_North_req_X_S, err_East_req_X_L, err_West_req_X_N, err_South_req_X_E, err_Local_req_X_W,
err_IDLE_req_X_L, err_North_req_X_L, err_East_req_X_N, err_West_req_X_E, err_South_req_X_W, err_Local_req_X_S,
err_state_in_onehot, err_no_request_grants, err_request_IDLE_state,
err_request_IDLE_not_Grants, err_state_North_Invalid_Grant, err_state_East_Invalid_Grant,
err_state_West_Invalid_Grant, err_state_South_Invalid_Grant, err_state_Local_Invalid_Grant,
err_Grants_onehot_or_all_zero : out std_logic
);
end component;
component arbiter_out port (
reset: in std_logic;
clk: in std_logic;
X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y :in std_logic; -- From LBDR modules
credit: in std_logic_vector(1 downto 0);
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
-- fault injector shift register with serial input signals
--TCK: in std_logic;
--SE: in std_logic; -- shift enable
--UE: in std_logic; -- update enable
--SI: in std_logic; -- serial Input
--SO: out std_logic; -- serial output
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_req_X_N, err_North_req_X_N, err_North_credit_not_zero_req_X_N_grant_N,
err_North_credit_zero_or_not_req_X_N_not_grant_N,
err_East_req_X_E, err_East_credit_not_zero_req_X_E_grant_E,
err_East_credit_zero_or_not_req_X_E_not_grant_E,
err_West_req_X_W, err_West_credit_not_zero_req_X_W_grant_W,
err_West_credit_zero_or_not_req_X_W_not_grant_W,
err_South_req_X_S, err_South_credit_not_zero_req_X_S_grant_S,
err_South_credit_zero_or_not_req_X_S_not_grant_S,
err_Local_req_X_L, err_Local_credit_not_zero_req_X_L_grant_L,
err_Local_credit_zero_or_not_req_X_L_not_grant_L,
err_IDLE_req_X_E, err_North_req_X_E, err_East_req_X_W, err_West_req_X_S, err_South_req_X_L, err_Local_req_X_N,
err_IDLE_req_X_W, err_North_req_X_W, err_East_req_X_S, err_West_req_X_L, err_South_req_X_N, err_Local_req_X_E,
err_IDLE_req_X_S, err_North_req_X_S, err_East_req_X_L, err_West_req_X_N, err_South_req_X_E, err_Local_req_X_W,
err_IDLE_req_X_L, err_North_req_X_L, err_East_req_X_N, err_West_req_X_E, err_South_req_X_W, err_Local_req_X_S,
err_state_in_onehot, err_no_request_grants, err_request_IDLE_state,
err_request_IDLE_not_Grants, err_state_North_Invalid_Grant, err_state_East_Invalid_Grant,
err_state_West_Invalid_Grant, err_state_South_Invalid_Grant, err_state_Local_Invalid_Grant,
err_Grants_onehot_or_all_zero : out std_logic );
end component;
component allocator_logic_pseudo_checkers
port (
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
grant_N_N_sig, grant_N_E_sig, grant_N_W_sig, grant_N_S_sig, grant_N_L_sig: in std_logic;
grant_E_N_sig, grant_E_E_sig, grant_E_W_sig, grant_E_S_sig, grant_E_L_sig: in std_logic;
grant_W_N_sig, grant_W_E_sig, grant_W_W_sig, grant_W_S_sig, grant_W_L_sig: in std_logic;
grant_S_N_sig, grant_S_E_sig, grant_S_W_sig, grant_S_S_sig, grant_S_L_sig: in std_logic;
grant_L_N_sig, grant_L_E_sig, grant_L_W_sig, grant_L_S_sig, grant_L_L_sig: in std_logic;
valid_N, valid_E, valid_W, valid_S, valid_L : in std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: in std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: in std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: in std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: in std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: in std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L : in std_logic;
-- Checker outputs
err_grant_N_N_sig_not_empty_N_grant_N_N, err_not_grant_N_N_sig_or_empty_N_not_grant_N_N,
err_grant_N_E_sig_not_empty_E_grant_N_E, err_not_grant_N_E_sig_or_empty_E_not_grant_N_E,
err_grant_N_W_sig_not_empty_W_grant_N_W, err_not_grant_N_W_sig_or_empty_W_not_grant_N_W,
err_grant_N_S_sig_not_empty_S_grant_N_S, err_not_grant_N_S_sig_or_empty_S_not_grant_N_S,
err_grant_N_L_sig_not_empty_L_grant_N_L, err_not_grant_N_L_sig_or_empty_L_not_grant_N_L,
err_grant_E_N_sig_not_empty_N_grant_E_N, err_not_grant_E_N_sig_or_empty_N_not_grant_E_N,
err_grant_E_E_sig_not_empty_E_grant_E_E, err_not_grant_E_E_sig_or_empty_E_not_grant_E_E,
err_grant_E_W_sig_not_empty_W_grant_E_W, err_not_grant_E_W_sig_or_empty_W_not_grant_E_W,
err_grant_E_S_sig_not_empty_S_grant_E_S, err_not_grant_E_S_sig_or_empty_S_not_grant_E_S,
err_grant_E_L_sig_not_empty_L_grant_E_L, err_not_grant_E_L_sig_or_empty_L_not_grant_E_L,
err_grant_W_N_sig_not_empty_N_grant_W_N, err_not_grant_W_N_sig_or_empty_N_not_grant_W_N,
err_grant_W_E_sig_not_empty_E_grant_W_E, err_not_grant_W_E_sig_or_empty_E_not_grant_W_E,
err_grant_W_W_sig_not_empty_W_grant_W_W, err_not_grant_W_W_sig_or_empty_W_not_grant_W_W,
err_grant_W_S_sig_not_empty_S_grant_W_S, err_not_grant_W_S_sig_or_empty_S_not_grant_W_S,
err_grant_W_L_sig_not_empty_L_grant_W_L, err_not_grant_W_L_sig_or_empty_L_not_grant_W_L,
err_grant_S_N_sig_not_empty_N_grant_S_N, err_not_grant_S_N_sig_or_empty_N_not_grant_S_N,
err_grant_S_E_sig_not_empty_E_grant_S_E, err_not_grant_S_E_sig_or_empty_E_not_grant_S_E,
err_grant_S_W_sig_not_empty_W_grant_S_W, err_not_grant_S_W_sig_or_empty_W_not_grant_S_W,
err_grant_S_S_sig_not_empty_S_grant_S_S, err_not_grant_S_S_sig_or_empty_S_not_grant_S_S,
err_grant_S_L_sig_not_empty_L_grant_S_L, err_not_grant_S_L_sig_or_empty_L_not_grant_S_L,
err_grant_L_N_sig_not_empty_N_grant_L_N, err_not_grant_L_N_sig_or_empty_N_not_grant_L_N,
err_grant_L_E_sig_not_empty_E_grant_L_E, err_not_grant_L_E_sig_or_empty_E_not_grant_L_E,
err_grant_L_W_sig_not_empty_W_grant_L_W, err_not_grant_L_W_sig_or_empty_W_not_grant_L_W,
err_grant_L_S_sig_not_empty_S_grant_L_S, err_not_grant_L_S_sig_or_empty_S_not_grant_L_S,
err_grant_L_L_sig_not_empty_L_grant_L_L, err_not_grant_L_L_sig_or_empty_L_not_grant_L_L,
err_grant_signals_not_empty_grant_N, err_not_grant_signals_empty_not_grant_N,
err_grant_signals_not_empty_grant_E, err_not_grant_signals_empty_not_grant_E,
err_grant_signals_not_empty_grant_W, err_not_grant_signals_empty_not_grant_W,
err_grant_signals_not_empty_grant_S, err_not_grant_signals_empty_not_grant_S,
err_grant_signals_not_empty_grant_L, err_not_grant_signals_empty_not_grant_L,
err_grants_valid_not_match : out std_logic
);
end component;
component allocator_credit_counter_logic_pseudo_checkers
port (
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
credit_counter_N_out, credit_counter_E_out, credit_counter_W_out, credit_counter_S_out, credit_counter_L_out : in std_logic_vector(1 downto 0);
valid_N, valid_E, valid_W, valid_S, valid_L: in std_logic; -- ?? Not sure yet ! grant or valid !
credit_counter_N_in, credit_counter_E_in, credit_counter_W_in, credit_counter_S_in, credit_counter_L_in : in std_logic_vector(1 downto 0);
-- Checker outputs
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_N_credit_counter_N_out_increment,
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change,
err_grant_N_credit_counter_N_out_decrement,
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change,
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_E_credit_counter_E_out_increment,
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change,
err_grant_E_credit_counter_E_out_decrement,
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change,
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_W_credit_counter_W_out_increment,
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change,
err_grant_W_credit_counter_W_out_decrement,
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change,
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_S_credit_counter_S_out_increment,
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change,
err_grant_S_credit_counter_S_out_decrement,
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change,
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal,
err_credit_in_L_credit_counter_L_out_increment,
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change,
err_grant_L_credit_counter_L_out_decrement,
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change,
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal : out std_logic
);
end component;
component allocator
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic;
-- fault injector shift register with serial input signals
--TCK: in std_logic;
--SE: in std_logic; -- shift enable
--UE: in std_logic; -- update enable
--SI: in std_logic; -- serial Input
--SO: out std_logic; -- serial output
-- Allocator logic checker outputs
err_grant_N_N_sig_not_empty_N_grant_N_N, err_not_grant_N_N_sig_or_empty_N_not_grant_N_N, err_grant_N_E_sig_not_empty_E_grant_N_E,
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E, err_grant_N_W_sig_not_empty_W_grant_N_W, err_not_grant_N_W_sig_or_empty_W_not_grant_N_W,
err_grant_N_S_sig_not_empty_S_grant_N_S, err_not_grant_N_S_sig_or_empty_S_not_grant_N_S, err_grant_N_L_sig_not_empty_L_grant_N_L,
err_not_grant_N_L_sig_or_empty_L_not_grant_N_L,
err_grant_E_N_sig_not_empty_N_grant_E_N, err_not_grant_E_N_sig_or_empty_N_not_grant_E_N, err_grant_E_E_sig_not_empty_E_grant_E_E,
err_not_grant_E_E_sig_or_empty_E_not_grant_E_E, err_grant_E_W_sig_not_empty_W_grant_E_W, err_not_grant_E_W_sig_or_empty_W_not_grant_E_W,
err_grant_E_S_sig_not_empty_S_grant_E_S, err_not_grant_E_S_sig_or_empty_S_not_grant_E_S, err_grant_E_L_sig_not_empty_L_grant_E_L,
err_not_grant_E_L_sig_or_empty_L_not_grant_E_L,
err_grant_W_N_sig_not_empty_N_grant_W_N, err_not_grant_W_N_sig_or_empty_N_not_grant_W_N, err_grant_W_E_sig_not_empty_E_grant_W_E,
err_not_grant_W_E_sig_or_empty_E_not_grant_W_E, err_grant_W_W_sig_not_empty_W_grant_W_W, err_not_grant_W_W_sig_or_empty_W_not_grant_W_W,
err_grant_W_S_sig_not_empty_S_grant_W_S, err_not_grant_W_S_sig_or_empty_S_not_grant_W_S, err_grant_W_L_sig_not_empty_L_grant_W_L,
err_not_grant_W_L_sig_or_empty_L_not_grant_W_L,
err_grant_S_N_sig_not_empty_N_grant_S_N, err_not_grant_S_N_sig_or_empty_N_not_grant_S_N, err_grant_S_E_sig_not_empty_E_grant_S_E,
err_not_grant_S_E_sig_or_empty_E_not_grant_S_E, err_grant_S_W_sig_not_empty_W_grant_S_W, err_not_grant_S_W_sig_or_empty_W_not_grant_S_W,
err_grant_S_S_sig_not_empty_S_grant_S_S, err_not_grant_S_S_sig_or_empty_S_not_grant_S_S, err_grant_S_L_sig_not_empty_L_grant_S_L,
err_not_grant_S_L_sig_or_empty_L_not_grant_S_L,
err_grant_L_N_sig_not_empty_N_grant_L_N, err_not_grant_L_N_sig_or_empty_N_not_grant_L_N, err_grant_L_E_sig_not_empty_E_grant_L_E,
err_not_grant_L_E_sig_or_empty_E_not_grant_L_E, err_grant_L_W_sig_not_empty_W_grant_L_W, err_not_grant_L_W_sig_or_empty_W_not_grant_L_W,
err_grant_L_S_sig_not_empty_S_grant_L_S, err_not_grant_L_S_sig_or_empty_S_not_grant_L_S, err_grant_L_L_sig_not_empty_L_grant_L_L,
err_not_grant_L_L_sig_or_empty_L_not_grant_L_L,
err_grant_signals_not_empty_grant_N, err_not_grant_signals_empty_not_grant_N, err_grant_signals_not_empty_grant_E,
err_not_grant_signals_empty_not_grant_E, err_grant_signals_not_empty_grant_W, err_not_grant_signals_empty_not_grant_W,
err_grant_signals_not_empty_grant_S, err_not_grant_signals_empty_not_grant_S, err_grant_signals_not_empty_grant_L,
err_not_grant_signals_empty_not_grant_L,
err_grants_valid_not_match,
-- Allocator credit counter logic checker outputs
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal, err_credit_in_N_credit_counter_N_out_increment,
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change, err_grant_N_credit_counter_N_out_decrement,
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change,
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal, err_credit_in_E_credit_counter_E_out_increment,
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change, err_grant_E_credit_counter_E_out_decrement,
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change,
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal, err_credit_in_W_credit_counter_W_out_increment,
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change, err_grant_W_credit_counter_W_out_decrement,
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change,
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal, err_credit_in_S_credit_counter_S_out_increment,
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change, err_grant_S_credit_counter_S_out_decrement,
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change,
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal, err_credit_in_L_credit_counter_L_out_increment,
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change, err_grant_L_credit_counter_L_out_decrement,
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change,
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal,
-- Arbiter_in checker outputs
-- North Arbiter_in checker outputs
N_err_Requests_state_in_state_not_equal,
N_err_IDLE_Req_N, N_err_IDLE_grant_N, N_err_North_Req_N, N_err_North_grant_N, N_err_East_Req_E, N_err_East_grant_E,
N_err_West_Req_W, N_err_West_grant_W, N_err_South_Req_S,N_err_South_grant_S,N_err_Local_Req_L, N_err_Local_grant_L,
N_err_IDLE_Req_E, N_err_IDLE_grant_E, N_err_North_Req_E, N_err_North_grant_E, N_err_East_Req_W, N_err_East_grant_W,
N_err_West_Req_S, N_err_West_grant_S, N_err_South_Req_L, N_err_South_grant_L, N_err_Local_Req_N, N_err_Local_grant_N,
N_err_IDLE_Req_W, N_err_IDLE_grant_W, N_err_North_Req_W, N_err_North_grant_W, N_err_East_Req_S, N_err_East_grant_S,
N_err_West_Req_L, N_err_West_grant_L, N_err_South_Req_N, N_err_South_grant_N, N_err_Local_Req_E, N_err_Local_grant_E,
N_err_IDLE_Req_S, N_err_IDLE_grant_S, N_err_North_Req_S, N_err_North_grant_S, N_err_East_Req_L, N_err_East_grant_L,
N_err_West_Req_N, N_err_West_grant_N, N_err_South_Req_E, N_err_South_grant_E, N_err_Local_Req_W, N_err_Local_grant_W,
N_err_IDLE_Req_L, N_err_IDLE_grant_L, N_err_North_Req_L, N_err_North_grant_L, N_err_East_Req_N, N_err_East_grant_N,
N_err_West_Req_E, N_err_West_grant_E, N_err_South_Req_W, N_err_South_grant_W, N_err_Local_Req_S, N_err_Local_grant_S,
N_err_state_in_onehot, N_err_no_request_grants, N_err_request_no_grants,
N_err_no_Req_N_grant_N, N_err_no_Req_E_grant_E, N_err_no_Req_W_grant_W, N_err_no_Req_S_grant_S, N_err_no_Req_L_grant_L,
-- East Arbiter_in checker outputs
E_err_Requests_state_in_state_not_equal,
E_err_IDLE_Req_N, E_err_IDLE_grant_N, E_err_North_Req_N, E_err_North_grant_N, E_err_East_Req_E, E_err_East_grant_E,
E_err_West_Req_W, E_err_West_grant_W, E_err_South_Req_S, E_err_South_grant_S, E_err_Local_Req_L, E_err_Local_grant_L,
E_err_IDLE_Req_E, E_err_IDLE_grant_E, E_err_North_Req_E, E_err_North_grant_E, E_err_East_Req_W, E_err_East_grant_W,
E_err_West_Req_S, E_err_West_grant_S, E_err_South_Req_L, E_err_South_grant_L, E_err_Local_Req_N, E_err_Local_grant_N,
E_err_IDLE_Req_W, E_err_IDLE_grant_W, E_err_North_Req_W, E_err_North_grant_W, E_err_East_Req_S, E_err_East_grant_S,
E_err_West_Req_L, E_err_West_grant_L, E_err_South_Req_N, E_err_South_grant_N, E_err_Local_Req_E, E_err_Local_grant_E,
E_err_IDLE_Req_S, E_err_IDLE_grant_S, E_err_North_Req_S, E_err_North_grant_S, E_err_East_Req_L, E_err_East_grant_L,
E_err_West_Req_N, E_err_West_grant_N, E_err_South_Req_E, E_err_South_grant_E, E_err_Local_Req_W, E_err_Local_grant_W,
E_err_IDLE_Req_L, E_err_IDLE_grant_L, E_err_North_Req_L, E_err_North_grant_L, E_err_East_Req_N, E_err_East_grant_N,
E_err_West_Req_E, E_err_West_grant_E, E_err_South_Req_W, E_err_South_grant_W, E_err_Local_Req_S, E_err_Local_grant_S,
E_err_state_in_onehot, E_err_no_request_grants, E_err_request_no_grants,
E_err_no_Req_N_grant_N, E_err_no_Req_E_grant_E, E_err_no_Req_W_grant_W, E_err_no_Req_S_grant_S, E_err_no_Req_L_grant_L,
-- West Arbiter_in checker outputs
W_err_Requests_state_in_state_not_equal,
W_err_IDLE_Req_N, W_err_IDLE_grant_N, W_err_North_Req_N, W_err_North_grant_N, W_err_East_Req_E, W_err_East_grant_E,
W_err_West_Req_W, W_err_West_grant_W, W_err_South_Req_S, W_err_South_grant_S, W_err_Local_Req_L, W_err_Local_grant_L,
W_err_IDLE_Req_E, W_err_IDLE_grant_E, W_err_North_Req_E, W_err_North_grant_E, W_err_East_Req_W, W_err_East_grant_W,
W_err_West_Req_S, W_err_West_grant_S, W_err_South_Req_L, W_err_South_grant_L, W_err_Local_Req_N, W_err_Local_grant_N,
W_err_IDLE_Req_W, W_err_IDLE_grant_W, W_err_North_Req_W, W_err_North_grant_W, W_err_East_Req_S, W_err_East_grant_S,
W_err_West_Req_L, W_err_West_grant_L, W_err_South_Req_N, W_err_South_grant_N, W_err_Local_Req_E, W_err_Local_grant_E,
W_err_IDLE_Req_S, W_err_IDLE_grant_S, W_err_North_Req_S, W_err_North_grant_S, W_err_East_Req_L, W_err_East_grant_L,
W_err_West_Req_N, W_err_West_grant_N, W_err_South_Req_E, W_err_South_grant_E, W_err_Local_Req_W, W_err_Local_grant_W,
W_err_IDLE_Req_L, W_err_IDLE_grant_L, W_err_North_Req_L, W_err_North_grant_L, W_err_East_Req_N, W_err_East_grant_N,
W_err_West_Req_E, W_err_West_grant_E, W_err_South_Req_W, W_err_South_grant_W, W_err_Local_Req_S, W_err_Local_grant_S,
W_err_state_in_onehot, W_err_no_request_grants, W_err_request_no_grants,
W_err_no_Req_N_grant_N, W_err_no_Req_E_grant_E, W_err_no_Req_W_grant_W, W_err_no_Req_S_grant_S, W_err_no_Req_L_grant_L,
-- South Arbiter_in checker outputs
S_err_Requests_state_in_state_not_equal,
S_err_IDLE_Req_N, S_err_IDLE_grant_N, S_err_North_Req_N, S_err_North_grant_N, S_err_East_Req_E, S_err_East_grant_E,
S_err_West_Req_W, S_err_West_grant_W, S_err_South_Req_S,S_err_South_grant_S,S_err_Local_Req_L, S_err_Local_grant_L,
S_err_IDLE_Req_E, S_err_IDLE_grant_E, S_err_North_Req_E, S_err_North_grant_E, S_err_East_Req_W, S_err_East_grant_W,
S_err_West_Req_S, S_err_West_grant_S, S_err_South_Req_L, S_err_South_grant_L, S_err_Local_Req_N, S_err_Local_grant_N,
S_err_IDLE_Req_W, S_err_IDLE_grant_W, S_err_North_Req_W, S_err_North_grant_W, S_err_East_Req_S, S_err_East_grant_S,
S_err_West_Req_L, S_err_West_grant_L, S_err_South_Req_N, S_err_South_grant_N, S_err_Local_Req_E, S_err_Local_grant_E,
S_err_IDLE_Req_S, S_err_IDLE_grant_S, S_err_North_Req_S, S_err_North_grant_S, S_err_East_Req_L, S_err_East_grant_L,
S_err_West_Req_N, S_err_West_grant_N, S_err_South_Req_E, S_err_South_grant_E, S_err_Local_Req_W, S_err_Local_grant_W,
S_err_IDLE_Req_L, S_err_IDLE_grant_L, S_err_North_Req_L, S_err_North_grant_L, S_err_East_Req_N, S_err_East_grant_N,
S_err_West_Req_E, S_err_West_grant_E, S_err_South_Req_W, S_err_South_grant_W, S_err_Local_Req_S, S_err_Local_grant_S,
S_err_state_in_onehot, S_err_no_request_grants, S_err_request_no_grants,
S_err_no_Req_N_grant_N, S_err_no_Req_E_grant_E, S_err_no_Req_W_grant_W, S_err_no_Req_S_grant_S, S_err_no_Req_L_grant_L,
-- Local Arbiter_in checker outputs
L_err_Requests_state_in_state_not_equal,
L_err_IDLE_Req_N, L_err_IDLE_grant_N, L_err_North_Req_N, L_err_North_grant_N, L_err_East_Req_E, L_err_East_grant_E,
L_err_West_Req_W, L_err_West_grant_W, L_err_South_Req_S, L_err_South_grant_S, L_err_Local_Req_L, L_err_Local_grant_L,
L_err_IDLE_Req_E, L_err_IDLE_grant_E, L_err_North_Req_E, L_err_North_grant_E, L_err_East_Req_W, L_err_East_grant_W,
L_err_West_Req_S, L_err_West_grant_S, L_err_South_Req_L, L_err_South_grant_L, L_err_Local_Req_N, L_err_Local_grant_N,
L_err_IDLE_Req_W, L_err_IDLE_grant_W, L_err_North_Req_W, L_err_North_grant_W, L_err_East_Req_S, L_err_East_grant_S,
L_err_West_Req_L, L_err_West_grant_L, L_err_South_Req_N, L_err_South_grant_N, L_err_Local_Req_E, L_err_Local_grant_E,
L_err_IDLE_Req_S, L_err_IDLE_grant_S, L_err_North_Req_S, L_err_North_grant_S, L_err_East_Req_L, L_err_East_grant_L,
L_err_West_Req_N, L_err_West_grant_N, L_err_South_Req_E, L_err_South_grant_E, L_err_Local_Req_W, L_err_Local_grant_W,
L_err_IDLE_Req_L, L_err_IDLE_grant_L, L_err_North_Req_L, L_err_North_grant_L, L_err_East_Req_N, L_err_East_grant_N,
L_err_West_Req_E, L_err_West_grant_E, L_err_South_Req_W, L_err_South_grant_W, L_err_Local_Req_S, L_err_Local_grant_S,
L_err_state_in_onehot, L_err_no_request_grants, L_err_request_no_grants,
L_err_no_Req_N_grant_N, L_err_no_Req_E_grant_E, L_err_no_Req_W_grant_W, L_err_no_Req_S_grant_S, L_err_no_Req_L_grant_L,
-- Arbiter_out checker outputs
-- North Arbiter_out checker outputs
N_arbiter_out_err_Requests_state_in_state_not_equal,
N_err_IDLE_req_X_N, N_err_North_req_X_N, N_err_North_credit_not_zero_req_X_N_grant_N, N_err_North_credit_zero_or_not_req_X_N_not_grant_N,
N_err_East_req_X_E, N_err_East_credit_not_zero_req_X_E_grant_E, N_err_East_credit_zero_or_not_req_X_E_not_grant_E,
N_err_West_req_X_W, N_err_West_credit_not_zero_req_X_W_grant_W, N_err_West_credit_zero_or_not_req_X_W_not_grant_W,
N_err_South_req_X_S, N_err_South_credit_not_zero_req_X_S_grant_S, N_err_South_credit_zero_or_not_req_X_S_not_grant_S,
N_err_Local_req_X_L, N_err_Local_credit_not_zero_req_X_L_grant_L, N_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
N_err_IDLE_req_X_E, N_err_North_req_X_E, N_err_East_req_X_W, N_err_West_req_X_S, N_err_South_req_X_L, N_err_Local_req_X_N,
N_err_IDLE_req_X_W, N_err_North_req_X_W, N_err_East_req_X_S, N_err_West_req_X_L, N_err_South_req_X_N, N_err_Local_req_X_E,
N_err_IDLE_req_X_S, N_err_North_req_X_S, N_err_East_req_X_L, N_err_West_req_X_N, N_err_South_req_X_E, N_err_Local_req_X_W,
N_err_IDLE_req_X_L, N_err_North_req_X_L, N_err_East_req_X_N, N_err_West_req_X_E, N_err_South_req_X_W, N_err_Local_req_X_S,
N_arbiter_out_err_state_in_onehot, N_arbiter_out_err_no_request_grants, N_err_request_IDLE_state,
N_err_request_IDLE_not_Grants, N_err_state_North_Invalid_Grant, N_err_state_East_Invalid_Grant, N_err_state_West_Invalid_Grant,
N_err_state_South_Invalid_Grant, N_err_state_Local_Invalid_Grant, N_err_Grants_onehot_or_all_zero,
-- East Arbiter_out checker outputs
E_arbiter_out_err_Requests_state_in_state_not_equal,
E_err_IDLE_req_X_N, E_err_North_req_X_N, E_err_North_credit_not_zero_req_X_N_grant_N, E_err_North_credit_zero_or_not_req_X_N_not_grant_N,
E_err_East_req_X_E, E_err_East_credit_not_zero_req_X_E_grant_E, E_err_East_credit_zero_or_not_req_X_E_not_grant_E,
E_err_West_req_X_W, E_err_West_credit_not_zero_req_X_W_grant_W, E_err_West_credit_zero_or_not_req_X_W_not_grant_W,
E_err_South_req_X_S, E_err_South_credit_not_zero_req_X_S_grant_S, E_err_South_credit_zero_or_not_req_X_S_not_grant_S,
E_err_Local_req_X_L, E_err_Local_credit_not_zero_req_X_L_grant_L, E_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
E_err_IDLE_req_X_E, E_err_North_req_X_E, E_err_East_req_X_W, E_err_West_req_X_S, E_err_South_req_X_L, E_err_Local_req_X_N,
E_err_IDLE_req_X_W, E_err_North_req_X_W, E_err_East_req_X_S, E_err_West_req_X_L, E_err_South_req_X_N, E_err_Local_req_X_E,
E_err_IDLE_req_X_S, E_err_North_req_X_S, E_err_East_req_X_L, E_err_West_req_X_N, E_err_South_req_X_E, E_err_Local_req_X_W,
E_err_IDLE_req_X_L, E_err_North_req_X_L, E_err_East_req_X_N, E_err_West_req_X_E, E_err_South_req_X_W, E_err_Local_req_X_S,
E_arbiter_out_err_state_in_onehot, E_arbiter_out_err_no_request_grants, E_err_request_IDLE_state,
E_err_request_IDLE_not_Grants, E_err_state_North_Invalid_Grant,E_err_state_East_Invalid_Grant, E_err_state_West_Invalid_Grant,
E_err_state_South_Invalid_Grant, E_err_state_Local_Invalid_Grant, E_err_Grants_onehot_or_all_zero,
-- West Arbiter_out checker outputs
W_arbiter_out_err_Requests_state_in_state_not_equal,
W_err_IDLE_req_X_N, W_err_North_req_X_N, W_err_North_credit_not_zero_req_X_N_grant_N, W_err_North_credit_zero_or_not_req_X_N_not_grant_N,
W_err_East_req_X_E, W_err_East_credit_not_zero_req_X_E_grant_E, W_err_East_credit_zero_or_not_req_X_E_not_grant_E,
W_err_West_req_X_W, W_err_West_credit_not_zero_req_X_W_grant_W, W_err_West_credit_zero_or_not_req_X_W_not_grant_W,
W_err_South_req_X_S, W_err_South_credit_not_zero_req_X_S_grant_S, W_err_South_credit_zero_or_not_req_X_S_not_grant_S,
W_err_Local_req_X_L, W_err_Local_credit_not_zero_req_X_L_grant_L, W_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
W_err_IDLE_req_X_E, W_err_North_req_X_E, W_err_East_req_X_W, W_err_West_req_X_S, W_err_South_req_X_L, W_err_Local_req_X_N,
W_err_IDLE_req_X_W, W_err_North_req_X_W, W_err_East_req_X_S, W_err_West_req_X_L, W_err_South_req_X_N, W_err_Local_req_X_E,
W_err_IDLE_req_X_S, W_err_North_req_X_S, W_err_East_req_X_L, W_err_West_req_X_N, W_err_South_req_X_E, W_err_Local_req_X_W,
W_err_IDLE_req_X_L, W_err_North_req_X_L, W_err_East_req_X_N, W_err_West_req_X_E, W_err_South_req_X_W, W_err_Local_req_X_S,
W_arbiter_out_err_state_in_onehot, W_arbiter_out_err_no_request_grants, W_err_request_IDLE_state,
W_err_request_IDLE_not_Grants, W_err_state_North_Invalid_Grant, W_err_state_East_Invalid_Grant, W_err_state_West_Invalid_Grant,
W_err_state_South_Invalid_Grant, W_err_state_Local_Invalid_Grant, W_err_Grants_onehot_or_all_zero,
-- South Arbiter_out checker outputs
S_arbiter_out_err_Requests_state_in_state_not_equal,
S_err_IDLE_req_X_N, S_err_North_req_X_N, S_err_North_credit_not_zero_req_X_N_grant_N, S_err_North_credit_zero_or_not_req_X_N_not_grant_N,
S_err_East_req_X_E, S_err_East_credit_not_zero_req_X_E_grant_E, S_err_East_credit_zero_or_not_req_X_E_not_grant_E,
S_err_West_req_X_W, S_err_West_credit_not_zero_req_X_W_grant_W, S_err_West_credit_zero_or_not_req_X_W_not_grant_W,
S_err_South_req_X_S, S_err_South_credit_not_zero_req_X_S_grant_S, S_err_South_credit_zero_or_not_req_X_S_not_grant_S,
S_err_Local_req_X_L, S_err_Local_credit_not_zero_req_X_L_grant_L, S_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
S_err_IDLE_req_X_E, S_err_North_req_X_E, S_err_East_req_X_W, S_err_West_req_X_S, S_err_South_req_X_L, S_err_Local_req_X_N,
S_err_IDLE_req_X_W, S_err_North_req_X_W, S_err_East_req_X_S, S_err_West_req_X_L, S_err_South_req_X_N, S_err_Local_req_X_E,
S_err_IDLE_req_X_S, S_err_North_req_X_S, S_err_East_req_X_L, S_err_West_req_X_N, S_err_South_req_X_E, S_err_Local_req_X_W,
S_err_IDLE_req_X_L, S_err_North_req_X_L, S_err_East_req_X_N, S_err_West_req_X_E, S_err_South_req_X_W, S_err_Local_req_X_S,
S_arbiter_out_err_state_in_onehot, S_arbiter_out_err_no_request_grants, S_err_request_IDLE_state,
S_err_request_IDLE_not_Grants, S_err_state_North_Invalid_Grant, S_err_state_East_Invalid_Grant, S_err_state_West_Invalid_Grant,
S_err_state_South_Invalid_Grant, S_err_state_Local_Invalid_Grant, S_err_Grants_onehot_or_all_zero,
-- Local Arbiter_out checker outputs
L_arbiter_out_err_Requests_state_in_state_not_equal,
L_err_IDLE_req_X_N, L_err_North_req_X_N, L_err_North_credit_not_zero_req_X_N_grant_N, L_err_North_credit_zero_or_not_req_X_N_not_grant_N,
L_err_East_req_X_E, L_err_East_credit_not_zero_req_X_E_grant_E, L_err_East_credit_zero_or_not_req_X_E_not_grant_E, L_err_West_req_X_W,
L_err_West_credit_not_zero_req_X_W_grant_W, L_err_West_credit_zero_or_not_req_X_W_not_grant_W,
L_err_South_req_X_S, L_err_South_credit_not_zero_req_X_S_grant_S, L_err_South_credit_zero_or_not_req_X_S_not_grant_S,
L_err_Local_req_X_L, L_err_Local_credit_not_zero_req_X_L_grant_L, L_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
L_err_IDLE_req_X_E, L_err_North_req_X_E, L_err_East_req_X_W, L_err_West_req_X_S, L_err_South_req_X_L, L_err_Local_req_X_N,
L_err_IDLE_req_X_W, L_err_North_req_X_W, L_err_East_req_X_S, L_err_West_req_X_L, L_err_South_req_X_N, L_err_Local_req_X_E,
L_err_IDLE_req_X_S, L_err_North_req_X_S, L_err_East_req_X_L, L_err_West_req_X_N, L_err_South_req_X_E, L_err_Local_req_X_W,
L_err_IDLE_req_X_L, L_err_North_req_X_L, L_err_East_req_X_N, L_err_West_req_X_E, L_err_South_req_X_W, L_err_Local_req_X_S,
L_arbiter_out_err_state_in_onehot, L_arbiter_out_err_no_request_grants, L_err_request_IDLE_state,
L_err_request_IDLE_not_Grants, L_err_state_North_Invalid_Grant, L_err_state_East_Invalid_Grant, L_err_state_West_Invalid_Grant,
L_err_state_South_Invalid_Grant, L_err_state_Local_Invalid_Grant, L_err_Grants_onehot_or_all_zero : out std_logic
);
end component;
end; --package body
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
package component_pack is
-- constant definitions
CONSTANT IDLE: std_logic_vector (5 downto 0) := "000001";
CONSTANT Local: std_logic_vector (5 downto 0) := "000010";
CONSTANT North: std_logic_vector (5 downto 0) := "000100";
CONSTANT East: std_logic_vector (5 downto 0) := "001000";
CONSTANT West: std_logic_vector (5 downto 0) := "010000";
CONSTANT South: std_logic_vector (5 downto 0) := "100000";
constant fake_tail : std_logic_vector := "10000000000000000000000000000001";
component router_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Rxy_rst : integer := 10;
Cx_rst : integer := 10;
healthy_counter_threshold : integer := 8;
faulty_counter_threshold: integer := 2;
counter_depth: integer := 4;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
Faulty_N_in, Faulty_E_in, Faulty_W_in, Faulty_S_in: in std_logic;
Faulty_N_out, Faulty_E_out, Faulty_W_out, Faulty_S_out: out std_logic;
-- should be connected to NI (Outputs for classified fault information)
link_faults: out std_logic_vector(4 downto 0);
turn_faults: out std_logic_vector(19 downto 0);
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic
---- fault injector shift register with serial input signals
--TCK: in std_logic;
--SE: in std_logic; -- shift enable
--UE: in std_logic; -- update enable
--SI: in std_logic; -- serial Input
--SO: out std_logic; -- serial output
---- Outputs for non-classified fault information
--link_faults_async: out std_logic_vector(4 downto 0);
--turn_faults_async: out std_logic_vector(19 downto 0)
);
end component;
-- component declarations
component network_2x2 is
generic (DATA_WIDTH: integer := 32; DATA_WIDTH_LV: integer := 11);
port (reset: in std_logic;
clk: in std_logic;
--------------
--------------
RX_L_0: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_0, valid_out_L_0: out std_logic;
credit_in_L_0, valid_in_L_0: in std_logic;
TX_L_0: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_1: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_1, valid_out_L_1: out std_logic;
credit_in_L_1, valid_in_L_1: in std_logic;
TX_L_1: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_2: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_2, valid_out_L_2: out std_logic;
credit_in_L_2, valid_in_L_2: in std_logic;
TX_L_2: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_3: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_3, valid_out_L_3: out std_logic;
credit_in_L_3, valid_in_L_3: in std_logic;
TX_L_3: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
link_faults_0: out std_logic_vector(4 downto 0);
turn_faults_0: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_0: in std_logic_vector(7 downto 0);
Cx_reconf_PE_0: in std_logic_vector(3 downto 0);
Reconfig_command_0 : in std_logic;
--------------
link_faults_1: out std_logic_vector(4 downto 0);
turn_faults_1: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_1: in std_logic_vector(7 downto 0);
Cx_reconf_PE_1: in std_logic_vector(3 downto 0);
Reconfig_command_1 : in std_logic;
--------------
link_faults_2: out std_logic_vector(4 downto 0);
turn_faults_2: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_2: in std_logic_vector(7 downto 0);
Cx_reconf_PE_2: in std_logic_vector(3 downto 0);
Reconfig_command_2 : in std_logic;
--------------
link_faults_3: out std_logic_vector(4 downto 0);
turn_faults_3: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_3: in std_logic_vector(7 downto 0);
Cx_reconf_PE_3: in std_logic_vector(3 downto 0);
Reconfig_command_3 : in std_logic;
-- IJTAG network for fault injection and checker status monitoring
TCK : in std_logic;
RST : in std_logic;
SEL : in std_logic;
SI : in std_logic;
SE : in std_logic;
UE : in std_logic;
CE : in std_logic;
SO : out std_logic;
toF : out std_logic;
toC : out std_logic
);
end component;
component NoC_Node is
generic( current_address : integer := 0;
stim_file: string :="code.txt";
log_file : string := "output.txt";
memory_type : string :=
"TRI_PORT_X"
-- "DUAL_PORT_"
-- "ALTERA_LPM"
-- "XILINX_16X"
);
port( reset : in std_logic;
clk : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0);
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(19 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0); -- if you are not going to update Cx you should write all ones! (it will be and will the current Cx bits)
Reconfig_command : out std_logic;
GPIO_out: out std_logic_vector(15 downto 0);
GPIO_in: in std_logic_vector(21 downto 0)
);
end component; --entity NoC_Node
COMPONENT counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, intermittent, Faulty: out std_logic
);
end COMPONENT;
--COMPONENT checkers_counter_threshold_classifier is
-- generic (
-- counter_depth: integer := 8;
-- healthy_counter_threshold: integer := 4;
-- faulty_counter_threshold: integer := 4
-- );
-- port ( reset: in std_logic;
-- clk: in std_logic;
-- data_input: in std_logic;
-- Healthy, Intermittent, Faulty: out std_logic
-- );
--end COMPONENT;
component LBDR_packet_drop_routing_part_pseudo_checkers is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port (
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
faulty: in std_logic;
Cx: in std_logic_vector(3 downto 0);
Rxy: in std_logic_vector(7 downto 0);
packet_drop: in std_logic;
N1_out, E1_out, W1_out, S1_out: in std_logic;
Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: in std_logic;
grants: in std_logic;
packet_drop_order: in std_logic;
packet_drop_in: in std_logic;
-- Checker outputs
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot,
err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in,
err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in, err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order : out std_logic
);
end component;
component Cx_Reconf_pseudo_checkers is
port ( reconfig_cx: in std_logic; -- *
flit_type: in std_logic_vector(2 downto 0); -- *
empty: in std_logic; -- *
grants: in std_logic; -- *
Cx_in: in std_logic_vector(3 downto 0); -- *
Temp_Cx: in std_logic_vector(3 downto 0); -- *
reconfig_cx_in: in std_logic; -- *
Cx: in std_logic_vector(3 downto 0); -- *
Cx_reconf_PE: in std_logic_vector(3 downto 0); -- newly added
Reconfig_command : in std_logic; -- newly added
Faulty_C_N: in std_logic; -- *
Faulty_C_E: in std_logic; -- *
Faulty_C_W: in std_logic; -- *
Faulty_C_S: in std_logic; -- *
Temp_Cx_in: in std_logic_vector(3 downto 0); -- *
-- Checker Outputs
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal : out std_logic -- Added
);
end component;
component Rxy_Reconf_pseudo_checkers is
port ( ReConf_FF_out: in std_logic;
Rxy: in std_logic_vector(7 downto 0);
Rxy_tmp: in std_logic_vector(7 downto 0);
Reconfig_command : in std_logic;
flit_type: in std_logic_vector(2 downto 0);
grants: in std_logic;
empty: in std_logic;
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Rxy_in: in std_logic_vector(7 downto 0);
Rxy_tmp_in: in std_logic_vector(7 downto 0);
ReConf_FF_in: in std_logic;
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal : out std_logic
);
end component;
component FIFO_credit_based_control_part_checkers is
port ( valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
read_pointer_in: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
write_pointer_in: in std_logic_vector(3 downto 0);
credit_out: in std_logic;
empty_out: in std_logic;
full_out: in std_logic;
read_en_out: in std_logic;
write_en_out: in std_logic;
fake_credit: in std_logic;
fake_credit_counter: in std_logic_vector(1 downto 0);
fake_credit_counter_in: in std_logic_vector(1 downto 0);
state_out: in std_logic_vector(4 downto 0);
state_in: in std_logic_vector(4 downto 0);
fault_info: in std_logic;
fault_info_out: in std_logic;
fault_info_in: in std_logic;
health_info: in std_logic;
faulty_packet_out: in std_logic;
faulty_packet_in: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
fault_out: in std_logic;
write_fake_flit: in std_logic;
-- Functional checkers
err_empty_full, err_empty_read_en, err_full_write_en, err_state_in_onehot,
err_read_pointer_in_onehot, err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer, err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full,
err_read_pointer_increment, err_read_pointer_not_increment, err_write_en, err_not_write_en,
err_not_write_en1, err_not_write_en2, err_read_en_mismatch, err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in : out std_logic
);
end component;
COMPONENT FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
fault_info, health_info: out std_logic;
---- fault injector shift register with serial input signals
--TCK: in std_logic;
--SE: in std_logic; -- shift enable
--UE: in std_logic; -- update enable
--SI: in std_logic; -- serial Input
--SO: out std_logic; -- serial output
-- Checker outputs
-- Functional checkers
err_empty_full, err_empty_read_en, err_full_write_en, err_state_in_onehot,
err_read_pointer_in_onehot, err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_write_en, err_not_write_en, err_not_write_en1, err_not_write_en2,
err_read_en_mismatch, err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in : out std_logic
);
end COMPONENT;
COMPONENT parity_checker_for_LBDR is
generic(DATA_WIDTH : integer := 32);
port(
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
empty: in std_logic;
faulty: out std_logic
);
end COMPONENT;
COMPONENT LBDR_packet_drop is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
faulty: in std_logic;
packet_drop_order: out std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic;
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic;
---- fault injector shift register with serial input signals
--TCK: in std_logic;
--SE: in std_logic; -- shift enable
--UE: in std_logic; -- update enable
--SI: in std_logic; -- serial Input
--SO: out std_logic; -- serial output
-- Checker outputs
-- Routing part checkers
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot,
err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in,
err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in,
err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order,
-- Cx_Reconf checkers
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added
-- Rxy_Reconf checkers
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal : out std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
--component fault_injector
-- generic(
-- DATA_WIDTH : integer := 32;
-- ADDRESS_WIDTH : integer := 5
-- );
-- port(
-- data_in: in std_logic_vector (DATA_WIDTH-1 downto 0);
-- address: in std_logic_vector (ADDRESS_WIDTH-1 downto 0);
-- sta_0: in std_logic;
-- sta_1: in std_logic;
-- data_out: out std_logic_vector (DATA_WIDTH-1 downto 0)
-- );
--end component;
--component shift_register_serial_in
-- generic (
-- REG_WIDTH: integer := 32
-- );
-- port (
-- TCK, reset : in std_logic;
-- SE: in std_logic; -- shift enable
-- UE: in std_logic; -- update enable
-- SI: in std_logic; -- serial Input
-- SO: out std_logic; -- serial output
-- data_out_parallel: out std_logic_vector(REG_WIDTH-1 downto 0)
-- );
--end component;
component Arbiter_in
port ( reset: in std_logic;
clk: in std_logic;
Req_X_N, Req_X_E, Req_X_W, Req_X_S, Req_X_L: in std_logic; -- From LBDR modules
X_N, X_E, X_W, X_S, X_L: out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
-- fault injector shift register with serial input signals
--TCK: in std_logic;
--SE: in std_logic; -- shift enable
--UE: in std_logic; -- update enable
--SI: in std_logic; -- serial Input
--SO: out std_logic; -- serial output
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N, err_IDLE_grant_N,err_North_Req_N, err_North_grant_N, err_East_Req_E, err_East_grant_E,
err_West_Req_W, err_West_grant_W, err_South_Req_S,err_South_grant_S,err_Local_Req_L, err_Local_grant_L,
err_IDLE_Req_E, err_IDLE_grant_E, err_North_Req_E, err_North_grant_E, err_East_Req_W, err_East_grant_W,
err_West_Req_S, err_West_grant_S, err_South_Req_L, err_South_grant_L, err_Local_Req_N, err_Local_grant_N,
err_IDLE_Req_W, err_IDLE_grant_W, err_North_Req_W, err_North_grant_W, err_East_Req_S, err_East_grant_S,
err_West_Req_L, err_West_grant_L, err_South_Req_N, err_South_grant_N, err_Local_Req_E, err_Local_grant_E,
err_IDLE_Req_S, err_IDLE_grant_S, err_North_Req_S, err_North_grant_S, err_East_Req_L, err_East_grant_L,
err_West_Req_N, err_West_grant_N, err_South_Req_E, err_South_grant_E, err_Local_Req_W, err_Local_grant_W,
err_IDLE_Req_L, err_IDLE_grant_L, err_North_Req_L, err_North_grant_L, err_East_Req_N, err_East_grant_N,
err_West_Req_E, err_West_grant_E, err_South_Req_W, err_South_grant_W, err_Local_Req_S, err_Local_grant_S,
err_state_in_onehot, err_no_request_grants, err_request_no_grants,
err_no_Req_N_grant_N, err_no_Req_E_grant_E, err_no_Req_W_grant_W, err_no_Req_S_grant_S, err_no_Req_L_grant_L : out std_logic
);
end component;
component Arbiter_in_one_hot_checkers
port (
req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_logic;
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
X_N, X_E, X_W, X_S, X_L :in std_logic;
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N, err_IDLE_grant_N,err_North_Req_N, err_North_grant_N, err_East_Req_E, err_East_grant_E,
err_West_Req_W, err_West_grant_W, err_South_Req_S,err_South_grant_S,err_Local_Req_L, err_Local_grant_L,
err_IDLE_Req_E, err_IDLE_grant_E, err_North_Req_E, err_North_grant_E, err_East_Req_W, err_East_grant_W,
err_West_Req_S, err_West_grant_S, err_South_Req_L, err_South_grant_L, err_Local_Req_N, err_Local_grant_N,
err_IDLE_Req_W, err_IDLE_grant_W, err_North_Req_W, err_North_grant_W, err_East_Req_S, err_East_grant_S,
err_West_Req_L, err_West_grant_L, err_South_Req_N, err_South_grant_N, err_Local_Req_E, err_Local_grant_E,
err_IDLE_Req_S, err_IDLE_grant_S, err_North_Req_S, err_North_grant_S, err_East_Req_L, err_East_grant_L,
err_West_Req_N, err_West_grant_N, err_South_Req_E, err_South_grant_E, err_Local_Req_W, err_Local_grant_W,
err_IDLE_Req_L, err_IDLE_grant_L, err_North_Req_L, err_North_grant_L, err_East_Req_N, err_East_grant_N,
err_West_Req_E, err_West_grant_E, err_South_Req_W, err_South_grant_W, err_Local_Req_S, err_Local_grant_S,
err_state_in_onehot, err_no_request_grants, err_request_no_grants, err_no_Req_N_grant_N,
err_no_Req_E_grant_E, err_no_Req_W_grant_W, err_no_Req_S_grant_S, err_no_Req_L_grant_L : out std_logic
);
end component;
component Arbiter_out_one_hot_pseudo_checkers
port ( credit: in std_logic_vector(1 downto 0);
req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_logic; -- From LBDR modules
state: in std_logic_vector (5 downto 0); -- 6 states for Arbiter_out's FSM
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : in std_logic; -- Grants given to LBDR requests (encoded as one-hot)
state_in: in std_logic_vector (5 downto 0); -- 6 states for Arbiter's FSM
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_req_X_N, err_North_req_X_N, err_North_credit_not_zero_req_X_N_grant_N,
err_North_credit_zero_or_not_req_X_N_not_grant_N,
err_East_req_X_E, err_East_credit_not_zero_req_X_E_grant_E, err_East_credit_zero_or_not_req_X_E_not_grant_E,
err_West_req_X_W, err_West_credit_not_zero_req_X_W_grant_W, err_West_credit_zero_or_not_req_X_W_not_grant_W,
err_South_req_X_S, err_South_credit_not_zero_req_X_S_grant_S, err_South_credit_zero_or_not_req_X_S_not_grant_S,
err_Local_req_X_L, err_Local_credit_not_zero_req_X_L_grant_L, err_Local_credit_zero_or_not_req_X_L_not_grant_L,
err_IDLE_req_X_E, err_North_req_X_E, err_East_req_X_W, err_West_req_X_S, err_South_req_X_L, err_Local_req_X_N,
err_IDLE_req_X_W, err_North_req_X_W, err_East_req_X_S, err_West_req_X_L, err_South_req_X_N, err_Local_req_X_E,
err_IDLE_req_X_S, err_North_req_X_S, err_East_req_X_L, err_West_req_X_N, err_South_req_X_E, err_Local_req_X_W,
err_IDLE_req_X_L, err_North_req_X_L, err_East_req_X_N, err_West_req_X_E, err_South_req_X_W, err_Local_req_X_S,
err_state_in_onehot, err_no_request_grants, err_request_IDLE_state,
err_request_IDLE_not_Grants, err_state_North_Invalid_Grant, err_state_East_Invalid_Grant,
err_state_West_Invalid_Grant, err_state_South_Invalid_Grant, err_state_Local_Invalid_Grant,
err_Grants_onehot_or_all_zero : out std_logic
);
end component;
component arbiter_out port (
reset: in std_logic;
clk: in std_logic;
X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y :in std_logic; -- From LBDR modules
credit: in std_logic_vector(1 downto 0);
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
-- fault injector shift register with serial input signals
--TCK: in std_logic;
--SE: in std_logic; -- shift enable
--UE: in std_logic; -- update enable
--SI: in std_logic; -- serial Input
--SO: out std_logic; -- serial output
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_req_X_N, err_North_req_X_N, err_North_credit_not_zero_req_X_N_grant_N,
err_North_credit_zero_or_not_req_X_N_not_grant_N,
err_East_req_X_E, err_East_credit_not_zero_req_X_E_grant_E,
err_East_credit_zero_or_not_req_X_E_not_grant_E,
err_West_req_X_W, err_West_credit_not_zero_req_X_W_grant_W,
err_West_credit_zero_or_not_req_X_W_not_grant_W,
err_South_req_X_S, err_South_credit_not_zero_req_X_S_grant_S,
err_South_credit_zero_or_not_req_X_S_not_grant_S,
err_Local_req_X_L, err_Local_credit_not_zero_req_X_L_grant_L,
err_Local_credit_zero_or_not_req_X_L_not_grant_L,
err_IDLE_req_X_E, err_North_req_X_E, err_East_req_X_W, err_West_req_X_S, err_South_req_X_L, err_Local_req_X_N,
err_IDLE_req_X_W, err_North_req_X_W, err_East_req_X_S, err_West_req_X_L, err_South_req_X_N, err_Local_req_X_E,
err_IDLE_req_X_S, err_North_req_X_S, err_East_req_X_L, err_West_req_X_N, err_South_req_X_E, err_Local_req_X_W,
err_IDLE_req_X_L, err_North_req_X_L, err_East_req_X_N, err_West_req_X_E, err_South_req_X_W, err_Local_req_X_S,
err_state_in_onehot, err_no_request_grants, err_request_IDLE_state,
err_request_IDLE_not_Grants, err_state_North_Invalid_Grant, err_state_East_Invalid_Grant,
err_state_West_Invalid_Grant, err_state_South_Invalid_Grant, err_state_Local_Invalid_Grant,
err_Grants_onehot_or_all_zero : out std_logic );
end component;
component allocator_logic_pseudo_checkers
port (
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
grant_N_N_sig, grant_N_E_sig, grant_N_W_sig, grant_N_S_sig, grant_N_L_sig: in std_logic;
grant_E_N_sig, grant_E_E_sig, grant_E_W_sig, grant_E_S_sig, grant_E_L_sig: in std_logic;
grant_W_N_sig, grant_W_E_sig, grant_W_W_sig, grant_W_S_sig, grant_W_L_sig: in std_logic;
grant_S_N_sig, grant_S_E_sig, grant_S_W_sig, grant_S_S_sig, grant_S_L_sig: in std_logic;
grant_L_N_sig, grant_L_E_sig, grant_L_W_sig, grant_L_S_sig, grant_L_L_sig: in std_logic;
valid_N, valid_E, valid_W, valid_S, valid_L : in std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: in std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: in std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: in std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: in std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: in std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L : in std_logic;
-- Checker outputs
err_grant_N_N_sig_not_empty_N_grant_N_N, err_not_grant_N_N_sig_or_empty_N_not_grant_N_N,
err_grant_N_E_sig_not_empty_E_grant_N_E, err_not_grant_N_E_sig_or_empty_E_not_grant_N_E,
err_grant_N_W_sig_not_empty_W_grant_N_W, err_not_grant_N_W_sig_or_empty_W_not_grant_N_W,
err_grant_N_S_sig_not_empty_S_grant_N_S, err_not_grant_N_S_sig_or_empty_S_not_grant_N_S,
err_grant_N_L_sig_not_empty_L_grant_N_L, err_not_grant_N_L_sig_or_empty_L_not_grant_N_L,
err_grant_E_N_sig_not_empty_N_grant_E_N, err_not_grant_E_N_sig_or_empty_N_not_grant_E_N,
err_grant_E_E_sig_not_empty_E_grant_E_E, err_not_grant_E_E_sig_or_empty_E_not_grant_E_E,
err_grant_E_W_sig_not_empty_W_grant_E_W, err_not_grant_E_W_sig_or_empty_W_not_grant_E_W,
err_grant_E_S_sig_not_empty_S_grant_E_S, err_not_grant_E_S_sig_or_empty_S_not_grant_E_S,
err_grant_E_L_sig_not_empty_L_grant_E_L, err_not_grant_E_L_sig_or_empty_L_not_grant_E_L,
err_grant_W_N_sig_not_empty_N_grant_W_N, err_not_grant_W_N_sig_or_empty_N_not_grant_W_N,
err_grant_W_E_sig_not_empty_E_grant_W_E, err_not_grant_W_E_sig_or_empty_E_not_grant_W_E,
err_grant_W_W_sig_not_empty_W_grant_W_W, err_not_grant_W_W_sig_or_empty_W_not_grant_W_W,
err_grant_W_S_sig_not_empty_S_grant_W_S, err_not_grant_W_S_sig_or_empty_S_not_grant_W_S,
err_grant_W_L_sig_not_empty_L_grant_W_L, err_not_grant_W_L_sig_or_empty_L_not_grant_W_L,
err_grant_S_N_sig_not_empty_N_grant_S_N, err_not_grant_S_N_sig_or_empty_N_not_grant_S_N,
err_grant_S_E_sig_not_empty_E_grant_S_E, err_not_grant_S_E_sig_or_empty_E_not_grant_S_E,
err_grant_S_W_sig_not_empty_W_grant_S_W, err_not_grant_S_W_sig_or_empty_W_not_grant_S_W,
err_grant_S_S_sig_not_empty_S_grant_S_S, err_not_grant_S_S_sig_or_empty_S_not_grant_S_S,
err_grant_S_L_sig_not_empty_L_grant_S_L, err_not_grant_S_L_sig_or_empty_L_not_grant_S_L,
err_grant_L_N_sig_not_empty_N_grant_L_N, err_not_grant_L_N_sig_or_empty_N_not_grant_L_N,
err_grant_L_E_sig_not_empty_E_grant_L_E, err_not_grant_L_E_sig_or_empty_E_not_grant_L_E,
err_grant_L_W_sig_not_empty_W_grant_L_W, err_not_grant_L_W_sig_or_empty_W_not_grant_L_W,
err_grant_L_S_sig_not_empty_S_grant_L_S, err_not_grant_L_S_sig_or_empty_S_not_grant_L_S,
err_grant_L_L_sig_not_empty_L_grant_L_L, err_not_grant_L_L_sig_or_empty_L_not_grant_L_L,
err_grant_signals_not_empty_grant_N, err_not_grant_signals_empty_not_grant_N,
err_grant_signals_not_empty_grant_E, err_not_grant_signals_empty_not_grant_E,
err_grant_signals_not_empty_grant_W, err_not_grant_signals_empty_not_grant_W,
err_grant_signals_not_empty_grant_S, err_not_grant_signals_empty_not_grant_S,
err_grant_signals_not_empty_grant_L, err_not_grant_signals_empty_not_grant_L,
err_grants_valid_not_match : out std_logic
);
end component;
component allocator_credit_counter_logic_pseudo_checkers
port (
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
credit_counter_N_out, credit_counter_E_out, credit_counter_W_out, credit_counter_S_out, credit_counter_L_out : in std_logic_vector(1 downto 0);
valid_N, valid_E, valid_W, valid_S, valid_L: in std_logic; -- ?? Not sure yet ! grant or valid !
credit_counter_N_in, credit_counter_E_in, credit_counter_W_in, credit_counter_S_in, credit_counter_L_in : in std_logic_vector(1 downto 0);
-- Checker outputs
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_N_credit_counter_N_out_increment,
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change,
err_grant_N_credit_counter_N_out_decrement,
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change,
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_E_credit_counter_E_out_increment,
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change,
err_grant_E_credit_counter_E_out_decrement,
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change,
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_W_credit_counter_W_out_increment,
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change,
err_grant_W_credit_counter_W_out_decrement,
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change,
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_S_credit_counter_S_out_increment,
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change,
err_grant_S_credit_counter_S_out_decrement,
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change,
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal,
err_credit_in_L_credit_counter_L_out_increment,
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change,
err_grant_L_credit_counter_L_out_decrement,
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change,
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal : out std_logic
);
end component;
component allocator
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic;
-- fault injector shift register with serial input signals
--TCK: in std_logic;
--SE: in std_logic; -- shift enable
--UE: in std_logic; -- update enable
--SI: in std_logic; -- serial Input
--SO: out std_logic; -- serial output
-- Allocator logic checker outputs
err_grant_N_N_sig_not_empty_N_grant_N_N, err_not_grant_N_N_sig_or_empty_N_not_grant_N_N, err_grant_N_E_sig_not_empty_E_grant_N_E,
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E, err_grant_N_W_sig_not_empty_W_grant_N_W, err_not_grant_N_W_sig_or_empty_W_not_grant_N_W,
err_grant_N_S_sig_not_empty_S_grant_N_S, err_not_grant_N_S_sig_or_empty_S_not_grant_N_S, err_grant_N_L_sig_not_empty_L_grant_N_L,
err_not_grant_N_L_sig_or_empty_L_not_grant_N_L,
err_grant_E_N_sig_not_empty_N_grant_E_N, err_not_grant_E_N_sig_or_empty_N_not_grant_E_N, err_grant_E_E_sig_not_empty_E_grant_E_E,
err_not_grant_E_E_sig_or_empty_E_not_grant_E_E, err_grant_E_W_sig_not_empty_W_grant_E_W, err_not_grant_E_W_sig_or_empty_W_not_grant_E_W,
err_grant_E_S_sig_not_empty_S_grant_E_S, err_not_grant_E_S_sig_or_empty_S_not_grant_E_S, err_grant_E_L_sig_not_empty_L_grant_E_L,
err_not_grant_E_L_sig_or_empty_L_not_grant_E_L,
err_grant_W_N_sig_not_empty_N_grant_W_N, err_not_grant_W_N_sig_or_empty_N_not_grant_W_N, err_grant_W_E_sig_not_empty_E_grant_W_E,
err_not_grant_W_E_sig_or_empty_E_not_grant_W_E, err_grant_W_W_sig_not_empty_W_grant_W_W, err_not_grant_W_W_sig_or_empty_W_not_grant_W_W,
err_grant_W_S_sig_not_empty_S_grant_W_S, err_not_grant_W_S_sig_or_empty_S_not_grant_W_S, err_grant_W_L_sig_not_empty_L_grant_W_L,
err_not_grant_W_L_sig_or_empty_L_not_grant_W_L,
err_grant_S_N_sig_not_empty_N_grant_S_N, err_not_grant_S_N_sig_or_empty_N_not_grant_S_N, err_grant_S_E_sig_not_empty_E_grant_S_E,
err_not_grant_S_E_sig_or_empty_E_not_grant_S_E, err_grant_S_W_sig_not_empty_W_grant_S_W, err_not_grant_S_W_sig_or_empty_W_not_grant_S_W,
err_grant_S_S_sig_not_empty_S_grant_S_S, err_not_grant_S_S_sig_or_empty_S_not_grant_S_S, err_grant_S_L_sig_not_empty_L_grant_S_L,
err_not_grant_S_L_sig_or_empty_L_not_grant_S_L,
err_grant_L_N_sig_not_empty_N_grant_L_N, err_not_grant_L_N_sig_or_empty_N_not_grant_L_N, err_grant_L_E_sig_not_empty_E_grant_L_E,
err_not_grant_L_E_sig_or_empty_E_not_grant_L_E, err_grant_L_W_sig_not_empty_W_grant_L_W, err_not_grant_L_W_sig_or_empty_W_not_grant_L_W,
err_grant_L_S_sig_not_empty_S_grant_L_S, err_not_grant_L_S_sig_or_empty_S_not_grant_L_S, err_grant_L_L_sig_not_empty_L_grant_L_L,
err_not_grant_L_L_sig_or_empty_L_not_grant_L_L,
err_grant_signals_not_empty_grant_N, err_not_grant_signals_empty_not_grant_N, err_grant_signals_not_empty_grant_E,
err_not_grant_signals_empty_not_grant_E, err_grant_signals_not_empty_grant_W, err_not_grant_signals_empty_not_grant_W,
err_grant_signals_not_empty_grant_S, err_not_grant_signals_empty_not_grant_S, err_grant_signals_not_empty_grant_L,
err_not_grant_signals_empty_not_grant_L,
err_grants_valid_not_match,
-- Allocator credit counter logic checker outputs
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal, err_credit_in_N_credit_counter_N_out_increment,
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change, err_grant_N_credit_counter_N_out_decrement,
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change,
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal, err_credit_in_E_credit_counter_E_out_increment,
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change, err_grant_E_credit_counter_E_out_decrement,
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change,
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal, err_credit_in_W_credit_counter_W_out_increment,
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change, err_grant_W_credit_counter_W_out_decrement,
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change,
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal, err_credit_in_S_credit_counter_S_out_increment,
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change, err_grant_S_credit_counter_S_out_decrement,
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change,
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal, err_credit_in_L_credit_counter_L_out_increment,
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change, err_grant_L_credit_counter_L_out_decrement,
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change,
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal,
-- Arbiter_in checker outputs
-- North Arbiter_in checker outputs
N_err_Requests_state_in_state_not_equal,
N_err_IDLE_Req_N, N_err_IDLE_grant_N, N_err_North_Req_N, N_err_North_grant_N, N_err_East_Req_E, N_err_East_grant_E,
N_err_West_Req_W, N_err_West_grant_W, N_err_South_Req_S,N_err_South_grant_S,N_err_Local_Req_L, N_err_Local_grant_L,
N_err_IDLE_Req_E, N_err_IDLE_grant_E, N_err_North_Req_E, N_err_North_grant_E, N_err_East_Req_W, N_err_East_grant_W,
N_err_West_Req_S, N_err_West_grant_S, N_err_South_Req_L, N_err_South_grant_L, N_err_Local_Req_N, N_err_Local_grant_N,
N_err_IDLE_Req_W, N_err_IDLE_grant_W, N_err_North_Req_W, N_err_North_grant_W, N_err_East_Req_S, N_err_East_grant_S,
N_err_West_Req_L, N_err_West_grant_L, N_err_South_Req_N, N_err_South_grant_N, N_err_Local_Req_E, N_err_Local_grant_E,
N_err_IDLE_Req_S, N_err_IDLE_grant_S, N_err_North_Req_S, N_err_North_grant_S, N_err_East_Req_L, N_err_East_grant_L,
N_err_West_Req_N, N_err_West_grant_N, N_err_South_Req_E, N_err_South_grant_E, N_err_Local_Req_W, N_err_Local_grant_W,
N_err_IDLE_Req_L, N_err_IDLE_grant_L, N_err_North_Req_L, N_err_North_grant_L, N_err_East_Req_N, N_err_East_grant_N,
N_err_West_Req_E, N_err_West_grant_E, N_err_South_Req_W, N_err_South_grant_W, N_err_Local_Req_S, N_err_Local_grant_S,
N_err_state_in_onehot, N_err_no_request_grants, N_err_request_no_grants,
N_err_no_Req_N_grant_N, N_err_no_Req_E_grant_E, N_err_no_Req_W_grant_W, N_err_no_Req_S_grant_S, N_err_no_Req_L_grant_L,
-- East Arbiter_in checker outputs
E_err_Requests_state_in_state_not_equal,
E_err_IDLE_Req_N, E_err_IDLE_grant_N, E_err_North_Req_N, E_err_North_grant_N, E_err_East_Req_E, E_err_East_grant_E,
E_err_West_Req_W, E_err_West_grant_W, E_err_South_Req_S, E_err_South_grant_S, E_err_Local_Req_L, E_err_Local_grant_L,
E_err_IDLE_Req_E, E_err_IDLE_grant_E, E_err_North_Req_E, E_err_North_grant_E, E_err_East_Req_W, E_err_East_grant_W,
E_err_West_Req_S, E_err_West_grant_S, E_err_South_Req_L, E_err_South_grant_L, E_err_Local_Req_N, E_err_Local_grant_N,
E_err_IDLE_Req_W, E_err_IDLE_grant_W, E_err_North_Req_W, E_err_North_grant_W, E_err_East_Req_S, E_err_East_grant_S,
E_err_West_Req_L, E_err_West_grant_L, E_err_South_Req_N, E_err_South_grant_N, E_err_Local_Req_E, E_err_Local_grant_E,
E_err_IDLE_Req_S, E_err_IDLE_grant_S, E_err_North_Req_S, E_err_North_grant_S, E_err_East_Req_L, E_err_East_grant_L,
E_err_West_Req_N, E_err_West_grant_N, E_err_South_Req_E, E_err_South_grant_E, E_err_Local_Req_W, E_err_Local_grant_W,
E_err_IDLE_Req_L, E_err_IDLE_grant_L, E_err_North_Req_L, E_err_North_grant_L, E_err_East_Req_N, E_err_East_grant_N,
E_err_West_Req_E, E_err_West_grant_E, E_err_South_Req_W, E_err_South_grant_W, E_err_Local_Req_S, E_err_Local_grant_S,
E_err_state_in_onehot, E_err_no_request_grants, E_err_request_no_grants,
E_err_no_Req_N_grant_N, E_err_no_Req_E_grant_E, E_err_no_Req_W_grant_W, E_err_no_Req_S_grant_S, E_err_no_Req_L_grant_L,
-- West Arbiter_in checker outputs
W_err_Requests_state_in_state_not_equal,
W_err_IDLE_Req_N, W_err_IDLE_grant_N, W_err_North_Req_N, W_err_North_grant_N, W_err_East_Req_E, W_err_East_grant_E,
W_err_West_Req_W, W_err_West_grant_W, W_err_South_Req_S, W_err_South_grant_S, W_err_Local_Req_L, W_err_Local_grant_L,
W_err_IDLE_Req_E, W_err_IDLE_grant_E, W_err_North_Req_E, W_err_North_grant_E, W_err_East_Req_W, W_err_East_grant_W,
W_err_West_Req_S, W_err_West_grant_S, W_err_South_Req_L, W_err_South_grant_L, W_err_Local_Req_N, W_err_Local_grant_N,
W_err_IDLE_Req_W, W_err_IDLE_grant_W, W_err_North_Req_W, W_err_North_grant_W, W_err_East_Req_S, W_err_East_grant_S,
W_err_West_Req_L, W_err_West_grant_L, W_err_South_Req_N, W_err_South_grant_N, W_err_Local_Req_E, W_err_Local_grant_E,
W_err_IDLE_Req_S, W_err_IDLE_grant_S, W_err_North_Req_S, W_err_North_grant_S, W_err_East_Req_L, W_err_East_grant_L,
W_err_West_Req_N, W_err_West_grant_N, W_err_South_Req_E, W_err_South_grant_E, W_err_Local_Req_W, W_err_Local_grant_W,
W_err_IDLE_Req_L, W_err_IDLE_grant_L, W_err_North_Req_L, W_err_North_grant_L, W_err_East_Req_N, W_err_East_grant_N,
W_err_West_Req_E, W_err_West_grant_E, W_err_South_Req_W, W_err_South_grant_W, W_err_Local_Req_S, W_err_Local_grant_S,
W_err_state_in_onehot, W_err_no_request_grants, W_err_request_no_grants,
W_err_no_Req_N_grant_N, W_err_no_Req_E_grant_E, W_err_no_Req_W_grant_W, W_err_no_Req_S_grant_S, W_err_no_Req_L_grant_L,
-- South Arbiter_in checker outputs
S_err_Requests_state_in_state_not_equal,
S_err_IDLE_Req_N, S_err_IDLE_grant_N, S_err_North_Req_N, S_err_North_grant_N, S_err_East_Req_E, S_err_East_grant_E,
S_err_West_Req_W, S_err_West_grant_W, S_err_South_Req_S,S_err_South_grant_S,S_err_Local_Req_L, S_err_Local_grant_L,
S_err_IDLE_Req_E, S_err_IDLE_grant_E, S_err_North_Req_E, S_err_North_grant_E, S_err_East_Req_W, S_err_East_grant_W,
S_err_West_Req_S, S_err_West_grant_S, S_err_South_Req_L, S_err_South_grant_L, S_err_Local_Req_N, S_err_Local_grant_N,
S_err_IDLE_Req_W, S_err_IDLE_grant_W, S_err_North_Req_W, S_err_North_grant_W, S_err_East_Req_S, S_err_East_grant_S,
S_err_West_Req_L, S_err_West_grant_L, S_err_South_Req_N, S_err_South_grant_N, S_err_Local_Req_E, S_err_Local_grant_E,
S_err_IDLE_Req_S, S_err_IDLE_grant_S, S_err_North_Req_S, S_err_North_grant_S, S_err_East_Req_L, S_err_East_grant_L,
S_err_West_Req_N, S_err_West_grant_N, S_err_South_Req_E, S_err_South_grant_E, S_err_Local_Req_W, S_err_Local_grant_W,
S_err_IDLE_Req_L, S_err_IDLE_grant_L, S_err_North_Req_L, S_err_North_grant_L, S_err_East_Req_N, S_err_East_grant_N,
S_err_West_Req_E, S_err_West_grant_E, S_err_South_Req_W, S_err_South_grant_W, S_err_Local_Req_S, S_err_Local_grant_S,
S_err_state_in_onehot, S_err_no_request_grants, S_err_request_no_grants,
S_err_no_Req_N_grant_N, S_err_no_Req_E_grant_E, S_err_no_Req_W_grant_W, S_err_no_Req_S_grant_S, S_err_no_Req_L_grant_L,
-- Local Arbiter_in checker outputs
L_err_Requests_state_in_state_not_equal,
L_err_IDLE_Req_N, L_err_IDLE_grant_N, L_err_North_Req_N, L_err_North_grant_N, L_err_East_Req_E, L_err_East_grant_E,
L_err_West_Req_W, L_err_West_grant_W, L_err_South_Req_S, L_err_South_grant_S, L_err_Local_Req_L, L_err_Local_grant_L,
L_err_IDLE_Req_E, L_err_IDLE_grant_E, L_err_North_Req_E, L_err_North_grant_E, L_err_East_Req_W, L_err_East_grant_W,
L_err_West_Req_S, L_err_West_grant_S, L_err_South_Req_L, L_err_South_grant_L, L_err_Local_Req_N, L_err_Local_grant_N,
L_err_IDLE_Req_W, L_err_IDLE_grant_W, L_err_North_Req_W, L_err_North_grant_W, L_err_East_Req_S, L_err_East_grant_S,
L_err_West_Req_L, L_err_West_grant_L, L_err_South_Req_N, L_err_South_grant_N, L_err_Local_Req_E, L_err_Local_grant_E,
L_err_IDLE_Req_S, L_err_IDLE_grant_S, L_err_North_Req_S, L_err_North_grant_S, L_err_East_Req_L, L_err_East_grant_L,
L_err_West_Req_N, L_err_West_grant_N, L_err_South_Req_E, L_err_South_grant_E, L_err_Local_Req_W, L_err_Local_grant_W,
L_err_IDLE_Req_L, L_err_IDLE_grant_L, L_err_North_Req_L, L_err_North_grant_L, L_err_East_Req_N, L_err_East_grant_N,
L_err_West_Req_E, L_err_West_grant_E, L_err_South_Req_W, L_err_South_grant_W, L_err_Local_Req_S, L_err_Local_grant_S,
L_err_state_in_onehot, L_err_no_request_grants, L_err_request_no_grants,
L_err_no_Req_N_grant_N, L_err_no_Req_E_grant_E, L_err_no_Req_W_grant_W, L_err_no_Req_S_grant_S, L_err_no_Req_L_grant_L,
-- Arbiter_out checker outputs
-- North Arbiter_out checker outputs
N_arbiter_out_err_Requests_state_in_state_not_equal,
N_err_IDLE_req_X_N, N_err_North_req_X_N, N_err_North_credit_not_zero_req_X_N_grant_N, N_err_North_credit_zero_or_not_req_X_N_not_grant_N,
N_err_East_req_X_E, N_err_East_credit_not_zero_req_X_E_grant_E, N_err_East_credit_zero_or_not_req_X_E_not_grant_E,
N_err_West_req_X_W, N_err_West_credit_not_zero_req_X_W_grant_W, N_err_West_credit_zero_or_not_req_X_W_not_grant_W,
N_err_South_req_X_S, N_err_South_credit_not_zero_req_X_S_grant_S, N_err_South_credit_zero_or_not_req_X_S_not_grant_S,
N_err_Local_req_X_L, N_err_Local_credit_not_zero_req_X_L_grant_L, N_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
N_err_IDLE_req_X_E, N_err_North_req_X_E, N_err_East_req_X_W, N_err_West_req_X_S, N_err_South_req_X_L, N_err_Local_req_X_N,
N_err_IDLE_req_X_W, N_err_North_req_X_W, N_err_East_req_X_S, N_err_West_req_X_L, N_err_South_req_X_N, N_err_Local_req_X_E,
N_err_IDLE_req_X_S, N_err_North_req_X_S, N_err_East_req_X_L, N_err_West_req_X_N, N_err_South_req_X_E, N_err_Local_req_X_W,
N_err_IDLE_req_X_L, N_err_North_req_X_L, N_err_East_req_X_N, N_err_West_req_X_E, N_err_South_req_X_W, N_err_Local_req_X_S,
N_arbiter_out_err_state_in_onehot, N_arbiter_out_err_no_request_grants, N_err_request_IDLE_state,
N_err_request_IDLE_not_Grants, N_err_state_North_Invalid_Grant, N_err_state_East_Invalid_Grant, N_err_state_West_Invalid_Grant,
N_err_state_South_Invalid_Grant, N_err_state_Local_Invalid_Grant, N_err_Grants_onehot_or_all_zero,
-- East Arbiter_out checker outputs
E_arbiter_out_err_Requests_state_in_state_not_equal,
E_err_IDLE_req_X_N, E_err_North_req_X_N, E_err_North_credit_not_zero_req_X_N_grant_N, E_err_North_credit_zero_or_not_req_X_N_not_grant_N,
E_err_East_req_X_E, E_err_East_credit_not_zero_req_X_E_grant_E, E_err_East_credit_zero_or_not_req_X_E_not_grant_E,
E_err_West_req_X_W, E_err_West_credit_not_zero_req_X_W_grant_W, E_err_West_credit_zero_or_not_req_X_W_not_grant_W,
E_err_South_req_X_S, E_err_South_credit_not_zero_req_X_S_grant_S, E_err_South_credit_zero_or_not_req_X_S_not_grant_S,
E_err_Local_req_X_L, E_err_Local_credit_not_zero_req_X_L_grant_L, E_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
E_err_IDLE_req_X_E, E_err_North_req_X_E, E_err_East_req_X_W, E_err_West_req_X_S, E_err_South_req_X_L, E_err_Local_req_X_N,
E_err_IDLE_req_X_W, E_err_North_req_X_W, E_err_East_req_X_S, E_err_West_req_X_L, E_err_South_req_X_N, E_err_Local_req_X_E,
E_err_IDLE_req_X_S, E_err_North_req_X_S, E_err_East_req_X_L, E_err_West_req_X_N, E_err_South_req_X_E, E_err_Local_req_X_W,
E_err_IDLE_req_X_L, E_err_North_req_X_L, E_err_East_req_X_N, E_err_West_req_X_E, E_err_South_req_X_W, E_err_Local_req_X_S,
E_arbiter_out_err_state_in_onehot, E_arbiter_out_err_no_request_grants, E_err_request_IDLE_state,
E_err_request_IDLE_not_Grants, E_err_state_North_Invalid_Grant,E_err_state_East_Invalid_Grant, E_err_state_West_Invalid_Grant,
E_err_state_South_Invalid_Grant, E_err_state_Local_Invalid_Grant, E_err_Grants_onehot_or_all_zero,
-- West Arbiter_out checker outputs
W_arbiter_out_err_Requests_state_in_state_not_equal,
W_err_IDLE_req_X_N, W_err_North_req_X_N, W_err_North_credit_not_zero_req_X_N_grant_N, W_err_North_credit_zero_or_not_req_X_N_not_grant_N,
W_err_East_req_X_E, W_err_East_credit_not_zero_req_X_E_grant_E, W_err_East_credit_zero_or_not_req_X_E_not_grant_E,
W_err_West_req_X_W, W_err_West_credit_not_zero_req_X_W_grant_W, W_err_West_credit_zero_or_not_req_X_W_not_grant_W,
W_err_South_req_X_S, W_err_South_credit_not_zero_req_X_S_grant_S, W_err_South_credit_zero_or_not_req_X_S_not_grant_S,
W_err_Local_req_X_L, W_err_Local_credit_not_zero_req_X_L_grant_L, W_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
W_err_IDLE_req_X_E, W_err_North_req_X_E, W_err_East_req_X_W, W_err_West_req_X_S, W_err_South_req_X_L, W_err_Local_req_X_N,
W_err_IDLE_req_X_W, W_err_North_req_X_W, W_err_East_req_X_S, W_err_West_req_X_L, W_err_South_req_X_N, W_err_Local_req_X_E,
W_err_IDLE_req_X_S, W_err_North_req_X_S, W_err_East_req_X_L, W_err_West_req_X_N, W_err_South_req_X_E, W_err_Local_req_X_W,
W_err_IDLE_req_X_L, W_err_North_req_X_L, W_err_East_req_X_N, W_err_West_req_X_E, W_err_South_req_X_W, W_err_Local_req_X_S,
W_arbiter_out_err_state_in_onehot, W_arbiter_out_err_no_request_grants, W_err_request_IDLE_state,
W_err_request_IDLE_not_Grants, W_err_state_North_Invalid_Grant, W_err_state_East_Invalid_Grant, W_err_state_West_Invalid_Grant,
W_err_state_South_Invalid_Grant, W_err_state_Local_Invalid_Grant, W_err_Grants_onehot_or_all_zero,
-- South Arbiter_out checker outputs
S_arbiter_out_err_Requests_state_in_state_not_equal,
S_err_IDLE_req_X_N, S_err_North_req_X_N, S_err_North_credit_not_zero_req_X_N_grant_N, S_err_North_credit_zero_or_not_req_X_N_not_grant_N,
S_err_East_req_X_E, S_err_East_credit_not_zero_req_X_E_grant_E, S_err_East_credit_zero_or_not_req_X_E_not_grant_E,
S_err_West_req_X_W, S_err_West_credit_not_zero_req_X_W_grant_W, S_err_West_credit_zero_or_not_req_X_W_not_grant_W,
S_err_South_req_X_S, S_err_South_credit_not_zero_req_X_S_grant_S, S_err_South_credit_zero_or_not_req_X_S_not_grant_S,
S_err_Local_req_X_L, S_err_Local_credit_not_zero_req_X_L_grant_L, S_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
S_err_IDLE_req_X_E, S_err_North_req_X_E, S_err_East_req_X_W, S_err_West_req_X_S, S_err_South_req_X_L, S_err_Local_req_X_N,
S_err_IDLE_req_X_W, S_err_North_req_X_W, S_err_East_req_X_S, S_err_West_req_X_L, S_err_South_req_X_N, S_err_Local_req_X_E,
S_err_IDLE_req_X_S, S_err_North_req_X_S, S_err_East_req_X_L, S_err_West_req_X_N, S_err_South_req_X_E, S_err_Local_req_X_W,
S_err_IDLE_req_X_L, S_err_North_req_X_L, S_err_East_req_X_N, S_err_West_req_X_E, S_err_South_req_X_W, S_err_Local_req_X_S,
S_arbiter_out_err_state_in_onehot, S_arbiter_out_err_no_request_grants, S_err_request_IDLE_state,
S_err_request_IDLE_not_Grants, S_err_state_North_Invalid_Grant, S_err_state_East_Invalid_Grant, S_err_state_West_Invalid_Grant,
S_err_state_South_Invalid_Grant, S_err_state_Local_Invalid_Grant, S_err_Grants_onehot_or_all_zero,
-- Local Arbiter_out checker outputs
L_arbiter_out_err_Requests_state_in_state_not_equal,
L_err_IDLE_req_X_N, L_err_North_req_X_N, L_err_North_credit_not_zero_req_X_N_grant_N, L_err_North_credit_zero_or_not_req_X_N_not_grant_N,
L_err_East_req_X_E, L_err_East_credit_not_zero_req_X_E_grant_E, L_err_East_credit_zero_or_not_req_X_E_not_grant_E, L_err_West_req_X_W,
L_err_West_credit_not_zero_req_X_W_grant_W, L_err_West_credit_zero_or_not_req_X_W_not_grant_W,
L_err_South_req_X_S, L_err_South_credit_not_zero_req_X_S_grant_S, L_err_South_credit_zero_or_not_req_X_S_not_grant_S,
L_err_Local_req_X_L, L_err_Local_credit_not_zero_req_X_L_grant_L, L_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
L_err_IDLE_req_X_E, L_err_North_req_X_E, L_err_East_req_X_W, L_err_West_req_X_S, L_err_South_req_X_L, L_err_Local_req_X_N,
L_err_IDLE_req_X_W, L_err_North_req_X_W, L_err_East_req_X_S, L_err_West_req_X_L, L_err_South_req_X_N, L_err_Local_req_X_E,
L_err_IDLE_req_X_S, L_err_North_req_X_S, L_err_East_req_X_L, L_err_West_req_X_N, L_err_South_req_X_E, L_err_Local_req_X_W,
L_err_IDLE_req_X_L, L_err_North_req_X_L, L_err_East_req_X_N, L_err_West_req_X_E, L_err_South_req_X_W, L_err_Local_req_X_S,
L_arbiter_out_err_state_in_onehot, L_arbiter_out_err_no_request_grants, L_err_request_IDLE_state,
L_err_request_IDLE_not_Grants, L_err_state_North_Invalid_Grant, L_err_state_East_Invalid_Grant, L_err_state_West_Invalid_Grant,
L_err_state_South_Invalid_Grant, L_err_state_Local_Invalid_Grant, L_err_Grants_onehot_or_all_zero : out std_logic
);
end component;
end; --package body
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
package component_pack is
-- constant definitions
CONSTANT IDLE: std_logic_vector (5 downto 0) := "000001";
CONSTANT Local: std_logic_vector (5 downto 0) := "000010";
CONSTANT North: std_logic_vector (5 downto 0) := "000100";
CONSTANT East: std_logic_vector (5 downto 0) := "001000";
CONSTANT West: std_logic_vector (5 downto 0) := "010000";
CONSTANT South: std_logic_vector (5 downto 0) := "100000";
constant fake_tail : std_logic_vector := "10000000000000000000000000000001";
component router_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Rxy_rst : integer := 10;
Cx_rst : integer := 10;
healthy_counter_threshold : integer := 8;
faulty_counter_threshold: integer := 2;
counter_depth: integer := 4;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
Faulty_N_in, Faulty_E_in, Faulty_W_in, Faulty_S_in: in std_logic;
Faulty_N_out, Faulty_E_out, Faulty_W_out, Faulty_S_out: out std_logic;
-- should be connected to NI (Outputs for classified fault information)
link_faults: out std_logic_vector(4 downto 0);
turn_faults: out std_logic_vector(19 downto 0);
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic
---- fault injector shift register with serial input signals
--TCK: in std_logic;
--SE: in std_logic; -- shift enable
--UE: in std_logic; -- update enable
--SI: in std_logic; -- serial Input
--SO: out std_logic; -- serial output
---- Outputs for non-classified fault information
--link_faults_async: out std_logic_vector(4 downto 0);
--turn_faults_async: out std_logic_vector(19 downto 0)
);
end component;
-- component declarations
component network_2x2 is
generic (DATA_WIDTH: integer := 32; DATA_WIDTH_LV: integer := 11);
port (reset: in std_logic;
clk: in std_logic;
--------------
--------------
RX_L_0: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_0, valid_out_L_0: out std_logic;
credit_in_L_0, valid_in_L_0: in std_logic;
TX_L_0: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_1: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_1, valid_out_L_1: out std_logic;
credit_in_L_1, valid_in_L_1: in std_logic;
TX_L_1: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_2: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_2, valid_out_L_2: out std_logic;
credit_in_L_2, valid_in_L_2: in std_logic;
TX_L_2: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_3: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_3, valid_out_L_3: out std_logic;
credit_in_L_3, valid_in_L_3: in std_logic;
TX_L_3: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
link_faults_0: out std_logic_vector(4 downto 0);
turn_faults_0: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_0: in std_logic_vector(7 downto 0);
Cx_reconf_PE_0: in std_logic_vector(3 downto 0);
Reconfig_command_0 : in std_logic;
--------------
link_faults_1: out std_logic_vector(4 downto 0);
turn_faults_1: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_1: in std_logic_vector(7 downto 0);
Cx_reconf_PE_1: in std_logic_vector(3 downto 0);
Reconfig_command_1 : in std_logic;
--------------
link_faults_2: out std_logic_vector(4 downto 0);
turn_faults_2: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_2: in std_logic_vector(7 downto 0);
Cx_reconf_PE_2: in std_logic_vector(3 downto 0);
Reconfig_command_2 : in std_logic;
--------------
link_faults_3: out std_logic_vector(4 downto 0);
turn_faults_3: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_3: in std_logic_vector(7 downto 0);
Cx_reconf_PE_3: in std_logic_vector(3 downto 0);
Reconfig_command_3 : in std_logic;
-- IJTAG network for fault injection and checker status monitoring
TCK : in std_logic;
RST : in std_logic;
SEL : in std_logic;
SI : in std_logic;
SE : in std_logic;
UE : in std_logic;
CE : in std_logic;
SO : out std_logic;
toF : out std_logic;
toC : out std_logic
);
end component;
component NoC_Node is
generic( current_address : integer := 0;
stim_file: string :="code.txt";
log_file : string := "output.txt";
memory_type : string :=
"TRI_PORT_X"
-- "DUAL_PORT_"
-- "ALTERA_LPM"
-- "XILINX_16X"
);
port( reset : in std_logic;
clk : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0);
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(19 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0); -- if you are not going to update Cx you should write all ones! (it will be and will the current Cx bits)
Reconfig_command : out std_logic;
GPIO_out: out std_logic_vector(15 downto 0);
GPIO_in: in std_logic_vector(21 downto 0)
);
end component; --entity NoC_Node
COMPONENT counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, intermittent, Faulty: out std_logic
);
end COMPONENT;
--COMPONENT checkers_counter_threshold_classifier is
-- generic (
-- counter_depth: integer := 8;
-- healthy_counter_threshold: integer := 4;
-- faulty_counter_threshold: integer := 4
-- );
-- port ( reset: in std_logic;
-- clk: in std_logic;
-- data_input: in std_logic;
-- Healthy, Intermittent, Faulty: out std_logic
-- );
--end COMPONENT;
component LBDR_packet_drop_routing_part_pseudo_checkers is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port (
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
faulty: in std_logic;
Cx: in std_logic_vector(3 downto 0);
Rxy: in std_logic_vector(7 downto 0);
packet_drop: in std_logic;
N1_out, E1_out, W1_out, S1_out: in std_logic;
Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: in std_logic;
grants: in std_logic;
packet_drop_order: in std_logic;
packet_drop_in: in std_logic;
-- Checker outputs
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot,
err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in,
err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in, err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order : out std_logic
);
end component;
component Cx_Reconf_pseudo_checkers is
port ( reconfig_cx: in std_logic; -- *
flit_type: in std_logic_vector(2 downto 0); -- *
empty: in std_logic; -- *
grants: in std_logic; -- *
Cx_in: in std_logic_vector(3 downto 0); -- *
Temp_Cx: in std_logic_vector(3 downto 0); -- *
reconfig_cx_in: in std_logic; -- *
Cx: in std_logic_vector(3 downto 0); -- *
Cx_reconf_PE: in std_logic_vector(3 downto 0); -- newly added
Reconfig_command : in std_logic; -- newly added
Faulty_C_N: in std_logic; -- *
Faulty_C_E: in std_logic; -- *
Faulty_C_W: in std_logic; -- *
Faulty_C_S: in std_logic; -- *
Temp_Cx_in: in std_logic_vector(3 downto 0); -- *
-- Checker Outputs
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal : out std_logic -- Added
);
end component;
component Rxy_Reconf_pseudo_checkers is
port ( ReConf_FF_out: in std_logic;
Rxy: in std_logic_vector(7 downto 0);
Rxy_tmp: in std_logic_vector(7 downto 0);
Reconfig_command : in std_logic;
flit_type: in std_logic_vector(2 downto 0);
grants: in std_logic;
empty: in std_logic;
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Rxy_in: in std_logic_vector(7 downto 0);
Rxy_tmp_in: in std_logic_vector(7 downto 0);
ReConf_FF_in: in std_logic;
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal : out std_logic
);
end component;
component FIFO_credit_based_control_part_checkers is
port ( valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
read_pointer_in: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
write_pointer_in: in std_logic_vector(3 downto 0);
credit_out: in std_logic;
empty_out: in std_logic;
full_out: in std_logic;
read_en_out: in std_logic;
write_en_out: in std_logic;
fake_credit: in std_logic;
fake_credit_counter: in std_logic_vector(1 downto 0);
fake_credit_counter_in: in std_logic_vector(1 downto 0);
state_out: in std_logic_vector(4 downto 0);
state_in: in std_logic_vector(4 downto 0);
fault_info: in std_logic;
fault_info_out: in std_logic;
fault_info_in: in std_logic;
health_info: in std_logic;
faulty_packet_out: in std_logic;
faulty_packet_in: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
fault_out: in std_logic;
write_fake_flit: in std_logic;
-- Functional checkers
err_empty_full, err_empty_read_en, err_full_write_en, err_state_in_onehot,
err_read_pointer_in_onehot, err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer, err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full,
err_read_pointer_increment, err_read_pointer_not_increment, err_write_en, err_not_write_en,
err_not_write_en1, err_not_write_en2, err_read_en_mismatch, err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in : out std_logic
);
end component;
COMPONENT FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
fault_info, health_info: out std_logic;
---- fault injector shift register with serial input signals
--TCK: in std_logic;
--SE: in std_logic; -- shift enable
--UE: in std_logic; -- update enable
--SI: in std_logic; -- serial Input
--SO: out std_logic; -- serial output
-- Checker outputs
-- Functional checkers
err_empty_full, err_empty_read_en, err_full_write_en, err_state_in_onehot,
err_read_pointer_in_onehot, err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_write_en, err_not_write_en, err_not_write_en1, err_not_write_en2,
err_read_en_mismatch, err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in : out std_logic
);
end COMPONENT;
COMPONENT parity_checker_for_LBDR is
generic(DATA_WIDTH : integer := 32);
port(
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
empty: in std_logic;
faulty: out std_logic
);
end COMPONENT;
COMPONENT LBDR_packet_drop is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
faulty: in std_logic;
packet_drop_order: out std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic;
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic;
---- fault injector shift register with serial input signals
--TCK: in std_logic;
--SE: in std_logic; -- shift enable
--UE: in std_logic; -- update enable
--SI: in std_logic; -- serial Input
--SO: out std_logic; -- serial output
-- Checker outputs
-- Routing part checkers
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot,
err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in,
err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in,
err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order,
-- Cx_Reconf checkers
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added
-- Rxy_Reconf checkers
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal : out std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
--component fault_injector
-- generic(
-- DATA_WIDTH : integer := 32;
-- ADDRESS_WIDTH : integer := 5
-- );
-- port(
-- data_in: in std_logic_vector (DATA_WIDTH-1 downto 0);
-- address: in std_logic_vector (ADDRESS_WIDTH-1 downto 0);
-- sta_0: in std_logic;
-- sta_1: in std_logic;
-- data_out: out std_logic_vector (DATA_WIDTH-1 downto 0)
-- );
--end component;
--component shift_register_serial_in
-- generic (
-- REG_WIDTH: integer := 32
-- );
-- port (
-- TCK, reset : in std_logic;
-- SE: in std_logic; -- shift enable
-- UE: in std_logic; -- update enable
-- SI: in std_logic; -- serial Input
-- SO: out std_logic; -- serial output
-- data_out_parallel: out std_logic_vector(REG_WIDTH-1 downto 0)
-- );
--end component;
component Arbiter_in
port ( reset: in std_logic;
clk: in std_logic;
Req_X_N, Req_X_E, Req_X_W, Req_X_S, Req_X_L: in std_logic; -- From LBDR modules
X_N, X_E, X_W, X_S, X_L: out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
-- fault injector shift register with serial input signals
--TCK: in std_logic;
--SE: in std_logic; -- shift enable
--UE: in std_logic; -- update enable
--SI: in std_logic; -- serial Input
--SO: out std_logic; -- serial output
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N, err_IDLE_grant_N,err_North_Req_N, err_North_grant_N, err_East_Req_E, err_East_grant_E,
err_West_Req_W, err_West_grant_W, err_South_Req_S,err_South_grant_S,err_Local_Req_L, err_Local_grant_L,
err_IDLE_Req_E, err_IDLE_grant_E, err_North_Req_E, err_North_grant_E, err_East_Req_W, err_East_grant_W,
err_West_Req_S, err_West_grant_S, err_South_Req_L, err_South_grant_L, err_Local_Req_N, err_Local_grant_N,
err_IDLE_Req_W, err_IDLE_grant_W, err_North_Req_W, err_North_grant_W, err_East_Req_S, err_East_grant_S,
err_West_Req_L, err_West_grant_L, err_South_Req_N, err_South_grant_N, err_Local_Req_E, err_Local_grant_E,
err_IDLE_Req_S, err_IDLE_grant_S, err_North_Req_S, err_North_grant_S, err_East_Req_L, err_East_grant_L,
err_West_Req_N, err_West_grant_N, err_South_Req_E, err_South_grant_E, err_Local_Req_W, err_Local_grant_W,
err_IDLE_Req_L, err_IDLE_grant_L, err_North_Req_L, err_North_grant_L, err_East_Req_N, err_East_grant_N,
err_West_Req_E, err_West_grant_E, err_South_Req_W, err_South_grant_W, err_Local_Req_S, err_Local_grant_S,
err_state_in_onehot, err_no_request_grants, err_request_no_grants,
err_no_Req_N_grant_N, err_no_Req_E_grant_E, err_no_Req_W_grant_W, err_no_Req_S_grant_S, err_no_Req_L_grant_L : out std_logic
);
end component;
component Arbiter_in_one_hot_checkers
port (
req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_logic;
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
X_N, X_E, X_W, X_S, X_L :in std_logic;
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N, err_IDLE_grant_N,err_North_Req_N, err_North_grant_N, err_East_Req_E, err_East_grant_E,
err_West_Req_W, err_West_grant_W, err_South_Req_S,err_South_grant_S,err_Local_Req_L, err_Local_grant_L,
err_IDLE_Req_E, err_IDLE_grant_E, err_North_Req_E, err_North_grant_E, err_East_Req_W, err_East_grant_W,
err_West_Req_S, err_West_grant_S, err_South_Req_L, err_South_grant_L, err_Local_Req_N, err_Local_grant_N,
err_IDLE_Req_W, err_IDLE_grant_W, err_North_Req_W, err_North_grant_W, err_East_Req_S, err_East_grant_S,
err_West_Req_L, err_West_grant_L, err_South_Req_N, err_South_grant_N, err_Local_Req_E, err_Local_grant_E,
err_IDLE_Req_S, err_IDLE_grant_S, err_North_Req_S, err_North_grant_S, err_East_Req_L, err_East_grant_L,
err_West_Req_N, err_West_grant_N, err_South_Req_E, err_South_grant_E, err_Local_Req_W, err_Local_grant_W,
err_IDLE_Req_L, err_IDLE_grant_L, err_North_Req_L, err_North_grant_L, err_East_Req_N, err_East_grant_N,
err_West_Req_E, err_West_grant_E, err_South_Req_W, err_South_grant_W, err_Local_Req_S, err_Local_grant_S,
err_state_in_onehot, err_no_request_grants, err_request_no_grants, err_no_Req_N_grant_N,
err_no_Req_E_grant_E, err_no_Req_W_grant_W, err_no_Req_S_grant_S, err_no_Req_L_grant_L : out std_logic
);
end component;
component Arbiter_out_one_hot_pseudo_checkers
port ( credit: in std_logic_vector(1 downto 0);
req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_logic; -- From LBDR modules
state: in std_logic_vector (5 downto 0); -- 6 states for Arbiter_out's FSM
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : in std_logic; -- Grants given to LBDR requests (encoded as one-hot)
state_in: in std_logic_vector (5 downto 0); -- 6 states for Arbiter's FSM
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_req_X_N, err_North_req_X_N, err_North_credit_not_zero_req_X_N_grant_N,
err_North_credit_zero_or_not_req_X_N_not_grant_N,
err_East_req_X_E, err_East_credit_not_zero_req_X_E_grant_E, err_East_credit_zero_or_not_req_X_E_not_grant_E,
err_West_req_X_W, err_West_credit_not_zero_req_X_W_grant_W, err_West_credit_zero_or_not_req_X_W_not_grant_W,
err_South_req_X_S, err_South_credit_not_zero_req_X_S_grant_S, err_South_credit_zero_or_not_req_X_S_not_grant_S,
err_Local_req_X_L, err_Local_credit_not_zero_req_X_L_grant_L, err_Local_credit_zero_or_not_req_X_L_not_grant_L,
err_IDLE_req_X_E, err_North_req_X_E, err_East_req_X_W, err_West_req_X_S, err_South_req_X_L, err_Local_req_X_N,
err_IDLE_req_X_W, err_North_req_X_W, err_East_req_X_S, err_West_req_X_L, err_South_req_X_N, err_Local_req_X_E,
err_IDLE_req_X_S, err_North_req_X_S, err_East_req_X_L, err_West_req_X_N, err_South_req_X_E, err_Local_req_X_W,
err_IDLE_req_X_L, err_North_req_X_L, err_East_req_X_N, err_West_req_X_E, err_South_req_X_W, err_Local_req_X_S,
err_state_in_onehot, err_no_request_grants, err_request_IDLE_state,
err_request_IDLE_not_Grants, err_state_North_Invalid_Grant, err_state_East_Invalid_Grant,
err_state_West_Invalid_Grant, err_state_South_Invalid_Grant, err_state_Local_Invalid_Grant,
err_Grants_onehot_or_all_zero : out std_logic
);
end component;
component arbiter_out port (
reset: in std_logic;
clk: in std_logic;
X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y :in std_logic; -- From LBDR modules
credit: in std_logic_vector(1 downto 0);
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
-- fault injector shift register with serial input signals
--TCK: in std_logic;
--SE: in std_logic; -- shift enable
--UE: in std_logic; -- update enable
--SI: in std_logic; -- serial Input
--SO: out std_logic; -- serial output
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_req_X_N, err_North_req_X_N, err_North_credit_not_zero_req_X_N_grant_N,
err_North_credit_zero_or_not_req_X_N_not_grant_N,
err_East_req_X_E, err_East_credit_not_zero_req_X_E_grant_E,
err_East_credit_zero_or_not_req_X_E_not_grant_E,
err_West_req_X_W, err_West_credit_not_zero_req_X_W_grant_W,
err_West_credit_zero_or_not_req_X_W_not_grant_W,
err_South_req_X_S, err_South_credit_not_zero_req_X_S_grant_S,
err_South_credit_zero_or_not_req_X_S_not_grant_S,
err_Local_req_X_L, err_Local_credit_not_zero_req_X_L_grant_L,
err_Local_credit_zero_or_not_req_X_L_not_grant_L,
err_IDLE_req_X_E, err_North_req_X_E, err_East_req_X_W, err_West_req_X_S, err_South_req_X_L, err_Local_req_X_N,
err_IDLE_req_X_W, err_North_req_X_W, err_East_req_X_S, err_West_req_X_L, err_South_req_X_N, err_Local_req_X_E,
err_IDLE_req_X_S, err_North_req_X_S, err_East_req_X_L, err_West_req_X_N, err_South_req_X_E, err_Local_req_X_W,
err_IDLE_req_X_L, err_North_req_X_L, err_East_req_X_N, err_West_req_X_E, err_South_req_X_W, err_Local_req_X_S,
err_state_in_onehot, err_no_request_grants, err_request_IDLE_state,
err_request_IDLE_not_Grants, err_state_North_Invalid_Grant, err_state_East_Invalid_Grant,
err_state_West_Invalid_Grant, err_state_South_Invalid_Grant, err_state_Local_Invalid_Grant,
err_Grants_onehot_or_all_zero : out std_logic );
end component;
component allocator_logic_pseudo_checkers
port (
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
grant_N_N_sig, grant_N_E_sig, grant_N_W_sig, grant_N_S_sig, grant_N_L_sig: in std_logic;
grant_E_N_sig, grant_E_E_sig, grant_E_W_sig, grant_E_S_sig, grant_E_L_sig: in std_logic;
grant_W_N_sig, grant_W_E_sig, grant_W_W_sig, grant_W_S_sig, grant_W_L_sig: in std_logic;
grant_S_N_sig, grant_S_E_sig, grant_S_W_sig, grant_S_S_sig, grant_S_L_sig: in std_logic;
grant_L_N_sig, grant_L_E_sig, grant_L_W_sig, grant_L_S_sig, grant_L_L_sig: in std_logic;
valid_N, valid_E, valid_W, valid_S, valid_L : in std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: in std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: in std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: in std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: in std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: in std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L : in std_logic;
-- Checker outputs
err_grant_N_N_sig_not_empty_N_grant_N_N, err_not_grant_N_N_sig_or_empty_N_not_grant_N_N,
err_grant_N_E_sig_not_empty_E_grant_N_E, err_not_grant_N_E_sig_or_empty_E_not_grant_N_E,
err_grant_N_W_sig_not_empty_W_grant_N_W, err_not_grant_N_W_sig_or_empty_W_not_grant_N_W,
err_grant_N_S_sig_not_empty_S_grant_N_S, err_not_grant_N_S_sig_or_empty_S_not_grant_N_S,
err_grant_N_L_sig_not_empty_L_grant_N_L, err_not_grant_N_L_sig_or_empty_L_not_grant_N_L,
err_grant_E_N_sig_not_empty_N_grant_E_N, err_not_grant_E_N_sig_or_empty_N_not_grant_E_N,
err_grant_E_E_sig_not_empty_E_grant_E_E, err_not_grant_E_E_sig_or_empty_E_not_grant_E_E,
err_grant_E_W_sig_not_empty_W_grant_E_W, err_not_grant_E_W_sig_or_empty_W_not_grant_E_W,
err_grant_E_S_sig_not_empty_S_grant_E_S, err_not_grant_E_S_sig_or_empty_S_not_grant_E_S,
err_grant_E_L_sig_not_empty_L_grant_E_L, err_not_grant_E_L_sig_or_empty_L_not_grant_E_L,
err_grant_W_N_sig_not_empty_N_grant_W_N, err_not_grant_W_N_sig_or_empty_N_not_grant_W_N,
err_grant_W_E_sig_not_empty_E_grant_W_E, err_not_grant_W_E_sig_or_empty_E_not_grant_W_E,
err_grant_W_W_sig_not_empty_W_grant_W_W, err_not_grant_W_W_sig_or_empty_W_not_grant_W_W,
err_grant_W_S_sig_not_empty_S_grant_W_S, err_not_grant_W_S_sig_or_empty_S_not_grant_W_S,
err_grant_W_L_sig_not_empty_L_grant_W_L, err_not_grant_W_L_sig_or_empty_L_not_grant_W_L,
err_grant_S_N_sig_not_empty_N_grant_S_N, err_not_grant_S_N_sig_or_empty_N_not_grant_S_N,
err_grant_S_E_sig_not_empty_E_grant_S_E, err_not_grant_S_E_sig_or_empty_E_not_grant_S_E,
err_grant_S_W_sig_not_empty_W_grant_S_W, err_not_grant_S_W_sig_or_empty_W_not_grant_S_W,
err_grant_S_S_sig_not_empty_S_grant_S_S, err_not_grant_S_S_sig_or_empty_S_not_grant_S_S,
err_grant_S_L_sig_not_empty_L_grant_S_L, err_not_grant_S_L_sig_or_empty_L_not_grant_S_L,
err_grant_L_N_sig_not_empty_N_grant_L_N, err_not_grant_L_N_sig_or_empty_N_not_grant_L_N,
err_grant_L_E_sig_not_empty_E_grant_L_E, err_not_grant_L_E_sig_or_empty_E_not_grant_L_E,
err_grant_L_W_sig_not_empty_W_grant_L_W, err_not_grant_L_W_sig_or_empty_W_not_grant_L_W,
err_grant_L_S_sig_not_empty_S_grant_L_S, err_not_grant_L_S_sig_or_empty_S_not_grant_L_S,
err_grant_L_L_sig_not_empty_L_grant_L_L, err_not_grant_L_L_sig_or_empty_L_not_grant_L_L,
err_grant_signals_not_empty_grant_N, err_not_grant_signals_empty_not_grant_N,
err_grant_signals_not_empty_grant_E, err_not_grant_signals_empty_not_grant_E,
err_grant_signals_not_empty_grant_W, err_not_grant_signals_empty_not_grant_W,
err_grant_signals_not_empty_grant_S, err_not_grant_signals_empty_not_grant_S,
err_grant_signals_not_empty_grant_L, err_not_grant_signals_empty_not_grant_L,
err_grants_valid_not_match : out std_logic
);
end component;
component allocator_credit_counter_logic_pseudo_checkers
port (
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
credit_counter_N_out, credit_counter_E_out, credit_counter_W_out, credit_counter_S_out, credit_counter_L_out : in std_logic_vector(1 downto 0);
valid_N, valid_E, valid_W, valid_S, valid_L: in std_logic; -- ?? Not sure yet ! grant or valid !
credit_counter_N_in, credit_counter_E_in, credit_counter_W_in, credit_counter_S_in, credit_counter_L_in : in std_logic_vector(1 downto 0);
-- Checker outputs
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_N_credit_counter_N_out_increment,
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change,
err_grant_N_credit_counter_N_out_decrement,
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change,
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_E_credit_counter_E_out_increment,
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change,
err_grant_E_credit_counter_E_out_decrement,
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change,
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_W_credit_counter_W_out_increment,
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change,
err_grant_W_credit_counter_W_out_decrement,
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change,
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_S_credit_counter_S_out_increment,
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change,
err_grant_S_credit_counter_S_out_decrement,
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change,
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal,
err_credit_in_L_credit_counter_L_out_increment,
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change,
err_grant_L_credit_counter_L_out_decrement,
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change,
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal : out std_logic
);
end component;
component allocator
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic;
-- fault injector shift register with serial input signals
--TCK: in std_logic;
--SE: in std_logic; -- shift enable
--UE: in std_logic; -- update enable
--SI: in std_logic; -- serial Input
--SO: out std_logic; -- serial output
-- Allocator logic checker outputs
err_grant_N_N_sig_not_empty_N_grant_N_N, err_not_grant_N_N_sig_or_empty_N_not_grant_N_N, err_grant_N_E_sig_not_empty_E_grant_N_E,
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E, err_grant_N_W_sig_not_empty_W_grant_N_W, err_not_grant_N_W_sig_or_empty_W_not_grant_N_W,
err_grant_N_S_sig_not_empty_S_grant_N_S, err_not_grant_N_S_sig_or_empty_S_not_grant_N_S, err_grant_N_L_sig_not_empty_L_grant_N_L,
err_not_grant_N_L_sig_or_empty_L_not_grant_N_L,
err_grant_E_N_sig_not_empty_N_grant_E_N, err_not_grant_E_N_sig_or_empty_N_not_grant_E_N, err_grant_E_E_sig_not_empty_E_grant_E_E,
err_not_grant_E_E_sig_or_empty_E_not_grant_E_E, err_grant_E_W_sig_not_empty_W_grant_E_W, err_not_grant_E_W_sig_or_empty_W_not_grant_E_W,
err_grant_E_S_sig_not_empty_S_grant_E_S, err_not_grant_E_S_sig_or_empty_S_not_grant_E_S, err_grant_E_L_sig_not_empty_L_grant_E_L,
err_not_grant_E_L_sig_or_empty_L_not_grant_E_L,
err_grant_W_N_sig_not_empty_N_grant_W_N, err_not_grant_W_N_sig_or_empty_N_not_grant_W_N, err_grant_W_E_sig_not_empty_E_grant_W_E,
err_not_grant_W_E_sig_or_empty_E_not_grant_W_E, err_grant_W_W_sig_not_empty_W_grant_W_W, err_not_grant_W_W_sig_or_empty_W_not_grant_W_W,
err_grant_W_S_sig_not_empty_S_grant_W_S, err_not_grant_W_S_sig_or_empty_S_not_grant_W_S, err_grant_W_L_sig_not_empty_L_grant_W_L,
err_not_grant_W_L_sig_or_empty_L_not_grant_W_L,
err_grant_S_N_sig_not_empty_N_grant_S_N, err_not_grant_S_N_sig_or_empty_N_not_grant_S_N, err_grant_S_E_sig_not_empty_E_grant_S_E,
err_not_grant_S_E_sig_or_empty_E_not_grant_S_E, err_grant_S_W_sig_not_empty_W_grant_S_W, err_not_grant_S_W_sig_or_empty_W_not_grant_S_W,
err_grant_S_S_sig_not_empty_S_grant_S_S, err_not_grant_S_S_sig_or_empty_S_not_grant_S_S, err_grant_S_L_sig_not_empty_L_grant_S_L,
err_not_grant_S_L_sig_or_empty_L_not_grant_S_L,
err_grant_L_N_sig_not_empty_N_grant_L_N, err_not_grant_L_N_sig_or_empty_N_not_grant_L_N, err_grant_L_E_sig_not_empty_E_grant_L_E,
err_not_grant_L_E_sig_or_empty_E_not_grant_L_E, err_grant_L_W_sig_not_empty_W_grant_L_W, err_not_grant_L_W_sig_or_empty_W_not_grant_L_W,
err_grant_L_S_sig_not_empty_S_grant_L_S, err_not_grant_L_S_sig_or_empty_S_not_grant_L_S, err_grant_L_L_sig_not_empty_L_grant_L_L,
err_not_grant_L_L_sig_or_empty_L_not_grant_L_L,
err_grant_signals_not_empty_grant_N, err_not_grant_signals_empty_not_grant_N, err_grant_signals_not_empty_grant_E,
err_not_grant_signals_empty_not_grant_E, err_grant_signals_not_empty_grant_W, err_not_grant_signals_empty_not_grant_W,
err_grant_signals_not_empty_grant_S, err_not_grant_signals_empty_not_grant_S, err_grant_signals_not_empty_grant_L,
err_not_grant_signals_empty_not_grant_L,
err_grants_valid_not_match,
-- Allocator credit counter logic checker outputs
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal, err_credit_in_N_credit_counter_N_out_increment,
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change, err_grant_N_credit_counter_N_out_decrement,
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change,
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal, err_credit_in_E_credit_counter_E_out_increment,
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change, err_grant_E_credit_counter_E_out_decrement,
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change,
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal, err_credit_in_W_credit_counter_W_out_increment,
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change, err_grant_W_credit_counter_W_out_decrement,
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change,
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal, err_credit_in_S_credit_counter_S_out_increment,
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change, err_grant_S_credit_counter_S_out_decrement,
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change,
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal, err_credit_in_L_credit_counter_L_out_increment,
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change, err_grant_L_credit_counter_L_out_decrement,
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change,
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal,
-- Arbiter_in checker outputs
-- North Arbiter_in checker outputs
N_err_Requests_state_in_state_not_equal,
N_err_IDLE_Req_N, N_err_IDLE_grant_N, N_err_North_Req_N, N_err_North_grant_N, N_err_East_Req_E, N_err_East_grant_E,
N_err_West_Req_W, N_err_West_grant_W, N_err_South_Req_S,N_err_South_grant_S,N_err_Local_Req_L, N_err_Local_grant_L,
N_err_IDLE_Req_E, N_err_IDLE_grant_E, N_err_North_Req_E, N_err_North_grant_E, N_err_East_Req_W, N_err_East_grant_W,
N_err_West_Req_S, N_err_West_grant_S, N_err_South_Req_L, N_err_South_grant_L, N_err_Local_Req_N, N_err_Local_grant_N,
N_err_IDLE_Req_W, N_err_IDLE_grant_W, N_err_North_Req_W, N_err_North_grant_W, N_err_East_Req_S, N_err_East_grant_S,
N_err_West_Req_L, N_err_West_grant_L, N_err_South_Req_N, N_err_South_grant_N, N_err_Local_Req_E, N_err_Local_grant_E,
N_err_IDLE_Req_S, N_err_IDLE_grant_S, N_err_North_Req_S, N_err_North_grant_S, N_err_East_Req_L, N_err_East_grant_L,
N_err_West_Req_N, N_err_West_grant_N, N_err_South_Req_E, N_err_South_grant_E, N_err_Local_Req_W, N_err_Local_grant_W,
N_err_IDLE_Req_L, N_err_IDLE_grant_L, N_err_North_Req_L, N_err_North_grant_L, N_err_East_Req_N, N_err_East_grant_N,
N_err_West_Req_E, N_err_West_grant_E, N_err_South_Req_W, N_err_South_grant_W, N_err_Local_Req_S, N_err_Local_grant_S,
N_err_state_in_onehot, N_err_no_request_grants, N_err_request_no_grants,
N_err_no_Req_N_grant_N, N_err_no_Req_E_grant_E, N_err_no_Req_W_grant_W, N_err_no_Req_S_grant_S, N_err_no_Req_L_grant_L,
-- East Arbiter_in checker outputs
E_err_Requests_state_in_state_not_equal,
E_err_IDLE_Req_N, E_err_IDLE_grant_N, E_err_North_Req_N, E_err_North_grant_N, E_err_East_Req_E, E_err_East_grant_E,
E_err_West_Req_W, E_err_West_grant_W, E_err_South_Req_S, E_err_South_grant_S, E_err_Local_Req_L, E_err_Local_grant_L,
E_err_IDLE_Req_E, E_err_IDLE_grant_E, E_err_North_Req_E, E_err_North_grant_E, E_err_East_Req_W, E_err_East_grant_W,
E_err_West_Req_S, E_err_West_grant_S, E_err_South_Req_L, E_err_South_grant_L, E_err_Local_Req_N, E_err_Local_grant_N,
E_err_IDLE_Req_W, E_err_IDLE_grant_W, E_err_North_Req_W, E_err_North_grant_W, E_err_East_Req_S, E_err_East_grant_S,
E_err_West_Req_L, E_err_West_grant_L, E_err_South_Req_N, E_err_South_grant_N, E_err_Local_Req_E, E_err_Local_grant_E,
E_err_IDLE_Req_S, E_err_IDLE_grant_S, E_err_North_Req_S, E_err_North_grant_S, E_err_East_Req_L, E_err_East_grant_L,
E_err_West_Req_N, E_err_West_grant_N, E_err_South_Req_E, E_err_South_grant_E, E_err_Local_Req_W, E_err_Local_grant_W,
E_err_IDLE_Req_L, E_err_IDLE_grant_L, E_err_North_Req_L, E_err_North_grant_L, E_err_East_Req_N, E_err_East_grant_N,
E_err_West_Req_E, E_err_West_grant_E, E_err_South_Req_W, E_err_South_grant_W, E_err_Local_Req_S, E_err_Local_grant_S,
E_err_state_in_onehot, E_err_no_request_grants, E_err_request_no_grants,
E_err_no_Req_N_grant_N, E_err_no_Req_E_grant_E, E_err_no_Req_W_grant_W, E_err_no_Req_S_grant_S, E_err_no_Req_L_grant_L,
-- West Arbiter_in checker outputs
W_err_Requests_state_in_state_not_equal,
W_err_IDLE_Req_N, W_err_IDLE_grant_N, W_err_North_Req_N, W_err_North_grant_N, W_err_East_Req_E, W_err_East_grant_E,
W_err_West_Req_W, W_err_West_grant_W, W_err_South_Req_S, W_err_South_grant_S, W_err_Local_Req_L, W_err_Local_grant_L,
W_err_IDLE_Req_E, W_err_IDLE_grant_E, W_err_North_Req_E, W_err_North_grant_E, W_err_East_Req_W, W_err_East_grant_W,
W_err_West_Req_S, W_err_West_grant_S, W_err_South_Req_L, W_err_South_grant_L, W_err_Local_Req_N, W_err_Local_grant_N,
W_err_IDLE_Req_W, W_err_IDLE_grant_W, W_err_North_Req_W, W_err_North_grant_W, W_err_East_Req_S, W_err_East_grant_S,
W_err_West_Req_L, W_err_West_grant_L, W_err_South_Req_N, W_err_South_grant_N, W_err_Local_Req_E, W_err_Local_grant_E,
W_err_IDLE_Req_S, W_err_IDLE_grant_S, W_err_North_Req_S, W_err_North_grant_S, W_err_East_Req_L, W_err_East_grant_L,
W_err_West_Req_N, W_err_West_grant_N, W_err_South_Req_E, W_err_South_grant_E, W_err_Local_Req_W, W_err_Local_grant_W,
W_err_IDLE_Req_L, W_err_IDLE_grant_L, W_err_North_Req_L, W_err_North_grant_L, W_err_East_Req_N, W_err_East_grant_N,
W_err_West_Req_E, W_err_West_grant_E, W_err_South_Req_W, W_err_South_grant_W, W_err_Local_Req_S, W_err_Local_grant_S,
W_err_state_in_onehot, W_err_no_request_grants, W_err_request_no_grants,
W_err_no_Req_N_grant_N, W_err_no_Req_E_grant_E, W_err_no_Req_W_grant_W, W_err_no_Req_S_grant_S, W_err_no_Req_L_grant_L,
-- South Arbiter_in checker outputs
S_err_Requests_state_in_state_not_equal,
S_err_IDLE_Req_N, S_err_IDLE_grant_N, S_err_North_Req_N, S_err_North_grant_N, S_err_East_Req_E, S_err_East_grant_E,
S_err_West_Req_W, S_err_West_grant_W, S_err_South_Req_S,S_err_South_grant_S,S_err_Local_Req_L, S_err_Local_grant_L,
S_err_IDLE_Req_E, S_err_IDLE_grant_E, S_err_North_Req_E, S_err_North_grant_E, S_err_East_Req_W, S_err_East_grant_W,
S_err_West_Req_S, S_err_West_grant_S, S_err_South_Req_L, S_err_South_grant_L, S_err_Local_Req_N, S_err_Local_grant_N,
S_err_IDLE_Req_W, S_err_IDLE_grant_W, S_err_North_Req_W, S_err_North_grant_W, S_err_East_Req_S, S_err_East_grant_S,
S_err_West_Req_L, S_err_West_grant_L, S_err_South_Req_N, S_err_South_grant_N, S_err_Local_Req_E, S_err_Local_grant_E,
S_err_IDLE_Req_S, S_err_IDLE_grant_S, S_err_North_Req_S, S_err_North_grant_S, S_err_East_Req_L, S_err_East_grant_L,
S_err_West_Req_N, S_err_West_grant_N, S_err_South_Req_E, S_err_South_grant_E, S_err_Local_Req_W, S_err_Local_grant_W,
S_err_IDLE_Req_L, S_err_IDLE_grant_L, S_err_North_Req_L, S_err_North_grant_L, S_err_East_Req_N, S_err_East_grant_N,
S_err_West_Req_E, S_err_West_grant_E, S_err_South_Req_W, S_err_South_grant_W, S_err_Local_Req_S, S_err_Local_grant_S,
S_err_state_in_onehot, S_err_no_request_grants, S_err_request_no_grants,
S_err_no_Req_N_grant_N, S_err_no_Req_E_grant_E, S_err_no_Req_W_grant_W, S_err_no_Req_S_grant_S, S_err_no_Req_L_grant_L,
-- Local Arbiter_in checker outputs
L_err_Requests_state_in_state_not_equal,
L_err_IDLE_Req_N, L_err_IDLE_grant_N, L_err_North_Req_N, L_err_North_grant_N, L_err_East_Req_E, L_err_East_grant_E,
L_err_West_Req_W, L_err_West_grant_W, L_err_South_Req_S, L_err_South_grant_S, L_err_Local_Req_L, L_err_Local_grant_L,
L_err_IDLE_Req_E, L_err_IDLE_grant_E, L_err_North_Req_E, L_err_North_grant_E, L_err_East_Req_W, L_err_East_grant_W,
L_err_West_Req_S, L_err_West_grant_S, L_err_South_Req_L, L_err_South_grant_L, L_err_Local_Req_N, L_err_Local_grant_N,
L_err_IDLE_Req_W, L_err_IDLE_grant_W, L_err_North_Req_W, L_err_North_grant_W, L_err_East_Req_S, L_err_East_grant_S,
L_err_West_Req_L, L_err_West_grant_L, L_err_South_Req_N, L_err_South_grant_N, L_err_Local_Req_E, L_err_Local_grant_E,
L_err_IDLE_Req_S, L_err_IDLE_grant_S, L_err_North_Req_S, L_err_North_grant_S, L_err_East_Req_L, L_err_East_grant_L,
L_err_West_Req_N, L_err_West_grant_N, L_err_South_Req_E, L_err_South_grant_E, L_err_Local_Req_W, L_err_Local_grant_W,
L_err_IDLE_Req_L, L_err_IDLE_grant_L, L_err_North_Req_L, L_err_North_grant_L, L_err_East_Req_N, L_err_East_grant_N,
L_err_West_Req_E, L_err_West_grant_E, L_err_South_Req_W, L_err_South_grant_W, L_err_Local_Req_S, L_err_Local_grant_S,
L_err_state_in_onehot, L_err_no_request_grants, L_err_request_no_grants,
L_err_no_Req_N_grant_N, L_err_no_Req_E_grant_E, L_err_no_Req_W_grant_W, L_err_no_Req_S_grant_S, L_err_no_Req_L_grant_L,
-- Arbiter_out checker outputs
-- North Arbiter_out checker outputs
N_arbiter_out_err_Requests_state_in_state_not_equal,
N_err_IDLE_req_X_N, N_err_North_req_X_N, N_err_North_credit_not_zero_req_X_N_grant_N, N_err_North_credit_zero_or_not_req_X_N_not_grant_N,
N_err_East_req_X_E, N_err_East_credit_not_zero_req_X_E_grant_E, N_err_East_credit_zero_or_not_req_X_E_not_grant_E,
N_err_West_req_X_W, N_err_West_credit_not_zero_req_X_W_grant_W, N_err_West_credit_zero_or_not_req_X_W_not_grant_W,
N_err_South_req_X_S, N_err_South_credit_not_zero_req_X_S_grant_S, N_err_South_credit_zero_or_not_req_X_S_not_grant_S,
N_err_Local_req_X_L, N_err_Local_credit_not_zero_req_X_L_grant_L, N_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
N_err_IDLE_req_X_E, N_err_North_req_X_E, N_err_East_req_X_W, N_err_West_req_X_S, N_err_South_req_X_L, N_err_Local_req_X_N,
N_err_IDLE_req_X_W, N_err_North_req_X_W, N_err_East_req_X_S, N_err_West_req_X_L, N_err_South_req_X_N, N_err_Local_req_X_E,
N_err_IDLE_req_X_S, N_err_North_req_X_S, N_err_East_req_X_L, N_err_West_req_X_N, N_err_South_req_X_E, N_err_Local_req_X_W,
N_err_IDLE_req_X_L, N_err_North_req_X_L, N_err_East_req_X_N, N_err_West_req_X_E, N_err_South_req_X_W, N_err_Local_req_X_S,
N_arbiter_out_err_state_in_onehot, N_arbiter_out_err_no_request_grants, N_err_request_IDLE_state,
N_err_request_IDLE_not_Grants, N_err_state_North_Invalid_Grant, N_err_state_East_Invalid_Grant, N_err_state_West_Invalid_Grant,
N_err_state_South_Invalid_Grant, N_err_state_Local_Invalid_Grant, N_err_Grants_onehot_or_all_zero,
-- East Arbiter_out checker outputs
E_arbiter_out_err_Requests_state_in_state_not_equal,
E_err_IDLE_req_X_N, E_err_North_req_X_N, E_err_North_credit_not_zero_req_X_N_grant_N, E_err_North_credit_zero_or_not_req_X_N_not_grant_N,
E_err_East_req_X_E, E_err_East_credit_not_zero_req_X_E_grant_E, E_err_East_credit_zero_or_not_req_X_E_not_grant_E,
E_err_West_req_X_W, E_err_West_credit_not_zero_req_X_W_grant_W, E_err_West_credit_zero_or_not_req_X_W_not_grant_W,
E_err_South_req_X_S, E_err_South_credit_not_zero_req_X_S_grant_S, E_err_South_credit_zero_or_not_req_X_S_not_grant_S,
E_err_Local_req_X_L, E_err_Local_credit_not_zero_req_X_L_grant_L, E_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
E_err_IDLE_req_X_E, E_err_North_req_X_E, E_err_East_req_X_W, E_err_West_req_X_S, E_err_South_req_X_L, E_err_Local_req_X_N,
E_err_IDLE_req_X_W, E_err_North_req_X_W, E_err_East_req_X_S, E_err_West_req_X_L, E_err_South_req_X_N, E_err_Local_req_X_E,
E_err_IDLE_req_X_S, E_err_North_req_X_S, E_err_East_req_X_L, E_err_West_req_X_N, E_err_South_req_X_E, E_err_Local_req_X_W,
E_err_IDLE_req_X_L, E_err_North_req_X_L, E_err_East_req_X_N, E_err_West_req_X_E, E_err_South_req_X_W, E_err_Local_req_X_S,
E_arbiter_out_err_state_in_onehot, E_arbiter_out_err_no_request_grants, E_err_request_IDLE_state,
E_err_request_IDLE_not_Grants, E_err_state_North_Invalid_Grant,E_err_state_East_Invalid_Grant, E_err_state_West_Invalid_Grant,
E_err_state_South_Invalid_Grant, E_err_state_Local_Invalid_Grant, E_err_Grants_onehot_or_all_zero,
-- West Arbiter_out checker outputs
W_arbiter_out_err_Requests_state_in_state_not_equal,
W_err_IDLE_req_X_N, W_err_North_req_X_N, W_err_North_credit_not_zero_req_X_N_grant_N, W_err_North_credit_zero_or_not_req_X_N_not_grant_N,
W_err_East_req_X_E, W_err_East_credit_not_zero_req_X_E_grant_E, W_err_East_credit_zero_or_not_req_X_E_not_grant_E,
W_err_West_req_X_W, W_err_West_credit_not_zero_req_X_W_grant_W, W_err_West_credit_zero_or_not_req_X_W_not_grant_W,
W_err_South_req_X_S, W_err_South_credit_not_zero_req_X_S_grant_S, W_err_South_credit_zero_or_not_req_X_S_not_grant_S,
W_err_Local_req_X_L, W_err_Local_credit_not_zero_req_X_L_grant_L, W_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
W_err_IDLE_req_X_E, W_err_North_req_X_E, W_err_East_req_X_W, W_err_West_req_X_S, W_err_South_req_X_L, W_err_Local_req_X_N,
W_err_IDLE_req_X_W, W_err_North_req_X_W, W_err_East_req_X_S, W_err_West_req_X_L, W_err_South_req_X_N, W_err_Local_req_X_E,
W_err_IDLE_req_X_S, W_err_North_req_X_S, W_err_East_req_X_L, W_err_West_req_X_N, W_err_South_req_X_E, W_err_Local_req_X_W,
W_err_IDLE_req_X_L, W_err_North_req_X_L, W_err_East_req_X_N, W_err_West_req_X_E, W_err_South_req_X_W, W_err_Local_req_X_S,
W_arbiter_out_err_state_in_onehot, W_arbiter_out_err_no_request_grants, W_err_request_IDLE_state,
W_err_request_IDLE_not_Grants, W_err_state_North_Invalid_Grant, W_err_state_East_Invalid_Grant, W_err_state_West_Invalid_Grant,
W_err_state_South_Invalid_Grant, W_err_state_Local_Invalid_Grant, W_err_Grants_onehot_or_all_zero,
-- South Arbiter_out checker outputs
S_arbiter_out_err_Requests_state_in_state_not_equal,
S_err_IDLE_req_X_N, S_err_North_req_X_N, S_err_North_credit_not_zero_req_X_N_grant_N, S_err_North_credit_zero_or_not_req_X_N_not_grant_N,
S_err_East_req_X_E, S_err_East_credit_not_zero_req_X_E_grant_E, S_err_East_credit_zero_or_not_req_X_E_not_grant_E,
S_err_West_req_X_W, S_err_West_credit_not_zero_req_X_W_grant_W, S_err_West_credit_zero_or_not_req_X_W_not_grant_W,
S_err_South_req_X_S, S_err_South_credit_not_zero_req_X_S_grant_S, S_err_South_credit_zero_or_not_req_X_S_not_grant_S,
S_err_Local_req_X_L, S_err_Local_credit_not_zero_req_X_L_grant_L, S_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
S_err_IDLE_req_X_E, S_err_North_req_X_E, S_err_East_req_X_W, S_err_West_req_X_S, S_err_South_req_X_L, S_err_Local_req_X_N,
S_err_IDLE_req_X_W, S_err_North_req_X_W, S_err_East_req_X_S, S_err_West_req_X_L, S_err_South_req_X_N, S_err_Local_req_X_E,
S_err_IDLE_req_X_S, S_err_North_req_X_S, S_err_East_req_X_L, S_err_West_req_X_N, S_err_South_req_X_E, S_err_Local_req_X_W,
S_err_IDLE_req_X_L, S_err_North_req_X_L, S_err_East_req_X_N, S_err_West_req_X_E, S_err_South_req_X_W, S_err_Local_req_X_S,
S_arbiter_out_err_state_in_onehot, S_arbiter_out_err_no_request_grants, S_err_request_IDLE_state,
S_err_request_IDLE_not_Grants, S_err_state_North_Invalid_Grant, S_err_state_East_Invalid_Grant, S_err_state_West_Invalid_Grant,
S_err_state_South_Invalid_Grant, S_err_state_Local_Invalid_Grant, S_err_Grants_onehot_or_all_zero,
-- Local Arbiter_out checker outputs
L_arbiter_out_err_Requests_state_in_state_not_equal,
L_err_IDLE_req_X_N, L_err_North_req_X_N, L_err_North_credit_not_zero_req_X_N_grant_N, L_err_North_credit_zero_or_not_req_X_N_not_grant_N,
L_err_East_req_X_E, L_err_East_credit_not_zero_req_X_E_grant_E, L_err_East_credit_zero_or_not_req_X_E_not_grant_E, L_err_West_req_X_W,
L_err_West_credit_not_zero_req_X_W_grant_W, L_err_West_credit_zero_or_not_req_X_W_not_grant_W,
L_err_South_req_X_S, L_err_South_credit_not_zero_req_X_S_grant_S, L_err_South_credit_zero_or_not_req_X_S_not_grant_S,
L_err_Local_req_X_L, L_err_Local_credit_not_zero_req_X_L_grant_L, L_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
L_err_IDLE_req_X_E, L_err_North_req_X_E, L_err_East_req_X_W, L_err_West_req_X_S, L_err_South_req_X_L, L_err_Local_req_X_N,
L_err_IDLE_req_X_W, L_err_North_req_X_W, L_err_East_req_X_S, L_err_West_req_X_L, L_err_South_req_X_N, L_err_Local_req_X_E,
L_err_IDLE_req_X_S, L_err_North_req_X_S, L_err_East_req_X_L, L_err_West_req_X_N, L_err_South_req_X_E, L_err_Local_req_X_W,
L_err_IDLE_req_X_L, L_err_North_req_X_L, L_err_East_req_X_N, L_err_West_req_X_E, L_err_South_req_X_W, L_err_Local_req_X_S,
L_arbiter_out_err_state_in_onehot, L_arbiter_out_err_no_request_grants, L_err_request_IDLE_state,
L_err_request_IDLE_not_Grants, L_err_state_North_Invalid_Grant, L_err_state_East_Invalid_Grant, L_err_state_West_Invalid_Grant,
L_err_state_South_Invalid_Grant, L_err_state_Local_Invalid_Grant, L_err_Grants_onehot_or_all_zero : out std_logic
);
end component;
end; --package body
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12/01/2014 10:27:20 AM
-- Design Name:
-- Module Name: mmc_crc7 - rtl
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mmc_crc7 is
Port ( clk : in std_logic;
clk_en : in std_logic;
reset : in std_logic;
enable : in std_logic;
serial_in : in std_logic;
crc7_out : out std_logic_vector (6 downto 0)
);
end mmc_crc7;
architecture rtl of mmc_crc7 is
signal crc_reg : std_logic_vector (6 downto 0) := (others => '0');
begin
crc7_out <= crc_reg;
process
begin
wait until rising_edge(clk);
if reset='1' then
crc_reg <= (others => '0');
elsif enable='1' and clk_en='1' then
crc_reg(0) <= crc_reg(6) xor serial_in;
crc_reg(1) <= crc_reg(0);
crc_reg(2) <= crc_reg(1);
crc_reg(3) <= crc_reg(2) xor crc_reg(6) xor serial_in;
crc_reg(4) <= crc_reg(3);
crc_reg(5) <= crc_reg(4);
crc_reg(6) <= crc_reg(5);
end if;
end process;
end rtl;
|
-------------------------------------------------------------------------------
-- OpenMAC DMA FIFO
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.all;
entity openMAC_DMAfifo is
generic (
fifo_data_width_g : natural := 16;
fifo_word_size_g : natural := 32;
fifo_word_size_log2_g : natural := 5
);
port
(
aclr : in std_logic;
rd_clk : in std_logic;
wr_clk : in std_logic;
--read port
rd_req : in std_logic;
rd_data : out std_logic_vector(fifo_data_width_g-1 downto 0);
rd_empty : out std_logic;
rd_full : out std_logic;
rd_usedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0);
--write port
wr_req : in std_logic;
wr_data : in std_logic_vector(fifo_data_width_g-1 downto 0);
wr_empty : out std_logic;
wr_full : out std_logic;
wr_usedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0)
);
end openMAC_DMAfifo;
architecture struct of openMAC_DMAfifo is
component dcfifo
generic (
lpm_width : natural; --width of data and q ports (input/output)
lpm_widthu : natural; --width of wrusedw and rdusedw
lpm_numwords : natural; --depth of fifo
lpm_showahead : string; --fifo showahead off/on (rdreq works as req/ack)
lpm_type : string; --SCFIFO or DCFIFO (single/dual clocked)
overflow_checking : string; --protection circuit for wrreq
underflow_checking : string; --protection circuit for rdreq
rdsync_delaypipe : natural; --number of sync from wr to rd
wrsync_delaypipe : natural; --number of sync from rd to wr
use_eab : string; --construct fifo as LE/RAM (off/on)
write_aclr_synch : string; --sync async. clear to wr clk (avoids race cond.)
intended_device_family : string --specifies the intended device for functional simulation
);
port (
wrclk : in std_logic; --clock for wr port
rdclk : in std_logic; --clock for rd port
data : in std_logic_vector(fifo_data_width_g-1 downto 0); --data to be written
wrreq : in std_logic; --write request
rdreq : in std_logic; --read request
aclr : in std_logic; --asynchronous clear fifo
q : out std_logic_vector(fifo_data_width_g-1 downto 0); --read data
wrfull : out std_logic; --fifo is full on wr port
rdfull : out std_logic; --fifo is full on rd port
wrempty : out std_logic; --fifo is empty on wr port
rdempty : out std_logic; --fifo is empty on rd port
wrusedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0); --number of words stored on wr port
rdusedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0) --number of words stored on rd port
);
end component;
constant fifo_useRam_c : string := "ON";
constant fifo_words_c : natural := fifo_word_size_g; --e.g. 32
constant fifo_usedw_c : natural := fifo_word_size_log2_g; --e.g. log2(32) = 5
--constant fifo_rd_usedw_c : natural := 5;
--constant fifo_wr_usedw_c : natural := 5;
constant fifo_data_width_c : natural := fifo_data_width_g;
--constant fifo_rd_data_width_c : natural := 16;
--constant fifo_wr_data_width_c : natural := 16;
begin
dcfifo_inst : dcfifo
generic map (
lpm_width => fifo_data_width_c, --width of data and q ports (input/output)
lpm_widthu => fifo_usedw_c, --width of wrusedw and rdusedw
lpm_numwords => fifo_words_c, --depth of fifo
lpm_showahead => "OFF", --fifo showahead off/on (rdreq works as req/ack)
lpm_type => "DCFIFO", --SCFIFO or DCFIFO (single/dual clocked)
overflow_checking => "ON", --protection circuit for wrreq
underflow_checking => "ON", --protection circuit for rdreq
rdsync_delaypipe => 4, --number of sync from wr to rd
wrsync_delaypipe => 4, --number of sync from rd to wr
use_eab => fifo_useRam_c, --construct fifo as LE/RAM (off/on)
write_aclr_synch => "ON", --sync async. clear to wr clk (avoids race cond.)
intended_device_family => "Cyclone IV" --specifies the intended device for functional simulation
)
port map (
wrclk => wr_clk, --clock for wr port
rdclk => rd_clk, --clock for rd port
data => wr_data, --data to be written
wrreq => wr_req, --write request
rdreq => rd_req, --read request
aclr => aclr, --asynchronous clear fifo
q => rd_data, --read data
wrfull => wr_full, --fifo is full on wr port
rdfull => rd_full, --fifo is full on rd port
wrempty => wr_empty, --fifo is empty on wr port
rdempty => rd_empty, --fifo is empty on rd port
wrusedw => wr_usedw, --number of words stored on wr port
rdusedw => rd_usedw --number of words stored on rd port
);
end struct;
|
-------------------------------------------------------------------------------
-- OpenMAC DMA FIFO
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.all;
entity openMAC_DMAfifo is
generic (
fifo_data_width_g : natural := 16;
fifo_word_size_g : natural := 32;
fifo_word_size_log2_g : natural := 5
);
port
(
aclr : in std_logic;
rd_clk : in std_logic;
wr_clk : in std_logic;
--read port
rd_req : in std_logic;
rd_data : out std_logic_vector(fifo_data_width_g-1 downto 0);
rd_empty : out std_logic;
rd_full : out std_logic;
rd_usedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0);
--write port
wr_req : in std_logic;
wr_data : in std_logic_vector(fifo_data_width_g-1 downto 0);
wr_empty : out std_logic;
wr_full : out std_logic;
wr_usedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0)
);
end openMAC_DMAfifo;
architecture struct of openMAC_DMAfifo is
component dcfifo
generic (
lpm_width : natural; --width of data and q ports (input/output)
lpm_widthu : natural; --width of wrusedw and rdusedw
lpm_numwords : natural; --depth of fifo
lpm_showahead : string; --fifo showahead off/on (rdreq works as req/ack)
lpm_type : string; --SCFIFO or DCFIFO (single/dual clocked)
overflow_checking : string; --protection circuit for wrreq
underflow_checking : string; --protection circuit for rdreq
rdsync_delaypipe : natural; --number of sync from wr to rd
wrsync_delaypipe : natural; --number of sync from rd to wr
use_eab : string; --construct fifo as LE/RAM (off/on)
write_aclr_synch : string; --sync async. clear to wr clk (avoids race cond.)
intended_device_family : string --specifies the intended device for functional simulation
);
port (
wrclk : in std_logic; --clock for wr port
rdclk : in std_logic; --clock for rd port
data : in std_logic_vector(fifo_data_width_g-1 downto 0); --data to be written
wrreq : in std_logic; --write request
rdreq : in std_logic; --read request
aclr : in std_logic; --asynchronous clear fifo
q : out std_logic_vector(fifo_data_width_g-1 downto 0); --read data
wrfull : out std_logic; --fifo is full on wr port
rdfull : out std_logic; --fifo is full on rd port
wrempty : out std_logic; --fifo is empty on wr port
rdempty : out std_logic; --fifo is empty on rd port
wrusedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0); --number of words stored on wr port
rdusedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0) --number of words stored on rd port
);
end component;
constant fifo_useRam_c : string := "ON";
constant fifo_words_c : natural := fifo_word_size_g; --e.g. 32
constant fifo_usedw_c : natural := fifo_word_size_log2_g; --e.g. log2(32) = 5
--constant fifo_rd_usedw_c : natural := 5;
--constant fifo_wr_usedw_c : natural := 5;
constant fifo_data_width_c : natural := fifo_data_width_g;
--constant fifo_rd_data_width_c : natural := 16;
--constant fifo_wr_data_width_c : natural := 16;
begin
dcfifo_inst : dcfifo
generic map (
lpm_width => fifo_data_width_c, --width of data and q ports (input/output)
lpm_widthu => fifo_usedw_c, --width of wrusedw and rdusedw
lpm_numwords => fifo_words_c, --depth of fifo
lpm_showahead => "OFF", --fifo showahead off/on (rdreq works as req/ack)
lpm_type => "DCFIFO", --SCFIFO or DCFIFO (single/dual clocked)
overflow_checking => "ON", --protection circuit for wrreq
underflow_checking => "ON", --protection circuit for rdreq
rdsync_delaypipe => 4, --number of sync from wr to rd
wrsync_delaypipe => 4, --number of sync from rd to wr
use_eab => fifo_useRam_c, --construct fifo as LE/RAM (off/on)
write_aclr_synch => "ON", --sync async. clear to wr clk (avoids race cond.)
intended_device_family => "Cyclone IV" --specifies the intended device for functional simulation
)
port map (
wrclk => wr_clk, --clock for wr port
rdclk => rd_clk, --clock for rd port
data => wr_data, --data to be written
wrreq => wr_req, --write request
rdreq => rd_req, --read request
aclr => aclr, --asynchronous clear fifo
q => rd_data, --read data
wrfull => wr_full, --fifo is full on wr port
rdfull => rd_full, --fifo is full on rd port
wrempty => wr_empty, --fifo is empty on wr port
rdempty => rd_empty, --fifo is empty on rd port
wrusedw => wr_usedw, --number of words stored on wr port
rdusedw => rd_usedw --number of words stored on rd port
);
end struct;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
entity interrupt_handler is
port (
data_in1, data_in2 : in std_logic_vector(7 downto 0);
raddr1, raddr2 : inout std_logic_vector(3 downto 0);
raddr_write : out std_logic_vector(3 downto 0);
reg_re, reg_we : out std_logic;
data_out : out std_logic_vector(7 downto 0);
PC_in : in std_logic_vector(7 downto 0);
PC_out : out std_logic_vector(7 downto 0);
interrupt_reg_data : in std_logic_vector(7 downto 0);
interrupt_reg_we : in std_logic;
interrupt_or_return_happened, interrupt_or_return_handled : out std_logic;
return_opcode : in std_logic;
clk, rst : in std_logic
);
end entity;
architecture behav of interrupt_handler is
signal interrupt_reg : std_logic_vector(7 downto 0);
signal count : integer range 0 to 20;
signal scratch_PC : std_logic_vector(7 downto 0);
signal scratch_interrupt_reg : std_logic_vector(7 downto 0);
signal raddr1_out, raddr2_out, raddr_read : std_logic_vector(3 downto 0);
signal re, we, rise_we : std_logic;
signal interrupt_happened, interrupt_handled, return_happened, return_handled : std_logic;
component scratch_pad is
port (
data_in1, data_in2 : in std_logic_vector(7 downto 0);
raddr_write1, raddr_write2 : in std_logic_vector(3 downto 0);
data_out : out std_logic_vector(7 downto 0);
raddr_read : in std_logic_vector(3 downto 0);
re, we, clk : in std_logic
);
end component;
begin
scratch_pad1 : scratch_pad
port map (
data_in1 => data_in1,
data_in2 => data_in2,
raddr_write1 => raddr1_out,
raddr_write2 => raddr2_out,
data_out => data_out,
raddr_read => raddr_read,
re => re,
we => we,
clk => clk
);
process (clk, rst) is
variable verify : std_logic_vector(3 downto 0);
variable tmp_sr: std_logic_vector(7 downto 0);
variable tmp_scratch_interrupt_reg : std_logic_vector(7 downto 0);
begin
if (rst = '1') then
interrupt_reg <= X"00";
interrupt_happened <= '0';
interrupt_handled <= '0';
return_happened <= '0';
return_handled <= '0';
elsif (rising_edge(clk)) then
verify := interrupt_reg(7 downto 4) and interrupt_reg(3 downto 0);
if (interrupt_happened = '0') then
if (verify /= "0000") then
interrupt_happened <= '1';
interrupt_handled <= '0';
return_happened <= '0';
return_handled <= '0';
count <= 0;
scratch_PC <= PC_in;
if (verify(3) = '1') then
PC_out <= "00010100";
scratch_interrupt_reg <= (interrupt_reg and "01111111" );
interrupt_reg <= ("00000000" );
elsif (verify(2) = '1') then
PC_out <= "00100000";
scratch_interrupt_reg <= (interrupt_reg and "10111111" );
interrupt_reg <= ("00000000");
elsif (verify(1) = '1') then
PC_out <= "01000000";
scratch_interrupt_reg <= (interrupt_reg and "11011111" );
interrupt_reg <= ( "00000000" );
elsif (verify(0) = '1') then
PC_out <= "10000000";
scratch_interrupt_reg <= (interrupt_reg and "11101111" );
interrupt_reg <= ("00000000");
end if;
end if;
elsif (interrupt_handled = '0') then
if (count = 0) then
count <= count + 1;
elsif (count = 1) then
count <= count + 1;
raddr1 <= X"0";
raddr2 <= X"1";
reg_re <= '1';
rise_we <= '1';
elsif (count = 2) then
count <= count + 1;
raddr1 <= X"2";
raddr2 <= X"3";
reg_re <= '1';
rise_we <= '1';
elsif (count = 3) then
count <= count + 1;
raddr1 <= X"4";
raddr2 <= X"5";
reg_re <= '1';
rise_we <= '1';
elsif (count = 4) then
count <= count + 1;
raddr1 <= X"6";
raddr2 <= X"7";
reg_re <= '1';
rise_we <= '1';
elsif (count = 5) then
count <= count + 1;
raddr1 <= X"8";
raddr2 <= X"9";
reg_re <= '1';
rise_we <= '1';
elsif (count = 6) then
count <= count + 1;
raddr1 <= X"A";
raddr2 <= X"B";
reg_re <= '1';
rise_we <= '1';
elsif (count = 7) then
count <= count + 1;
raddr1 <= X"C";
raddr2 <= X"D";
reg_re <= '1';
rise_we <= '1';
elsif (count = 8) then
count <= 9;
raddr1 <= X"E";
raddr2 <= X"F";
reg_re <= '1';
rise_we <= '1';
elsif (count = 9) then
interrupt_handled <= '1';
interrupt_happened <= '0';
reg_re <= '0';
reg_we <= '0';
we <= '0';
re <= '0';
rise_we <= '0';
end if;
end if;
--------------------------------------------------------------------------- checking for next interrupt
if (return_opcode = '1') then
return_happened <= '1';
return_handled <= '0';
interrupt_happened <= '0';
interrupt_handled <= '0';
count <= 0;
elsif (return_happened = '1') then
report "Return from interrupt";
tmp_sr := interrupt_reg or scratch_interrupt_reg;
verify := tmp_sr(7 downto 4) and tmp_sr(3 downto 0);
if (verify /= "0000") then
if (count = 0) then
if (verify(3) = '1') then
PC_out <= "00010100";
tmp_scratch_interrupt_reg := (tmp_sr and "01111111" );
--interrupt_reg <= ("00000000" );
elsif (verify(2) = '1') then
PC_out <= "00100000";
tmp_scratch_interrupt_reg := (tmp_sr and "10111111" );
--interrupt_reg <= ("00000000");
elsif (verify(1) = '1') then
PC_out <= "01000000";
tmp_scratch_interrupt_reg := (tmp_sr and "11011111" );
--interrupt_reg <= ( "00000000" );
elsif (verify(0) = '1') then
PC_out <= "10000000";
tmp_scratch_interrupt_reg := (tmp_sr and "11101111" );
--interrupt_reg <= ("00000000");
end if;
count <= count + 1;
elsif (count = 1) then
count <= count + 1;
elsif (count = 2) then
return_happened <= '0';
return_handled <= '1';
count <= 0;
interrupt_reg <= X"00";
scratch_interrupt_reg <= tmp_scratch_interrupt_reg;
end if;
else
report "No interrupt. Return to normal";
if (count = 0) then
count <= count + 1;
PC_out <= scratch_PC;
interrupt_reg <= interrupt_reg or scratch_interrupt_reg;
report "count = 0";
elsif (count = 1) then
count <= count + 1;
raddr_read <= X"0";
rise_we <= '1';
re <= '1';
elsif (count = 2) then
count <= count + 1;
raddr_read <= X"1";
rise_we <= '1';
re <= '1';
elsif (count = 3) then
count <= count + 1;
raddr_read <= X"2";
rise_we <= '1';
re <= '1';
elsif (count = 4) then
count <= count + 1;
raddr_read <= X"3";
rise_we <= '1';
re <= '1';
elsif (count = 5) then
count <= count + 1;
raddr_read <= X"4";
rise_we <= '1';
re <= '1';
elsif (count = 6) then
count <= count + 1;
raddr_read <= X"5";
rise_we <= '1';
re <= '1';
elsif (count = 7) then
count <= count + 1;
raddr_read <= X"6";
rise_we <= '1';
re <= '1';
elsif (count = 8) then
count <= count + 1;
raddr_read <= X"7";
rise_we <= '1';
re <= '1';
elsif (count = 9) then
count <= count + 1;
raddr_read <= X"8";
rise_we <= '1';
re <= '1';
elsif (count = 10) then
count <= count + 1;
raddr_read <= X"9";
rise_we <= '1';
re <= '1';
elsif (count = 11) then
count <= count + 1;
raddr_read <= X"A";
rise_we <= '1';
re <= '1';
elsif (count = 12) then
count <= count + 1;
raddr_read <= X"B";
rise_we <= '1';
re <= '1';
elsif (count = 13) then
count <= count + 1;
raddr_read <= X"C";
rise_we <= '1';
re <= '1';
elsif (count = 14) then
count <= count + 1;
raddr_read <= X"D";
rise_we <= '1';
re <= '1';
elsif (count = 15) then
count <= count + 1;
raddr_read <= X"E";
rise_we <= '1';
re <= '1';
elsif (count = 16) then
count <= count + 1;
raddr_read <= X"F";
rise_we <= '1';
re <= '1';
elsif (count = 17) then
count <= 0;
return_happened <= '0';
return_handled <= '1';
reg_we <= '0';
reg_re <= '0';
re <= '0';
we <= '0';
rise_we <= '0';
end if;
end if;
end if;
elsif (falling_edge(clk)) then
if (interrupt_reg_we = '1') then
interrupt_reg <= interrupt_reg or interrupt_reg_data;
end if;
if ((interrupt_happened = '1') and (interrupt_handled = '0')) then
raddr1_out <= raddr1;
raddr2_out <= raddr2;
we <= rise_we;
end if;
if ((return_happened = '1') and (return_handled = '0')) then
raddr_write <= raddr_read;
reg_we <= rise_we;
end if;
end if;
end process;
process (interrupt_happened, interrupt_handled, return_happened, return_handled)
begin
interrupt_or_return_happened <= interrupt_happened or return_happened;
interrupt_or_return_handled <= interrupt_handled or return_handled;
end process;
end architecture;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_iic:2.0
-- IP Revision: 14
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_axi_iic_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
iic2intc_irpt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
sda_i : IN STD_LOGIC;
sda_o : OUT STD_LOGIC;
sda_t : OUT STD_LOGIC;
scl_i : IN STD_LOGIC;
scl_o : OUT STD_LOGIC;
scl_t : OUT STD_LOGIC;
gpo : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END system_axi_iic_0_0;
ARCHITECTURE system_axi_iic_0_0_arch OF system_axi_iic_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_iic_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_iic IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_IIC_FREQ : INTEGER;
C_TEN_BIT_ADR : INTEGER;
C_GPO_WIDTH : INTEGER;
C_S_AXI_ACLK_FREQ_HZ : INTEGER;
C_SCL_INERTIAL_DELAY : INTEGER;
C_SDA_INERTIAL_DELAY : INTEGER;
C_SDA_LEVEL : INTEGER;
C_SMBUS_PMBUS_HOST : INTEGER;
C_DEFAULT_VALUE : STD_LOGIC_VECTOR(7 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
iic2intc_irpt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
sda_i : IN STD_LOGIC;
sda_o : OUT STD_LOGIC;
sda_t : OUT STD_LOGIC;
scl_i : IN STD_LOGIC;
scl_o : OUT STD_LOGIC;
scl_t : OUT STD_LOGIC;
gpo : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT axi_iic;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_axi_iic_0_0_arch: ARCHITECTURE IS "axi_iic,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_axi_iic_0_0_arch : ARCHITECTURE IS "system_axi_iic_0_0,axi_iic,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_axi_iic_0_0_arch: ARCHITECTURE IS "system_axi_iic_0_0,axi_iic,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_iic,x_ipVersion=2.0,x_ipCoreRevision=14,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_IIC_FREQ=100000,C_TEN_BIT_ADR=0,C_GPO_WIDTH=1,C_S_AXI_ACLK_FREQ_HZ=100000000,C_SCL_INERTIAL_DELAY=0,C_SDA_INERTIAL_DELAY=0,C_SDA_LEVEL=1,C_SMBUS_PMBUS_HOST=0,C_DEFAULT_VALUE=0x00}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF iic2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF sda_i: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SDA_I";
ATTRIBUTE X_INTERFACE_INFO OF sda_o: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SDA_O";
ATTRIBUTE X_INTERFACE_INFO OF sda_t: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SDA_T";
ATTRIBUTE X_INTERFACE_INFO OF scl_i: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SCL_I";
ATTRIBUTE X_INTERFACE_INFO OF scl_o: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SCL_O";
ATTRIBUTE X_INTERFACE_INFO OF scl_t: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SCL_T";
BEGIN
U0 : axi_iic
GENERIC MAP (
C_FAMILY => "artix7",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_IIC_FREQ => 100000,
C_TEN_BIT_ADR => 0,
C_GPO_WIDTH => 1,
C_S_AXI_ACLK_FREQ_HZ => 100000000,
C_SCL_INERTIAL_DELAY => 0,
C_SDA_INERTIAL_DELAY => 0,
C_SDA_LEVEL => 1,
C_SMBUS_PMBUS_HOST => 0,
C_DEFAULT_VALUE => X"00"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
iic2intc_irpt => iic2intc_irpt,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
sda_i => sda_i,
sda_o => sda_o,
sda_t => sda_t,
scl_i => scl_i,
scl_o => scl_o,
scl_t => scl_t,
gpo => gpo
);
END system_axi_iic_0_0_arch;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file hw_multiplier.vhd when simulating
-- the core, hw_multiplier. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY hw_multiplier IS
PORT (
clk : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
p : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END hw_multiplier;
ARCHITECTURE hw_multiplier_a OF hw_multiplier IS
-- synthesis translate_off
COMPONENT wrapped_hw_multiplier
PORT (
clk : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
p : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_hw_multiplier USE ENTITY XilinxCoreLib.mult_gen_v11_2(behavioral)
GENERIC MAP (
c_a_type => 0,
c_a_width => 32,
c_b_type => 0,
c_b_value => "10000001",
c_b_width => 32,
c_ccm_imp => 0,
c_ce_overrides_sclr => 0,
c_has_ce => 0,
c_has_sclr => 0,
c_has_zero_detect => 0,
c_latency => 1,
c_model_type => 0,
c_mult_type => 1,
c_optimize_goal => 1,
c_out_high => 63,
c_out_low => 0,
c_round_output => 0,
c_round_pt => 0,
c_verbosity => 0,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_hw_multiplier
PORT MAP (
clk => clk,
a => a,
b => b,
p => p
);
-- synthesis translate_on
END hw_multiplier_a;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
entity dpram_sc is
generic (
g_width_bits : positive := 16;
g_depth_bits : positive := 9;
g_read_first_a : boolean := false;
g_read_first_b : boolean := false;
g_global_init : std_logic_vector := X"0000";
g_storage : string := "auto" -- can also be "block" or "distributed"
);
port (
clock : in std_logic;
a_address : in unsigned(g_depth_bits-1 downto 0);
a_rdata : out std_logic_vector(g_width_bits-1 downto 0);
a_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0');
a_en : in std_logic := '1';
a_we : in std_logic := '0';
b_address : in unsigned(g_depth_bits-1 downto 0) := (others => '0');
b_rdata : out std_logic_vector(g_width_bits-1 downto 0);
b_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0');
b_en : in std_logic := '1';
b_we : in std_logic := '0' );
end entity;
architecture altera of dpram_sc is
function string_select(a,b: string; s:boolean) return string is
begin
if s then
return a;
end if;
return b;
end function;
-- Error (14271): Illegal value NEW_DATA for port_b_read_during_write_mode parameter in WYSIWYG primitive "ram_block1a9" -- value must be new_data_no_nbe_read, new_data_with_nbe_read or old_data
constant a_new_data : string := string_select("OLD_DATA", "new_data_no_nbe_read", g_read_first_a);
constant b_new_data : string := string_select("OLD_DATA", "new_data_no_nbe_read", g_read_first_b);
signal wren_a : std_logic;
signal wren_b : std_logic;
begin
-- assert g_global_init = X"0000"
-- report "Output register initialization of BRAM is not supported for Altera"
-- severity failure;
assert not g_read_first_a report "Port A. Cyclone V does not support reading of old data while writing. Forcing new data to be read! Results may differ!" severity warning;
assert not g_read_first_b report "Port B. Cyclone V does not support reading of old data while writing. Forcing new data to be read! Results may differ!" severity warning;
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK0",
intended_device_family => "Cyclone IV E",
lpm_type => "altsyncram",
numwords_a => 2 ** g_depth_bits,
numwords_b => 2 ** g_depth_bits,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_mixed_ports => "dont_care", --"OLD_DATA",
read_during_write_mode_port_a => "new_data_no_nbe_read",
read_during_write_mode_port_b => "new_data_no_nbe_read",
widthad_a => g_depth_bits,
widthad_b => g_depth_bits,
width_a => g_width_bits,
width_b => g_width_bits,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK0"
)
PORT MAP (
address_a => std_logic_vector(a_address),
address_b => std_logic_vector(b_address),
clock0 => clock,
data_a => a_wdata,
data_b => b_wdata,
rden_a => a_en,
rden_b => b_en,
wren_a => wren_a,
wren_b => wren_b,
q_a => a_rdata,
q_b => b_rdata );
wren_a <= a_we and a_en;
wren_b <= b_we and b_en;
end architecture;
|
LIBRARY IEEE;
USE ieee.numeric_std.all;
USE ieee.std_logic_1164.all;
USE ieee.math_real.all;
--alu_ops_map = {
-- "+": "000",
-- "-": "001",
-- "*": "010",
-- "/": "011",
-- "!": "100",
-- "&": "101",
-- "^": "110",
-- "|": "111"
-- }
ENTITY ALU IS
GENERIC(
data_width: INTEGER := 16);
PORT(
in_1: IN STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
in_2: IN STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
outp: OUT STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
sel: IN STD_LOGIC_VECTOR( 0 TO 2 ) := (others => '0'));
END ENTITY;
architecture alu_le_le of ALU is
signal add_out, sub_out, mul_out, div_out, not_out, and_out, xor_out, or_out: std_logic_vector(0 to data_width-1) := (others => '0');
begin
process(in_1, in_2)
begin
add_out <= std_logic_vector((unsigned(in_1)) + (unsigned(in_2)));-- after 2 ns;
--sub_out <= std_logic_vector(to_integer(unsigned(in_1)) - to_integer(unsigned(in_2)));-- after 2 ns;
--mul_out <= std_logic_vector(to_integer(unsigned(in_1)) * to_integer(unsigned(in_2)));-- after 3 ns;
--div_out <= std_logic_vector(to_integer(unsigned(in_1)) / to_integer(unsigned(in_2)));-- after 3 ns;
or_out <= in_1 or in_2;-- after 1 ns;
and_out <= in_1 and in_2;-- after 1 ns;
not_out <= not in_1;-- after 1 ns;
xor_out <= in_1 xor in_2;-- after 1 ns;
end process;
process(sel,add_out,sub_out,mul_out,div_out,or_out,and_out,not_out,xor_out)
begin
if(sel = "000") then
outp <= add_out;
elsif(sel = "001") then
outp <= sub_out;
elsif(sel = "010") then
outp <= mul_out;
elsif(sel = "011") then
outp <= div_out;
elsif(sel = "100") then
outp <= not_out;
elsif(sel = "101") then
outp <= and_out;
elsif(sel = "110") then
outp <= xor_out;
elsif(sel = "111") then
outp <= or_out;
else
outp <= (others => '0');
end if;
end process;
end architecture;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:20:08 07/12/05
-- Design Name:
-- Module Name: combine_g_bar - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity combine_g_bar is
Port ( g1 : in std_logic_vector(8 downto 0);
g2 : in std_logic_vector(8 downto 0);
b1 : in std_logic_vector(8 downto 0);
b2 : in std_logic_vector(8 downto 0);
b3 : in std_logic_vector(8 downto 0);
b4 : in std_logic_vector(8 downto 0);
g1_2 : in std_logic_vector(8 downto 0);
g2_2 : in std_logic_vector(8 downto 0);
b1_2 : in std_logic_vector(8 downto 0);
b2_2 : in std_logic_vector(8 downto 0);
b3_2 : in std_logic_vector(8 downto 0);
b4_2 : in std_logic_vector(8 downto 0);
g_bar : out std_logic_vector(8 downto 0));
end combine_g_bar;
architecture Behavioral of combine_g_bar is
component sub_to_adder
Port ( pixel_in1 : in std_logic_vector(8 downto 0);
pixel_in2 : in std_logic_vector(8 downto 0);
pixel_in3 : in std_logic_vector(8 downto 0);
pixel_in4 : in std_logic_vector(8 downto 0);
pixel_in5 : in std_logic_vector(8 downto 0);
pixel_in6 : in std_logic_vector(8 downto 0);
adder_out : out std_logic_vector(10 downto 0));
end component;
component compare
Port ( Dhor : in std_logic_vector(10 downto 0);
Dver : in std_logic_vector(10 downto 0);
choose : out std_logic );
end component;
component adder_shift
Port ( g1 , g2 : in std_logic_vector(8 downto 0);
-- C0 : in std_logic;
S : out std_logic_vector(8 downto 0) );
end component;
component mux2t1_zoe
Port ( G1_adder_shift : in std_logic_vector(8 downto 0);
G2_adder_shift : in std_logic_vector(8 downto 0);
sele : in std_logic;
G_bar : out std_logic_vector(8 downto 0));
end component;
signal adder_out1: std_logic_vector(10 downto 0);
signal adder_out2: std_logic_vector(10 downto 0);
signal choose: std_logic;
signal G_choose1: std_logic_vector(8 downto 0);
signal G_choose2: std_logic_vector(8 downto 0);
begin
element1: sub_to_adder port map(
g1,g2,b1,b2,b3,b4,adder_out1);
element2: sub_to_adder port map(
g1_2,g2_2,b1_2,b2_2,b3_2,b4_2,adder_out2);
element3: compare port map(
adder_out1,adder_out2,choose);
element4: adder_shift port map(
g1,g2,G_choose1);
element5: adder_shift port map(
g1_2,g2_2,G_choose2);
element6: mux2t1_zoe port map(
G_choose1 , G_choose2 , choose , g_bar);
end Behavioral;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mult_gen:12.0
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mult_gen_v12_0_12;
USE mult_gen_v12_0_12.mult_gen_v12_0_12;
ENTITY mul_16_32 IS
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
P : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
);
END mul_16_32;
ARCHITECTURE mul_16_32_arch OF mul_16_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF mul_16_32_arch: ARCHITECTURE IS "yes";
COMPONENT mult_gen_v12_0_12 IS
GENERIC (
C_VERBOSITY : INTEGER;
C_MODEL_TYPE : INTEGER;
C_OPTIMIZE_GOAL : INTEGER;
C_XDEVICEFAMILY : STRING;
C_HAS_CE : INTEGER;
C_HAS_SCLR : INTEGER;
C_LATENCY : INTEGER;
C_A_WIDTH : INTEGER;
C_A_TYPE : INTEGER;
C_B_WIDTH : INTEGER;
C_B_TYPE : INTEGER;
C_OUT_HIGH : INTEGER;
C_OUT_LOW : INTEGER;
C_MULT_TYPE : INTEGER;
C_CE_OVERRIDES_SCLR : INTEGER;
C_CCM_IMP : INTEGER;
C_B_VALUE : STRING;
C_HAS_ZERO_DETECT : INTEGER;
C_ROUND_OUTPUT : INTEGER;
C_ROUND_PT : INTEGER
);
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
CE : IN STD_LOGIC;
SCLR : IN STD_LOGIC;
P : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
);
END COMPONENT mult_gen_v12_0_12;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF P: SIGNAL IS "xilinx.com:signal:data:1.0 p_intf DATA";
BEGIN
U0 : mult_gen_v12_0_12
GENERIC MAP (
C_VERBOSITY => 0,
C_MODEL_TYPE => 0,
C_OPTIMIZE_GOAL => 1,
C_XDEVICEFAMILY => "kintexu",
C_HAS_CE => 0,
C_HAS_SCLR => 0,
C_LATENCY => 4,
C_A_WIDTH => 16,
C_A_TYPE => 1,
C_B_WIDTH => 32,
C_B_TYPE => 1,
C_OUT_HIGH => 47,
C_OUT_LOW => 0,
C_MULT_TYPE => 0,
C_CE_OVERRIDES_SCLR => 0,
C_CCM_IMP => 0,
C_B_VALUE => "10000001",
C_HAS_ZERO_DETECT => 0,
C_ROUND_OUTPUT => 0,
C_ROUND_PT => 0
)
PORT MAP (
CLK => CLK,
A => A,
B => B,
CE => '1',
SCLR => '0',
P => P
);
END mul_16_32_arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:41:32 02/12/2014
-- Design Name:
-- Module Name: full_adder_1_bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity cl_logic is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
Cin1 : out STD_LOGIC;
Cin2 : out STD_LOGIC;
Cin3 : out STD_LOGIC;
Cout : out STD_LOGIC);
end cl_logic;
architecture Behavioral of cl_logic is
begin
-- Cin1 = G_0 + P_0 * Cin0
Cin1 <= ( A(0) AND B(0) )
OR ( (Cin)
AND (A(0) OR B(0)) );
-- Cin2 = G_1 + P_1 * Cin1
Cin2 <= ( A(1) AND B(1) )
OR ( (A(0) AND B(0))
AND (A(1) OR B(1)) )
OR ( (Cin)
AND (A(0) OR B(0))
AND (A(1) OR B(1)) );
-- Cin3 = G_2 + P_2 * Cin2
Cin3 <= ( A(2) AND B(2) )
OR ( (A(1) AND B(1))
AND (A(2) OR B(2)) )
OR ( (A(0) AND B(0))
AND (A(1) OR B(1))
AND (A(2) OR B(2)) )
OR ( (Cin)
AND (A(0) OR B(0))
AND (A(1) OR B(1))
AND (A(2) OR B(2)) );
-- Cout = G_3 + P_3 * Cin3
Cout <= ( A(3) AND B(3) )
OR ( (A(2) AND B(2))
AND (A(3) OR B(3)) )
OR ( (A(1) AND B(1))
AND (A(2) OR B(2))
AND (A(3) OR B(3)) )
OR ( (A(0) AND B(0))
AND (A(1) OR B(1))
AND (A(2) OR B(2))
AND (A(3) OR B(3)) )
OR ( (Cin)
AND (A(0) OR B(0))
AND (A(1) OR B(1))
AND (A(2) OR B(2))
AND (A(3) OR B(3)) );
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:41:32 02/12/2014
-- Design Name:
-- Module Name: full_adder_1_bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity cl_logic is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
Cin1 : out STD_LOGIC;
Cin2 : out STD_LOGIC;
Cin3 : out STD_LOGIC;
Cout : out STD_LOGIC);
end cl_logic;
architecture Behavioral of cl_logic is
begin
-- Cin1 = G_0 + P_0 * Cin0
Cin1 <= ( A(0) AND B(0) )
OR ( (Cin)
AND (A(0) OR B(0)) );
-- Cin2 = G_1 + P_1 * Cin1
Cin2 <= ( A(1) AND B(1) )
OR ( (A(0) AND B(0))
AND (A(1) OR B(1)) )
OR ( (Cin)
AND (A(0) OR B(0))
AND (A(1) OR B(1)) );
-- Cin3 = G_2 + P_2 * Cin2
Cin3 <= ( A(2) AND B(2) )
OR ( (A(1) AND B(1))
AND (A(2) OR B(2)) )
OR ( (A(0) AND B(0))
AND (A(1) OR B(1))
AND (A(2) OR B(2)) )
OR ( (Cin)
AND (A(0) OR B(0))
AND (A(1) OR B(1))
AND (A(2) OR B(2)) );
-- Cout = G_3 + P_3 * Cin3
Cout <= ( A(3) AND B(3) )
OR ( (A(2) AND B(2))
AND (A(3) OR B(3)) )
OR ( (A(1) AND B(1))
AND (A(2) OR B(2))
AND (A(3) OR B(3)) )
OR ( (A(0) AND B(0))
AND (A(1) OR B(1))
AND (A(2) OR B(2))
AND (A(3) OR B(3)) )
OR ( (Cin)
AND (A(0) OR B(0))
AND (A(1) OR B(1))
AND (A(2) OR B(2))
AND (A(3) OR B(3)) );
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:22:12 02/06/2015
-- Design Name:
-- Module Name: addN - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity addN is
generic(N: integer := 5);
port ( a,b: in std_logic_vector ( N-1 downto 0);
s: out std_logic_vector (N-1 downto 0));
end addN;
architecture archi of addN is
begin
process(a,b)
begin
s <= a + b ;
end process ;
end archi; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:22:12 02/06/2015
-- Design Name:
-- Module Name: addN - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity addN is
generic(N: integer := 5);
port ( a,b: in std_logic_vector ( N-1 downto 0);
s: out std_logic_vector (N-1 downto 0));
end addN;
architecture archi of addN is
begin
process(a,b)
begin
s <= a + b ;
end process ;
end archi; |
-------------------------------------------------------------------------------
--
-- SNESpad controller core
--
-- $Id: snespad.vhd,v 1.2 2004/10/05 18:22:40 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/gamepads/
--
-- The project homepage is located at:
-- http://www.opencores.org/projects.cgi/web/gamepads/overview
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity snespad is
generic (
-- number of pads connected to this core
num_pads_g : natural := 1;
-- active level of reset_i
reset_level_g : natural := 0;
-- active level of the button outputs
button_level_g : natural := 0;
-- number of clk_i periods during 6us
clocks_per_6us_g : natural := 6
);
port (
-- System Interface -------------------------------------------------------
clk_i : in std_logic;
reset_i : in std_logic;
-- Gamepad Interface ------------------------------------------------------
pad_clk_o : out std_logic;
pad_latch_o : out std_logic;
pad_data_i : in std_logic_vector(num_pads_g-1 downto 0);
-- Buttons Interface ------------------------------------------------------
but_a_o : out std_logic_vector(num_pads_g-1 downto 0);
but_b_o : out std_logic_vector(num_pads_g-1 downto 0);
but_x_o : out std_logic_vector(num_pads_g-1 downto 0);
but_y_o : out std_logic_vector(num_pads_g-1 downto 0);
but_start_o : out std_logic_vector(num_pads_g-1 downto 0);
but_sel_o : out std_logic_vector(num_pads_g-1 downto 0);
but_tl_o : out std_logic_vector(num_pads_g-1 downto 0);
but_tr_o : out std_logic_vector(num_pads_g-1 downto 0);
but_up_o : out std_logic_vector(num_pads_g-1 downto 0);
but_down_o : out std_logic_vector(num_pads_g-1 downto 0);
but_left_o : out std_logic_vector(num_pads_g-1 downto 0);
but_right_o : out std_logic_vector(num_pads_g-1 downto 0)
);
end snespad;
architecture struct of snespad is
component snespad_ctrl
generic (
reset_level_g : natural := 0;
clocks_per_6us_g : natural := 6
);
port (
clk_i : in std_logic;
reset_i : in std_logic;
clk_en_o : out boolean;
shift_buttons_o : out boolean;
save_buttons_o : out boolean;
pad_clk_o : out std_logic;
pad_latch_o : out std_logic
);
end component snespad_ctrl;
component snespad_pad
generic (
reset_level_g : natural := 0;
button_level_g : natural := 0
);
port (
clk_i : in std_logic;
reset_i : in std_logic;
clk_en_i : in boolean;
shift_buttons_i : in boolean;
save_buttons_i : in boolean;
pad_data_i : in std_logic;
but_a_o : out std_logic;
but_b_o : out std_logic;
but_x_o : out std_logic;
but_y_o : out std_logic;
but_start_o : out std_logic;
but_sel_o : out std_logic;
but_tl_o : out std_logic;
but_tr_o : out std_logic;
but_up_o : out std_logic;
but_down_o : out std_logic;
but_left_o : out std_logic;
but_right_o : out std_logic
);
end component snespad_pad;
signal clk_en_s : boolean;
signal shift_buttons_s : boolean;
signal save_buttons_s : boolean;
begin
ctrl_b : snespad_ctrl
generic map (
reset_level_g => reset_level_g,
clocks_per_6us_g => clocks_per_6us_g
)
port map (
clk_i => clk_i,
reset_i => reset_i,
clk_en_o => clk_en_s,
shift_buttons_o => shift_buttons_s,
save_buttons_o => save_buttons_s,
pad_clk_o => pad_clk_o,
pad_latch_o => pad_latch_o
);
pads: for i in 0 to num_pads_g-1 generate
pad_b : snespad_pad
generic map (
reset_level_g => reset_level_g,
button_level_g => button_level_g
)
port map (
clk_i => clk_i,
reset_i => reset_i,
clk_en_i => clk_en_s,
shift_buttons_i => shift_buttons_s,
save_buttons_i => save_buttons_s,
pad_data_i => pad_data_i(i),
but_a_o => but_a_o(i),
but_b_o => but_b_o(i),
but_x_o => but_x_o(i),
but_y_o => but_y_o(i),
but_start_o => but_start_o(i),
but_sel_o => but_sel_o(i),
but_tl_o => but_tl_o(i),
but_tr_o => but_tr_o(i),
but_up_o => but_up_o(i),
but_down_o => but_down_o(i),
but_left_o => but_left_o(i),
but_right_o => but_right_o(i)
);
end generate;
end struct;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: snespad.vhd,v $
-- Revision 1.2 2004/10/05 18:22:40 arniml
-- comments for the generic parameters
--
-- Revision 1.1 2004/10/05 17:01:27 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
Library Ieee;
Use Ieee.Std_Logic_1164.all;
Entity Mips8B_DataPath is
Generic( N: Natural := 8;
RF_SIZE: Natural := 8;
SH_SIZE: Natural := 3;
RF_ADDR_SIZE: Natural := 3);
Port(clock: in Std_Logic;
-- Controle dos Registradores do Shift Register.
en_Reg_SH: in Std_Logic;
-- Controle para Shifter.
crt_SH: in Std_Logic_Vector(1 downto 0);
S_SH: in Std_Logic_Vector(SH_SIZE-1 downto 0);
-- Controle dos Registradores da ULA.
en_R1A_ULA: in Std_Logic;
en_R1B_ULA: in Std_Logic;
en_R2_ULA: in Std_Logic;
-- Controle para ULA.
crt_ULA: in Std_Logic_Vector(2 downto 0);
crt_Mux_ULA: in Std_Logic_Vector(1 downto 0);
-- Controle para Register File.
crt_RFile: in Std_Logic;
crt_Mux_RF: in Std_Logic;
address_RF: in Std_Logic_Vector(RF_ADDR_SIZE-1 downto 0);
en_Raddress_RF: in Std_logic;
-- Controle para o Acumulador.
crt_Acc: in Std_Logic_Vector(1 downto 0);
crt_Mux_Acc: in Std_Logic;
-- Entradas do Datapath.
in_PC: in Std_Logic_Vector(N-3 downto 0);
in_IMM: in Std_Logic_Vector(N-1 downto 0);
-- Flag de Igualdade de Operandos.
eq_Flag: out Std_Logic;
-- Saida do resultado do Acumulador.
out_Acc: out Std_Logic_Vector(N-1 downto 0));
End Entity Mips8B_DataPath;
Architecture behave of Mips8B_DataPath is
Use Ieee.Numeric_Std.all;
Use Work.MIPS8B_Base.all;
type mem_type is Array(Natural Range <>) of Std_Logic_Vector(N-1 downto 0);
-- Repesentacao do Register File
Signal RFile_Mem: mem_type(1 to RF_SIZE-1);
Signal Raddress_RF: Std_Logic_Vector(RF_ADDR_SIZE-1 downto 0);
Signal out_RF: Std_Logic_Vector(N-1 downto 0);
-- Representacao das saidas dos multiplexadores.
Signal mux_R2A_ULA, mux_R2B_ULA: Std_Logic_Vector(N-1 downto 0);
Signal mux_RF, mux_Acc: Std_Logic_Vector(N-1 downto 0);
-- Saida do Acumulador
Signal int_out_Acc: Std_Logic_Vector(N-1 downto 0);
-- Registradores para os operandos na ULA e no Shifter.
Signal R1A_ULA, R1B_ULA: Std_Logic_Vector(N-1 downto 0);
Signal R2A_ULA, R2B_ULA: Std_Logic_Vector(N-1 downto 0);
Signal RCRT_ULA: Std_Logic_Vector(2 downto 0);
Signal RD_SH: Std_Logic_Vector(N-1 downto 0);
Signal RS_SH: Std_Logic_Vector(SH_SIZE-1 downto 0);
Signal RCRT_SH: Std_Logic_Vector(1 downto 0);
-- Resulatdos da ULA e do Shifter.
Signal res_ULA, res_SH: Std_Logic_Vector(N-1 downto 0);
Signal Flags: Std_Logic_Vector(1 downto 0);
Begin
-- Saida do Acumulador para fora do Datapath
out_Acc <= int_out_Acc;
-- Flag de Igualdade.
eq_Flag <= Flags(1);
---------------------------------------------------------------------------
-- Controle dos multiplexadores.
With crt_Mux_ULA(1) select
mux_R2A_ULA <= R1A_ULA when '0',
"00" & in_PC when others;
With crt_Mux_ULA(0) select
mux_R2B_ULA <= R1B_ULA when '0',
in_IMM when others;
With crt_Mux_Acc select
mux_Acc <= res_ULA when '0',
res_SH when others;
With crt_Mux_RF select
mux_RF <= int_out_Acc when '0',
in_IMM when others;
---------------------------------------------------------------------------
-- Representalcao do Register File.
RFILE_PROCESS: Process(clock,crt_RFile,Raddress_RF,RFile_Mem,mux_RF)
Begin
If clock'event and clock ='1' then
If Raddress_RF /= R0 and crt_RFile = '1' then
RFile_Mem(to_integer(to_01(Unsigned(Raddress_RF),'1'))) <= mux_RF;
End If;
End If;
If Raddress_RF /= R0 then
out_RF <= RFile_Mem(to_integer(to_01(Unsigned(Raddress_RF),'1')));
Else
out_RF <= (Others => '0');
End If;
End Process RFILE_PROCESS;
---------------------------------------------------------------------------
-- Processo responsavel pela controle dos registradores intermediarios.
MIPS8B_Regs: Process
Begin
Wait Until clock'Event and clock = '1';
If en_Raddress_RF = '1' then
Raddress_RF <= address_RF;
End If;
If en_R1A_ULA = '1' then
R1A_ULA <= out_RF;
End If;
If en_R1B_ULA = '1' then
R1B_ULA <= out_RF;
End If;
If en_R2_ULA = '1' then
R2A_ULA <= mux_R2A_ULA;
R2B_ULA <= mux_R2B_ULA;
RCRT_ULA <= crt_ULA;
End If;
If en_Reg_SH = '1' then
RD_SH <= R1A_ULA;
RS_SH <= S_SH;
RCRT_SH <= crt_SH;
End If;
End Process MIPS8B_Regs;
---------------------------------------------------------------------------
-- Processo responsavel pelas operacoes logicas e aritmeticas
MIPS8B_ULA: Process(R2A_ULA,R2B_ULA,RCRT_ULA,R1A_ULA,R1B_ULA)
Variable TempA, TempB, TempResult: Signed(N downto 0);
Begin
-- Copiando as entradas para execucao das operacoes aritmeticas
TempA := Signed(R2A_ULA(N-1) & R2A_ULA);
TempB := Signed(R2B_ULA(N-1) & R2B_ULA);
-- Realizando a operacao aritimetica
Case RCRT_ULA is
When uSUB =>
TempResult := TempA - TempB;
When uAND =>
TempResult := TempA and TempB;
When uOR =>
TempResult := TempA or TempB;
When Others =>
TempResult := TempA + TempB;
End Case;
-- Levando os resultados para Saida
res_ULA <= Std_Logic_Vector(TempResult(N-1 downto 0));
-- Flag para resultado negativo.
Flags(0) <= TempResult(N);
-- Flag para igualdade.
If R1A_ULA = R1B_ULA then
Flags(1) <= '1';
Else
Flags(1) <= '0';
End If;
End Process MIPS8B_ULA;
---------------------------------------------------------------------------
-- Processo responsavel pelas operacoes de Shifter
MIPS8B_SHIFTER: Process(RD_SH,RS_SH,RCRT_SH)
Begin
Case RCRT_SH is
When sRAR =>
res_SH <= Std_Logic_Vector(SHIFT_RIGHT(Signed(RD_SH),to_integer(Unsigned(RS_SH))));
When sRLL =>
res_SH <= Std_Logic_Vector(SHIFT_RIGHT(Unsigned(RD_SH),to_integer(Unsigned(RS_SH))));
When Others =>
res_SH <= Std_Logic_Vector(SHIFT_LEFT(Signed(RD_SH),to_integer(Unsigned(RS_SH))));
End Case;
End Process MIPS8B_SHIFTER;
---------------------------------------------------------------------------
-- Processo responsavel pelas operacoes no Acumulador
Acc: Process
Variable Temp: Std_Logic_Vector(N-1 downto 0);
Begin
Wait Until clock'Event and clock = '1';
Case crt_Acc is
When AccPar =>
int_out_Acc <= mux_Acc;
When AccFlag =>
Temp := (Others => '0');
If Flags ="01" then -- Comparacao resultou em Menor
Temp(0) := '1';
End If;
int_out_Acc <= Temp;
When Others =>
End Case;
End Process Acc;
End Architecture behave;
Configuration Mips8B_DataPath_behave_conf of Mips8B_DataPath is
For behave
End For;
End Configuration Mips8B_DataPath_behave_conf;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
library util;
use util.logic_pkg.all;
use util.types_pkg.all;
library tech;
library sys;
use sys.sys_config_pkg.all;
use sys.sys_pkg.all;
use work.cpu_l1mem_inst_cache_pkg.all;
use work.cpu_l1mem_inst_cache_config_pkg.all;
use work.cpu_types_pkg.all;
architecture rtl of cpu_l1mem_inst_cache_dp is
type reg_type is record
b_request_vpn : cpu_vpn_type;
b_request_poffset : cpu_ipoffset_type;
b_bus_op_paddr : cpu_ipaddr_type;
end record;
type comb_type is record
b_replace_rstate : cpu_l1mem_inst_cache_replace_state_type;
b_tram_rdata : std_ulogic_vector2(cpu_l1mem_inst_cache_assoc-1 downto 0,
cpu_l1mem_inst_cache_tag_bits-1 downto 0);
b_dram_rdata : std_ulogic_vector2(cpu_l1mem_inst_cache_assoc-1 downto 0,
cpu_inst_bits-1 downto 0);
b_bus_op_tag : std_ulogic_vector(cpu_l1mem_inst_cache_tag_bits-1 downto 0);
b_bus_op_index : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
b_bus_op_offset : std_ulogic_vector(cpu_l1mem_inst_cache_offset_bits-1 downto 0);
b_request_ppn : cpu_ppn_type;
b_request_paddr : cpu_ipaddr_type;
b_request_tag : std_ulogic_vector(cpu_l1mem_inst_cache_tag_bits-1 downto 0);
b_request_index : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
b_request_offset : std_ulogic_vector(cpu_l1mem_inst_cache_offset_bits-1 downto 0);
b_request_cache_tag_match : std_ulogic_vector(cpu_l1mem_inst_cache_assoc-1 downto 0);
b_request_last_in_block : std_ulogic;
b_cache_way_read_data : std_ulogic_vector2(cpu_l1mem_inst_cache_assoc-1 downto 0,
cpu_inst_bits-1 downto 0);
b_cache_read_data : std_ulogic_vector(cpu_inst_bits-1 downto 0);
b_result_inst_bus : std_ulogic_vector(cpu_inst_bits-1 downto 0);
b_result_inst_cache : std_ulogic_vector(cpu_inst_bits-1 downto 0);
b_result_paddr : cpu_ipaddr_type;
b_result_inst : cpu_inst_type;
b_replace_windex : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
b_replace_wstate : cpu_l1mem_inst_cache_replace_state_type;
b_vram_waddr : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
b_mram_waddr : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
a_new_request_poffset : cpu_ipoffset_type;
a_new_request_vpn : cpu_vpn_type;
a_request_poffset : cpu_ipoffset_type;
a_request_vpn : cpu_vpn_type;
a_request_ppn : cpu_ppn_type;
a_request_bus_op_data : cpu_inst_type;
a_request_vaddr : cpu_vaddr_type;
a_request_paddr : cpu_ipaddr_type;
a_request_tag : std_ulogic_vector(cpu_l1mem_inst_cache_tag_bits-1 downto 0);
a_request_index : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
a_request_offset : std_ulogic_vector(cpu_l1mem_inst_cache_offset_bits-1 downto 0);
a_bus_op_paddr_block_inst_offset_next : std_ulogic_vector(cpu_l1mem_inst_cache_offset_bits-1 downto 0);
a_bus_op_paddr : cpu_ipaddr_type;
a_bus_op_size : cpu_data_size_type;
a_bus_op_data : cpu_inst_type;
a_bus_op_index : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
a_bus_op_offset : std_ulogic_vector(cpu_l1mem_inst_cache_offset_bits-1 downto 0);
a_bus_op_cache_wtag : std_ulogic_vector(cpu_l1mem_inst_cache_tag_bits-1 downto 0);
a_bus_op_cache_index : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
a_bus_op_cache_offset : std_ulogic_vector(cpu_l1mem_inst_cache_offset_bits-1 downto 0);
a_bus_op_tram_wdata_tag : std_ulogic_vector(cpu_l1mem_inst_cache_tag_bits-1 downto 0);
a_bus_op_sys_paddr : cpu_ipaddr_type;
a_bus_op_sys_data : cpu_inst_type;
a_bus_op_dram_wdata : std_ulogic_vector(cpu_inst_bits-1 downto 0);
a_sys_size : sys_transfer_size_type;
a_sys_paddr : sys_paddr_type;
a_sys_data : sys_bus_type;
a_cache_index : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
a_cache_offset : std_ulogic_vector(cpu_l1mem_inst_cache_offset_bits-1 downto 0);
a_vram_raddr : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
a_tram_addr : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
a_tram_wtag : std_ulogic_vector(cpu_l1mem_inst_cache_tag_bits-1 downto 0);
a_tram_wdata : std_ulogic_vector2(cpu_l1mem_inst_cache_assoc-1 downto 0,
cpu_l1mem_inst_cache_tag_bits-1 downto 0);
a_dram_addr : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits+cpu_l1mem_inst_cache_offset_bits-1 downto 0);
a_dram_wdata_inst : std_ulogic_vector(cpu_inst_bits-1 downto 0);
a_dram_wdata : std_ulogic_vector2(cpu_l1mem_inst_cache_assoc-1 downto 0,
cpu_inst_bits-1 downto 0);
a_replace_rindex : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
end record;
signal c : comb_type;
signal r, r_next : reg_type;
begin
c.b_replace_rstate <= cpu_l1mem_inst_cache_replace_dp_out.rstate;
c.b_tram_rdata <= cpu_l1mem_inst_cache_dp_in_tram.rdata;
c.b_dram_rdata <= cpu_l1mem_inst_cache_dp_in_dram.rdata;
----------------------------------
c.b_request_ppn <= cpu_mmu_inst_dp_out.ppn;
c.b_request_paddr <= c.b_request_ppn & r.b_request_poffset;
c.b_request_tag <= c.b_request_paddr(cpu_ipaddr_bits-1 downto
cpu_l1mem_inst_cache_index_bits+cpu_l1mem_inst_cache_offset_bits);
c.b_request_index <= c.b_request_paddr(cpu_l1mem_inst_cache_index_bits+cpu_l1mem_inst_cache_offset_bits-1
downto cpu_l1mem_inst_cache_offset_bits);
c.b_request_offset <= c.b_request_paddr(cpu_l1mem_inst_cache_offset_bits-1 downto 0);
b_request_tag_match_gen : for n in cpu_l1mem_inst_cache_assoc-1 downto 0 generate
c.b_request_cache_tag_match(n) <=
logic_eq(c.b_request_tag,
std_ulogic_vector2_slice2(c.b_tram_rdata, n));
end generate;
c.b_request_last_in_block <= all_ones(c.b_request_offset);
----------------------------------
b_cache_read_data_way_gen : for n in cpu_l1mem_inst_cache_assoc-1 downto 0 generate
bit_loop : for b in cpu_inst_bits-1 downto 0 generate
c.b_cache_way_read_data(n, b) <= c.b_dram_rdata(n, b);
end generate;
end generate;
b_cache_read_data_mux : entity tech.mux_1hot(rtl)
generic map (
data_bits => cpu_inst_bits,
sel_bits => cpu_l1mem_inst_cache_assoc
)
port map (
din => c.b_cache_way_read_data,
sel => cpu_l1mem_inst_cache_dp_in_ctrl.b_cache_read_data_way,
dout => c.b_cache_read_data
);
----------------------------------
c.b_bus_op_tag <= r.b_bus_op_paddr(cpu_ipaddr_bits-1 downto
cpu_l1mem_inst_cache_index_bits+cpu_l1mem_inst_cache_offset_bits);
c.b_bus_op_index <= r.b_bus_op_paddr(cpu_l1mem_inst_cache_index_bits+cpu_l1mem_inst_cache_offset_bits-1 downto
cpu_l1mem_inst_cache_offset_bits);
c.b_bus_op_offset <= r.b_bus_op_paddr(cpu_l1mem_inst_cache_offset_bits-1 downto 0);
----------------------------------
c.b_result_inst_bus <= sys_slave_dp_out.data(cpu_inst_bits-1 downto 0);
c.b_result_inst_cache <= c.b_cache_read_data;
with cpu_l1mem_inst_cache_dp_in_ctrl.b_result_inst_sel select
c.b_result_inst <= c.b_result_inst_cache when cpu_l1mem_inst_cache_b_result_inst_sel_b_cache,
c.b_result_inst_bus when cpu_l1mem_inst_cache_b_result_inst_sel_b_bus,
(others => 'X') when others;
----------------------------------
with cpu_l1mem_inst_cache_dp_in_ctrl.b_cache_owner select
c.b_replace_windex <= c.b_request_index when cpu_l1mem_inst_cache_owner_request,
c.b_bus_op_index when cpu_l1mem_inst_cache_owner_bus_op,
(others => 'X') when others;
c.b_replace_wstate <= c.b_replace_rstate;
with cpu_l1mem_inst_cache_dp_in_ctrl.b_cache_owner select
c.b_vram_waddr <= c.b_request_index when cpu_l1mem_inst_cache_owner_request,
c.b_bus_op_index when cpu_l1mem_inst_cache_owner_bus_op,
(others => 'X') when others;
--------------------------
c.a_new_request_poffset <= cpu_l1mem_inst_cache_dp_in.vaddr(cpu_ipoffset_bits-1 downto 0);
c.a_new_request_vpn <= cpu_l1mem_inst_cache_dp_in.vaddr(cpu_ivaddr_bits-1 downto cpu_ipoffset_bits);
with cpu_l1mem_inst_cache_dp_in_ctrl.b_request_complete select
c.a_request_poffset <= c.a_new_request_poffset when '1',
r.b_request_poffset when '0',
(others => 'X') when others;
with cpu_l1mem_inst_cache_dp_in_ctrl.b_request_complete select
c.a_request_vpn <= c.a_new_request_vpn when '1',
r.b_request_vpn when '0',
(others => 'X') when others;
c.a_request_ppn <= c.b_request_ppn;
c.a_request_paddr <= c.a_request_ppn & c.a_request_poffset;
c.a_request_tag <= c.a_request_paddr(cpu_ipaddr_bits-1 downto
cpu_l1mem_inst_cache_index_bits+cpu_l1mem_inst_cache_offset_bits);
c.a_request_index <= c.a_request_paddr(cpu_l1mem_inst_cache_index_bits+cpu_l1mem_inst_cache_offset_bits-1 downto
cpu_l1mem_inst_cache_offset_bits);
c.a_request_offset <= c.a_request_paddr(cpu_l1mem_inst_cache_offset_bits-1 downto 0);
--------------------------------
c.a_bus_op_dram_wdata <= sys_slave_dp_out.data;
a_bus_op_paddr_block_inst_offset_next_gen : if cpu_l1mem_inst_cache_offset_bits > 0 generate
c.a_bus_op_paddr_block_inst_offset_next <=
std_ulogic_vector(unsigned(r.b_bus_op_paddr(cpu_l1mem_inst_cache_offset_bits-1 downto 0)) +
to_unsigned(1, cpu_l1mem_inst_cache_offset_bits));
end generate;
with cpu_l1mem_inst_cache_dp_in_ctrl.a_bus_op_paddr_tag_sel select
c.a_bus_op_paddr(cpu_ipaddr_bits-1 downto cpu_l1mem_inst_cache_index_bits+cpu_l1mem_inst_cache_offset_bits) <=
c.a_request_tag when cpu_l1mem_inst_cache_a_bus_op_paddr_tag_sel_request,
c.b_bus_op_tag when cpu_l1mem_inst_cache_a_bus_op_paddr_tag_sel_old,
(others => 'X') when others;
with cpu_l1mem_inst_cache_dp_in_ctrl.a_bus_op_paddr_index_sel select
c.a_bus_op_paddr(cpu_l1mem_inst_cache_index_bits+cpu_l1mem_inst_cache_offset_bits-1 downto cpu_l1mem_inst_cache_offset_bits) <=
c.a_request_index when cpu_l1mem_inst_cache_a_bus_op_paddr_index_sel_request,
c.b_bus_op_index when cpu_l1mem_inst_cache_a_bus_op_paddr_index_sel_old,
(others => 'X') when others;
a_bus_op_paddr_block_inst_offset_gen : if cpu_l1mem_inst_cache_offset_bits > 0 generate
with cpu_l1mem_inst_cache_dp_in_ctrl.a_bus_op_paddr_offset_sel select
c.a_bus_op_paddr(cpu_l1mem_inst_cache_offset_bits-1 downto 0) <=
c.b_bus_op_offset(cpu_l1mem_inst_cache_offset_bits-1 downto 0)
when cpu_l1mem_inst_cache_a_bus_op_paddr_offset_sel_old,
c.a_bus_op_paddr_block_inst_offset_next when cpu_l1mem_inst_cache_a_bus_op_paddr_offset_sel_next,
c.a_request_offset(cpu_l1mem_inst_cache_offset_bits-1 downto 0)
when cpu_l1mem_inst_cache_a_bus_op_paddr_offset_sel_request,
(others => 'X') when others;
end generate;
c.a_bus_op_index <= c.a_bus_op_paddr(cpu_l1mem_inst_cache_index_bits+cpu_l1mem_inst_cache_offset_bits-1 downto
cpu_l1mem_inst_cache_offset_bits);
c.a_bus_op_offset <= c.a_bus_op_paddr(cpu_l1mem_inst_cache_offset_bits-1 downto 0);
c.a_bus_op_cache_wtag <= r.b_bus_op_paddr(cpu_ipaddr_bits-1 downto
cpu_l1mem_inst_cache_index_bits+cpu_l1mem_inst_cache_offset_bits);
with cpu_l1mem_inst_cache_dp_in_ctrl.a_bus_op_cache_paddr_sel_old select
c.a_bus_op_cache_index <=
c.a_bus_op_index when '0',
c.b_bus_op_index when '1',
(others => 'X') when others;
with cpu_l1mem_inst_cache_dp_in_ctrl.a_bus_op_cache_paddr_sel_old select
c.a_bus_op_cache_offset <=
c.a_bus_op_offset when '0',
c.b_bus_op_offset when '1',
(others => 'X') when others;
c.a_bus_op_sys_paddr <= c.a_bus_op_paddr;
--------------------------------
with cpu_l1mem_inst_cache_dp_in_ctrl.a_cache_owner select
c.a_cache_index <= c.a_request_index when cpu_l1mem_inst_cache_owner_request,
c.a_bus_op_cache_index when cpu_l1mem_inst_cache_owner_bus_op,
(others => 'X') when others;
with cpu_l1mem_inst_cache_dp_in_ctrl.a_cache_owner select
c.a_cache_offset <= c.a_request_paddr(cpu_l1mem_inst_cache_offset_bits-1 downto 0)
when cpu_l1mem_inst_cache_owner_request,
c.a_bus_op_cache_offset
when cpu_l1mem_inst_cache_owner_bus_op,
(others => 'X') when others;
c.a_vram_raddr <= c.a_cache_index;
c.a_tram_addr <= c.a_cache_index;
c.a_tram_wtag <= c.a_bus_op_cache_wtag;
a_tram_wdata_gen : for n in cpu_l1mem_inst_cache_assoc-1 downto 0 generate
bit_gen : for b in cpu_l1mem_inst_cache_tag_bits-1 downto 0 generate
c.a_tram_wdata(n, b) <= c.a_tram_wtag(b);
end generate;
end generate;
c.a_replace_rindex <= c.a_cache_index;
c.a_dram_addr <= c.a_cache_index & c.a_cache_offset;
with cpu_l1mem_inst_cache_dp_in_ctrl.a_cache_owner select
c.a_dram_wdata_inst <= c.a_bus_op_dram_wdata when cpu_l1mem_inst_cache_owner_bus_op,
(others => 'X') when others;
a_dram_wdata_gen : for n in cpu_l1mem_inst_cache_assoc-1 downto 0 generate
bit_loop : for b in cpu_inst_bits-1 downto 0 generate
c.a_dram_wdata(n, b) <= c.a_dram_wdata_inst(b);
end generate;
end generate;
c.a_sys_size <= std_ulogic_vector(to_unsigned(cpu_log2_inst_bytes, sys_transfer_size_bits));
c.a_sys_paddr <= (sys_paddr_bits-1 downto cpu_paddr_bits => '0') & c.a_bus_op_sys_paddr & (cpu_log2_inst_bytes-1 downto 0 => '0');
c.b_result_paddr <= r.b_bus_op_paddr;
r_next <= (
b_request_poffset => c.a_request_poffset,
b_request_vpn => c.a_request_vpn,
b_bus_op_paddr => c.a_bus_op_paddr
);
cpu_l1mem_inst_cache_dp_out_ctrl <= (
b_request_last_in_block => c.b_request_last_in_block,
b_request_cache_tag_match => c.b_request_cache_tag_match
);
cpu_l1mem_inst_cache_dp_out_vram <= (
raddr => c.a_vram_raddr,
waddr => c.b_vram_waddr
);
cpu_l1mem_inst_cache_dp_out_tram <= (
addr => c.a_tram_addr,
wdata => c.a_tram_wdata
);
cpu_l1mem_inst_cache_dp_out_dram <= (
addr => c.a_dram_addr,
wdata => c.a_dram_wdata
);
cpu_l1mem_inst_cache_replace_dp_in <= (
rindex => c.a_replace_rindex,
windex => c.b_replace_windex,
wstate => c.b_replace_wstate
);
cpu_l1mem_inst_cache_dp_out <= (
paddr => c.b_result_paddr,
data => c.b_result_inst
);
cpu_mmu_inst_dp_in <= (
vpn => c.a_request_vpn
);
sys_master_dp_out <= (
size => c.a_sys_size,
paddr => c.a_sys_paddr,
data => (others => 'X')
);
process (clk) is
begin
if rising_edge(clk) then
r <= r_next;
end if;
end process;
end;
|
-- test2 - clock divider controlled by quadrature decoder
-- Written in 2016 by <Ahmet Inan> <[email protected]>
-- To the extent possible under law, the author(s) have dedicated all copyright and related and neighboring rights to this software to the public domain worldwide. This software is distributed without any warranty.
-- You should have received a copy of the CC0 Public Domain Dedication along with this software. If not, see <http://creativecommons.org/publicdomain/zero/1.0/>.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test2 is
generic (
NUM_LEDS : positive := 5
);
port (
clock : in std_logic;
reset : in std_logic;
rotary : in std_logic_vector (1 downto 0);
leds : out std_logic_vector (NUM_LEDS-1 downto 0);
dclock : out std_logic
);
end test2;
architecture rtl of test2 is
signal pulse : std_logic;
signal direction : std_logic;
signal divided : std_logic;
signal divider : integer range 0 to 2**NUM_LEDS-1 := 0;
signal counter : integer range 0 to 2**NUM_LEDS-1 := 0;
begin
leds <= std_logic_vector(to_unsigned(divider, NUM_LEDS));
dclock <= divided;
quadrature_decoder_inst: entity work.quadrature_decoder
port map (clock, rotary, direction, pulse);
process (reset, clock)
begin
if reset = '1' then
counter <= 0;
divided <= '0';
elsif rising_edge(clock) then
if counter = 0 then
counter <= divider;
divided <= not divided;
else
counter <= counter - 1;
end if;
end if;
end process;
process (reset, pulse)
begin
if reset = '1' then
divider <= 0;
elsif rising_edge(pulse) then
if direction = '0' then
divider <= divider + 1;
else
divider <= divider - 1;
end if;
end if;
end process;
end rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library IEEE;
use IEEE.STD_LOGIC_TEXTIO.all;
use STD.TEXTIO.all;
entity Task2_ent_tb2 is
end entity Task2_ent_tb2;
architecture Task2_arch_tb2 of Task2_ent_tb2 is
constant delay_wr_in : Time := 5 ns;
constant delay_pos_edge : Time := 5 ns;
constant delay_wr_out : Time := 5 ns;
constant delay_neg_edge : Time := 5 ns;
file RESULTS : Text open WRITE_MODE is "results.txt";
procedure WRITE_RESULTS(
constant CLK : in Std_logic;
constant RST : in Std_logic;
constant IP : in Std_logic_Vector (3 downto 0);
constant OP : in Std_logic_Vector (1 downto 0)
) is
variable l_out : Line;
begin
WRITE(l_out, now, right, 15, ps);
-- write input signals
WRITE(l_out, CLK, right, 8);
WRITE(l_out, RST, right, 8);
WRITE(l_out, IP, right, 11);
-- write output signals
WRITE(l_out, OP, right, 9);
WRITELINE(RESULTS, l_out);
end;
component Task2 is
port(
CLK : in Std_logic;
RST : in Std_logic;
IP : in Std_logic_Vector (3 downto 0);
OP :out Std_logic_Vector (1 downto 0));
end component; -- Task2;
signal CLK : Std_logic;
signal RST : Std_logic;
signal IP : Std_logic_Vector (3 downto 0);
signal OP : Std_logic_Vector (1 downto 0);
signal cycle_num : Integer; -- takt number
-- this signal is added for compare test simulation results only
type test_state_type is (S0, S1, S2, S3, S4, any_state);
signal test_state : test_state_type;
begin
UUT : Task2
port map(
CLK => CLK,
RST => RST,
IP => IP,
OP => OP);
STIMULI : process
begin
-- Test for all transition of finite state machine
CLK <= '0';
cycle_num <= 0;
wait for delay_wr_in;
RST <= '1';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 1;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 2;
wait for delay_wr_in;
RST <= '0';
IP <= "0011";
wait for delay_pos_edge;
test_state <= S1;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S1
CLK <= '0';
cycle_num <= 3;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S1;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S1
CLK <= '0';
cycle_num <= 4;
wait for delay_wr_in;
RST <= '0';
IP <= "1111";
wait for delay_pos_edge;
test_state <= S2;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S2
CLK <= '0';
cycle_num <= 5;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S2;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S2
CLK <= '0';
cycle_num <= 6;
wait for delay_wr_in;
RST <= '0';
IP <= "1100";
wait for delay_pos_edge;
test_state <= S3;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S3
CLK <= '0';
cycle_num <= 7;
wait for delay_wr_in;
RST <= '0';
IP <= "0001";
wait for delay_pos_edge;
test_state <= S3;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S3
CLK <= '0';
cycle_num <= 8;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
CLK <= '0';
cycle_num <= 9;
wait for delay_wr_in;
RST <= '0';
wait for delay_pos_edge;
test_state <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
-- Test length 10
wait; -- stop simulation
end process; -- STIMULI;
WRITE_RESULTS(CLK,RST,IP,OP);
end architecture Task2_arch_tb2;
configuration Task2_cfg_tb2 of Task2_ent_tb2 is
for Task2_arch_tb2
for UUT : Task2 use entity work.Task2(Beh);
end for;
end for;
end Task2_cfg_tb2;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc170.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b03x01p03n01i00170ent IS
END c04s03b03x01p03n01i00170ent;
ARCHITECTURE c04s03b03x01p03n01i00170arch OF c04s03b03x01p03n01i00170ent IS
type x is range 1 to 10;
signal Addr : bit;
alias SIGN1 : x is x; -- fails_here
alias SIGN2 : bit is Addr;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST:c04s03b03x01p03n01i00170 - The name referred to in the alias declaration for SIGN1 is not a static name that refers to an object."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b03x01p03n01i00170arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc170.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b03x01p03n01i00170ent IS
END c04s03b03x01p03n01i00170ent;
ARCHITECTURE c04s03b03x01p03n01i00170arch OF c04s03b03x01p03n01i00170ent IS
type x is range 1 to 10;
signal Addr : bit;
alias SIGN1 : x is x; -- fails_here
alias SIGN2 : bit is Addr;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST:c04s03b03x01p03n01i00170 - The name referred to in the alias declaration for SIGN1 is not a static name that refers to an object."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b03x01p03n01i00170arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc170.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b03x01p03n01i00170ent IS
END c04s03b03x01p03n01i00170ent;
ARCHITECTURE c04s03b03x01p03n01i00170arch OF c04s03b03x01p03n01i00170ent IS
type x is range 1 to 10;
signal Addr : bit;
alias SIGN1 : x is x; -- fails_here
alias SIGN2 : bit is Addr;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST:c04s03b03x01p03n01i00170 - The name referred to in the alias declaration for SIGN1 is not a static name that refers to an object."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b03x01p03n01i00170arch;
|
-------------------------------------------------------------------------------
-- Copyright Institut Pascal Equipe Dream (19-10-2016)
-- Francois Berry, El Mehdi Abdali, Maxime Pelcat
-- This software is a computer program whose purpose is to manage dynamic
-- partial reconfiguration.
-- This software is governed by the CeCILL-C license under French law and
-- abiding by the rules of distribution of free software. You can use,
-- modify and/ or redistribute the software under the terms of the CeCILL-C
-- license as circulated by CEA, CNRS and INRIA at the following URL
-- "http://www.cecill.info".
-- As a counterpart to the access to the source code and rights to copy,
-- modify and redistribute granted by the license, users are provided only
-- with a limited warranty and the software's author, the holder of the
-- economic rights, and the successive licensors have only limited
-- liability.
-- In this respect, the user's attention is drawn to the risks associated
-- with loading, using, modifying and/or developing or reproducing the
-- software by the user in light of its specific status of free software,
-- that may mean that it is complicated to manipulate, and that also
-- therefore means that it is reserved for developers and experienced
-- professionals having in-depth computer knowledge. Users are therefore
-- encouraged to load and test the software's suitability as regards their
-- requirements in conditions enabling the security of their systems and/or
-- data to be ensured and, more generally, to use and operate it in the
-- same conditions as regards security.
-- The fact that you are presently reading this means that you have had
-- knowledge of the CeCILL-C license and that you accept its terms.
-------------------------------------------------------------------------------
-- Doxygen Comments -----------------------------------------------------------
--! @file generic_window_extractor.vhd
--
--! @brief generic window extractor
--! @author Francois Berry, El Mehdi Abdali, Maxime Pelcat
--! @board SoCKit from Arrow and Terasic
--! @version 1.0
--! @date 11/01/2017
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library std;
library altera_mf;
use work.window_extractor_pkg.all;
entity generic_window_extractor is
generic
(
line_width_max : integer;
pix_width : integer;
matrix_width : integer
);
port
(
clk : in std_logic;
reset_n : in std_logic;
--/* input flow */
in_data : in std_logic_vector((pix_width-1) downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
out_fv : out std_logic;
out_dv : out std_logic;
widthimg_i : in std_logic_vector(15 downto 0);
pixel_window : out generic_pixel_window(0 to matrix_width-1, 0 to matrix_width-1)(pix_width-1 downto 0)
);
end generic_window_extractor;
architecture arch of generic_window_extractor is
type pix_out_signal is array (0 to matrix_width-2) of std_logic_vector((pix_width-1) downto 0);
constant FIFO_LENGHT : integer := line_width_max;
constant FIFO_LENGHT_WIDTH : integer := integer(ceil(log2(real(FIFO_LENGHT))));
signal widthimg_temp : std_logic_vector(15 downto 0):=widthimg_i;
signal sig_rdreq : std_logic := '0';
signal line_pix_out : generic_pixel_line(0 to matrix_width-1)(pix_width-1 downto 0);
shared variable param_changing_reset : std_logic := '0';
shared variable aclr : std_logic := '0';
shared variable pixel_matrix_kernel : generic_pixel_window(0 to matrix_width-1, 0 to matrix_width-1)(pix_width-1 downto 0);
component scfifo
generic
(
LPM_WIDTH : positive;
LPM_WIDTHU : positive;
LPM_NUMWORDS : positive;
LPM_SHOWAHEAD : string := "OFF";
ALLOW_RWCYCLE_WHEN_FULL : string := "OFF";
OVERFLOW_CHECKING : string := "ON";
UNDERFLOW_CHECKING : string := "ON"
);
port
(
data : in std_logic_vector(LPM_WIDTH-1 downto 0);
clock,
wrreq,
rdreq,
aclr : in std_logic;
full,
empty,
almost_full,
almost_empty : out std_logic;
q : out std_logic_vector(LPM_WIDTH-1 downto 0);
usedw : out std_logic_vector(LPM_WIDTHU-1 downto 0)
);
end component;
begin
--/* generating the matrix_width-1 line buffers */
G_1 : for i in 0 to matrix_width-2 generate
line_fifo_inst : scfifo
generic map
(
LPM_WIDTH => pix_width,
LPM_WIDTHU => FIFO_LENGHT_WIDTH,
LPM_NUMWORDS => FIFO_LENGHT
)
port map
(
data => pixel_matrix_kernel(i+1,0),
clock => clk,
wrreq => in_dv,
q => line_pix_out(i),
rdreq => sig_rdreq and in_dv,
aclr => param_changing_reset or(not(reset_n))
);
end generate;
process (clk, reset_n)
variable counter :integer:=0;
begin
if(reset_n='0') then
elsif(rising_edge(clk)) then
out_fv <= in_fv;
out_dv <= in_dv;
if(in_fv='0') then
elsif(in_dv='1') then
counter:=counter+1;
if(counter=(unsigned(widthimg_i)-matrix_width-1)) then
sig_rdreq <= '1';
end if;
--/* updating the matrix */
for o in 0 to matrix_width-1 loop
for p in 0 to matrix_width-2 loop
pixel_matrix_kernel(o,p):=pixel_matrix_kernel(o,p+1);
end loop;
if (o<matrix_width-1) then
pixel_matrix_kernel(o,matrix_width-1):=line_pix_out(o);
end if;
end loop;
pixel_matrix_kernel(matrix_width-1,matrix_width-1):=in_data;
else
end if;
--/* fifo reset when widthimg_i changes */
if (unsigned(widthimg_i)=unsigned(widthimg_temp)) then
param_changing_reset := '0';
else
param_changing_reset := '1';
counter := 0;
sig_rdreq <= '0';
end if;
widthimg_temp<=widthimg_i;
else
end if;
end process;
pixel_window <= pixel_matrix_kernel;
end arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity top is
port (
MOSI_ext : out std_logic;
CSB_ext : out std_logic
);
end top;
architecture Behavioral of top is
signal CAPTURE: std_logic;
signal UPDATE: std_logic;
signal DRCK1: std_logic;
signal TDI: std_logic;
signal TDO1: std_logic;
signal CSB: std_logic := '1';
signal header: std_logic_vector(47 downto 0);
signal len: std_logic_vector(15 downto 0);
signal have_header : std_logic := '0';
signal MISO: std_logic;
signal MOSI: std_logic;
signal SEL1: std_logic;
signal SHIFT: std_logic;
signal RESET: std_logic;
signal CS_GO: std_logic := '0';
signal CS_GO_PREP: std_logic := '0';
signal CS_STOP: std_logic := '0';
signal CS_STOP_PREP: std_logic := '0';
signal RAM_RADDR: std_logic_vector(13 downto 0);
signal RAM_WADDR: std_logic_vector(13 downto 0);
signal DRCK1_INV : std_logic;
signal RAM_DO: std_logic_vector(0 downto 0);
signal RAM_DI: std_logic_vector(0 downto 0);
signal RAM_WE: std_logic := '0';
begin
MOSI_ext <= MOSI;
CSB_ext <= CSB;
DRCK1_INV <= not DRCK1;
RAMB16_S1_S1_inst : RAMB16_S1_S1
port map (
DOA => RAM_DO, -- Port A 1-bit Data Output
DOB => open, -- Port B 1-bit Data Output
ADDRA => RAM_RADDR, -- Port A 14-bit Address Input
ADDRB => RAM_WADDR, -- Port B 14-bit Address Input
CLKA => DRCK1_inv, -- Port A Clock
CLKB => DRCK1, -- Port B Clock
DIA => "0", -- Port A 1-bit Data Input
DIB => RAM_DI, -- Port B 1-bit Data Input
ENA => '1', -- Port A RAM Enable Input
ENB => '1', -- PortB RAM Enable Input
SSRA => '0', -- Port A Synchronous Set/Reset Input
SSRB => '0', -- Port B Synchronous Set/Reset Input
WEA => '0', -- Port A Write Enable Input
WEB => RAM_WE -- Port B Write Enable Input
);
BSCAN_VIRTEX5_inst : BSCAN_VIRTEX5
generic map (
JTAG_CHAIN => 1 -- Value for USER command. Possible values: (1,2,3 or 4)
)
port map (
CAPTURE => CAPTURE, -- CAPTURE output from TAP controller
DRCK => DRCK1, -- Data register output for USER functions
RESET => RESET, -- Reset output from TAP controller
SEL => SEL1, -- USER active output
SHIFT => SHIFT, -- SHIFT output from TAP controller
TDI => TDI, -- TDI output from TAP controller
UPDATE => UPDATE, -- UPDATE output from TAP controller
TDO => TDO1 -- Data input for USER function
);
-- see XAPP1020
STARTUP_VIRTEX5_inst : STARTUP_VIRTEX5
port map (
CFGCLK => open, -- Config logic clock 1-bit output
CFGMCLK => open, -- Config internal osc clock 1-bit output
DINSPI => MISO, -- DIN SPI PROM access 1-bit output
EOS => open, -- End of Startup 1-bit output
TCKSPI => open, -- TCK SPI PROM access 1-bit output
CLK => open, -- Clock input for start-up sequence
GSR => '0', -- Global Set/Reset input (GSR cannot be used for the port name)
GTS => '0', -- Global 3-state input (GTS cannot be used for the port name)
USRCCLKO => DRCK1, -- User CCLK 1-bit input
USRCCLKTS => '0', -- User CCLK 3-state, 1-bit input
USRDONEO => open, -- User Done 1-bit input
USRDONETS => open -- User Done 3-state, 1-bit input
);
MOSI <= TDI;
CSB <= '0' when CS_GO = '1' and CS_STOP = '0' else '1';
RAM_DI <= MISO & "";
TDO1 <= RAM_DO(0);
-- falling edges
process(DRCK1, CAPTURE, RESET, UPDATE, SEL1)
begin
if CAPTURE = '1' or RESET='1' or UPDATE='1' or SEL1='0' then
have_header <= '0';
-- disable CSB
CS_GO_PREP <= '0';
CS_STOP <= '0';
elsif falling_edge(DRCK1) then
-- disable CSB?
CS_STOP <= CS_STOP_PREP;
-- waiting for header?
if have_header='0' then
-- got magic + len
if header(46 downto 15) = x"59a659a6" then
len <= header(14 downto 0) & "0";
have_header <= '1';
-- enable CSB on rising edge (if len > 0?)
if (header(14 downto 0) & "0") /= x"0000" then
CS_GO_PREP <= '1';
end if;
end if;
elsif len /= x"0000" then
len <= len - 1;
end if;
end if;
end process;
-- rising edges
process(DRCK1, CAPTURE, RESET, UPDATE, SEL1)
begin
if CAPTURE = '1' or RESET='1' or UPDATE='1' or SEL1='0' then
-- disable CSB
CS_GO <= '0';
CS_STOP_PREP <= '0';
RAM_WADDR <= (others => '0');
RAM_RADDR <= (others => '0');
RAM_WE <= '0';
elsif rising_edge(DRCK1) then
RAM_RADDR <= RAM_RADDR + 1;
RAM_WE <= not CSB;
if RAM_WE='1' then
RAM_WADDR <= RAM_WADDR + 1;
end if;
header <= header(46 downto 0) & TDI;
-- enable CSB?
CS_GO <= CS_GO_PREP;
-- disable CSB on falling edge
if CS_GO = '1' and len = x"0000" then
CS_STOP_PREP <= '1';
end if;
end if;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity top is
port (
MOSI_ext : out std_logic;
CSB_ext : out std_logic
);
end top;
architecture Behavioral of top is
signal CAPTURE: std_logic;
signal UPDATE: std_logic;
signal DRCK1: std_logic;
signal TDI: std_logic;
signal TDO1: std_logic;
signal CSB: std_logic := '1';
signal header: std_logic_vector(47 downto 0);
signal len: std_logic_vector(15 downto 0);
signal have_header : std_logic := '0';
signal MISO: std_logic;
signal MOSI: std_logic;
signal SEL1: std_logic;
signal SHIFT: std_logic;
signal RESET: std_logic;
signal CS_GO: std_logic := '0';
signal CS_GO_PREP: std_logic := '0';
signal CS_STOP: std_logic := '0';
signal CS_STOP_PREP: std_logic := '0';
signal RAM_RADDR: std_logic_vector(13 downto 0);
signal RAM_WADDR: std_logic_vector(13 downto 0);
signal DRCK1_INV : std_logic;
signal RAM_DO: std_logic_vector(0 downto 0);
signal RAM_DI: std_logic_vector(0 downto 0);
signal RAM_WE: std_logic := '0';
begin
MOSI_ext <= MOSI;
CSB_ext <= CSB;
DRCK1_INV <= not DRCK1;
RAMB16_S1_S1_inst : RAMB16_S1_S1
port map (
DOA => RAM_DO, -- Port A 1-bit Data Output
DOB => open, -- Port B 1-bit Data Output
ADDRA => RAM_RADDR, -- Port A 14-bit Address Input
ADDRB => RAM_WADDR, -- Port B 14-bit Address Input
CLKA => DRCK1_inv, -- Port A Clock
CLKB => DRCK1, -- Port B Clock
DIA => "0", -- Port A 1-bit Data Input
DIB => RAM_DI, -- Port B 1-bit Data Input
ENA => '1', -- Port A RAM Enable Input
ENB => '1', -- PortB RAM Enable Input
SSRA => '0', -- Port A Synchronous Set/Reset Input
SSRB => '0', -- Port B Synchronous Set/Reset Input
WEA => '0', -- Port A Write Enable Input
WEB => RAM_WE -- Port B Write Enable Input
);
BSCAN_VIRTEX5_inst : BSCAN_VIRTEX5
generic map (
JTAG_CHAIN => 1 -- Value for USER command. Possible values: (1,2,3 or 4)
)
port map (
CAPTURE => CAPTURE, -- CAPTURE output from TAP controller
DRCK => DRCK1, -- Data register output for USER functions
RESET => RESET, -- Reset output from TAP controller
SEL => SEL1, -- USER active output
SHIFT => SHIFT, -- SHIFT output from TAP controller
TDI => TDI, -- TDI output from TAP controller
UPDATE => UPDATE, -- UPDATE output from TAP controller
TDO => TDO1 -- Data input for USER function
);
-- see XAPP1020
STARTUP_VIRTEX5_inst : STARTUP_VIRTEX5
port map (
CFGCLK => open, -- Config logic clock 1-bit output
CFGMCLK => open, -- Config internal osc clock 1-bit output
DINSPI => MISO, -- DIN SPI PROM access 1-bit output
EOS => open, -- End of Startup 1-bit output
TCKSPI => open, -- TCK SPI PROM access 1-bit output
CLK => open, -- Clock input for start-up sequence
GSR => '0', -- Global Set/Reset input (GSR cannot be used for the port name)
GTS => '0', -- Global 3-state input (GTS cannot be used for the port name)
USRCCLKO => DRCK1, -- User CCLK 1-bit input
USRCCLKTS => '0', -- User CCLK 3-state, 1-bit input
USRDONEO => open, -- User Done 1-bit input
USRDONETS => open -- User Done 3-state, 1-bit input
);
MOSI <= TDI;
CSB <= '0' when CS_GO = '1' and CS_STOP = '0' else '1';
RAM_DI <= MISO & "";
TDO1 <= RAM_DO(0);
-- falling edges
process(DRCK1, CAPTURE, RESET, UPDATE, SEL1)
begin
if CAPTURE = '1' or RESET='1' or UPDATE='1' or SEL1='0' then
have_header <= '0';
-- disable CSB
CS_GO_PREP <= '0';
CS_STOP <= '0';
elsif falling_edge(DRCK1) then
-- disable CSB?
CS_STOP <= CS_STOP_PREP;
-- waiting for header?
if have_header='0' then
-- got magic + len
if header(46 downto 15) = x"59a659a6" then
len <= header(14 downto 0) & "0";
have_header <= '1';
-- enable CSB on rising edge (if len > 0?)
if (header(14 downto 0) & "0") /= x"0000" then
CS_GO_PREP <= '1';
end if;
end if;
elsif len /= x"0000" then
len <= len - 1;
end if;
end if;
end process;
-- rising edges
process(DRCK1, CAPTURE, RESET, UPDATE, SEL1)
begin
if CAPTURE = '1' or RESET='1' or UPDATE='1' or SEL1='0' then
-- disable CSB
CS_GO <= '0';
CS_STOP_PREP <= '0';
RAM_WADDR <= (others => '0');
RAM_RADDR <= (others => '0');
RAM_WE <= '0';
elsif rising_edge(DRCK1) then
RAM_RADDR <= RAM_RADDR + 1;
RAM_WE <= not CSB;
if RAM_WE='1' then
RAM_WADDR <= RAM_WADDR + 1;
end if;
header <= header(46 downto 0) & TDI;
-- enable CSB?
CS_GO <= CS_GO_PREP;
-- disable CSB on falling edge
if CS_GO = '1' and len = x"0000" then
CS_STOP_PREP <= '1';
end if;
end if;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity top is
port (
MOSI_ext : out std_logic;
CSB_ext : out std_logic
);
end top;
architecture Behavioral of top is
signal CAPTURE: std_logic;
signal UPDATE: std_logic;
signal DRCK1: std_logic;
signal TDI: std_logic;
signal TDO1: std_logic;
signal CSB: std_logic := '1';
signal header: std_logic_vector(47 downto 0);
signal len: std_logic_vector(15 downto 0);
signal have_header : std_logic := '0';
signal MISO: std_logic;
signal MOSI: std_logic;
signal SEL1: std_logic;
signal SHIFT: std_logic;
signal RESET: std_logic;
signal CS_GO: std_logic := '0';
signal CS_GO_PREP: std_logic := '0';
signal CS_STOP: std_logic := '0';
signal CS_STOP_PREP: std_logic := '0';
signal RAM_RADDR: std_logic_vector(13 downto 0);
signal RAM_WADDR: std_logic_vector(13 downto 0);
signal DRCK1_INV : std_logic;
signal RAM_DO: std_logic_vector(0 downto 0);
signal RAM_DI: std_logic_vector(0 downto 0);
signal RAM_WE: std_logic := '0';
begin
MOSI_ext <= MOSI;
CSB_ext <= CSB;
DRCK1_INV <= not DRCK1;
RAMB16_S1_S1_inst : RAMB16_S1_S1
port map (
DOA => RAM_DO, -- Port A 1-bit Data Output
DOB => open, -- Port B 1-bit Data Output
ADDRA => RAM_RADDR, -- Port A 14-bit Address Input
ADDRB => RAM_WADDR, -- Port B 14-bit Address Input
CLKA => DRCK1_inv, -- Port A Clock
CLKB => DRCK1, -- Port B Clock
DIA => "0", -- Port A 1-bit Data Input
DIB => RAM_DI, -- Port B 1-bit Data Input
ENA => '1', -- Port A RAM Enable Input
ENB => '1', -- PortB RAM Enable Input
SSRA => '0', -- Port A Synchronous Set/Reset Input
SSRB => '0', -- Port B Synchronous Set/Reset Input
WEA => '0', -- Port A Write Enable Input
WEB => RAM_WE -- Port B Write Enable Input
);
BSCAN_VIRTEX5_inst : BSCAN_VIRTEX5
generic map (
JTAG_CHAIN => 1 -- Value for USER command. Possible values: (1,2,3 or 4)
)
port map (
CAPTURE => CAPTURE, -- CAPTURE output from TAP controller
DRCK => DRCK1, -- Data register output for USER functions
RESET => RESET, -- Reset output from TAP controller
SEL => SEL1, -- USER active output
SHIFT => SHIFT, -- SHIFT output from TAP controller
TDI => TDI, -- TDI output from TAP controller
UPDATE => UPDATE, -- UPDATE output from TAP controller
TDO => TDO1 -- Data input for USER function
);
-- see XAPP1020
STARTUP_VIRTEX5_inst : STARTUP_VIRTEX5
port map (
CFGCLK => open, -- Config logic clock 1-bit output
CFGMCLK => open, -- Config internal osc clock 1-bit output
DINSPI => MISO, -- DIN SPI PROM access 1-bit output
EOS => open, -- End of Startup 1-bit output
TCKSPI => open, -- TCK SPI PROM access 1-bit output
CLK => open, -- Clock input for start-up sequence
GSR => '0', -- Global Set/Reset input (GSR cannot be used for the port name)
GTS => '0', -- Global 3-state input (GTS cannot be used for the port name)
USRCCLKO => DRCK1, -- User CCLK 1-bit input
USRCCLKTS => '0', -- User CCLK 3-state, 1-bit input
USRDONEO => open, -- User Done 1-bit input
USRDONETS => open -- User Done 3-state, 1-bit input
);
MOSI <= TDI;
CSB <= '0' when CS_GO = '1' and CS_STOP = '0' else '1';
RAM_DI <= MISO & "";
TDO1 <= RAM_DO(0);
-- falling edges
process(DRCK1, CAPTURE, RESET, UPDATE, SEL1)
begin
if CAPTURE = '1' or RESET='1' or UPDATE='1' or SEL1='0' then
have_header <= '0';
-- disable CSB
CS_GO_PREP <= '0';
CS_STOP <= '0';
elsif falling_edge(DRCK1) then
-- disable CSB?
CS_STOP <= CS_STOP_PREP;
-- waiting for header?
if have_header='0' then
-- got magic + len
if header(46 downto 15) = x"59a659a6" then
len <= header(14 downto 0) & "0";
have_header <= '1';
-- enable CSB on rising edge (if len > 0?)
if (header(14 downto 0) & "0") /= x"0000" then
CS_GO_PREP <= '1';
end if;
end if;
elsif len /= x"0000" then
len <= len - 1;
end if;
end if;
end process;
-- rising edges
process(DRCK1, CAPTURE, RESET, UPDATE, SEL1)
begin
if CAPTURE = '1' or RESET='1' or UPDATE='1' or SEL1='0' then
-- disable CSB
CS_GO <= '0';
CS_STOP_PREP <= '0';
RAM_WADDR <= (others => '0');
RAM_RADDR <= (others => '0');
RAM_WE <= '0';
elsif rising_edge(DRCK1) then
RAM_RADDR <= RAM_RADDR + 1;
RAM_WE <= not CSB;
if RAM_WE='1' then
RAM_WADDR <= RAM_WADDR + 1;
end if;
header <= header(46 downto 0) & TDI;
-- enable CSB?
CS_GO <= CS_GO_PREP;
-- disable CSB on falling edge
if CS_GO = '1' and len = x"0000" then
CS_STOP_PREP <= '1';
end if;
end if;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity top is
port (
MOSI_ext : out std_logic;
CSB_ext : out std_logic
);
end top;
architecture Behavioral of top is
signal CAPTURE: std_logic;
signal UPDATE: std_logic;
signal DRCK1: std_logic;
signal TDI: std_logic;
signal TDO1: std_logic;
signal CSB: std_logic := '1';
signal header: std_logic_vector(47 downto 0);
signal len: std_logic_vector(15 downto 0);
signal have_header : std_logic := '0';
signal MISO: std_logic;
signal MOSI: std_logic;
signal SEL1: std_logic;
signal SHIFT: std_logic;
signal RESET: std_logic;
signal CS_GO: std_logic := '0';
signal CS_GO_PREP: std_logic := '0';
signal CS_STOP: std_logic := '0';
signal CS_STOP_PREP: std_logic := '0';
signal RAM_RADDR: std_logic_vector(13 downto 0);
signal RAM_WADDR: std_logic_vector(13 downto 0);
signal DRCK1_INV : std_logic;
signal RAM_DO: std_logic_vector(0 downto 0);
signal RAM_DI: std_logic_vector(0 downto 0);
signal RAM_WE: std_logic := '0';
begin
MOSI_ext <= MOSI;
CSB_ext <= CSB;
DRCK1_INV <= not DRCK1;
RAMB16_S1_S1_inst : RAMB16_S1_S1
port map (
DOA => RAM_DO, -- Port A 1-bit Data Output
DOB => open, -- Port B 1-bit Data Output
ADDRA => RAM_RADDR, -- Port A 14-bit Address Input
ADDRB => RAM_WADDR, -- Port B 14-bit Address Input
CLKA => DRCK1_inv, -- Port A Clock
CLKB => DRCK1, -- Port B Clock
DIA => "0", -- Port A 1-bit Data Input
DIB => RAM_DI, -- Port B 1-bit Data Input
ENA => '1', -- Port A RAM Enable Input
ENB => '1', -- PortB RAM Enable Input
SSRA => '0', -- Port A Synchronous Set/Reset Input
SSRB => '0', -- Port B Synchronous Set/Reset Input
WEA => '0', -- Port A Write Enable Input
WEB => RAM_WE -- Port B Write Enable Input
);
BSCAN_VIRTEX5_inst : BSCAN_VIRTEX5
generic map (
JTAG_CHAIN => 1 -- Value for USER command. Possible values: (1,2,3 or 4)
)
port map (
CAPTURE => CAPTURE, -- CAPTURE output from TAP controller
DRCK => DRCK1, -- Data register output for USER functions
RESET => RESET, -- Reset output from TAP controller
SEL => SEL1, -- USER active output
SHIFT => SHIFT, -- SHIFT output from TAP controller
TDI => TDI, -- TDI output from TAP controller
UPDATE => UPDATE, -- UPDATE output from TAP controller
TDO => TDO1 -- Data input for USER function
);
-- see XAPP1020
STARTUP_VIRTEX5_inst : STARTUP_VIRTEX5
port map (
CFGCLK => open, -- Config logic clock 1-bit output
CFGMCLK => open, -- Config internal osc clock 1-bit output
DINSPI => MISO, -- DIN SPI PROM access 1-bit output
EOS => open, -- End of Startup 1-bit output
TCKSPI => open, -- TCK SPI PROM access 1-bit output
CLK => open, -- Clock input for start-up sequence
GSR => '0', -- Global Set/Reset input (GSR cannot be used for the port name)
GTS => '0', -- Global 3-state input (GTS cannot be used for the port name)
USRCCLKO => DRCK1, -- User CCLK 1-bit input
USRCCLKTS => '0', -- User CCLK 3-state, 1-bit input
USRDONEO => open, -- User Done 1-bit input
USRDONETS => open -- User Done 3-state, 1-bit input
);
MOSI <= TDI;
CSB <= '0' when CS_GO = '1' and CS_STOP = '0' else '1';
RAM_DI <= MISO & "";
TDO1 <= RAM_DO(0);
-- falling edges
process(DRCK1, CAPTURE, RESET, UPDATE, SEL1)
begin
if CAPTURE = '1' or RESET='1' or UPDATE='1' or SEL1='0' then
have_header <= '0';
-- disable CSB
CS_GO_PREP <= '0';
CS_STOP <= '0';
elsif falling_edge(DRCK1) then
-- disable CSB?
CS_STOP <= CS_STOP_PREP;
-- waiting for header?
if have_header='0' then
-- got magic + len
if header(46 downto 15) = x"59a659a6" then
len <= header(14 downto 0) & "0";
have_header <= '1';
-- enable CSB on rising edge (if len > 0?)
if (header(14 downto 0) & "0") /= x"0000" then
CS_GO_PREP <= '1';
end if;
end if;
elsif len /= x"0000" then
len <= len - 1;
end if;
end if;
end process;
-- rising edges
process(DRCK1, CAPTURE, RESET, UPDATE, SEL1)
begin
if CAPTURE = '1' or RESET='1' or UPDATE='1' or SEL1='0' then
-- disable CSB
CS_GO <= '0';
CS_STOP_PREP <= '0';
RAM_WADDR <= (others => '0');
RAM_RADDR <= (others => '0');
RAM_WE <= '0';
elsif rising_edge(DRCK1) then
RAM_RADDR <= RAM_RADDR + 1;
RAM_WE <= not CSB;
if RAM_WE='1' then
RAM_WADDR <= RAM_WADDR + 1;
end if;
header <= header(46 downto 0) & TDI;
-- enable CSB?
CS_GO <= CS_GO_PREP;
-- disable CSB on falling edge
if CS_GO = '1' and len = x"0000" then
CS_STOP_PREP <= '1';
end if;
end if;
end process;
end Behavioral;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_b_e
--
-- Generated
-- by: wig
-- on: Wed Apr 5 12:50:28 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_b_e-e.vhd,v 1.1 2006/04/10 15:42:11 wig Exp $
-- $Date: 2006/04/10 15:42:11 $
-- $Log: inst_b_e-e.vhd,v $
-- Revision 1.1 2006/04/10 15:42:11 wig
-- Updated testcase (__TOP__)
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_b_e
--
entity inst_b_e is
HOOK: global hook in entity
-- Generics:
-- No Generated Generics for Entity inst_b_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_b_e
p_mix_signal_aa_ba_gi : in std_ulogic;
p_mix_signal_bb_ab_go : out std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity inst_b_e
);
end inst_b_e;
--
-- End of Generated Entity inst_b_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
ENTITY repro1_ent IS
port( S : inout string := "abcdef");
END repro1_ent;
ARCHITECTURE repro1_arch OF repro1_ent IS
constant C : string := "abcdef";
BEGIN
assert S = C;
END repro1_arch;
|
ENTITY repro1_ent IS
port( S : inout string := "abcdef");
END repro1_ent;
ARCHITECTURE repro1_arch OF repro1_ent IS
constant C : string := "abcdef";
BEGIN
assert S = C;
END repro1_arch;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := inferred;
constant CFG_MEMTECH : integer := inferred;
constant CFG_PADTECH : integer := inferred;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := inferred;
constant CFG_CLKMUL : integer := 2;
constant CFG_CLKDIV : integer := 2;
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 0 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 0;
constant CFG_ITBSZ : integer := 0 + 64*0;
constant CFG_ATBSZ : integer := 0;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 0;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- PROM/SRAM controller
constant CFG_SRCTRL : integer := 0;
constant CFG_SRCTRL_PROMWS : integer := 0;
constant CFG_SRCTRL_RAMWS : integer := 0;
constant CFG_SRCTRL_IOWS : integer := 0;
constant CFG_SRCTRL_RMW : integer := 0;
constant CFG_SRCTRL_8BIT : integer := 0;
constant CFG_SRCTRL_SRBANKS : integer := 1;
constant CFG_SRCTRL_BANKSZ : integer := 0;
constant CFG_SRCTRL_ROMASEL : integer := 0;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 1 + 0;
-- SDRAM controller
constant CFG_SDCTRL : integer := 0;
constant CFG_SDCTRL_INVCLK : integer := 0;
constant CFG_SDCTRL_SD64 : integer := 0;
constant CFG_SDCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 0;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANLOOP : integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- GRPCI2 interface
constant CFG_GRPCI2_MASTER : integer := 0;
constant CFG_GRPCI2_TARGET : integer := 0;
constant CFG_GRPCI2_DMA : integer := 0;
constant CFG_GRPCI2_VID : integer := 16#0#;
constant CFG_GRPCI2_DID : integer := 16#0#;
constant CFG_GRPCI2_CLASS : integer := 16#0#;
constant CFG_GRPCI2_RID : integer := 16#0#;
constant CFG_GRPCI2_CAP : integer := 16#40#;
constant CFG_GRPCI2_NCAP : integer := 16#0#;
constant CFG_GRPCI2_BAR0 : integer := 0;
constant CFG_GRPCI2_BAR1 : integer := 0;
constant CFG_GRPCI2_BAR2 : integer := 0;
constant CFG_GRPCI2_BAR3 : integer := 0;
constant CFG_GRPCI2_BAR4 : integer := 0;
constant CFG_GRPCI2_BAR5 : integer := 0;
constant CFG_GRPCI2_FDEPTH : integer := 3;
constant CFG_GRPCI2_FCOUNT : integer := 2;
constant CFG_GRPCI2_ENDIAN : integer := 0;
constant CFG_GRPCI2_DEVINT : integer := 0;
constant CFG_GRPCI2_DEVINTMSK : integer := 16#0#;
constant CFG_GRPCI2_HOSTINT : integer := 0;
constant CFG_GRPCI2_HOSTINTMSK: integer := 16#0#;
constant CFG_GRPCI2_TRACE : integer := 0;
constant CFG_GRPCI2_TRACEAPB : integer := 0;
constant CFG_GRPCI2_BYPASS : integer := 0;
constant CFG_GRPCI2_EXTCFG : integer := (0);
-- PCI arbiter
constant CFG_PCI_ARB : integer := 0;
constant CFG_PCI_ARBAPB : integer := 0;
constant CFG_PCI_ARB_NGNT : integer := 4;
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 0;
constant CFG_UART2_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 1;
constant CFG_GPT_WDOG : integer := 16#FFFF#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
architecture RTL of FIFO is
begin
FOR_LABEL : for i in 0 to 7 generate
end generate FOR_LABEL;
IF_LABEL : if a = '1' generate
end generate IF_LABEL;
CASE_LABEL : case data generate
end generate CASE_LABEL;
-- Violations below
FOR_LABEL : for i in 0 to 7 generate end generate FOR_LABEL;
IF_LABEL : if a = '1' generate end generate IF_LABEL;
CASE_LABEL : case data generate end generate CASE_LABEL;
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06.03.2014 15:08:57
-- Design Name:
-- Module Name: top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.VHDL_lib.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top is
Port ( clk_raw : in STD_LOGIC;
leds : out STD_LOGIC_VECTOR (7 downto 0);
VGA_DATA : out STD_LOGIC_VECTOR (11 downto 0);
VGA_HSYNC : out STD_LOGIC;
VGA_VSYNC : out STD_LOGIC
);
end top;
architecture Behavioral of top is
constant horz : integer := 5;
signal clk_100MHz: std_logic;
signal clk_193MHz: std_logic;
signal clk_250MHz: std_logic;
signal hscnt: std_logic_vector(11 downto 0);
signal vscnt: std_logic_vector(11 downto 0);
signal data: std_logic_vector(11 downto 0):= (others=>'0');
signal addra: std_logic_vector(10 downto 0);
signal addrb: std_logic_vector(10 downto 0);
signal dina: std_logic_vector(15 downto 0);
signal doutb: std_logic_vector(15 downto 0);
component clk_base is
port (
clk_raw : in STD_LOGIC;
clk_250MHz : out STD_LOGIC;
clk_100MHz : out STD_LOGIC;
locked : out STD_LOGIC
);
end component;
component clk_video is
port (
clk_100MHz : in STD_LOGIC;
clk_193MHz : out STD_LOGIC;
locked : out STD_LOGIC
);
end component;
COMPONENT bram
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
begin
clk_base1: clk_base port map(clk_raw, clk_250MHz, clk_100MHz, leds(0));
clk_video1: clk_video port map(clk_100MHz, clk_193MHz, leds(1));
vga1: vga generic map(
Hsync=> 112,
Hact=> 1280,
Hfp=>48,
Hbp=>248,
Vsync=>3,
Vact=> 1024,
Vfp=> 1,
Vbp=> 38
) port map( clk_193MHz, hscnt,vscnt,VGA_HSYNC, VGA_VSYNC,open);
bram_disp : bram
PORT MAP (
clka => clk_250MHz,
wea => "1",
addra => addra,
dina => dina,
clkb => clk_193MHz,
addrb => addrb,
doutb => doutb
);
leds(7 downto 2) <= (others=>'0');
dina <= "00000"&addra;
addrb <= hscnt(10 downto 0);
process(clk_250MHz) begin
if(clk_250MHz'event and clk_250MHz='1')then
if(addra < 1024)then
addra <= addra+1;
else
addra <= (others=>'0');
end if;
end if;
end process;
process(clk_193MHz) begin
if(clk_193MHz'event and clk_193MHz='1')then
if( hscnt < 1280 and vscnt < 1024)then
VGA_DATA <= data;
else
VGA_DATA <= (others=>'0');
end if;
if (vscnt = 512)then
data <= X"07F";
elsif((hscnt = 0) or (hscnt = 128) or (hscnt = 256) or (hscnt = 384) or (hscnt = 512) or (hscnt = 640) or (hscnt = 768) or (hscnt = 896) or (hscnt = 1024) or (hscnt = 1152) or (hscnt = 1280-1)) then
data <= X"0F0";
elsif((vscnt = 0) or (vscnt = 128) or (vscnt = 256) or (vscnt = 384) or (vscnt = 640) or (vscnt = 768) or (vscnt = 896) or (vscnt = 1024-1)) then
data <= X"0F0";
else
if(doutb = 1023 - vscnt)then
data <= X"FFF";
else
data <= X"000";
end if;
end if;
end if;
end process;
end Behavioral;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 05:39:03 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../io.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-a.vhd,v 1.3 2006/06/26 07:42:19 wig Exp $
-- $Date: 2006/06/26 07:42:19 $
-- $Log: inst_t_e-rtl-a.vhd,v $
-- Revision 1.3 2006/06/26 07:42:19 wig
-- Updated io, generic and mde_tests testcases
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_t_e
--
architecture rtl of inst_t_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_a_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_a_e
p_mix_sig_in_01_gi : in std_ulogic;
p_mix_sig_in_03_gi : in std_ulogic_vector(7 downto 0);
p_mix_sig_io_05_gc : inout std_ulogic_vector(5 downto 0);
p_mix_sig_io_06_gc : inout std_ulogic_vector(6 downto 0);
p_mix_sig_out_02_go : out std_ulogic;
p_mix_sig_out_04_go : out std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity inst_a_e
);
end component;
-- ---------
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_a
inst_a: inst_a_e
port map (
p_mix_sig_in_01_gi => sig_in_01,
p_mix_sig_in_03_gi => sig_in_03,
p_mix_sig_io_05_gc => sig_io_05,
p_mix_sig_io_06_gc => sig_io_06,
p_mix_sig_out_02_go => sig_out_02,
p_mix_sig_out_04_go => sig_out_04
);
-- End of Generated Instance Port Map for inst_a
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
entity axi_adc_2c is
generic
(
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32;
C_CF_BUFTYPE : integer := 0;
C_IODELAY_GROUP : string := "adc_if_delay_group"
);
port
(
pid : in std_logic_vector(7 downto 0);
adc_clk_in_p : in std_logic;
adc_clk_in_n : in std_logic;
adc_data_in_p : in std_logic_vector(13 downto 0);
adc_data_in_n : in std_logic_vector(13 downto 0);
adc_data_or_p : in std_logic;
adc_data_or_n : in std_logic;
spi_cs0n : out std_logic;
spi_cs1n : out std_logic;
spi_clk : out std_logic;
spi_sdo : out std_logic;
spi_sdi : in std_logic;
delay_clk : in std_logic;
up_status : out std_logic_vector(7 downto 0);
up_adc_capture_int : out std_logic;
up_adc_capture_ext : in std_logic;
dma_dbg_data : out std_logic_vector(63 downto 0);
dma_dbg_trigger : out std_logic_vector(7 downto 0);
adc_clk : out std_logic;
adc_dbg_data : out std_logic_vector(63 downto 0);
adc_dbg_trigger : out std_logic_vector(7 downto 0);
adc_mon_valid : out std_logic;
adc_mon_data : out std_logic_vector(31 downto 0);
S_AXIS_S2MM_CLK : in std_logic;
S_AXIS_S2MM_TVALID : out std_logic;
S_AXIS_S2MM_TDATA : out std_logic_vector(63 downto 0);
S_AXIS_S2MM_TKEEP : out std_logic_vector(7 downto 0);
S_AXIS_S2MM_TLAST : out std_logic;
S_AXIS_S2MM_TREADY : in std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity axi_adc_2c;
architecture IMP of axi_adc_2c is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(ZERO_ADDR_PAD & USER_SLV_BASEADDR, ZERO_ADDR_PAD & USER_SLV_HIGHADDR);
constant USER_SLV_NUM_REG : integer := 32;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := (0 => (USER_SLV_NUM_REG));
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
component user_logic is
generic
(
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32;
C_CF_BUFTYPE : integer := 0;
C_IODELAY_GROUP : string := "adc_if_delay_group"
);
port
(
pid : in std_logic_vector(7 downto 0);
adc_clk_in_p : in std_logic;
adc_clk_in_n : in std_logic;
adc_data_in_p : in std_logic_vector(13 downto 0);
adc_data_in_n : in std_logic_vector(13 downto 0);
adc_data_or_p : in std_logic;
adc_data_or_n : in std_logic;
spi_cs0n : out std_logic;
spi_cs1n : out std_logic;
spi_clk : out std_logic;
spi_sd_o : out std_logic;
spi_sd_i : in std_logic;
dma_clk : in std_logic;
dma_valid : out std_logic;
dma_data : out std_logic_vector(63 downto 0);
dma_be : out std_logic_vector(7 downto 0);
dma_last : out std_logic;
dma_ready : in std_logic;
delay_clk : in std_logic;
up_status : out std_logic_vector(7 downto 0);
up_adc_capture_int : out std_logic;
up_adc_capture_ext : in std_logic;
dma_dbg_data : out std_logic_vector(63 downto 0);
dma_dbg_trigger : out std_logic_vector(7 downto 0);
adc_clk : out std_logic;
adc_dbg_data : out std_logic_vector(63 downto 0);
adc_dbg_trigger : out std_logic_vector(7 downto 0);
adc_mon_valid : out std_logic;
adc_mon_data : out std_logic_vector(31 downto 0);
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
);
end component user_logic;
begin
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
USER_LOGIC_I : component user_logic
generic map
(
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_CF_BUFTYPE => C_CF_BUFTYPE,
C_IODELAY_GROUP => C_IODELAY_GROUP
)
port map
(
pid => pid,
adc_clk_in_p => adc_clk_in_p,
adc_clk_in_n => adc_clk_in_n,
adc_data_in_p => adc_data_in_p,
adc_data_in_n => adc_data_in_n,
adc_data_or_p => adc_data_or_p,
adc_data_or_n => adc_data_or_n,
spi_cs0n => spi_cs0n,
spi_cs1n => spi_cs1n,
spi_clk => spi_clk,
spi_sd_o => spi_sdo,
spi_sd_i => spi_sdi,
dma_clk => S_AXIS_S2MM_CLK,
dma_valid => S_AXIS_S2MM_TVALID,
dma_data => S_AXIS_S2MM_TDATA,
dma_be => S_AXIS_S2MM_TKEEP,
dma_last => S_AXIS_S2MM_TLAST,
dma_ready => S_AXIS_S2MM_TREADY,
delay_clk => delay_clk,
up_status => up_status,
up_adc_capture_int => up_adc_capture_int,
up_adc_capture_ext => up_adc_capture_ext,
dma_dbg_data => dma_dbg_data,
dma_dbg_trigger => dma_dbg_trigger,
adc_clk => adc_clk,
adc_dbg_data => adc_dbg_data,
adc_dbg_trigger => adc_dbg_trigger,
adc_mon_valid => adc_mon_valid,
adc_mon_data => adc_mon_data,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
-- ***************************************************************************
-- ***************************************************************************
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_2;
USE floating_point_v7_1_2.floating_point_v7_1_2;
ENTITY frsqrt IS
PORT (
aclk : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END frsqrt;
ARCHITECTURE frsqrt_arch OF frsqrt IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF frsqrt_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_2 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_2;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_2
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 1,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 28,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 0,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => '0',
s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END frsqrt_arch;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY add_1bit_add_1bit_sch_tb IS
END add_1bit_add_1bit_sch_tb;
ARCHITECTURE behavioral OF add_1bit_add_1bit_sch_tb IS
COMPONENT add_1bit
PORT( Ak : IN STD_LOGIC;
Bk : IN STD_LOGIC;
Ck_1 : IN STD_LOGIC;
Sk : OUT STD_LOGIC;
Ck : OUT STD_LOGIC);
END COMPONENT;
SIGNAL Ak : STD_LOGIC;
SIGNAL Bk : STD_LOGIC;
SIGNAL Ck_1 : STD_LOGIC;
SIGNAL Sk : STD_LOGIC;
SIGNAL Ck : STD_LOGIC;
BEGIN
UUT: add_1bit PORT MAP(
Ak => Ak,
Bk => Bk,
Ck_1 => Ck_1,
Sk => Sk,
Ck => Ck
);
Ak <= '0', '0' after 20ns, '0' after 40ns, '0' after 60ns, '1' after 80ns, '1' after 100ns, '1' after 120ns, '1' after 140ns;
Bk <= '0', '0' after 20ns, '1' after 40ns, '1' after 60ns, '0' after 80ns, '0' after 100ns, '1' after 120ns, '1' after 140ns;
Ck_1 <= '0', '1' after 20ns, '0' after 40ns, '1' after 60ns, '0' after 80ns, '1' after 100ns, '0' after 120ns, '1' after 140ns;
END;
|
-------------------------------------------------------------------
-- System Generator version 11.1.00 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2007 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity plbaddrpref is
generic (
C_BASEADDR : std_logic_vector(31 downto 0) := X"80000000";
C_HIGHADDR : std_logic_vector(31 downto 0) := X"8000FFFF";
C_SPLB_DWIDTH : integer range 32 to 128 := 32;
C_SPLB_NATIVE_DWIDTH : integer range 32 to 32 := 32
);
port (
addrpref : out std_logic_vector(20-1 downto 0);
sl_rddbus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
plb_wrdbus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
sgsl_rddbus : in std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1);
sgplb_wrdbus : out std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1)
);
end plbaddrpref;
architecture behavior of plbaddrpref is
signal sl_rddbus_i : std_logic_vector(0 to C_SPLB_DWIDTH-1);
begin
addrpref <= C_BASEADDR(32-1 downto 12);
-------------------------------------------------------------------------------
-- Mux/Steer data/be's correctly for connect 32-bit slave to 128-bit plb
-------------------------------------------------------------------------------
GEN_128_TO_32_SLAVE : if C_SPLB_NATIVE_DWIDTH = 32 and C_SPLB_DWIDTH = 128 generate
begin
-----------------------------------------------------------------------
-- Map lower rd data to each quarter of the plb slave read bus
-----------------------------------------------------------------------
sl_rddbus_i(0 to 31) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(32 to 63) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(64 to 95) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(96 to 127) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
end generate GEN_128_TO_32_SLAVE;
-------------------------------------------------------------------------------
-- Mux/Steer data/be's correctly for connect 32-bit slave to 64-bit plb
-------------------------------------------------------------------------------
GEN_64_TO_32_SLAVE : if C_SPLB_NATIVE_DWIDTH = 32 and C_SPLB_DWIDTH = 64 generate
begin
---------------------------------------------------------------------------
-- Map lower rd data to upper and lower halves of plb slave read bus
---------------------------------------------------------------------------
sl_rddbus_i(0 to 31) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(32 to 63) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
end generate GEN_64_TO_32_SLAVE;
-------------------------------------------------------------------------------
-- IPIF DWidth = PLB DWidth
-- If IPIF Slave Data width is equal to the PLB Bus Data Width
-- Then BE and Read Data Bus map directly to eachother.
-------------------------------------------------------------------------------
GEN_FOR_EQUAL_SLAVE : if C_SPLB_NATIVE_DWIDTH = C_SPLB_DWIDTH generate
sl_rddbus_i <= sgsl_rddbus;
end generate GEN_FOR_EQUAL_SLAVE;
sl_rddbus <= sl_rddbus_i;
sgplb_wrdbus <= plb_wrdbus(0 to C_SPLB_NATIVE_DWIDTH-1);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity sg_2d_fir_plbw is
generic (
C_BASEADDR: std_logic_vector(31 downto 0) := X"80000000";
C_HIGHADDR: std_logic_vector(31 downto 0) := X"80000FFF";
C_SPLB_AWIDTH: integer := 0;
C_SPLB_DWIDTH: integer := 0;
C_SPLB_MID_WIDTH: integer := 0;
C_SPLB_NATIVE_DWIDTH: integer := 0;
C_SPLB_NUM_MASTERS: integer := 0;
C_SPLB_SUPPORT_BURSTS: integer := 0
);
port (
active_video_i: in std_logic;
hblank_i: in std_logic;
hsync_i: in std_logic;
plb_abus: in std_logic_vector(0 to 31);
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(0 to C_SPLB_DWIDTH-1);
reset: in std_logic;
splb_clk: in std_logic;
splb_rst: in std_logic;
sysgen_clk: in std_logic;
vblank_i: in std_logic;
video_data_i: in std_logic_vector(0 to 23);
vsync_i: in std_logic;
active_video_o: out std_logic;
hblank_o: out std_logic;
hsync_o: out std_logic;
sl_addrack: out std_logic;
sl_rdcomp: out std_logic;
sl_rddack: out std_logic;
sl_rddbus: out std_logic_vector(0 to C_SPLB_DWIDTH-1);
sl_wait: out std_logic;
sl_wrcomp: out std_logic;
sl_wrdack: out std_logic;
vblank_o: out std_logic;
video_data_o: out std_logic_vector(0 to 23);
vsync_o: out std_logic
);
end sg_2d_fir_plbw;
architecture structural of sg_2d_fir_plbw is
signal active_video_i_x0: std_logic;
signal active_video_o_x0: std_logic;
signal clk: std_logic;
signal hblank_i_x0: std_logic;
signal hblank_o_x0: std_logic;
signal hsync_i_x0: std_logic;
signal hsync_o_x0: std_logic;
signal plb_abus_x0: std_logic_vector(31 downto 0);
signal plb_pavalid_x0: std_logic;
signal plb_rnw_x0: std_logic;
signal plbaddrpref_addrpref_net: std_logic_vector(19 downto 0);
signal plbaddrpref_plb_wrdbus_net: std_logic_vector(C_SPLB_DWIDTH-1 downto 0);
signal plbaddrpref_sgplb_wrdbus_net: std_logic_vector(31 downto 0);
signal plbaddrpref_sgsl_rddbus_net: std_logic_vector(31 downto 0);
signal plbaddrpref_sl_rddbus_net: std_logic_vector(C_SPLB_DWIDTH-1 downto 0);
signal reset_x0: std_logic;
signal sl_addrack_x0: std_logic;
signal sl_rdcomp_x0: std_logic;
signal sl_rddack_x0: std_logic;
signal sl_wait_x0: std_logic;
signal sl_wrcomp_x0: std_logic;
signal sl_wrdack_x0: std_logic;
signal splb_rst_x0: std_logic;
signal vblank_i_x0: std_logic;
signal vblank_o_x0: std_logic;
signal video_data_i_x0: std_logic_vector(23 downto 0);
signal video_data_o_x0: std_logic_vector(23 downto 0);
signal vsync_i_x0: std_logic;
signal vsync_o_x0: std_logic;
signal xps_clk: std_logic;
begin
active_video_i_x0 <= active_video_i;
hblank_i_x0 <= hblank_i;
hsync_i_x0 <= hsync_i;
plb_abus_x0 <= plb_abus;
plb_pavalid_x0 <= plb_pavalid;
plb_rnw_x0 <= plb_rnw;
plbaddrpref_plb_wrdbus_net <= plb_wrdbus;
reset_x0 <= reset;
xps_clk <= splb_clk;
splb_rst_x0 <= splb_rst;
clk <= sysgen_clk;
vblank_i_x0 <= vblank_i;
video_data_i_x0 <= video_data_i;
vsync_i_x0 <= vsync_i;
active_video_o <= active_video_o_x0;
hblank_o <= hblank_o_x0;
hsync_o <= hsync_o_x0;
sl_addrack <= sl_addrack_x0;
sl_rdcomp <= sl_rdcomp_x0;
sl_rddack <= sl_rddack_x0;
sl_rddbus <= plbaddrpref_sl_rddbus_net;
sl_wait <= sl_wait_x0;
sl_wrcomp <= sl_wrcomp_x0;
sl_wrdack <= sl_wrdack_x0;
vblank_o <= vblank_o_x0;
video_data_o <= video_data_o_x0;
vsync_o <= vsync_o_x0;
plbaddrpref_x0: entity work.plbaddrpref
generic map (
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH
)
port map (
plb_wrdbus => plbaddrpref_plb_wrdbus_net,
sgsl_rddbus => plbaddrpref_sgsl_rddbus_net,
addrpref => plbaddrpref_addrpref_net,
sgplb_wrdbus => plbaddrpref_sgplb_wrdbus_net,
sl_rddbus => plbaddrpref_sl_rddbus_net
);
sysgen_dut: entity work.sg_2d_fir_cw
port map (
active_video_i => active_video_i_x0,
clk => clk,
hblank_i => hblank_i_x0,
hsync_i => hsync_i_x0,
plb_abus => plb_abus_x0,
plb_pavalid => plb_pavalid_x0,
plb_rnw => plb_rnw_x0,
plb_wrdbus => plbaddrpref_sgplb_wrdbus_net,
reset => reset_x0,
sg_plb_addrpref => plbaddrpref_addrpref_net,
splb_rst => splb_rst_x0,
vblank_i => vblank_i_x0,
video_data_i => video_data_i_x0,
vsync_i => vsync_i_x0,
xps_clk => xps_clk,
active_video_o => active_video_o_x0,
hblank_o => hblank_o_x0,
hsync_o => hsync_o_x0,
sl_addrack => sl_addrack_x0,
sl_rdcomp => sl_rdcomp_x0,
sl_rddack => sl_rddack_x0,
sl_rddbus => plbaddrpref_sgsl_rddbus_net,
sl_wait => sl_wait_x0,
sl_wrcomp => sl_wrcomp_x0,
sl_wrdack => sl_wrdack_x0,
vblank_o => vblank_o_x0,
video_data_o => video_data_o_x0,
vsync_o => vsync_o_x0
);
end structural;
|
-------------------------------------------------------------------
-- System Generator version 11.1.00 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2007 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity plbaddrpref is
generic (
C_BASEADDR : std_logic_vector(31 downto 0) := X"80000000";
C_HIGHADDR : std_logic_vector(31 downto 0) := X"8000FFFF";
C_SPLB_DWIDTH : integer range 32 to 128 := 32;
C_SPLB_NATIVE_DWIDTH : integer range 32 to 32 := 32
);
port (
addrpref : out std_logic_vector(20-1 downto 0);
sl_rddbus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
plb_wrdbus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
sgsl_rddbus : in std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1);
sgplb_wrdbus : out std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1)
);
end plbaddrpref;
architecture behavior of plbaddrpref is
signal sl_rddbus_i : std_logic_vector(0 to C_SPLB_DWIDTH-1);
begin
addrpref <= C_BASEADDR(32-1 downto 12);
-------------------------------------------------------------------------------
-- Mux/Steer data/be's correctly for connect 32-bit slave to 128-bit plb
-------------------------------------------------------------------------------
GEN_128_TO_32_SLAVE : if C_SPLB_NATIVE_DWIDTH = 32 and C_SPLB_DWIDTH = 128 generate
begin
-----------------------------------------------------------------------
-- Map lower rd data to each quarter of the plb slave read bus
-----------------------------------------------------------------------
sl_rddbus_i(0 to 31) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(32 to 63) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(64 to 95) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(96 to 127) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
end generate GEN_128_TO_32_SLAVE;
-------------------------------------------------------------------------------
-- Mux/Steer data/be's correctly for connect 32-bit slave to 64-bit plb
-------------------------------------------------------------------------------
GEN_64_TO_32_SLAVE : if C_SPLB_NATIVE_DWIDTH = 32 and C_SPLB_DWIDTH = 64 generate
begin
---------------------------------------------------------------------------
-- Map lower rd data to upper and lower halves of plb slave read bus
---------------------------------------------------------------------------
sl_rddbus_i(0 to 31) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(32 to 63) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
end generate GEN_64_TO_32_SLAVE;
-------------------------------------------------------------------------------
-- IPIF DWidth = PLB DWidth
-- If IPIF Slave Data width is equal to the PLB Bus Data Width
-- Then BE and Read Data Bus map directly to eachother.
-------------------------------------------------------------------------------
GEN_FOR_EQUAL_SLAVE : if C_SPLB_NATIVE_DWIDTH = C_SPLB_DWIDTH generate
sl_rddbus_i <= sgsl_rddbus;
end generate GEN_FOR_EQUAL_SLAVE;
sl_rddbus <= sl_rddbus_i;
sgplb_wrdbus <= plb_wrdbus(0 to C_SPLB_NATIVE_DWIDTH-1);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity sg_2d_fir_plbw is
generic (
C_BASEADDR: std_logic_vector(31 downto 0) := X"80000000";
C_HIGHADDR: std_logic_vector(31 downto 0) := X"80000FFF";
C_SPLB_AWIDTH: integer := 0;
C_SPLB_DWIDTH: integer := 0;
C_SPLB_MID_WIDTH: integer := 0;
C_SPLB_NATIVE_DWIDTH: integer := 0;
C_SPLB_NUM_MASTERS: integer := 0;
C_SPLB_SUPPORT_BURSTS: integer := 0
);
port (
active_video_i: in std_logic;
hblank_i: in std_logic;
hsync_i: in std_logic;
plb_abus: in std_logic_vector(0 to 31);
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(0 to C_SPLB_DWIDTH-1);
reset: in std_logic;
splb_clk: in std_logic;
splb_rst: in std_logic;
sysgen_clk: in std_logic;
vblank_i: in std_logic;
video_data_i: in std_logic_vector(0 to 23);
vsync_i: in std_logic;
active_video_o: out std_logic;
hblank_o: out std_logic;
hsync_o: out std_logic;
sl_addrack: out std_logic;
sl_rdcomp: out std_logic;
sl_rddack: out std_logic;
sl_rddbus: out std_logic_vector(0 to C_SPLB_DWIDTH-1);
sl_wait: out std_logic;
sl_wrcomp: out std_logic;
sl_wrdack: out std_logic;
vblank_o: out std_logic;
video_data_o: out std_logic_vector(0 to 23);
vsync_o: out std_logic
);
end sg_2d_fir_plbw;
architecture structural of sg_2d_fir_plbw is
signal active_video_i_x0: std_logic;
signal active_video_o_x0: std_logic;
signal clk: std_logic;
signal hblank_i_x0: std_logic;
signal hblank_o_x0: std_logic;
signal hsync_i_x0: std_logic;
signal hsync_o_x0: std_logic;
signal plb_abus_x0: std_logic_vector(31 downto 0);
signal plb_pavalid_x0: std_logic;
signal plb_rnw_x0: std_logic;
signal plbaddrpref_addrpref_net: std_logic_vector(19 downto 0);
signal plbaddrpref_plb_wrdbus_net: std_logic_vector(C_SPLB_DWIDTH-1 downto 0);
signal plbaddrpref_sgplb_wrdbus_net: std_logic_vector(31 downto 0);
signal plbaddrpref_sgsl_rddbus_net: std_logic_vector(31 downto 0);
signal plbaddrpref_sl_rddbus_net: std_logic_vector(C_SPLB_DWIDTH-1 downto 0);
signal reset_x0: std_logic;
signal sl_addrack_x0: std_logic;
signal sl_rdcomp_x0: std_logic;
signal sl_rddack_x0: std_logic;
signal sl_wait_x0: std_logic;
signal sl_wrcomp_x0: std_logic;
signal sl_wrdack_x0: std_logic;
signal splb_rst_x0: std_logic;
signal vblank_i_x0: std_logic;
signal vblank_o_x0: std_logic;
signal video_data_i_x0: std_logic_vector(23 downto 0);
signal video_data_o_x0: std_logic_vector(23 downto 0);
signal vsync_i_x0: std_logic;
signal vsync_o_x0: std_logic;
signal xps_clk: std_logic;
begin
active_video_i_x0 <= active_video_i;
hblank_i_x0 <= hblank_i;
hsync_i_x0 <= hsync_i;
plb_abus_x0 <= plb_abus;
plb_pavalid_x0 <= plb_pavalid;
plb_rnw_x0 <= plb_rnw;
plbaddrpref_plb_wrdbus_net <= plb_wrdbus;
reset_x0 <= reset;
xps_clk <= splb_clk;
splb_rst_x0 <= splb_rst;
clk <= sysgen_clk;
vblank_i_x0 <= vblank_i;
video_data_i_x0 <= video_data_i;
vsync_i_x0 <= vsync_i;
active_video_o <= active_video_o_x0;
hblank_o <= hblank_o_x0;
hsync_o <= hsync_o_x0;
sl_addrack <= sl_addrack_x0;
sl_rdcomp <= sl_rdcomp_x0;
sl_rddack <= sl_rddack_x0;
sl_rddbus <= plbaddrpref_sl_rddbus_net;
sl_wait <= sl_wait_x0;
sl_wrcomp <= sl_wrcomp_x0;
sl_wrdack <= sl_wrdack_x0;
vblank_o <= vblank_o_x0;
video_data_o <= video_data_o_x0;
vsync_o <= vsync_o_x0;
plbaddrpref_x0: entity work.plbaddrpref
generic map (
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH
)
port map (
plb_wrdbus => plbaddrpref_plb_wrdbus_net,
sgsl_rddbus => plbaddrpref_sgsl_rddbus_net,
addrpref => plbaddrpref_addrpref_net,
sgplb_wrdbus => plbaddrpref_sgplb_wrdbus_net,
sl_rddbus => plbaddrpref_sl_rddbus_net
);
sysgen_dut: entity work.sg_2d_fir_cw
port map (
active_video_i => active_video_i_x0,
clk => clk,
hblank_i => hblank_i_x0,
hsync_i => hsync_i_x0,
plb_abus => plb_abus_x0,
plb_pavalid => plb_pavalid_x0,
plb_rnw => plb_rnw_x0,
plb_wrdbus => plbaddrpref_sgplb_wrdbus_net,
reset => reset_x0,
sg_plb_addrpref => plbaddrpref_addrpref_net,
splb_rst => splb_rst_x0,
vblank_i => vblank_i_x0,
video_data_i => video_data_i_x0,
vsync_i => vsync_i_x0,
xps_clk => xps_clk,
active_video_o => active_video_o_x0,
hblank_o => hblank_o_x0,
hsync_o => hsync_o_x0,
sl_addrack => sl_addrack_x0,
sl_rdcomp => sl_rdcomp_x0,
sl_rddack => sl_rddack_x0,
sl_rddbus => plbaddrpref_sgsl_rddbus_net,
sl_wait => sl_wait_x0,
sl_wrcomp => sl_wrcomp_x0,
sl_wrdack => sl_wrdack_x0,
vblank_o => vblank_o_x0,
video_data_o => video_data_o_x0,
vsync_o => vsync_o_x0
);
end structural;
|
-------------------------------------------------------------------
-- System Generator version 11.1.00 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2007 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity plbaddrpref is
generic (
C_BASEADDR : std_logic_vector(31 downto 0) := X"80000000";
C_HIGHADDR : std_logic_vector(31 downto 0) := X"8000FFFF";
C_SPLB_DWIDTH : integer range 32 to 128 := 32;
C_SPLB_NATIVE_DWIDTH : integer range 32 to 32 := 32
);
port (
addrpref : out std_logic_vector(20-1 downto 0);
sl_rddbus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
plb_wrdbus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
sgsl_rddbus : in std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1);
sgplb_wrdbus : out std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1)
);
end plbaddrpref;
architecture behavior of plbaddrpref is
signal sl_rddbus_i : std_logic_vector(0 to C_SPLB_DWIDTH-1);
begin
addrpref <= C_BASEADDR(32-1 downto 12);
-------------------------------------------------------------------------------
-- Mux/Steer data/be's correctly for connect 32-bit slave to 128-bit plb
-------------------------------------------------------------------------------
GEN_128_TO_32_SLAVE : if C_SPLB_NATIVE_DWIDTH = 32 and C_SPLB_DWIDTH = 128 generate
begin
-----------------------------------------------------------------------
-- Map lower rd data to each quarter of the plb slave read bus
-----------------------------------------------------------------------
sl_rddbus_i(0 to 31) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(32 to 63) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(64 to 95) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(96 to 127) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
end generate GEN_128_TO_32_SLAVE;
-------------------------------------------------------------------------------
-- Mux/Steer data/be's correctly for connect 32-bit slave to 64-bit plb
-------------------------------------------------------------------------------
GEN_64_TO_32_SLAVE : if C_SPLB_NATIVE_DWIDTH = 32 and C_SPLB_DWIDTH = 64 generate
begin
---------------------------------------------------------------------------
-- Map lower rd data to upper and lower halves of plb slave read bus
---------------------------------------------------------------------------
sl_rddbus_i(0 to 31) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(32 to 63) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
end generate GEN_64_TO_32_SLAVE;
-------------------------------------------------------------------------------
-- IPIF DWidth = PLB DWidth
-- If IPIF Slave Data width is equal to the PLB Bus Data Width
-- Then BE and Read Data Bus map directly to eachother.
-------------------------------------------------------------------------------
GEN_FOR_EQUAL_SLAVE : if C_SPLB_NATIVE_DWIDTH = C_SPLB_DWIDTH generate
sl_rddbus_i <= sgsl_rddbus;
end generate GEN_FOR_EQUAL_SLAVE;
sl_rddbus <= sl_rddbus_i;
sgplb_wrdbus <= plb_wrdbus(0 to C_SPLB_NATIVE_DWIDTH-1);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity sg_2d_fir_plbw is
generic (
C_BASEADDR: std_logic_vector(31 downto 0) := X"80000000";
C_HIGHADDR: std_logic_vector(31 downto 0) := X"80000FFF";
C_SPLB_AWIDTH: integer := 0;
C_SPLB_DWIDTH: integer := 0;
C_SPLB_MID_WIDTH: integer := 0;
C_SPLB_NATIVE_DWIDTH: integer := 0;
C_SPLB_NUM_MASTERS: integer := 0;
C_SPLB_SUPPORT_BURSTS: integer := 0
);
port (
active_video_i: in std_logic;
hblank_i: in std_logic;
hsync_i: in std_logic;
plb_abus: in std_logic_vector(0 to 31);
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(0 to C_SPLB_DWIDTH-1);
reset: in std_logic;
splb_clk: in std_logic;
splb_rst: in std_logic;
sysgen_clk: in std_logic;
vblank_i: in std_logic;
video_data_i: in std_logic_vector(0 to 23);
vsync_i: in std_logic;
active_video_o: out std_logic;
hblank_o: out std_logic;
hsync_o: out std_logic;
sl_addrack: out std_logic;
sl_rdcomp: out std_logic;
sl_rddack: out std_logic;
sl_rddbus: out std_logic_vector(0 to C_SPLB_DWIDTH-1);
sl_wait: out std_logic;
sl_wrcomp: out std_logic;
sl_wrdack: out std_logic;
vblank_o: out std_logic;
video_data_o: out std_logic_vector(0 to 23);
vsync_o: out std_logic
);
end sg_2d_fir_plbw;
architecture structural of sg_2d_fir_plbw is
signal active_video_i_x0: std_logic;
signal active_video_o_x0: std_logic;
signal clk: std_logic;
signal hblank_i_x0: std_logic;
signal hblank_o_x0: std_logic;
signal hsync_i_x0: std_logic;
signal hsync_o_x0: std_logic;
signal plb_abus_x0: std_logic_vector(31 downto 0);
signal plb_pavalid_x0: std_logic;
signal plb_rnw_x0: std_logic;
signal plbaddrpref_addrpref_net: std_logic_vector(19 downto 0);
signal plbaddrpref_plb_wrdbus_net: std_logic_vector(C_SPLB_DWIDTH-1 downto 0);
signal plbaddrpref_sgplb_wrdbus_net: std_logic_vector(31 downto 0);
signal plbaddrpref_sgsl_rddbus_net: std_logic_vector(31 downto 0);
signal plbaddrpref_sl_rddbus_net: std_logic_vector(C_SPLB_DWIDTH-1 downto 0);
signal reset_x0: std_logic;
signal sl_addrack_x0: std_logic;
signal sl_rdcomp_x0: std_logic;
signal sl_rddack_x0: std_logic;
signal sl_wait_x0: std_logic;
signal sl_wrcomp_x0: std_logic;
signal sl_wrdack_x0: std_logic;
signal splb_rst_x0: std_logic;
signal vblank_i_x0: std_logic;
signal vblank_o_x0: std_logic;
signal video_data_i_x0: std_logic_vector(23 downto 0);
signal video_data_o_x0: std_logic_vector(23 downto 0);
signal vsync_i_x0: std_logic;
signal vsync_o_x0: std_logic;
signal xps_clk: std_logic;
begin
active_video_i_x0 <= active_video_i;
hblank_i_x0 <= hblank_i;
hsync_i_x0 <= hsync_i;
plb_abus_x0 <= plb_abus;
plb_pavalid_x0 <= plb_pavalid;
plb_rnw_x0 <= plb_rnw;
plbaddrpref_plb_wrdbus_net <= plb_wrdbus;
reset_x0 <= reset;
xps_clk <= splb_clk;
splb_rst_x0 <= splb_rst;
clk <= sysgen_clk;
vblank_i_x0 <= vblank_i;
video_data_i_x0 <= video_data_i;
vsync_i_x0 <= vsync_i;
active_video_o <= active_video_o_x0;
hblank_o <= hblank_o_x0;
hsync_o <= hsync_o_x0;
sl_addrack <= sl_addrack_x0;
sl_rdcomp <= sl_rdcomp_x0;
sl_rddack <= sl_rddack_x0;
sl_rddbus <= plbaddrpref_sl_rddbus_net;
sl_wait <= sl_wait_x0;
sl_wrcomp <= sl_wrcomp_x0;
sl_wrdack <= sl_wrdack_x0;
vblank_o <= vblank_o_x0;
video_data_o <= video_data_o_x0;
vsync_o <= vsync_o_x0;
plbaddrpref_x0: entity work.plbaddrpref
generic map (
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH
)
port map (
plb_wrdbus => plbaddrpref_plb_wrdbus_net,
sgsl_rddbus => plbaddrpref_sgsl_rddbus_net,
addrpref => plbaddrpref_addrpref_net,
sgplb_wrdbus => plbaddrpref_sgplb_wrdbus_net,
sl_rddbus => plbaddrpref_sl_rddbus_net
);
sysgen_dut: entity work.sg_2d_fir_cw
port map (
active_video_i => active_video_i_x0,
clk => clk,
hblank_i => hblank_i_x0,
hsync_i => hsync_i_x0,
plb_abus => plb_abus_x0,
plb_pavalid => plb_pavalid_x0,
plb_rnw => plb_rnw_x0,
plb_wrdbus => plbaddrpref_sgplb_wrdbus_net,
reset => reset_x0,
sg_plb_addrpref => plbaddrpref_addrpref_net,
splb_rst => splb_rst_x0,
vblank_i => vblank_i_x0,
video_data_i => video_data_i_x0,
vsync_i => vsync_i_x0,
xps_clk => xps_clk,
active_video_o => active_video_o_x0,
hblank_o => hblank_o_x0,
hsync_o => hsync_o_x0,
sl_addrack => sl_addrack_x0,
sl_rdcomp => sl_rdcomp_x0,
sl_rddack => sl_rddack_x0,
sl_rddbus => plbaddrpref_sgsl_rddbus_net,
sl_wait => sl_wait_x0,
sl_wrcomp => sl_wrcomp_x0,
sl_wrdack => sl_wrdack_x0,
vblank_o => vblank_o_x0,
video_data_o => video_data_o_x0,
vsync_o => vsync_o_x0
);
end structural;
|
entity issue110 is
end entity;
use std.textio.all;
architecture test of issue110 is
impure function write_func(x : integer) return integer is
variable l : line;
begin
write(l, x);
writeline(output, l);
return x;
end function;
procedure write_proc(x : integer) is
variable l : line;
begin
write(l, x);
writeline(output, l);
end procedure;
begin
process is
begin
assert write_func(4) = 4;
write_proc(5);
wait;
end process;
end architecture;
|
entity issue110 is
end entity;
use std.textio.all;
architecture test of issue110 is
impure function write_func(x : integer) return integer is
variable l : line;
begin
write(l, x);
writeline(output, l);
return x;
end function;
procedure write_proc(x : integer) is
variable l : line;
begin
write(l, x);
writeline(output, l);
end procedure;
begin
process is
begin
assert write_func(4) = 4;
write_proc(5);
wait;
end process;
end architecture;
|
entity issue110 is
end entity;
use std.textio.all;
architecture test of issue110 is
impure function write_func(x : integer) return integer is
variable l : line;
begin
write(l, x);
writeline(output, l);
return x;
end function;
procedure write_proc(x : integer) is
variable l : line;
begin
write(l, x);
writeline(output, l);
end procedure;
begin
process is
begin
assert write_func(4) = 4;
write_proc(5);
wait;
end process;
end architecture;
|
entity issue110 is
end entity;
use std.textio.all;
architecture test of issue110 is
impure function write_func(x : integer) return integer is
variable l : line;
begin
write(l, x);
writeline(output, l);
return x;
end function;
procedure write_proc(x : integer) is
variable l : line;
begin
write(l, x);
writeline(output, l);
end procedure;
begin
process is
begin
assert write_func(4) = 4;
write_proc(5);
wait;
end process;
end architecture;
|
entity issue110 is
end entity;
use std.textio.all;
architecture test of issue110 is
impure function write_func(x : integer) return integer is
variable l : line;
begin
write(l, x);
writeline(output, l);
return x;
end function;
procedure write_proc(x : integer) is
variable l : line;
begin
write(l, x);
writeline(output, l);
end procedure;
begin
process is
begin
assert write_func(4) = 4;
write_proc(5);
wait;
end process;
end architecture;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "reg_file_bram_double_buffered"
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xilinx_block_ram_pkg.all;
use work.reg_file_pkg.all;
use work.bus_pkg.all;
-------------------------------------------------------------------------------
entity reg_file_bram_double_buffered_tb is
end reg_file_bram_double_buffered_tb;
-------------------------------------------------------------------------------
architecture tb of reg_file_bram_double_buffered_tb is
-- component generics
constant BASE_ADDRESS : integer range 0 to 16#7FFF# := 0;
-- component ports
signal bus_o : busdevice_out_type := (data => (others => '0'));
signal bus_i : busdevice_in_type := (addr => (others => '0'),
data => (others => '0'),
we => '0',
re => '0');
signal bram_data_i : std_logic_vector(35 downto 0) := (others => '0');
signal bram_data_o : std_logic_vector(35 downto 0) := (others => '0');
signal bram_addr_i : std_logic_vector(7 downto 0) := (others => '0');
signal bram_we_p : std_logic := '0';
signal irq_p : std_logic := '0';
signal ack_p : std_logic := '0';
signal ready_p : std_logic := '0';
signal enable_p : std_logic := '0';
-- clock
signal clk : std_logic := '1';
begin -- tb
-- component instantiation
DUT : reg_file_bram_double_buffered
generic map (
BASE_ADDRESS => BASE_ADDRESS)
port map (
bus_o => bus_o,
bus_i => bus_i,
bram_data_i => bram_data_i,
bram_data_o => bram_data_o,
bram_addr_i => bram_addr_i,
bram_we_p => bram_we_p,
irq_o => irq_p,
ack_i => ack_p,
ready_i => ready_p,
enable_o => enable_p,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
-- purpose: read data from BRAM to bus
bus_Proc : process
begin
-- wait until some data was written to BRAM
for ii in 0 to 10 loop
wait until Clk = '0';
end loop; -- ii
ready_p <= '1';
wait until clk = '0';
ready_p <= '0';
-- read from 0 to 511
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0000", bus_i.addr'length)));
bus_i.re <= '1';
wait until clk = '0';
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0001", bus_i.addr'length)));
wait until clk = '0';
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0002", bus_i.addr'length)));
wait until clk = '0';
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0003", bus_i.addr'length)));
-- do not repeat
wait for 10 ms;
end process bus_Proc;
-- purpose: Simulates the Application writing and reading data to and from the block RAM port B
-- type : sequential
application_proc : process
begin -- process application_proc
wait until clk = '0';
wait until clk = '0';
bram_we_p <= '1';
bram_addr_i <= (others => '0');
bram_data_i <= std_logic_vector(unsigned'(resize(x"3153853fa", bram_data_i'length)));
wait until clk = '0';
bram_addr_i <= std_logic_vector(unsigned'(resize(x"00001", bram_addr_i'length)));
bram_data_i <= std_logic_vector(unsigned'(resize(x"854ff5a41", bram_data_i'length)));
wait until clk = '0';
bram_we_p <= '0';
-- do not repeat
wait for 10 ms;
end process application_proc;
end tb;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "reg_file_bram_double_buffered"
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xilinx_block_ram_pkg.all;
use work.reg_file_pkg.all;
use work.bus_pkg.all;
-------------------------------------------------------------------------------
entity reg_file_bram_double_buffered_tb is
end reg_file_bram_double_buffered_tb;
-------------------------------------------------------------------------------
architecture tb of reg_file_bram_double_buffered_tb is
-- component generics
constant BASE_ADDRESS : integer range 0 to 16#7FFF# := 0;
-- component ports
signal bus_o : busdevice_out_type := (data => (others => '0'));
signal bus_i : busdevice_in_type := (addr => (others => '0'),
data => (others => '0'),
we => '0',
re => '0');
signal bram_data_i : std_logic_vector(35 downto 0) := (others => '0');
signal bram_data_o : std_logic_vector(35 downto 0) := (others => '0');
signal bram_addr_i : std_logic_vector(7 downto 0) := (others => '0');
signal bram_we_p : std_logic := '0';
signal irq_p : std_logic := '0';
signal ack_p : std_logic := '0';
signal ready_p : std_logic := '0';
signal enable_p : std_logic := '0';
-- clock
signal clk : std_logic := '1';
begin -- tb
-- component instantiation
DUT : reg_file_bram_double_buffered
generic map (
BASE_ADDRESS => BASE_ADDRESS)
port map (
bus_o => bus_o,
bus_i => bus_i,
bram_data_i => bram_data_i,
bram_data_o => bram_data_o,
bram_addr_i => bram_addr_i,
bram_we_p => bram_we_p,
irq_o => irq_p,
ack_i => ack_p,
ready_i => ready_p,
enable_o => enable_p,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
-- purpose: read data from BRAM to bus
bus_Proc : process
begin
-- wait until some data was written to BRAM
for ii in 0 to 10 loop
wait until Clk = '0';
end loop; -- ii
ready_p <= '1';
wait until clk = '0';
ready_p <= '0';
-- read from 0 to 511
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0000", bus_i.addr'length)));
bus_i.re <= '1';
wait until clk = '0';
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0001", bus_i.addr'length)));
wait until clk = '0';
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0002", bus_i.addr'length)));
wait until clk = '0';
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0003", bus_i.addr'length)));
-- do not repeat
wait for 10 ms;
end process bus_Proc;
-- purpose: Simulates the Application writing and reading data to and from the block RAM port B
-- type : sequential
application_proc : process
begin -- process application_proc
wait until clk = '0';
wait until clk = '0';
bram_we_p <= '1';
bram_addr_i <= (others => '0');
bram_data_i <= std_logic_vector(unsigned'(resize(x"3153853fa", bram_data_i'length)));
wait until clk = '0';
bram_addr_i <= std_logic_vector(unsigned'(resize(x"00001", bram_addr_i'length)));
bram_data_i <= std_logic_vector(unsigned'(resize(x"854ff5a41", bram_data_i'length)));
wait until clk = '0';
bram_we_p <= '0';
-- do not repeat
wait for 10 ms;
end process application_proc;
end tb;
|
CONFIGURATION memory_stage_struct_config OF memory_stage IS
FOR struct
END FOR;
END memory_stage_struct_config; |
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